[mirror_qemu.git] / hw / cxl / cxl-component-utils.c

/*
 * CXL Utility library for components
 *
 * Copyright(C) 2020 Intel Corporation.
 *
 * This work is licensed under the terms of the GNU GPL, version 2. See the
 * COPYING file in the top-level directory.
 */

#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qapi/error.h"
#include "hw/pci/pci.h"
#include "hw/cxl/cxl.h"

/* CXL r3.0 Section 8.2.4.19.1 CXL HDM Decoder Capability Register */
int cxl_decoder_count_enc(int count)
{
    switch (count) {
    case 1: return 0x0;
    case 2: return 0x1;
    case 4: return 0x2;
    case 6: return 0x3;
    case 8: return 0x4;
    case 10: return 0x5;
    /* Switches and Host Bridges may have more than 10 decoders */
    case 12: return 0x6;
    case 14: return 0x7;
    case 16: return 0x8;
    case 20: return 0x9;
    case 24: return 0xa;
    case 28: return 0xb;
    case 32: return 0xc;
    }
    return 0;
}

int cxl_decoder_count_dec(int enc_cnt)
{
    switch (enc_cnt) {
    case 0x0: return 1;
    case 0x1: return 2;
    case 0x2: return 4;
    case 0x3: return 6;
    case 0x4: return 8;
    case 0x5: return 10;
    /* Switches and Host Bridges may have more than 10 decoders */
    case 0x6: return 12;
    case 0x7: return 14;
    case 0x8: return 16;
    case 0x9: return 20;
    case 0xa: return 24;
    case 0xb: return 28;
    case 0xc: return 32;
    }
    return 0;
}

hwaddr cxl_decode_ig(int ig)
{
    return 1ULL << (ig + 8);
}

static uint64_t cxl_cache_mem_read_reg(void *opaque, hwaddr offset,
                                       unsigned size)
{
    CXLComponentState *cxl_cstate = opaque;
    ComponentRegisters *cregs = &cxl_cstate->crb;

    if (size == 8) {
        qemu_log_mask(LOG_UNIMP,
                      "CXL 8 byte cache mem registers not implemented\n");
        return 0;
    }

    if (cregs->special_ops && cregs->special_ops->read) {
        return cregs->special_ops->read(cxl_cstate, offset, size);
    } else {
        return cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)];
    }
}

static void dumb_hdm_handler(CXLComponentState *cxl_cstate, hwaddr offset,
                             uint32_t value)
{
    ComponentRegisters *cregs = &cxl_cstate->crb;
    uint32_t *cache_mem = cregs->cache_mem_registers;
    bool should_commit = false;
    bool should_uncommit = false;

    switch (offset) {
    case A_CXL_HDM_DECODER0_CTRL:
        should_commit = FIELD_EX32(value, CXL_HDM_DECODER0_CTRL, COMMIT);
        should_uncommit = !should_commit;
        break;
    default:
        break;
    }

    if (should_commit) {
        value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, ERR, 0);
        value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMITTED, 1);
    } else if (should_uncommit) {
        value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, ERR, 0);
        value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMITTED, 0);
    }
    stl_le_p((uint8_t *)cache_mem + offset, value);
}

static void cxl_cache_mem_write_reg(void *opaque, hwaddr offset, uint64_t value,
                                    unsigned size)
{
    CXLComponentState *cxl_cstate = opaque;
    ComponentRegisters *cregs = &cxl_cstate->crb;
    uint32_t mask;

    if (size == 8) {
        qemu_log_mask(LOG_UNIMP,
                      "CXL 8 byte cache mem registers not implemented\n");
        return;
    }
    mask = cregs->cache_mem_regs_write_mask[offset / sizeof(*cregs->cache_mem_regs_write_mask)];
    value &= mask;
    /* RO bits should remain constant. Done by reading existing value */
    value |= ~mask & cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)];
    if (cregs->special_ops && cregs->special_ops->write) {
        cregs->special_ops->write(cxl_cstate, offset, value, size);
        return;
    }

    if (offset >= A_CXL_HDM_DECODER_CAPABILITY &&
        offset <= A_CXL_HDM_DECODER0_TARGET_LIST_HI) {
        dumb_hdm_handler(cxl_cstate, offset, value);
    } else {
        cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)] = value;
    }
}

/*
 * 8.2.3
 *   The access restrictions specified in Section 8.2.2 also apply to CXL 2.0
 *   Component Registers.
 *
 * 8.2.2
 *   • A 32 bit register shall be accessed as a 4 Bytes quantity. Partial
 *   reads are not permitted.
 *   • A 64 bit register shall be accessed as a 8 Bytes quantity. Partial
 *   reads are not permitted.
 *
 * As of the spec defined today, only 4 byte registers exist.
 */
static const MemoryRegionOps cache_mem_ops = {
    .read = cxl_cache_mem_read_reg,
    .write = cxl_cache_mem_write_reg,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 8,
        .unaligned = false,
    },
    .impl = {
        .min_access_size = 4,
        .max_access_size = 8,
    },
};

void cxl_component_register_block_init(Object *obj,
                                       CXLComponentState *cxl_cstate,
                                       const char *type)
{
    ComponentRegisters *cregs = &cxl_cstate->crb;

    memory_region_init(&cregs->component_registers, obj, type,
                       CXL2_COMPONENT_BLOCK_SIZE);

    /* io registers controls link which we don't care about in QEMU */
    memory_region_init_io(&cregs->io, obj, NULL, cregs, ".io",
                          CXL2_COMPONENT_IO_REGION_SIZE);
    memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cregs,
                          ".cache_mem", CXL2_COMPONENT_CM_REGION_SIZE);

    memory_region_add_subregion(&cregs->component_registers, 0, &cregs->io);
    memory_region_add_subregion(&cregs->component_registers,
                                CXL2_COMPONENT_IO_REGION_SIZE,
                                &cregs->cache_mem);
}

static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk)
{
    /*
     * Error status is RW1C but given bits are not yet set, it can
     * be handled as RO.
     */
    stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_STATUS, 0);
    stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_STATUS, 0x1cfff);
    /* Bits 12-13 and 17-31 reserved in CXL 2.0 */
    stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff);
    stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff);
    stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff);
    stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff);
    stl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS, 0);
    stl_le_p(write_msk + R_CXL_RAS_COR_ERR_STATUS, 0x7f);
    stl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK, 0x7f);
    stl_le_p(write_msk + R_CXL_RAS_COR_ERR_MASK, 0x7f);
    /* CXL switches and devices must set */
    stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x200);
}

static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk,
                            enum reg_type type)
{
    int decoder_count = 1;
    int hdm_inc = R_CXL_HDM_DECODER1_BASE_LO - R_CXL_HDM_DECODER0_BASE_LO;
    int i;

    ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, DECODER_COUNT,
                     cxl_decoder_count_enc(decoder_count));
    ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 1);
    ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_256B, 1);
    ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K, 1);
    ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, POISON_ON_ERR_CAP, 0);
    ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_GLOBAL_CONTROL,
                     HDM_DECODER_ENABLE, 0);
    write_msk[R_CXL_HDM_DECODER_GLOBAL_CONTROL] = 0x3;
    for (i = 0; i < decoder_count; i++) {
        write_msk[R_CXL_HDM_DECODER0_BASE_LO + i * hdm_inc] = 0xf0000000;
        write_msk[R_CXL_HDM_DECODER0_BASE_HI + i * hdm_inc] = 0xffffffff;
        write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * hdm_inc] = 0xf0000000;
        write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * hdm_inc] = 0xffffffff;
        write_msk[R_CXL_HDM_DECODER0_CTRL + i * hdm_inc] = 0x13ff;
        if (type == CXL2_DEVICE ||
            type == CXL2_TYPE3_DEVICE ||
            type == CXL2_LOGICAL_DEVICE) {
            write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * hdm_inc] =
                0xf0000000;
        } else {
            write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * hdm_inc] =
                0xffffffff;
        }
        write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * hdm_inc] = 0xffffffff;
    }
}

void cxl_component_register_init_common(uint32_t *reg_state, uint32_t *write_msk,
                                        enum reg_type type)
{
    int caps = 0;

    /*
     * In CXL 2.0 the capabilities required for each CXL component are such that,
     * with the ordering chosen here, a single number can be used to define
     * which capabilities should be provided.
     */
    switch (type) {
    case CXL2_DOWNSTREAM_PORT:
    case CXL2_DEVICE:
        /* RAS, Link */
        caps = 2;
        break;
    case CXL2_UPSTREAM_PORT:
    case CXL2_TYPE3_DEVICE:
    case CXL2_LOGICAL_DEVICE:
        /* + HDM */
        caps = 3;
        break;
    case CXL2_ROOT_PORT:
        /* + Extended Security, + Snoop */
        caps = 5;
        break;
    default:
        abort();
    }

    memset(reg_state, 0, CXL2_COMPONENT_CM_REGION_SIZE);

    /* CXL Capability Header Register */
    ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ID, 1);
    ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, VERSION, 1);
    ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, CACHE_MEM_VERSION, 1);
    ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ARRAY_SIZE, caps);

#define init_cap_reg(reg, id, version)                                        \
    QEMU_BUILD_BUG_ON(CXL_##reg##_REGISTERS_OFFSET == 0);                     \
    do {                                                                      \
        int which = R_CXL_##reg##_CAPABILITY_HEADER;                          \
        reg_state[which] = FIELD_DP32(reg_state[which],                       \
                                      CXL_##reg##_CAPABILITY_HEADER, ID, id); \
        reg_state[which] =                                                    \
            FIELD_DP32(reg_state[which], CXL_##reg##_CAPABILITY_HEADER,       \
                       VERSION, version);                                     \
        reg_state[which] =                                                    \
            FIELD_DP32(reg_state[which], CXL_##reg##_CAPABILITY_HEADER, PTR,  \
                       CXL_##reg##_REGISTERS_OFFSET);                         \
    } while (0)

    init_cap_reg(RAS, 2, 2);
    ras_init_common(reg_state, write_msk);

    init_cap_reg(LINK, 4, 2);

    if (caps < 3) {
        return;
    }

    init_cap_reg(HDM, 5, 1);
    hdm_init_common(reg_state, write_msk, type);

    if (caps < 5) {
        return;
    }

    init_cap_reg(EXTSEC, 6, 1);
    init_cap_reg(SNOOP, 8, 1);

#undef init_cap_reg
}

/*
 * Helper to creates a DVSEC header for a CXL entity. The caller is responsible
 * for tracking the valid offset.
 *
 * This function will build the DVSEC header on behalf of the caller and then
 * copy in the remaining data for the vendor specific bits.
 * It will also set up appropriate write masks.
 */
void cxl_component_create_dvsec(CXLComponentState *cxl,
                                enum reg_type cxl_dev_type, uint16_t length,
                                uint16_t type, uint8_t rev, uint8_t *body)
{
    PCIDevice *pdev = cxl->pdev;
    uint16_t offset = cxl->dvsec_offset;
    uint8_t *wmask = pdev->wmask;

    assert(offset >= PCI_CFG_SPACE_SIZE &&
           ((offset + length) < PCI_CFG_SPACE_EXP_SIZE));
    assert((length & 0xf000) == 0);
    assert((rev & ~0xf) == 0);

    /* Create the DVSEC in the MCFG space */
    pcie_add_capability(pdev, PCI_EXT_CAP_ID_DVSEC, 1, offset, length);
    pci_set_long(pdev->config + offset + PCIE_DVSEC_HEADER1_OFFSET,
                 (length << 20) | (rev << 16) | CXL_VENDOR_ID);
    pci_set_word(pdev->config + offset + PCIE_DVSEC_ID_OFFSET, type);
    memcpy(pdev->config + offset + sizeof(DVSECHeader),
           body + sizeof(DVSECHeader),
           length - sizeof(DVSECHeader));

    /* Configure write masks */
    switch (type) {
    case PCIE_CXL_DEVICE_DVSEC:
        /* Cntrl RW Lock - so needs explicit blocking when lock is set */
        wmask[offset + offsetof(CXLDVSECDevice, ctrl)] = 0xFD;
        wmask[offset + offsetof(CXLDVSECDevice, ctrl) + 1] = 0x4F;
        /* Status is RW1CS */
        wmask[offset + offsetof(CXLDVSECDevice, ctrl2)] = 0x0F;
       /* Lock is RW Once */
        wmask[offset + offsetof(CXLDVSECDevice, lock)] = 0x01;
        /* range1/2_base_high/low is RW Lock */
        wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi)] = 0xFF;
        wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 1] = 0xFF;
        wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 2] = 0xFF;
        wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 3] = 0xFF;
        wmask[offset + offsetof(CXLDVSECDevice, range1_base_lo) + 3] = 0xF0;
        wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi)] = 0xFF;
        wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 1] = 0xFF;
        wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 2] = 0xFF;
        wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 3] = 0xFF;
        wmask[offset + offsetof(CXLDVSECDevice, range2_base_lo) + 3] = 0xF0;
        break;
    case NON_CXL_FUNCTION_MAP_DVSEC:
        break; /* Not yet implemented */
    case EXTENSIONS_PORT_DVSEC:
        wmask[offset + offsetof(CXLDVSECPortExtensions, control)] = 0x0F;
        wmask[offset + offsetof(CXLDVSECPortExtensions, control) + 1] = 0x40;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_bus_base)] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_bus_limit)] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_base)] = 0xF0;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_base) + 1] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_limit)] = 0xF0;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_limit) + 1] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base)] = 0xF0;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base) + 1] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit)] = 0xF0;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit) + 1] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high)] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 1] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 2] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 3] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high)] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 1] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 2] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 3] = 0xFF;
        break;
    case GPF_PORT_DVSEC:
        wmask[offset + offsetof(CXLDVSECPortGPF, phase1_ctrl)] = 0x0F;
        wmask[offset + offsetof(CXLDVSECPortGPF, phase1_ctrl) + 1] = 0x0F;
        wmask[offset + offsetof(CXLDVSECPortGPF, phase2_ctrl)] = 0x0F;
        wmask[offset + offsetof(CXLDVSECPortGPF, phase2_ctrl) + 1] = 0x0F;
        break;
    case GPF_DEVICE_DVSEC:
        wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_duration)] = 0x0F;
        wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_duration) + 1] = 0x0F;
        wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power)] = 0xFF;
        wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 1] = 0xFF;
        wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 2] = 0xFF;
        wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 3] = 0xFF;
        break;
    case PCIE_FLEXBUS_PORT_DVSEC:
        switch (cxl_dev_type) {
        case CXL2_ROOT_PORT:
            /* No MLD */
            wmask[offset + offsetof(CXLDVSECPortFlexBus, ctrl)] = 0xbd;
            break;
        case CXL2_DOWNSTREAM_PORT:
            wmask[offset + offsetof(CXLDVSECPortFlexBus, ctrl)] = 0xfd;
            break;
        default: /* Registers are RO for other component types */
            break;
        }
        /* There are rw1cs bits in the status register but never set currently */
        break;
    }

    /* Update state for future DVSEC additions */
    range_init_nofail(&cxl->dvsecs[type], cxl->dvsec_offset, length);
    cxl->dvsec_offset += length;
}

/* CXL r3.0 Section 8.2.4.19.7 CXL HDM Decoder n Control Register */
uint8_t cxl_interleave_ways_enc(int iw, Error **errp)
{
    switch (iw) {
    case 1: return 0x0;
    case 2: return 0x1;
    case 4: return 0x2;
    case 8: return 0x3;
    case 16: return 0x4;
    case 3: return 0x8;
    case 6: return 0x9;
    case 12: return 0xa;
    default:
        error_setg(errp, "Interleave ways: %d not supported", iw);
        return 0;
    }
}

int cxl_interleave_ways_dec(uint8_t iw_enc, Error **errp)
{
    switch (iw_enc) {
    case 0x0: return 1;
    case 0x1: return 2;
    case 0x2: return 4;
    case 0x3: return 8;
    case 0x4: return 16;
    case 0x8: return 3;
    case 0x9: return 6;
    case 0xa: return 12;
    default:
        error_setg(errp, "Encoded interleave ways: %d not supported", iw_enc);
        return 0;
    }
}

uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp)
{
    switch (gran) {
    case 256: return 0;
    case 512: return 1;
    case 1024: return 2;
    case 2048: return 3;
    case 4096: return 4;
    case 8192: return 5;
    case 16384: return 6;
    default:
        error_setg(errp, "Interleave granularity: %" PRIu64 " invalid", gran);
        return 0;
    }
}
Commit	Line	Data
9e58f52d BW	1	/*
	2	* CXL Utility library for components
	3	*
	4	* Copyright(C) 2020 Intel Corporation.
	5	*
	6	* This work is licensed under the terms of the GNU GPL, version 2. See the
	7	* COPYING file in the top-level directory.
	8	*/
	9
	10	#include "qemu/osdep.h"
	11	#include "qemu/log.h"
829de299	12	#include "qapi/error.h"
9e58f52d BW	13	#include "hw/pci/pci.h"
	14	#include "hw/cxl/cxl.h"
	15
87de174a	16	/* CXL r3.0 Section 8.2.4.19.1 CXL HDM Decoder Capability Register */
f5a4e1a6 JC	17	int cxl_decoder_count_enc(int count)
	18	{
	19	switch (count) {
87de174a JC	20	case 1: return 0x0;
	21	case 2: return 0x1;
	22	case 4: return 0x2;
	23	case 6: return 0x3;
	24	case 8: return 0x4;
	25	case 10: return 0x5;
	26	/* Switches and Host Bridges may have more than 10 decoders */
	27	case 12: return 0x6;
	28	case 14: return 0x7;
	29	case 16: return 0x8;
	30	case 20: return 0x9;
	31	case 24: return 0xa;
	32	case 28: return 0xb;
	33	case 32: return 0xc;
	34	}
	35	return 0;
	36	}
	37
	38	int cxl_decoder_count_dec(int enc_cnt)
	39	{
	40	switch (enc_cnt) {
	41	case 0x0: return 1;
	42	case 0x1: return 2;
	43	case 0x2: return 4;
	44	case 0x3: return 6;
	45	case 0x4: return 8;
	46	case 0x5: return 10;
	47	/* Switches and Host Bridges may have more than 10 decoders */
	48	case 0x6: return 12;
	49	case 0x7: return 14;
	50	case 0x8: return 16;
	51	case 0x9: return 20;
	52	case 0xa: return 24;
	53	case 0xb: return 28;
	54	case 0xc: return 32;
f5a4e1a6 JC	55	}
	56	return 0;
	57	}
	58
	59	hwaddr cxl_decode_ig(int ig)
	60	{
	61	return 1ULL << (ig + 8);
	62	}
	63
9e58f52d BW	64	static uint64_t cxl_cache_mem_read_reg(void *opaque, hwaddr offset,
	65	unsigned size)
	66	{
	67	CXLComponentState *cxl_cstate = opaque;
	68	ComponentRegisters *cregs = &cxl_cstate->crb;
	69
	70	if (size == 8) {
	71	qemu_log_mask(LOG_UNIMP,
	72	"CXL 8 byte cache mem registers not implemented\n");
	73	return 0;
	74	}
	75
	76	if (cregs->special_ops && cregs->special_ops->read) {
	77	return cregs->special_ops->read(cxl_cstate, offset, size);
	78	} else {
	79	return cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)];
	80	}
	81	}
	82
3540bf56 BW	83	static void dumb_hdm_handler(CXLComponentState *cxl_cstate, hwaddr offset,
	84	uint32_t value)
	85	{
	86	ComponentRegisters *cregs = &cxl_cstate->crb;
	87	uint32_t *cache_mem = cregs->cache_mem_registers;
	88	bool should_commit = false;
823371a6	89	bool should_uncommit = false;
3540bf56 BW	90
	91	switch (offset) {
	92	case A_CXL_HDM_DECODER0_CTRL:
	93	should_commit = FIELD_EX32(value, CXL_HDM_DECODER0_CTRL, COMMIT);
823371a6	94	should_uncommit = !should_commit;
3540bf56 BW	95	break;
	96	default:
	97	break;
	98	}
	99
3540bf56	100	if (should_commit) {
92ff7cab JC	101	value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, ERR, 0);
92ff7cab JC	102	value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMITTED, 1);
823371a6 JC	103	} else if (should_uncommit) {
	104	value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, ERR, 0);
	105	value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMITTED, 0);
3540bf56	106	}
92ff7cab	107	stl_le_p((uint8_t *)cache_mem + offset, value);
3540bf56 BW	108	}
3540bf56 BW	109
9e58f52d BW	110	static void cxl_cache_mem_write_reg(void *opaque, hwaddr offset, uint64_t value,
	111	unsigned size)
	112	{
	113	CXLComponentState *cxl_cstate = opaque;
	114	ComponentRegisters *cregs = &cxl_cstate->crb;
	115	uint32_t mask;
	116
	117	if (size == 8) {
	118	qemu_log_mask(LOG_UNIMP,
	119	"CXL 8 byte cache mem registers not implemented\n");
	120	return;
	121	}
	122	mask = cregs->cache_mem_regs_write_mask[offset / sizeof(*cregs->cache_mem_regs_write_mask)];
	123	value &= mask;
	124	/* RO bits should remain constant. Done by reading existing value */
	125	value \|= ~mask & cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)];
	126	if (cregs->special_ops && cregs->special_ops->write) {
	127	cregs->special_ops->write(cxl_cstate, offset, value, size);
3540bf56 BW	128	return;
	129	}
	130
	131	if (offset >= A_CXL_HDM_DECODER_CAPABILITY &&
	132	offset <= A_CXL_HDM_DECODER0_TARGET_LIST_HI) {
	133	dumb_hdm_handler(cxl_cstate, offset, value);
9e58f52d BW	134	} else {
	135	cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)] = value;
	136	}
	137	}
	138
	139	/*
	140	* 8.2.3
	141	* The access restrictions specified in Section 8.2.2 also apply to CXL 2.0
	142	* Component Registers.
	143	*
	144	* 8.2.2
	145	* • A 32 bit register shall be accessed as a 4 Bytes quantity. Partial
	146	* reads are not permitted.
	147	* • A 64 bit register shall be accessed as a 8 Bytes quantity. Partial
	148	* reads are not permitted.
	149	*
	150	* As of the spec defined today, only 4 byte registers exist.
	151	*/
	152	static const MemoryRegionOps cache_mem_ops = {
	153	.read = cxl_cache_mem_read_reg,
	154	.write = cxl_cache_mem_write_reg,
	155	.endianness = DEVICE_LITTLE_ENDIAN,
	156	.valid = {
	157	.min_access_size = 4,
	158	.max_access_size = 8,
	159	.unaligned = false,
	160	},
	161	.impl = {
	162	.min_access_size = 4,
	163	.max_access_size = 8,
	164	},
	165	};
	166
	167	void cxl_component_register_block_init(Object *obj,
	168	CXLComponentState *cxl_cstate,
	169	const char *type)
	170	{
	171	ComponentRegisters *cregs = &cxl_cstate->crb;
	172
	173	memory_region_init(&cregs->component_registers, obj, type,
	174	CXL2_COMPONENT_BLOCK_SIZE);
	175
	176	/* io registers controls link which we don't care about in QEMU */
	177	memory_region_init_io(&cregs->io, obj, NULL, cregs, ".io",
	178	CXL2_COMPONENT_IO_REGION_SIZE);
	179	memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cregs,
	180	".cache_mem", CXL2_COMPONENT_CM_REGION_SIZE);
	181
	182	memory_region_add_subregion(&cregs->component_registers, 0, &cregs->io);
	183	memory_region_add_subregion(&cregs->component_registers,
	184	CXL2_COMPONENT_IO_REGION_SIZE,
	185	&cregs->cache_mem);
	186	}
	187
	188	static void ras_init_common(uint32_t reg_state, uint32_t write_msk)
	189	{
	190	/*
	191	* Error status is RW1C but given bits are not yet set, it can
	192	* be handled as RO.
	193	*/
cb4e642c	194	stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_STATUS, 0);
415442a1	195	stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_STATUS, 0x1cfff);
9e58f52d	196	/* Bits 12-13 and 17-31 reserved in CXL 2.0 */
cb4e642c JC	197	stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff);
	198	stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff);
	199	stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff);
	200	stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff);
	201	stl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS, 0);
415442a1	202	stl_le_p(write_msk + R_CXL_RAS_COR_ERR_STATUS, 0x7f);
cb4e642c JC	203	stl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK, 0x7f);
cb4e642c JC	204	stl_le_p(write_msk + R_CXL_RAS_COR_ERR_MASK, 0x7f);
9e58f52d	205	/* CXL switches and devices must set */
415442a1	206	stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x200);
9e58f52d BW	207	}
9e58f52d BW	208
f824f529 JC	209	static void hdm_init_common(uint32_t reg_state, uint32_t write_msk,
f824f529 JC	210	enum reg_type type)
9e58f52d BW	211	{
9e58f52d BW	212	int decoder_count = 1;
61c44bcf	213	int hdm_inc = R_CXL_HDM_DECODER1_BASE_LO - R_CXL_HDM_DECODER0_BASE_LO;
9e58f52d BW	214	int i;
	215
	216	ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, DECODER_COUNT,
	217	cxl_decoder_count_enc(decoder_count));
	218	ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 1);
	219	ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_256B, 1);
	220	ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K, 1);
	221	ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, POISON_ON_ERR_CAP, 0);
	222	ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_GLOBAL_CONTROL,
	223	HDM_DECODER_ENABLE, 0);
	224	write_msk[R_CXL_HDM_DECODER_GLOBAL_CONTROL] = 0x3;
	225	for (i = 0; i < decoder_count; i++) {
61c44bcf JC	226	write_msk[R_CXL_HDM_DECODER0_BASE_LO + i * hdm_inc] = 0xf0000000;
	227	write_msk[R_CXL_HDM_DECODER0_BASE_HI + i * hdm_inc] = 0xffffffff;
	228	write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * hdm_inc] = 0xf0000000;
	229	write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * hdm_inc] = 0xffffffff;
	230	write_msk[R_CXL_HDM_DECODER0_CTRL + i * hdm_inc] = 0x13ff;
f824f529 JC	231	if (type == CXL2_DEVICE \|\|
	232	type == CXL2_TYPE3_DEVICE \|\|
	233	type == CXL2_LOGICAL_DEVICE) {
61c44bcf JC	234	write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * hdm_inc] =
61c44bcf JC	235	0xf0000000;
f824f529	236	} else {
61c44bcf JC	237	write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * hdm_inc] =
61c44bcf JC	238	0xffffffff;
f824f529	239	}
61c44bcf	240	write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * hdm_inc] = 0xffffffff;
9e58f52d BW	241	}
	242	}
	243
	244	void cxl_component_register_init_common(uint32_t reg_state, uint32_t write_msk,
	245	enum reg_type type)
	246	{
	247	int caps = 0;
	248
	249	/*
	250	* In CXL 2.0 the capabilities required for each CXL component are such that,
	251	* with the ordering chosen here, a single number can be used to define
	252	* which capabilities should be provided.
	253	*/
	254	switch (type) {
	255	case CXL2_DOWNSTREAM_PORT:
	256	case CXL2_DEVICE:
	257	/* RAS, Link */
	258	caps = 2;
	259	break;
	260	case CXL2_UPSTREAM_PORT:
	261	case CXL2_TYPE3_DEVICE:
	262	case CXL2_LOGICAL_DEVICE:
	263	/* + HDM */
	264	caps = 3;
	265	break;
	266	case CXL2_ROOT_PORT:
	267	/* + Extended Security, + Snoop */
	268	caps = 5;
	269	break;
	270	default:
	271	abort();
	272	}
	273
	274	memset(reg_state, 0, CXL2_COMPONENT_CM_REGION_SIZE);
	275
	276	/* CXL Capability Header Register */
	277	ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ID, 1);
	278	ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, VERSION, 1);
	279	ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, CACHE_MEM_VERSION, 1);
	280	ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ARRAY_SIZE, caps);
	281
	282	#define init_cap_reg(reg, id, version) \
	283	QEMU_BUILD_BUG_ON(CXL_##reg##_REGISTERS_OFFSET == 0); \
	284	do { \
	285	int which = R_CXL_##reg##_CAPABILITY_HEADER; \
	286	reg_state[which] = FIELD_DP32(reg_state[which], \
	287	CXL_##reg##_CAPABILITY_HEADER, ID, id); \
	288	reg_state[which] = \
	289	FIELD_DP32(reg_state[which], CXL_##reg##_CAPABILITY_HEADER, \
	290	VERSION, version); \
	291	reg_state[which] = \
	292	FIELD_DP32(reg_state[which], CXL_##reg##_CAPABILITY_HEADER, PTR, \
	293	CXL_##reg##_REGISTERS_OFFSET); \
	294	} while (0)
	295
	296	init_cap_reg(RAS, 2, 2);
	297	ras_init_common(reg_state, write_msk);
	298
	299	init_cap_reg(LINK, 4, 2);
	300
	301	if (caps < 3) {
	302	return;
	303	}
	304
305	init_cap_reg(HDM, 5, 1);
f824f529	306	hdm_init_common(reg_state, write_msk, type);
9e58f52d BW	307
	308	if (caps < 5) {
	309	return;
	310	}
	311
	312	init_cap_reg(EXTSEC, 6, 1);
	313	init_cap_reg(SNOOP, 8, 1);
	314
	315	#undef init_cap_reg
	316	}
	317
	318	/*
	319	* Helper to creates a DVSEC header for a CXL entity. The caller is responsible
	320	* for tracking the valid offset.
	321	*
	322	* This function will build the DVSEC header on behalf of the caller and then
	323	* copy in the remaining data for the vendor specific bits.
	324	* It will also set up appropriate write masks.
	325	*/
	326	void cxl_component_create_dvsec(CXLComponentState *cxl,
	327	enum reg_type cxl_dev_type, uint16_t length,
	328	uint16_t type, uint8_t rev, uint8_t *body)
	329	{
	330	PCIDevice *pdev = cxl->pdev;
	331	uint16_t offset = cxl->dvsec_offset;
	332	uint8_t *wmask = pdev->wmask;
	333
	334	assert(offset >= PCI_CFG_SPACE_SIZE &&
	335	((offset + length) < PCI_CFG_SPACE_EXP_SIZE));
	336	assert((length & 0xf000) == 0);
	337	assert((rev & ~0xf) == 0);
	338
	339	/* Create the DVSEC in the MCFG space */
	340	pcie_add_capability(pdev, PCI_EXT_CAP_ID_DVSEC, 1, offset, length);
	341	pci_set_long(pdev->config + offset + PCIE_DVSEC_HEADER1_OFFSET,
	342	(length << 20) \| (rev << 16) \| CXL_VENDOR_ID);
	343	pci_set_word(pdev->config + offset + PCIE_DVSEC_ID_OFFSET, type);
	344	memcpy(pdev->config + offset + sizeof(DVSECHeader),
	345	body + sizeof(DVSECHeader),
	346	length - sizeof(DVSECHeader));
	347
	348	/* Configure write masks */
	349	switch (type) {
	350	case PCIE_CXL_DEVICE_DVSEC:
e1706ea8 BW	351	/* Cntrl RW Lock - so needs explicit blocking when lock is set */
	352	wmask[offset + offsetof(CXLDVSECDevice, ctrl)] = 0xFD;
	353	wmask[offset + offsetof(CXLDVSECDevice, ctrl) + 1] = 0x4F;
	354	/* Status is RW1CS */
	355	wmask[offset + offsetof(CXLDVSECDevice, ctrl2)] = 0x0F;
	356	/* Lock is RW Once */
	357	wmask[offset + offsetof(CXLDVSECDevice, lock)] = 0x01;
	358	/* range1/2_base_high/low is RW Lock */
	359	wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi)] = 0xFF;
	360	wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 1] = 0xFF;
	361	wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 2] = 0xFF;
	362	wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 3] = 0xFF;
	363	wmask[offset + offsetof(CXLDVSECDevice, range1_base_lo) + 3] = 0xF0;
	364	wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi)] = 0xFF;
	365	wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 1] = 0xFF;
	366	wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 2] = 0xFF;
	367	wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 3] = 0xFF;
	368	wmask[offset + offsetof(CXLDVSECDevice, range2_base_lo) + 3] = 0xF0;
9e58f52d BW	369	break;
	370	case NON_CXL_FUNCTION_MAP_DVSEC:
	371	break; /* Not yet implemented */
	372	case EXTENSIONS_PORT_DVSEC:
	373	wmask[offset + offsetof(CXLDVSECPortExtensions, control)] = 0x0F;
	374	wmask[offset + offsetof(CXLDVSECPortExtensions, control) + 1] = 0x40;
	375	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_bus_base)] = 0xFF;
	376	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_bus_limit)] = 0xFF;
	377	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_base)] = 0xF0;
	378	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_base) + 1] = 0xFF;
	379	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_limit)] = 0xF0;
	380	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_limit) + 1] = 0xFF;
	381	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base)] = 0xF0;
	382	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base) + 1] = 0xFF;
	383	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit)] = 0xF0;
	384	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit) + 1] = 0xFF;
	385	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high)] = 0xFF;
	386	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 1] = 0xFF;
	387	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 2] = 0xFF;
	388	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 3] = 0xFF;
	389	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high)] = 0xFF;
	390	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 1] = 0xFF;
	391	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 2] = 0xFF;
	392	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 3] = 0xFF;
	393	break;
	394	case GPF_PORT_DVSEC:
	395	wmask[offset + offsetof(CXLDVSECPortGPF, phase1_ctrl)] = 0x0F;
	396	wmask[offset + offsetof(CXLDVSECPortGPF, phase1_ctrl) + 1] = 0x0F;
	397	wmask[offset + offsetof(CXLDVSECPortGPF, phase2_ctrl)] = 0x0F;
	398	wmask[offset + offsetof(CXLDVSECPortGPF, phase2_ctrl) + 1] = 0x0F;
	399	break;
	400	case GPF_DEVICE_DVSEC:
	401	wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_duration)] = 0x0F;
	402	wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_duration) + 1] = 0x0F;
	403	wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power)] = 0xFF;
	404	wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 1] = 0xFF;
	405	wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 2] = 0xFF;
	406	wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 3] = 0xFF;
	407	break;
	408	case PCIE_FLEXBUS_PORT_DVSEC:
	409	switch (cxl_dev_type) {
	410	case CXL2_ROOT_PORT:
	411	/* No MLD */
	412	wmask[offset + offsetof(CXLDVSECPortFlexBus, ctrl)] = 0xbd;
	413	break;
	414	case CXL2_DOWNSTREAM_PORT:
	415	wmask[offset + offsetof(CXLDVSECPortFlexBus, ctrl)] = 0xfd;
	416	break;
	417	default: /* Registers are RO for other component types */
	418	break;
	419	}
	420	/* There are rw1cs bits in the status register but never set currently */
	421	break;
	422	}
	423
	424	/* Update state for future DVSEC additions */
	425	range_init_nofail(&cxl->dvsecs[type], cxl->dvsec_offset, length);
	426	cxl->dvsec_offset += length;
	427	}
829de299	428
87de174a	429	/* CXL r3.0 Section 8.2.4.19.7 CXL HDM Decoder n Control Register */
829de299 JC	430	uint8_t cxl_interleave_ways_enc(int iw, Error **errp)
	431	{
	432	switch (iw) {
	433	case 1: return 0x0;
	434	case 2: return 0x1;
	435	case 4: return 0x2;
	436	case 8: return 0x3;
	437	case 16: return 0x4;
	438	case 3: return 0x8;
	439	case 6: return 0x9;
	440	case 12: return 0xa;
	441	default:
	442	error_setg(errp, "Interleave ways: %d not supported", iw);
	443	return 0;
	444	}
	445	}
	446
87de174a JC	447	int cxl_interleave_ways_dec(uint8_t iw_enc, Error **errp)
	448	{
	449	switch (iw_enc) {
	450	case 0x0: return 1;
	451	case 0x1: return 2;
	452	case 0x2: return 4;
	453	case 0x3: return 8;
	454	case 0x4: return 16;
	455	case 0x8: return 3;
	456	case 0x9: return 6;
	457	case 0xa: return 12;
	458	default:
	459	error_setg(errp, "Encoded interleave ways: %d not supported", iw_enc);
	460	return 0;
	461	}
	462	}
	463
829de299 JC	464	uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp)
	465	{
	466	switch (gran) {
	467	case 256: return 0;
	468	case 512: return 1;
	469	case 1024: return 2;
	470	case 2048: return 3;
	471	case 4096: return 4;
	472	case 8192: return 5;
	473	case 16384: return 6;
	474	default:
	475	error_setg(errp, "Interleave granularity: %" PRIu64 " invalid", gran);
	476	return 0;
	477	}
	478	}