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Commit | Line | Data |
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862b4a29 BZ |
1 | /* |
2 | * QEMU ATI SVGA emulation | |
3 | * 2D engine functions | |
4 | * | |
5 | * Copyright (c) 2019 BALATON Zoltan | |
6 | * | |
7 | * This work is licensed under the GNU GPL license version 2 or later. | |
8 | */ | |
9 | ||
bbfff196 | 10 | #include "qemu/osdep.h" |
862b4a29 BZ |
11 | #include "ati_int.h" |
12 | #include "ati_regs.h" | |
13 | #include "qemu/log.h" | |
14 | #include "ui/pixel_ops.h" | |
15 | ||
16 | /* | |
17 | * NOTE: | |
18 | * This is 2D _acceleration_ and supposed to be fast. Therefore, don't try to | |
19 | * reinvent the wheel (unlikely to get better with a naive implementation than | |
20 | * existing libraries) and avoid (poorly) reimplementing gfx primitives. | |
21 | * That is unnecessary and would become a performance problem. Instead, try to | |
22 | * map to and reuse existing optimised facilities (e.g. pixman) wherever | |
23 | * possible. | |
24 | */ | |
25 | ||
26 | static int ati_bpp_from_datatype(ATIVGAState *s) | |
27 | { | |
28 | switch (s->regs.dp_datatype & 0xf) { | |
29 | case 2: | |
30 | return 8; | |
31 | case 3: | |
32 | case 4: | |
33 | return 16; | |
34 | case 5: | |
35 | return 24; | |
36 | case 6: | |
37 | return 32; | |
38 | default: | |
39 | qemu_log_mask(LOG_UNIMP, "Unknown dst datatype %d\n", | |
40 | s->regs.dp_datatype & 0xf); | |
41 | return 0; | |
42 | } | |
43 | } | |
44 | ||
45 | void ati_2d_blt(ATIVGAState *s) | |
46 | { | |
47 | /* FIXME it is probably more complex than this and may need to be */ | |
48 | /* rewritten but for now as a start just to get some output: */ | |
49 | DisplaySurface *ds = qemu_console_surface(s->vga.con); | |
50 | DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr, | |
51 | s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds), | |
52 | surface_bits_per_pixel(ds), | |
53 | (s->regs.dp_mix & GMC_ROP3_MASK) >> 16); | |
866ad5f5 BZ |
54 | DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d\n", |
55 | s->regs.src_offset, s->regs.dst_offset, s->regs.default_offset, | |
56 | s->regs.src_pitch, s->regs.dst_pitch, s->regs.default_pitch, | |
862b4a29 BZ |
57 | s->regs.src_x, s->regs.src_y, s->regs.dst_x, s->regs.dst_y, |
58 | s->regs.dst_width, s->regs.dst_height); | |
59 | switch (s->regs.dp_mix & GMC_ROP3_MASK) { | |
60 | case ROP3_SRCCOPY: | |
61 | { | |
62 | uint8_t *src_bits, *dst_bits, *end; | |
63 | int src_stride, dst_stride, bpp = ati_bpp_from_datatype(s); | |
866ad5f5 BZ |
64 | src_bits = s->vga.vram_ptr + |
65 | (s->regs.dp_gui_master_cntl & GMC_SRC_PITCH_OFFSET_CNTL ? | |
66 | s->regs.src_offset : s->regs.default_offset); | |
67 | dst_bits = s->vga.vram_ptr + | |
68 | (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL ? | |
69 | s->regs.dst_offset : s->regs.default_offset); | |
70 | src_stride = (s->regs.dp_gui_master_cntl & GMC_SRC_PITCH_OFFSET_CNTL ? | |
71 | s->regs.src_pitch : s->regs.default_pitch); | |
72 | dst_stride = (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL ? | |
73 | s->regs.dst_pitch : s->regs.default_pitch); | |
862b4a29 BZ |
74 | |
75 | if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { | |
76 | src_bits += s->regs.crtc_offset & 0x07ffffff; | |
77 | dst_bits += s->regs.crtc_offset & 0x07ffffff; | |
78 | src_stride *= bpp; | |
79 | dst_stride *= bpp; | |
80 | } | |
81 | src_stride /= sizeof(uint32_t); | |
82 | dst_stride /= sizeof(uint32_t); | |
83 | ||
84 | DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d)\n", | |
85 | src_bits, dst_bits, src_stride, dst_stride, bpp, bpp, | |
86 | s->regs.src_x, s->regs.src_y, s->regs.dst_x, s->regs.dst_y, | |
87 | s->regs.dst_width, s->regs.dst_height); | |
88 | end = s->vga.vram_ptr + s->vga.vram_size; | |
89 | if (src_bits >= end || dst_bits >= end || | |
349ebdd7 BZ |
90 | src_bits + s->regs.src_x + (s->regs.src_y + s->regs.dst_height) * |
91 | src_stride * sizeof(uint32_t) >= end || | |
92 | dst_bits + s->regs.dst_x + (s->regs.dst_y + s->regs.dst_height) * | |
93 | dst_stride * sizeof(uint32_t) >= end) { | |
862b4a29 BZ |
94 | qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); |
95 | return; | |
96 | } | |
97 | pixman_blt((uint32_t *)src_bits, (uint32_t *)dst_bits, | |
98 | src_stride, dst_stride, bpp, bpp, | |
99 | s->regs.src_x, s->regs.src_y, | |
100 | s->regs.dst_x, s->regs.dst_y, | |
101 | s->regs.dst_width, s->regs.dst_height); | |
102 | if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr && | |
103 | dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr + | |
104 | s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) { | |
105 | memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr + | |
106 | s->regs.dst_offset + | |
107 | s->regs.dst_y * surface_stride(ds), | |
108 | s->regs.dst_height * surface_stride(ds)); | |
109 | } | |
110 | s->regs.dst_x += s->regs.dst_width; | |
111 | s->regs.dst_y += s->regs.dst_height; | |
112 | break; | |
113 | } | |
114 | case ROP3_PATCOPY: | |
115 | case ROP3_BLACKNESS: | |
116 | case ROP3_WHITENESS: | |
117 | { | |
118 | uint8_t *dst_bits, *end; | |
119 | int dst_stride, bpp = ati_bpp_from_datatype(s); | |
120 | uint32_t filler = 0; | |
866ad5f5 BZ |
121 | dst_bits = s->vga.vram_ptr + |
122 | (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL ? | |
123 | s->regs.dst_offset : s->regs.default_offset); | |
124 | dst_stride = (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL ? | |
125 | s->regs.dst_pitch : s->regs.default_pitch); | |
862b4a29 BZ |
126 | |
127 | if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { | |
128 | dst_bits += s->regs.crtc_offset & 0x07ffffff; | |
129 | dst_stride *= bpp; | |
130 | } | |
131 | dst_stride /= sizeof(uint32_t); | |
132 | ||
133 | switch (s->regs.dp_mix & GMC_ROP3_MASK) { | |
134 | case ROP3_PATCOPY: | |
135 | filler = bswap32(s->regs.dp_brush_frgd_clr); | |
136 | break; | |
137 | case ROP3_BLACKNESS: | |
138 | filler = rgb_to_pixel32(s->vga.palette[0], s->vga.palette[1], | |
139 | s->vga.palette[2]) << 8 | 0xff; | |
140 | break; | |
141 | case ROP3_WHITENESS: | |
142 | filler = rgb_to_pixel32(s->vga.palette[3], s->vga.palette[4], | |
143 | s->vga.palette[5]) << 8 | 0xff; | |
144 | break; | |
145 | } | |
146 | ||
147 | DPRINTF("pixman_fill(%p, %d, %d, %d, %d, %d, %d, %x)\n", | |
148 | dst_bits, dst_stride, bpp, | |
149 | s->regs.dst_x, s->regs.dst_y, | |
150 | s->regs.dst_width, s->regs.dst_height, | |
151 | filler); | |
152 | end = s->vga.vram_ptr + s->vga.vram_size; | |
153 | if (dst_bits >= end || | |
349ebdd7 BZ |
154 | dst_bits + s->regs.dst_x + (s->regs.dst_y + s->regs.dst_height) * |
155 | dst_stride * sizeof(uint32_t) >= end) { | |
862b4a29 BZ |
156 | qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); |
157 | return; | |
158 | } | |
159 | pixman_fill((uint32_t *)dst_bits, dst_stride, bpp, | |
160 | s->regs.dst_x, s->regs.dst_y, | |
161 | s->regs.dst_width, s->regs.dst_height, | |
162 | filler); | |
163 | if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr && | |
164 | dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr + | |
165 | s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) { | |
166 | memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr + | |
167 | s->regs.dst_offset + | |
168 | s->regs.dst_y * surface_stride(ds), | |
169 | s->regs.dst_height * surface_stride(ds)); | |
170 | } | |
171 | s->regs.dst_y += s->regs.dst_height; | |
172 | break; | |
173 | } | |
174 | default: | |
175 | qemu_log_mask(LOG_UNIMP, "Unimplemented ati_2d blt op %x\n", | |
176 | (s->regs.dp_mix & GMC_ROP3_MASK) >> 16); | |
177 | } | |
178 | } |