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Commit | Line | Data |
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bbfff196 | 1 | #include "qemu/osdep.h" |
862b4a29 BZ |
2 | #include "ati_int.h" |
3 | ||
4 | #ifdef DEBUG_ATI | |
5 | struct ati_regdesc { | |
6 | const char *name; | |
7 | int num; | |
8 | }; | |
9 | ||
10 | static struct ati_regdesc ati_reg_names[] = { | |
11 | {"MM_INDEX", 0x0000}, | |
12 | {"MM_DATA", 0x0004}, | |
13 | {"CLOCK_CNTL_INDEX", 0x0008}, | |
14 | {"CLOCK_CNTL_DATA", 0x000c}, | |
15 | {"BIOS_0_SCRATCH", 0x0010}, | |
16 | {"BUS_CNTL", 0x0030}, | |
17 | {"BUS_CNTL1", 0x0034}, | |
18 | {"GEN_INT_CNTL", 0x0040}, | |
19 | {"CRTC_GEN_CNTL", 0x0050}, | |
20 | {"CRTC_EXT_CNTL", 0x0054}, | |
21 | {"DAC_CNTL", 0x0058}, | |
c82c7336 BZ |
22 | {"GPIO_VGA_DDC", 0x0060}, |
23 | {"GPIO_DVI_DDC", 0x0064}, | |
862b4a29 BZ |
24 | {"GPIO_MONID", 0x0068}, |
25 | {"I2C_CNTL_1", 0x0094}, | |
26 | {"PALETTE_INDEX", 0x00b0}, | |
27 | {"PALETTE_DATA", 0x00b4}, | |
28 | {"CNFG_CNTL", 0x00e0}, | |
29 | {"GEN_RESET_CNTL", 0x00f0}, | |
30 | {"CNFG_MEMSIZE", 0x00f8}, | |
1d8d4d86 BZ |
31 | {"CONFIG_APER_0_BASE", 0x0100}, |
32 | {"CONFIG_APER_1_BASE", 0x0104}, | |
33 | {"CONFIG_APER_SIZE", 0x0108}, | |
34 | {"CONFIG_REG_1_BASE", 0x010c}, | |
35 | {"CONFIG_REG_APER_SIZE", 0x0110}, | |
862b4a29 BZ |
36 | {"MEM_CNTL", 0x0140}, |
37 | {"MC_FB_LOCATION", 0x0148}, | |
38 | {"MC_AGP_LOCATION", 0x014C}, | |
39 | {"MC_STATUS", 0x0150}, | |
40 | {"MEM_POWER_MISC", 0x015c}, | |
41 | {"AGP_BASE", 0x0170}, | |
42 | {"AGP_CNTL", 0x0174}, | |
43 | {"AGP_APER_OFFSET", 0x0178}, | |
44 | {"PCI_GART_PAGE", 0x017c}, | |
45 | {"PC_NGUI_MODE", 0x0180}, | |
46 | {"PC_NGUI_CTLSTAT", 0x0184}, | |
47 | {"MPP_TB_CONFIG", 0x01C0}, | |
48 | {"MPP_GP_CONFIG", 0x01C8}, | |
49 | {"VIPH_CONTROL", 0x01D0}, | |
50 | {"CRTC_H_TOTAL_DISP", 0x0200}, | |
51 | {"CRTC_H_SYNC_STRT_WID", 0x0204}, | |
52 | {"CRTC_V_TOTAL_DISP", 0x0208}, | |
53 | {"CRTC_V_SYNC_STRT_WID", 0x020c}, | |
54 | {"CRTC_VLINE_CRNT_VLINE", 0x0210}, | |
55 | {"CRTC_CRNT_FRAME", 0x0214}, | |
56 | {"CRTC_GUI_TRIG_VLINE", 0x0218}, | |
57 | {"CRTC_OFFSET", 0x0224}, | |
58 | {"CRTC_OFFSET_CNTL", 0x0228}, | |
59 | {"CRTC_PITCH", 0x022c}, | |
60 | {"OVR_CLR", 0x0230}, | |
61 | {"OVR_WID_LEFT_RIGHT", 0x0234}, | |
62 | {"OVR_WID_TOP_BOTTOM", 0x0238}, | |
63 | {"CUR_OFFSET", 0x0260}, | |
64 | {"CUR_HORZ_VERT_POSN", 0x0264}, | |
65 | {"CUR_HORZ_VERT_OFF", 0x0268}, | |
66 | {"CUR_CLR0", 0x026c}, | |
67 | {"CUR_CLR1", 0x0270}, | |
68 | {"LVDS_GEN_CNTL", 0x02d0}, | |
69 | {"DDA_CONFIG", 0x02e0}, | |
70 | {"DDA_ON_OFF", 0x02e4}, | |
71 | {"VGA_DDA_CONFIG", 0x02e8}, | |
72 | {"VGA_DDA_ON_OFF", 0x02ec}, | |
73 | {"CRTC2_H_TOTAL_DISP", 0x0300}, | |
74 | {"CRTC2_H_SYNC_STRT_WID", 0x0304}, | |
75 | {"CRTC2_V_TOTAL_DISP", 0x0308}, | |
76 | {"CRTC2_V_SYNC_STRT_WID", 0x030c}, | |
77 | {"CRTC2_VLINE_CRNT_VLINE", 0x0310}, | |
78 | {"CRTC2_CRNT_FRAME", 0x0314}, | |
79 | {"CRTC2_GUI_TRIG_VLINE", 0x0318}, | |
80 | {"CRTC2_OFFSET", 0x0324}, | |
81 | {"CRTC2_OFFSET_CNTL", 0x0328}, | |
82 | {"CRTC2_PITCH", 0x032c}, | |
83 | {"DDA2_CONFIG", 0x03e0}, | |
84 | {"DDA2_ON_OFF", 0x03e4}, | |
85 | {"CRTC2_GEN_CNTL", 0x03f8}, | |
86 | {"CRTC2_STATUS", 0x03fc}, | |
87 | {"OV0_SCALE_CNTL", 0x0420}, | |
88 | {"SUBPIC_CNTL", 0x0540}, | |
89 | {"PM4_BUFFER_OFFSET", 0x0700}, | |
90 | {"PM4_BUFFER_CNTL", 0x0704}, | |
91 | {"PM4_BUFFER_WM_CNTL", 0x0708}, | |
92 | {"PM4_BUFFER_DL_RPTR_ADDR", 0x070c}, | |
93 | {"PM4_BUFFER_DL_RPTR", 0x0710}, | |
94 | {"PM4_BUFFER_DL_WPTR", 0x0714}, | |
95 | {"PM4_VC_FPU_SETUP", 0x071c}, | |
96 | {"PM4_FPU_CNTL", 0x0720}, | |
97 | {"PM4_VC_FORMAT", 0x0724}, | |
98 | {"PM4_VC_CNTL", 0x0728}, | |
99 | {"PM4_VC_I01", 0x072c}, | |
100 | {"PM4_VC_VLOFF", 0x0730}, | |
101 | {"PM4_VC_VLSIZE", 0x0734}, | |
102 | {"PM4_IW_INDOFF", 0x0738}, | |
103 | {"PM4_IW_INDSIZE", 0x073c}, | |
104 | {"PM4_FPU_FPX0", 0x0740}, | |
105 | {"PM4_FPU_FPY0", 0x0744}, | |
106 | {"PM4_FPU_FPX1", 0x0748}, | |
107 | {"PM4_FPU_FPY1", 0x074c}, | |
108 | {"PM4_FPU_FPX2", 0x0750}, | |
109 | {"PM4_FPU_FPY2", 0x0754}, | |
110 | {"PM4_FPU_FPY3", 0x0758}, | |
111 | {"PM4_FPU_FPY4", 0x075c}, | |
112 | {"PM4_FPU_FPY5", 0x0760}, | |
113 | {"PM4_FPU_FPY6", 0x0764}, | |
114 | {"PM4_FPU_FPR", 0x0768}, | |
115 | {"PM4_FPU_FPG", 0x076c}, | |
116 | {"PM4_FPU_FPB", 0x0770}, | |
117 | {"PM4_FPU_FPA", 0x0774}, | |
118 | {"PM4_FPU_INTXY0", 0x0780}, | |
119 | {"PM4_FPU_INTXY1", 0x0784}, | |
120 | {"PM4_FPU_INTXY2", 0x0788}, | |
121 | {"PM4_FPU_INTARGB", 0x078c}, | |
122 | {"PM4_FPU_FPTWICEAREA", 0x0790}, | |
123 | {"PM4_FPU_DMAJOR01", 0x0794}, | |
124 | {"PM4_FPU_DMAJOR12", 0x0798}, | |
125 | {"PM4_FPU_DMAJOR02", 0x079c}, | |
126 | {"PM4_FPU_STAT", 0x07a0}, | |
127 | {"PM4_STAT", 0x07b8}, | |
128 | {"PM4_TEST_CNTL", 0x07d0}, | |
129 | {"PM4_MICROCODE_ADDR", 0x07d4}, | |
130 | {"PM4_MICROCODE_RADDR", 0x07d8}, | |
131 | {"PM4_MICROCODE_DATAH", 0x07dc}, | |
132 | {"PM4_MICROCODE_DATAL", 0x07e0}, | |
133 | {"PM4_CMDFIFO_ADDR", 0x07e4}, | |
134 | {"PM4_CMDFIFO_DATAH", 0x07e8}, | |
135 | {"PM4_CMDFIFO_DATAL", 0x07ec}, | |
136 | {"PM4_BUFFER_ADDR", 0x07f0}, | |
137 | {"PM4_BUFFER_DATAH", 0x07f4}, | |
138 | {"PM4_BUFFER_DATAL", 0x07f8}, | |
139 | {"PM4_MICRO_CNTL", 0x07fc}, | |
140 | {"CAP0_TRIG_CNTL", 0x0950}, | |
141 | {"CAP1_TRIG_CNTL", 0x09c0}, | |
142 | {"RBBM_STATUS", 0x0e40}, | |
143 | {"PM4_FIFO_DATA_EVEN", 0x1000}, | |
144 | {"PM4_FIFO_DATA_ODD", 0x1004}, | |
145 | {"DST_OFFSET", 0x1404}, | |
146 | {"DST_PITCH", 0x1408}, | |
147 | {"DST_WIDTH", 0x140c}, | |
148 | {"DST_HEIGHT", 0x1410}, | |
149 | {"SRC_X", 0x1414}, | |
150 | {"SRC_Y", 0x1418}, | |
151 | {"DST_X", 0x141c}, | |
152 | {"DST_Y", 0x1420}, | |
153 | {"SRC_PITCH_OFFSET", 0x1428}, | |
154 | {"DST_PITCH_OFFSET", 0x142c}, | |
155 | {"SRC_Y_X", 0x1434}, | |
156 | {"DST_Y_X", 0x1438}, | |
157 | {"DST_HEIGHT_WIDTH", 0x143c}, | |
158 | {"DP_GUI_MASTER_CNTL", 0x146c}, | |
159 | {"BRUSH_SCALE", 0x1470}, | |
160 | {"BRUSH_Y_X", 0x1474}, | |
161 | {"DP_BRUSH_BKGD_CLR", 0x1478}, | |
162 | {"DP_BRUSH_FRGD_CLR", 0x147c}, | |
163 | {"DST_WIDTH_X", 0x1588}, | |
164 | {"DST_HEIGHT_WIDTH_8", 0x158c}, | |
165 | {"SRC_X_Y", 0x1590}, | |
166 | {"DST_X_Y", 0x1594}, | |
167 | {"DST_WIDTH_HEIGHT", 0x1598}, | |
168 | {"DST_WIDTH_X_INCY", 0x159c}, | |
169 | {"DST_HEIGHT_Y", 0x15a0}, | |
170 | {"DST_X_SUB", 0x15a4}, | |
171 | {"DST_Y_SUB", 0x15a8}, | |
172 | {"SRC_OFFSET", 0x15ac}, | |
173 | {"SRC_PITCH", 0x15b0}, | |
174 | {"DST_HEIGHT_WIDTH_BW", 0x15b4}, | |
175 | {"CLR_CMP_CNTL", 0x15c0}, | |
176 | {"CLR_CMP_CLR_SRC", 0x15c4}, | |
177 | {"CLR_CMP_CLR_DST", 0x15c8}, | |
178 | {"CLR_CMP_MASK", 0x15cc}, | |
179 | {"DP_SRC_FRGD_CLR", 0x15d8}, | |
180 | {"DP_SRC_BKGD_CLR", 0x15dc}, | |
181 | {"DST_BRES_ERR", 0x1628}, | |
182 | {"DST_BRES_INC", 0x162c}, | |
183 | {"DST_BRES_DEC", 0x1630}, | |
184 | {"DST_BRES_LNTH", 0x1634}, | |
185 | {"DST_BRES_LNTH_SUB", 0x1638}, | |
186 | {"SC_LEFT", 0x1640}, | |
187 | {"SC_RIGHT", 0x1644}, | |
188 | {"SC_TOP", 0x1648}, | |
189 | {"SC_BOTTOM", 0x164c}, | |
190 | {"SRC_SC_RIGHT", 0x1654}, | |
191 | {"SRC_SC_BOTTOM", 0x165c}, | |
192 | {"GUI_DEBUG0", 0x16a0}, | |
193 | {"GUI_DEBUG1", 0x16a4}, | |
194 | {"GUI_TIMEOUT", 0x16b0}, | |
195 | {"GUI_TIMEOUT0", 0x16b4}, | |
196 | {"GUI_TIMEOUT1", 0x16b8}, | |
197 | {"GUI_PROBE", 0x16bc}, | |
198 | {"DP_CNTL", 0x16c0}, | |
199 | {"DP_DATATYPE", 0x16c4}, | |
200 | {"DP_MIX", 0x16c8}, | |
201 | {"DP_WRITE_MASK", 0x16cc}, | |
202 | {"DP_CNTL_XDIR_YDIR_YMAJOR", 0x16d0}, | |
203 | {"DEFAULT_OFFSET", 0x16e0}, | |
204 | {"DEFAULT_PITCH", 0x16e4}, | |
205 | {"DEFAULT_SC_BOTTOM_RIGHT", 0x16e8}, | |
206 | {"SC_TOP_LEFT", 0x16ec}, | |
207 | {"SC_BOTTOM_RIGHT", 0x16f0}, | |
208 | {"SRC_SC_BOTTOM_RIGHT", 0x16f4}, | |
209 | {"DST_TILE", 0x1700}, | |
210 | {"WAIT_UNTIL", 0x1720}, | |
211 | {"CACHE_CNTL", 0x1724}, | |
212 | {"GUI_STAT", 0x1740}, | |
213 | {"PC_GUI_MODE", 0x1744}, | |
214 | {"PC_GUI_CTLSTAT", 0x1748}, | |
215 | {"PC_DEBUG_MODE", 0x1760}, | |
216 | {"BRES_DST_ERR_DEC", 0x1780}, | |
217 | {"TRAIL_BRES_T12_ERR_DEC", 0x1784}, | |
218 | {"TRAIL_BRES_T12_INC", 0x1788}, | |
219 | {"DP_T12_CNTL", 0x178c}, | |
220 | {"DST_BRES_T1_LNTH", 0x1790}, | |
221 | {"DST_BRES_T2_LNTH", 0x1794}, | |
222 | {"SCALE_SRC_HEIGHT_WIDTH", 0x1994}, | |
223 | {"SCALE_OFFSET_0", 0x1998}, | |
224 | {"SCALE_PITCH", 0x199c}, | |
225 | {"SCALE_X_INC", 0x19a0}, | |
226 | {"SCALE_Y_INC", 0x19a4}, | |
227 | {"SCALE_HACC", 0x19a8}, | |
228 | {"SCALE_VACC", 0x19ac}, | |
229 | {"SCALE_DST_X_Y", 0x19b0}, | |
230 | {"SCALE_DST_HEIGHT_WIDTH", 0x19b4}, | |
231 | {"SCALE_3D_CNTL", 0x1a00}, | |
232 | {"SCALE_3D_DATATYPE", 0x1a20}, | |
233 | {"SETUP_CNTL", 0x1bc4}, | |
234 | {"SOLID_COLOR", 0x1bc8}, | |
235 | {"WINDOW_XY_OFFSET", 0x1bcc}, | |
236 | {"DRAW_LINE_POINT", 0x1bd0}, | |
237 | {"SETUP_CNTL_PM4", 0x1bd4}, | |
238 | {"DST_PITCH_OFFSET_C", 0x1c80}, | |
239 | {"DP_GUI_MASTER_CNTL_C", 0x1c84}, | |
240 | {"SC_TOP_LEFT_C", 0x1c88}, | |
241 | {"SC_BOTTOM_RIGHT_C", 0x1c8c}, | |
242 | {"CLR_CMP_MASK_3D", 0x1A28}, | |
243 | {"MISC_3D_STATE_CNTL_REG", 0x1CA0}, | |
244 | {"MC_SRC1_CNTL", 0x19D8}, | |
245 | {"TEX_CNTL", 0x1800}, | |
246 | {"RAGE128_MPP_TB_CONFIG", 0x01c0}, | |
247 | {NULL, -1} | |
248 | }; | |
249 | ||
250 | const char *ati_reg_name(int num) | |
251 | { | |
252 | int i; | |
253 | ||
254 | num &= ~3; | |
255 | for (i = 0; ati_reg_names[i].name; i++) { | |
256 | if (ati_reg_names[i].num == num) { | |
257 | return ati_reg_names[i].name; | |
258 | } | |
259 | } | |
260 | return "unknown"; | |
261 | } | |
262 | #else | |
263 | const char *ati_reg_name(int num) | |
264 | { | |
265 | return ""; | |
266 | } | |
267 | #endif |