[mirror_qemu.git] / hw / display / cg3.c

/*
 * QEMU CG3 Frame buffer
 *
 * Copyright (c) 2012 Bob Breuer
 * Copyright (c) 2013 Mark Cave-Ayland
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "qemu/error-report.h"
#include "ui/console.h"
#include "hw/sysbus.h"
#include "hw/loader.h"

/* Change to 1 to enable debugging */
#define DEBUG_CG3 0

#define CG3_ROM_FILE  "QEMU,cgthree.bin"
#define FCODE_MAX_ROM_SIZE 0x10000

#define CG3_REG_SIZE            0x20

#define CG3_REG_BT458_ADDR      0x0
#define CG3_REG_BT458_COLMAP    0x4
#define CG3_REG_FBC_CTRL        0x10
#define CG3_REG_FBC_STATUS      0x11
#define CG3_REG_FBC_CURSTART    0x12
#define CG3_REG_FBC_CUREND      0x13
#define CG3_REG_FBC_VCTRL       0x14

/* Control register flags */
#define CG3_CR_ENABLE_INTS      0x80

/* Status register flags */
#define CG3_SR_PENDING_INT      0x80
#define CG3_SR_1152_900_76_B    0x60
#define CG3_SR_ID_COLOR         0x01

#define CG3_VRAM_SIZE 0x100000
#define CG3_VRAM_OFFSET 0x800000

#define DPRINTF(fmt, ...) do { \
    if (DEBUG_CG3) { \
        printf("CG3: " fmt , ## __VA_ARGS__); \
    } \
} while (0);

#define TYPE_CG3 "cgthree"
#define CG3(obj) OBJECT_CHECK(CG3State, (obj), TYPE_CG3)

typedef struct CG3State {
    SysBusDevice parent_obj;

    QemuConsole *con;
    qemu_irq irq;
    hwaddr prom_addr;
    MemoryRegion vram_mem;
    MemoryRegion rom;
    MemoryRegion reg;
    uint32_t vram_size;
    int full_update;
    uint8_t regs[16];
    uint8_t r[256], g[256], b[256];
    uint16_t width, height, depth;
    uint8_t dac_index, dac_state;
} CG3State;

static void cg3_update_display(void *opaque)
{
    CG3State *s = opaque;
    DisplaySurface *surface = qemu_console_surface(s->con);
    const uint8_t *pix;
    uint32_t *data;
    uint32_t dval;
    int x, y, y_start;
    unsigned int width, height;
    ram_addr_t page, page_min, page_max;

    if (surface_bits_per_pixel(surface) != 32) {
        return;
    }
    width = s->width;
    height = s->height;

    y_start = -1;
    page_min = -1;
    page_max = 0;
    page = 0;
    pix = memory_region_get_ram_ptr(&s->vram_mem);
    data = (uint32_t *)surface_data(surface);

    memory_region_sync_dirty_bitmap(&s->vram_mem);
    for (y = 0; y < height; y++) {
        int update = s->full_update;

        page = (y * width) & TARGET_PAGE_MASK;
        update |= memory_region_get_dirty(&s->vram_mem, page, page + width,
                                          DIRTY_MEMORY_VGA);
        if (update) {
            if (y_start < 0) {
                y_start = y;
            }
            if (page < page_min) {
                page_min = page;
            }
            if (page > page_max) {
                page_max = page;
            }

            for (x = 0; x < width; x++) {
                dval = *pix++;
                dval = (s->r[dval] << 16) | (s->g[dval] << 8) | s->b[dval];
                *data++ = dval;
            }
        } else {
            if (y_start >= 0) {
                dpy_gfx_update(s->con, 0, y_start, s->width, y - y_start);
                y_start = -1;
            }
            pix += width;
            data += width;
        }
    }
    s->full_update = 0;
    if (y_start >= 0) {
        dpy_gfx_update(s->con, 0, y_start, s->width, y - y_start);
    }
    if (page_max >= page_min) {
        memory_region_reset_dirty(&s->vram_mem,
                              page_min, page_max - page_min + TARGET_PAGE_SIZE,
                              DIRTY_MEMORY_VGA);
    }
    /* vsync interrupt? */
    if (s->regs[0] & CG3_CR_ENABLE_INTS) {
        s->regs[1] |= CG3_SR_PENDING_INT;
        qemu_irq_raise(s->irq);
    }
}

static void cg3_invalidate_display(void *opaque)
{
    CG3State *s = opaque;

    memory_region_set_dirty(&s->vram_mem, 0, CG3_VRAM_SIZE);
}

static uint64_t cg3_reg_read(void *opaque, hwaddr addr, unsigned size)
{
    CG3State *s = opaque;
    int val;

    switch (addr) {
    case CG3_REG_BT458_ADDR:
    case CG3_REG_BT458_COLMAP:
        val = 0;
        break;
    case CG3_REG_FBC_CTRL:
        val = s->regs[0];
        break;
    case CG3_REG_FBC_STATUS:
        /* monitor ID 6, board type = 1 (color) */
        val = s->regs[1] | CG3_SR_1152_900_76_B | CG3_SR_ID_COLOR;
        break;
    case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1:
        val = s->regs[addr - 0x10];
        break;
    default:
        qemu_log_mask(LOG_UNIMP,
                  "cg3: Unimplemented register read "
                  "reg 0x%" HWADDR_PRIx " size 0x%x\n",
                  addr, size);
        val = 0;
        break;
    }
    DPRINTF("read %02x from reg %" HWADDR_PRIx "\n", val, addr);
    return val;
}

static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val,
                          unsigned size)
{
    CG3State *s = opaque;
    uint8_t regval;
    int i;

    DPRINTF("write %" PRIx64 " to reg %" HWADDR_PRIx " size %d\n",
            val, addr, size);

    switch (addr) {
    case CG3_REG_BT458_ADDR:
        s->dac_index = val;
        s->dac_state = 0;
        break;
    case CG3_REG_BT458_COLMAP:
        /* This register can be written to as either a long word or a byte */
        if (size == 1) {
            val <<= 24;
        }

        for (i = 0; i < size; i++) {
            regval = val >> 24;

            switch (s->dac_state) {
            case 0:
                s->r[s->dac_index] = regval;
                s->dac_state++;
                break;
            case 1:
                s->g[s->dac_index] = regval;
                s->dac_state++;
                break;
            case 2:
                s->b[s->dac_index] = regval;
                /* Index autoincrement */
                s->dac_index = (s->dac_index + 1) & 0xff;
            default:
                s->dac_state = 0;
                break;
            }
            val <<= 8;
        }
        s->full_update = 1;
        break;
    case CG3_REG_FBC_CTRL:
        s->regs[0] = val;
        break;
    case CG3_REG_FBC_STATUS:
        if (s->regs[1] & CG3_SR_PENDING_INT) {
            /* clear interrupt */
            s->regs[1] &= ~CG3_SR_PENDING_INT;
            qemu_irq_lower(s->irq);
        }
        break;
    case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1:
        s->regs[addr - 0x10] = val;
        break;
    default:
        qemu_log_mask(LOG_UNIMP,
                  "cg3: Unimplemented register write "
                  "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n",
                  addr, size, val);
        break;
    }
}

static const MemoryRegionOps cg3_reg_ops = {
    .read = cg3_reg_read,
    .write = cg3_reg_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 1,
        .max_access_size = 4,
    },
};

static const GraphicHwOps cg3_ops = {
    .invalidate = cg3_invalidate_display,
    .gfx_update = cg3_update_display,
};

static void cg3_initfn(Object *obj)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    CG3State *s = CG3(obj);

    memory_region_init_ram(&s->rom, obj, "cg3.prom", FCODE_MAX_ROM_SIZE,
                           &error_fatal);
    memory_region_set_readonly(&s->rom, true);
    sysbus_init_mmio(sbd, &s->rom);

    memory_region_init_io(&s->reg, obj, &cg3_reg_ops, s, "cg3.reg",
                          CG3_REG_SIZE);
    sysbus_init_mmio(sbd, &s->reg);
}

static void cg3_realizefn(DeviceState *dev, Error **errp)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
    CG3State *s = CG3(dev);
    int ret;
    char *fcode_filename;

    /* FCode ROM */
    vmstate_register_ram_global(&s->rom);
    fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, CG3_ROM_FILE);
    if (fcode_filename) {
        ret = load_image_targphys(fcode_filename, s->prom_addr,
                                  FCODE_MAX_ROM_SIZE);
        g_free(fcode_filename);
        if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) {
            error_report("cg3: could not load prom '%s'", CG3_ROM_FILE);
        }
    }

    memory_region_init_ram(&s->vram_mem, NULL, "cg3.vram", s->vram_size,
                           &error_fatal);
    memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA);
    vmstate_register_ram_global(&s->vram_mem);
    sysbus_init_mmio(sbd, &s->vram_mem);

    sysbus_init_irq(sbd, &s->irq);

    s->con = graphic_console_init(DEVICE(dev), 0, &cg3_ops, s);
    qemu_console_resize(s->con, s->width, s->height);
}

static int vmstate_cg3_post_load(void *opaque, int version_id)
{
    CG3State *s = opaque;

    cg3_invalidate_display(s);

    return 0;
}

static const VMStateDescription vmstate_cg3 = {
    .name = "cg3",
    .version_id = 1,
    .minimum_version_id = 1,
    .post_load = vmstate_cg3_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT16(height, CG3State),
        VMSTATE_UINT16(width, CG3State),
        VMSTATE_UINT16(depth, CG3State),
        VMSTATE_BUFFER(r, CG3State),
        VMSTATE_BUFFER(g, CG3State),
        VMSTATE_BUFFER(b, CG3State),
        VMSTATE_UINT8(dac_index, CG3State),
        VMSTATE_UINT8(dac_state, CG3State),
        VMSTATE_END_OF_LIST()
    }
};

static void cg3_reset(DeviceState *d)
{
    CG3State *s = CG3(d);

    /* Initialize palette */
    memset(s->r, 0, 256);
    memset(s->g, 0, 256);
    memset(s->b, 0, 256);

    s->dac_state = 0;
    s->full_update = 1;
    qemu_irq_lower(s->irq);
}

static Property cg3_properties[] = {
    DEFINE_PROP_UINT32("vram-size",    CG3State, vram_size, -1),
    DEFINE_PROP_UINT16("width",        CG3State, width,     -1),
    DEFINE_PROP_UINT16("height",       CG3State, height,    -1),
    DEFINE_PROP_UINT16("depth",        CG3State, depth,     -1),
    DEFINE_PROP_UINT64("prom-addr",    CG3State, prom_addr, -1),
    DEFINE_PROP_END_OF_LIST(),
};

static void cg3_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = cg3_realizefn;
    dc->reset = cg3_reset;
    dc->vmsd = &vmstate_cg3;
    dc->props = cg3_properties;
}

static const TypeInfo cg3_info = {
    .name          = TYPE_CG3,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(CG3State),
    .instance_init = cg3_initfn,
    .class_init    = cg3_class_init,
};

static void cg3_register_types(void)
{
    type_register_static(&cg3_info);
}

type_init(cg3_register_types)
Commit	Line	Data
9eb08a43 MCA	1	/*
	2	* QEMU CG3 Frame buffer
	3	*
	4	* Copyright (c) 2012 Bob Breuer
	5	* Copyright (c) 2013 Mark Cave-Ayland
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25
47df5154	26	#include "qemu/osdep.h"
da34e65c	27	#include "qapi/error.h"
9eb08a43 MCA	28	#include "qemu-common.h"
	29	#include "qemu/error-report.h"
	30	#include "ui/console.h"
	31	#include "hw/sysbus.h"
	32	#include "hw/loader.h"
	33
	34	/* Change to 1 to enable debugging */
	35	#define DEBUG_CG3 0
	36
	37	#define CG3_ROM_FILE "QEMU,cgthree.bin"
	38	#define FCODE_MAX_ROM_SIZE 0x10000
	39
	40	#define CG3_REG_SIZE 0x20
	41
	42	#define CG3_REG_BT458_ADDR 0x0
	43	#define CG3_REG_BT458_COLMAP 0x4
	44	#define CG3_REG_FBC_CTRL 0x10
	45	#define CG3_REG_FBC_STATUS 0x11
	46	#define CG3_REG_FBC_CURSTART 0x12
	47	#define CG3_REG_FBC_CUREND 0x13
	48	#define CG3_REG_FBC_VCTRL 0x14
	49
	50	/* Control register flags */
	51	#define CG3_CR_ENABLE_INTS 0x80
	52
	53	/* Status register flags */
	54	#define CG3_SR_PENDING_INT 0x80
	55	#define CG3_SR_1152_900_76_B 0x60
	56	#define CG3_SR_ID_COLOR 0x01
	57
	58	#define CG3_VRAM_SIZE 0x100000
	59	#define CG3_VRAM_OFFSET 0x800000
	60
	61	#define DPRINTF(fmt, ...) do { \
	62	if (DEBUG_CG3) { \
	63	printf("CG3: " fmt , ## __VA_ARGS__); \
	64	} \
	65	} while (0);
	66
	67	#define TYPE_CG3 "cgthree"
	68	#define CG3(obj) OBJECT_CHECK(CG3State, (obj), TYPE_CG3)
	69
	70	typedef struct CG3State {
	71	SysBusDevice parent_obj;
	72
	73	QemuConsole *con;
	74	qemu_irq irq;
	75	hwaddr prom_addr;
	76	MemoryRegion vram_mem;
	77	MemoryRegion rom;
	78	MemoryRegion reg;
	79	uint32_t vram_size;
	80	int full_update;
	81	uint8_t regs[16];
	82	uint8_t r[256], g[256], b[256];
	83	uint16_t width, height, depth;
	84	uint8_t dac_index, dac_state;
	85	} CG3State;
	86
	87	static void cg3_update_display(void *opaque)
	88	{
	89	CG3State *s = opaque;
	90	DisplaySurface *surface = qemu_console_surface(s->con);
	91	const uint8_t *pix;
92	uint32_t *data;
93	uint32_t dval;
94	int x, y, y_start;
95	unsigned int width, height;
96	ram_addr_t page, page_min, page_max;
97
98	if (surface_bits_per_pixel(surface) != 32) {
99	return;
100	}
101	width = s->width;
102	height = s->height;
103
104	y_start = -1;
105	page_min = -1;
106	page_max = 0;
107	page = 0;
108	pix = memory_region_get_ram_ptr(&s->vram_mem);
109	data = (uint32_t *)surface_data(surface);
110
5299c0f2	111	memory_region_sync_dirty_bitmap(&s->vram_mem);
9eb08a43 MCA	112	for (y = 0; y < height; y++) {
	113	int update = s->full_update;
	114
	115	page = (y * width) & TARGET_PAGE_MASK;
	116	update \|= memory_region_get_dirty(&s->vram_mem, page, page + width,
	117	DIRTY_MEMORY_VGA);
	118	if (update) {
	119	if (y_start < 0) {
	120	y_start = y;
	121	}
	122	if (page < page_min) {
	123	page_min = page;
	124	}
	125	if (page > page_max) {
	126	page_max = page;
	127	}
	128
	129	for (x = 0; x < width; x++) {
	130	dval = *pix++;
	131	dval = (s->r[dval] << 16) \| (s->g[dval] << 8) \| s->b[dval];
	132	*data++ = dval;
	133	}
	134	} else {
	135	if (y_start >= 0) {
	136	dpy_gfx_update(s->con, 0, y_start, s->width, y - y_start);
	137	y_start = -1;
	138	}
	139	pix += width;
	140	data += width;
	141	}
	142	}
	143	s->full_update = 0;
	144	if (y_start >= 0) {
	145	dpy_gfx_update(s->con, 0, y_start, s->width, y - y_start);
	146	}
	147	if (page_max >= page_min) {
	148	memory_region_reset_dirty(&s->vram_mem,
	149	page_min, page_max - page_min + TARGET_PAGE_SIZE,
	150	DIRTY_MEMORY_VGA);
	151	}
	152	/* vsync interrupt? */
	153	if (s->regs[0] & CG3_CR_ENABLE_INTS) {
	154	s->regs[1] \|= CG3_SR_PENDING_INT;
	155	qemu_irq_raise(s->irq);
	156	}
	157	}
	158
	159	static void cg3_invalidate_display(void *opaque)
	160	{
	161	CG3State *s = opaque;
	162
	163	memory_region_set_dirty(&s->vram_mem, 0, CG3_VRAM_SIZE);
	164	}
	165
	166	static uint64_t cg3_reg_read(void *opaque, hwaddr addr, unsigned size)
	167	{
	168	CG3State *s = opaque;
	169	int val;
	170
	171	switch (addr) {
	172	case CG3_REG_BT458_ADDR:
	173	case CG3_REG_BT458_COLMAP:
	174	val = 0;
	175	break;
176	case CG3_REG_FBC_CTRL:
177	val = s->regs[0];
178	break;
179	case CG3_REG_FBC_STATUS:
180	/* monitor ID 6, board type = 1 (color) */
181	val = s->regs[1] \| CG3_SR_1152_900_76_B \| CG3_SR_ID_COLOR;
182	break;
366d4f7e	183	case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1:
9eb08a43 MCA	184	val = s->regs[addr - 0x10];
	185	break;
	186	default:
	187	qemu_log_mask(LOG_UNIMP,
	188	"cg3: Unimplemented register read "
	189	"reg 0x%" HWADDR_PRIx " size 0x%x\n",
	190	addr, size);
	191	val = 0;
	192	break;
	193	}
	194	DPRINTF("read %02x from reg %" HWADDR_PRIx "\n", val, addr);
	195	return val;
	196	}
	197
	198	static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val,
	199	unsigned size)
	200	{
	201	CG3State *s = opaque;
	202	uint8_t regval;
	203	int i;
	204
	205	DPRINTF("write %" PRIx64 " to reg %" HWADDR_PRIx " size %d\n",
	206	val, addr, size);
	207
	208	switch (addr) {
	209	case CG3_REG_BT458_ADDR:
	210	s->dac_index = val;
	211	s->dac_state = 0;
	212	break;
	213	case CG3_REG_BT458_COLMAP:
	214	/* This register can be written to as either a long word or a byte */
	215	if (size == 1) {
	216	val <<= 24;
	217	}
	218
	219	for (i = 0; i < size; i++) {
	220	regval = val >> 24;
	221
	222	switch (s->dac_state) {
	223	case 0:
	224	s->r[s->dac_index] = regval;
	225	s->dac_state++;
	226	break;
	227	case 1:
	228	s->g[s->dac_index] = regval;
	229	s->dac_state++;
	230	break;
	231	case 2:
	232	s->b[s->dac_index] = regval;
	233	/* Index autoincrement */
	234	s->dac_index = (s->dac_index + 1) & 0xff;
	235	default:
	236	s->dac_state = 0;
	237	break;
	238	}
	239	val <<= 8;
	240	}
	241	s->full_update = 1;
	242	break;
	243	case CG3_REG_FBC_CTRL:
	244	s->regs[0] = val;
	245	break;
	246	case CG3_REG_FBC_STATUS:
	247	if (s->regs[1] & CG3_SR_PENDING_INT) {
248	/* clear interrupt */
249	s->regs[1] &= ~CG3_SR_PENDING_INT;
250	qemu_irq_lower(s->irq);
251	}
252	break;
366d4f7e	253	case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1:
9eb08a43 MCA	254	s->regs[addr - 0x10] = val;
	255	break;
	256	default:
	257	qemu_log_mask(LOG_UNIMP,
	258	"cg3: Unimplemented register write "
	259	"reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n",
	260	addr, size, val);
	261	break;
	262	}
	263	}
	264
	265	static const MemoryRegionOps cg3_reg_ops = {
	266	.read = cg3_reg_read,
	267	.write = cg3_reg_write,
	268	.endianness = DEVICE_NATIVE_ENDIAN,
	269	.valid = {
	270	.min_access_size = 1,
	271	.max_access_size = 4,
	272	},
	273	};
	274
	275	static const GraphicHwOps cg3_ops = {
	276	.invalidate = cg3_invalidate_display,
	277	.gfx_update = cg3_update_display,
	278	};
	279
e09c49f4 MCA	280	static void cg3_initfn(Object *obj)
	281	{
	282	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
	283	CG3State *s = CG3(obj);
	284
81e0ab48	285	memory_region_init_ram(&s->rom, obj, "cg3.prom", FCODE_MAX_ROM_SIZE,
f8ed85ac	286	&error_fatal);
e09c49f4 MCA	287	memory_region_set_readonly(&s->rom, true);
	288	sysbus_init_mmio(sbd, &s->rom);
	289
81e0ab48	290	memory_region_init_io(&s->reg, obj, &cg3_reg_ops, s, "cg3.reg",
e09c49f4 MCA	291	CG3_REG_SIZE);
	292	sysbus_init_mmio(sbd, &s->reg);
	293	}
	294
9eb08a43 MCA	295	static void cg3_realizefn(DeviceState dev, Error *errp)
	296	{
	297	SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
	298	CG3State *s = CG3(dev);
	299	int ret;
	300	char *fcode_filename;
	301
	302	/* FCode ROM */
9eb08a43	303	vmstate_register_ram_global(&s->rom);
9eb08a43 MCA	304	fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, CG3_ROM_FILE);
	305	if (fcode_filename) {
	306	ret = load_image_targphys(fcode_filename, s->prom_addr,
	307	FCODE_MAX_ROM_SIZE);
22b2aeb8	308	g_free(fcode_filename);
9eb08a43 MCA	309	if (ret < 0 \|\| ret > FCODE_MAX_ROM_SIZE) {
	310	error_report("cg3: could not load prom '%s'", CG3_ROM_FILE);
	311	}
	312	}
	313
49946538	314	memory_region_init_ram(&s->vram_mem, NULL, "cg3.vram", s->vram_size,
f8ed85ac	315	&error_fatal);
74259ae5	316	memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA);
9eb08a43 MCA	317	vmstate_register_ram_global(&s->vram_mem);
	318	sysbus_init_mmio(sbd, &s->vram_mem);
	319
	320	sysbus_init_irq(sbd, &s->irq);
	321
5643706a	322	s->con = graphic_console_init(DEVICE(dev), 0, &cg3_ops, s);
9eb08a43 MCA	323	qemu_console_resize(s->con, s->width, s->height);
	324	}
	325
	326	static int vmstate_cg3_post_load(void *opaque, int version_id)
	327	{
	328	CG3State *s = opaque;
	329
	330	cg3_invalidate_display(s);
	331
	332	return 0;
	333	}
	334
	335	static const VMStateDescription vmstate_cg3 = {
	336	.name = "cg3",
	337	.version_id = 1,
	338	.minimum_version_id = 1,
	339	.post_load = vmstate_cg3_post_load,
35d08458	340	.fields = (VMStateField[]) {
9eb08a43 MCA	341	VMSTATE_UINT16(height, CG3State),
	342	VMSTATE_UINT16(width, CG3State),
	343	VMSTATE_UINT16(depth, CG3State),
	344	VMSTATE_BUFFER(r, CG3State),
	345	VMSTATE_BUFFER(g, CG3State),
	346	VMSTATE_BUFFER(b, CG3State),
	347	VMSTATE_UINT8(dac_index, CG3State),
	348	VMSTATE_UINT8(dac_state, CG3State),
	349	VMSTATE_END_OF_LIST()
	350	}
	351	};
	352
	353	static void cg3_reset(DeviceState *d)
	354	{
	355	CG3State *s = CG3(d);
	356
	357	/* Initialize palette */
	358	memset(s->r, 0, 256);
	359	memset(s->g, 0, 256);
	360	memset(s->b, 0, 256);
	361
	362	s->dac_state = 0;
	363	s->full_update = 1;
	364	qemu_irq_lower(s->irq);
	365	}
	366
	367	static Property cg3_properties[] = {
	368	DEFINE_PROP_UINT32("vram-size", CG3State, vram_size, -1),
	369	DEFINE_PROP_UINT16("width", CG3State, width, -1),
	370	DEFINE_PROP_UINT16("height", CG3State, height, -1),
	371	DEFINE_PROP_UINT16("depth", CG3State, depth, -1),
	372	DEFINE_PROP_UINT64("prom-addr", CG3State, prom_addr, -1),
	373	DEFINE_PROP_END_OF_LIST(),
	374	};
	375
	376	static void cg3_class_init(ObjectClass klass, void data)
	377	{
	378	DeviceClass *dc = DEVICE_CLASS(klass);
	379
	380	dc->realize = cg3_realizefn;
	381	dc->reset = cg3_reset;
	382	dc->vmsd = &vmstate_cg3;
	383	dc->props = cg3_properties;
	384	}
	385
	386	static const TypeInfo cg3_info = {
	387	.name = TYPE_CG3,
	388	.parent = TYPE_SYS_BUS_DEVICE,
	389	.instance_size = sizeof(CG3State),
e09c49f4	390	.instance_init = cg3_initfn,
9eb08a43 MCA	391	.class_init = cg3_class_init,
	392	};
	393
	394	static void cg3_register_types(void)
	395	{
	396	type_register_static(&cg3_info);
	397	}
	398
	399	type_init(cg3_register_types)