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vga: Simplify vga_draw_blank() a bit
[mirror_qemu.git] / hw / display / cirrus_vga.c
CommitLineData
e6e5ad80 1/*
aeb3c85f 2 * QEMU Cirrus CLGD 54xx VGA Emulator.
5fafdf24 3 *
e6e5ad80 4 * Copyright (c) 2004 Fabrice Bellard
aeb3c85f 5 * Copyright (c) 2004 Makoto Suzuki (suzu)
5fafdf24 6 *
e6e5ad80
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
aeb3c85f
FB		 25/*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
83c9f4ca
PB		 29#include "hw/hw.h"
30#include "hw/pci/pci.h"
28ecbaee 31#include "ui/console.h"
d3c2343a 32#include "ui/pixel_ops.h"
47b43a1f 33#include "vga_int.h"
83c9f4ca 34#include "hw/loader.h"
e6e5ad80 35
a5082316
FB		 36/*
37 * TODO:
ad81218e 38 * - destination write mask support not complete (bits 5..7)
a5082316
FB		 39 * - optimize linear mappings
40 * - optimize bitblt functions
41 */
42
e36f36e1 43//#define DEBUG_CIRRUS
a21ae81d 44//#define DEBUG_BITBLT
e36f36e1 45
e6e5ad80
FB		 46/***************************************
47 *
48 * definitions
49 *
50 ***************************************/
51
e6e5ad80
FB		 52// ID
53#define CIRRUS_ID_CLGD5422 (0x23<<2)
54#define CIRRUS_ID_CLGD5426 (0x24<<2)
55#define CIRRUS_ID_CLGD5424 (0x25<<2)
56#define CIRRUS_ID_CLGD5428 (0x26<<2)
57#define CIRRUS_ID_CLGD5430 (0x28<<2)
58#define CIRRUS_ID_CLGD5434 (0x2A<<2)
a21ae81d 59#define CIRRUS_ID_CLGD5436 (0x2B<<2)
e6e5ad80
FB		 60#define CIRRUS_ID_CLGD5446 (0x2E<<2)
61
62// sequencer 0x07
63#define CIRRUS_SR7_BPP_VGA 0x00
64#define CIRRUS_SR7_BPP_SVGA 0x01
65#define CIRRUS_SR7_BPP_MASK 0x0e
66#define CIRRUS_SR7_BPP_8 0x00
67#define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
68#define CIRRUS_SR7_BPP_24 0x04
69#define CIRRUS_SR7_BPP_16 0x06
70#define CIRRUS_SR7_BPP_32 0x08
71#define CIRRUS_SR7_ISAADDR_MASK 0xe0
72
73// sequencer 0x0f
74#define CIRRUS_MEMSIZE_512k 0x08
75#define CIRRUS_MEMSIZE_1M 0x10
76#define CIRRUS_MEMSIZE_2M 0x18
77#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
78
79// sequencer 0x12
80#define CIRRUS_CURSOR_SHOW 0x01
81#define CIRRUS_CURSOR_HIDDENPEL 0x02
82#define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
83
84// sequencer 0x17
85#define CIRRUS_BUSTYPE_VLBFAST 0x10
86#define CIRRUS_BUSTYPE_PCI 0x20
87#define CIRRUS_BUSTYPE_VLBSLOW 0x30
88#define CIRRUS_BUSTYPE_ISA 0x38
89#define CIRRUS_MMIO_ENABLE 0x04
90#define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
91#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
92
93// control 0x0b
94#define CIRRUS_BANKING_DUAL 0x01
95#define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
96
97// control 0x30
98#define CIRRUS_BLTMODE_BACKWARDS 0x01
99#define CIRRUS_BLTMODE_MEMSYSDEST 0x02
100#define CIRRUS_BLTMODE_MEMSYSSRC 0x04
101#define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
102#define CIRRUS_BLTMODE_PATTERNCOPY 0x40
103#define CIRRUS_BLTMODE_COLOREXPAND 0x80
104#define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
105#define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
106#define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
107#define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
108#define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
109
110// control 0x31
111#define CIRRUS_BLT_BUSY 0x01
112#define CIRRUS_BLT_START 0x02
113#define CIRRUS_BLT_RESET 0x04
114#define CIRRUS_BLT_FIFOUSED 0x10
a5082316 115#define CIRRUS_BLT_AUTOSTART 0x80
e6e5ad80
FB		 116
117// control 0x32
118#define CIRRUS_ROP_0 0x00
119#define CIRRUS_ROP_SRC_AND_DST 0x05
120#define CIRRUS_ROP_NOP 0x06
121#define CIRRUS_ROP_SRC_AND_NOTDST 0x09
122#define CIRRUS_ROP_NOTDST 0x0b
123#define CIRRUS_ROP_SRC 0x0d
124#define CIRRUS_ROP_1 0x0e
125#define CIRRUS_ROP_NOTSRC_AND_DST 0x50
126#define CIRRUS_ROP_SRC_XOR_DST 0x59
127#define CIRRUS_ROP_SRC_OR_DST 0x6d
128#define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
129#define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
130#define CIRRUS_ROP_SRC_OR_NOTDST 0xad
131#define CIRRUS_ROP_NOTSRC 0xd0
132#define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
133#define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
134
a5082316
FB		 135#define CIRRUS_ROP_NOP_INDEX 2
136#define CIRRUS_ROP_SRC_INDEX 5
137
a21ae81d 138// control 0x33
a5082316 139#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
4c8732d7 140#define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
a5082316 141#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
a21ae81d 142
e6e5ad80
FB		 143// memory-mapped IO
144#define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
145#define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
146#define CIRRUS_MMIO_BLTWIDTH 0x08 // word
147#define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
148#define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
149#define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
150#define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
151#define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
152#define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
153#define CIRRUS_MMIO_BLTMODE 0x18 // byte
154#define CIRRUS_MMIO_BLTROP 0x1a // byte
155#define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
156#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
157#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
158#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
159#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
160#define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
161#define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
162#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
163#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
164#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
165#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
166#define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
167#define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
168#define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
169#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
170#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
171#define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
172#define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
173
a21ae81d 174#define CIRRUS_PNPMMIO_SIZE 0x1000
e6e5ad80 175
b2eb849d
AJ		 176#define BLTUNSAFE(s) \
177 ( \
178 ( /* check dst is within bounds */ \
b2b183c2 179 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
b2eb849d 180 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
4e12cd94 181 (s)->vga.vram_size \
b2eb849d
AJ		 182 ) || \
183 ( /* check src is within bounds */ \
b2b183c2 184 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
b2eb849d 185 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
4e12cd94 186 (s)->vga.vram_size \
b2eb849d
AJ		 187 ) \
188 )
189
a5082316
FB		 190struct CirrusVGAState;
191typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
192 uint8_t * dst, const uint8_t * src,
e6e5ad80
FB		 193 int dstpitch, int srcpitch,
194 int bltwidth, int bltheight);
a5082316
FB		 195typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
196 uint8_t *dst, int dst_pitch, int width, int height);
e6e5ad80
FB		 197
198typedef struct CirrusVGAState {
4e12cd94 199 VGACommonState vga;
e6e5ad80 200
c75e6d8e 201 MemoryRegion cirrus_vga_io;
b1950430
AK		 202 MemoryRegion cirrus_linear_io;
203 MemoryRegion cirrus_linear_bitblt_io;
204 MemoryRegion cirrus_mmio_io;
205 MemoryRegion pci_bar;
206 bool linear_vram; /* vga.vram mapped over cirrus_linear_io */
207 MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */
208 MemoryRegion low_mem; /* always mapped, overridden by: */
7969d9ed 209 MemoryRegion cirrus_bank[2]; /* aliases at 0xa0000-0xb0000 */
e6e5ad80 210 uint32_t cirrus_addr_mask;
78e127ef 211 uint32_t linear_mmio_mask;
e6e5ad80
FB		 212 uint8_t cirrus_shadow_gr0;
213 uint8_t cirrus_shadow_gr1;
214 uint8_t cirrus_hidden_dac_lockindex;
215 uint8_t cirrus_hidden_dac_data;
216 uint32_t cirrus_bank_base[2];
217 uint32_t cirrus_bank_limit[2];
218 uint8_t cirrus_hidden_palette[48];
a5082316
FB		 219 uint32_t hw_cursor_x;
220 uint32_t hw_cursor_y;
e6e5ad80
FB		 221 int cirrus_blt_pixelwidth;
222 int cirrus_blt_width;
223 int cirrus_blt_height;
224 int cirrus_blt_dstpitch;
225 int cirrus_blt_srcpitch;
a5082316
FB		 226 uint32_t cirrus_blt_fgcol;
227 uint32_t cirrus_blt_bgcol;
e6e5ad80
FB		 228 uint32_t cirrus_blt_dstaddr;
229 uint32_t cirrus_blt_srcaddr;
230 uint8_t cirrus_blt_mode;
a5082316 231 uint8_t cirrus_blt_modeext;
e6e5ad80 232 cirrus_bitblt_rop_t cirrus_rop;
a5082316 233#define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
e6e5ad80
FB		 234 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
235 uint8_t *cirrus_srcptr;
236 uint8_t *cirrus_srcptr_end;
237 uint32_t cirrus_srccounter;
a5082316
FB		 238 /* hwcursor display state */
239 int last_hw_cursor_size;
240 int last_hw_cursor_x;
241 int last_hw_cursor_y;
242 int last_hw_cursor_y_start;
243 int last_hw_cursor_y_end;
78e127ef 244 int real_vram_size; /* XXX: suppress that */
4abc796d
BS		 245 int device_id;
246 int bustype;
e6e5ad80
FB		 247} CirrusVGAState;
248
249typedef struct PCICirrusVGAState {
250 PCIDevice dev;
251 CirrusVGAState cirrus_vga;
252} PCICirrusVGAState;
253
6d4c2f17
AF		 254#define TYPE_ISA_CIRRUS_VGA "isa-cirrus-vga"
255#define ISA_CIRRUS_VGA(obj) \
256 OBJECT_CHECK(ISACirrusVGAState, (obj), TYPE_ISA_CIRRUS_VGA)
257
3d402831 258typedef struct ISACirrusVGAState {
6d4c2f17
AF		 259 ISADevice parent_obj;
260
3d402831
BS		 261 CirrusVGAState cirrus_vga;
262} ISACirrusVGAState;
263
a5082316 264static uint8_t rop_to_index[256];
3b46e624 265
e6e5ad80
FB		 266/***************************************
267 *
268 * prototypes.
269 *
270 ***************************************/
271
272
8926b517
FB		 273static void cirrus_bitblt_reset(CirrusVGAState *s);
274static void cirrus_update_memory_access(CirrusVGAState *s);
e6e5ad80
FB		 275
276/***************************************
277 *
278 * raster operations
279 *
280 ***************************************/
281
a5082316
FB		 282static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
283 uint8_t *dst,const uint8_t *src,
284 int dstpitch,int srcpitch,
285 int bltwidth,int bltheight)
286{
e6e5ad80
FB		 287}
288
a5082316
FB		 289static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
290 uint8_t *dst,
291 int dstpitch, int bltwidth,int bltheight)
e6e5ad80 292{
a5082316 293}
e6e5ad80 294
a5082316 295#define ROP_NAME 0
8c78881f 296#define ROP_FN(d, s) 0
47b43a1f 297#include "cirrus_vga_rop.h"
e6e5ad80 298
a5082316 299#define ROP_NAME src_and_dst
8c78881f 300#define ROP_FN(d, s) (s) & (d)
47b43a1f 301#include "cirrus_vga_rop.h"
e6e5ad80 302
a5082316 303#define ROP_NAME src_and_notdst
8c78881f 304#define ROP_FN(d, s) (s) & (~(d))
47b43a1f 305#include "cirrus_vga_rop.h"
e6e5ad80 306
a5082316 307#define ROP_NAME notdst
8c78881f 308#define ROP_FN(d, s) ~(d)
47b43a1f 309#include "cirrus_vga_rop.h"
e6e5ad80 310
a5082316 311#define ROP_NAME src
8c78881f 312#define ROP_FN(d, s) s
47b43a1f 313#include "cirrus_vga_rop.h"
e6e5ad80 314
a5082316 315#define ROP_NAME 1
8c78881f 316#define ROP_FN(d, s) ~0
47b43a1f 317#include "cirrus_vga_rop.h"
a5082316
FB		 318
319#define ROP_NAME notsrc_and_dst
8c78881f 320#define ROP_FN(d, s) (~(s)) & (d)
47b43a1f 321#include "cirrus_vga_rop.h"
a5082316
FB		 322
323#define ROP_NAME src_xor_dst
8c78881f 324#define ROP_FN(d, s) (s) ^ (d)
47b43a1f 325#include "cirrus_vga_rop.h"
a5082316
FB		 326
327#define ROP_NAME src_or_dst
8c78881f 328#define ROP_FN(d, s) (s) | (d)
47b43a1f 329#include "cirrus_vga_rop.h"
a5082316
FB		 330
331#define ROP_NAME notsrc_or_notdst
8c78881f 332#define ROP_FN(d, s) (~(s)) | (~(d))
47b43a1f 333#include "cirrus_vga_rop.h"
a5082316
FB		 334
335#define ROP_NAME src_notxor_dst
8c78881f 336#define ROP_FN(d, s) ~((s) ^ (d))
47b43a1f 337#include "cirrus_vga_rop.h"
e6e5ad80 338
a5082316 339#define ROP_NAME src_or_notdst
8c78881f 340#define ROP_FN(d, s) (s) | (~(d))
47b43a1f 341#include "cirrus_vga_rop.h"
a5082316
FB		 342
343#define ROP_NAME notsrc
8c78881f 344#define ROP_FN(d, s) (~(s))
47b43a1f 345#include "cirrus_vga_rop.h"
a5082316
FB		 346
347#define ROP_NAME notsrc_or_dst
8c78881f 348#define ROP_FN(d, s) (~(s)) | (d)
47b43a1f 349#include "cirrus_vga_rop.h"
a5082316
FB		 350
351#define ROP_NAME notsrc_and_notdst
8c78881f 352#define ROP_FN(d, s) (~(s)) & (~(d))
47b43a1f 353#include "cirrus_vga_rop.h"
a5082316
FB		 354
355static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
356 cirrus_bitblt_rop_fwd_0,
357 cirrus_bitblt_rop_fwd_src_and_dst,
358 cirrus_bitblt_rop_nop,
359 cirrus_bitblt_rop_fwd_src_and_notdst,
360 cirrus_bitblt_rop_fwd_notdst,
361 cirrus_bitblt_rop_fwd_src,
362 cirrus_bitblt_rop_fwd_1,
363 cirrus_bitblt_rop_fwd_notsrc_and_dst,
364 cirrus_bitblt_rop_fwd_src_xor_dst,
365 cirrus_bitblt_rop_fwd_src_or_dst,
366 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
367 cirrus_bitblt_rop_fwd_src_notxor_dst,
368 cirrus_bitblt_rop_fwd_src_or_notdst,
369 cirrus_bitblt_rop_fwd_notsrc,
370 cirrus_bitblt_rop_fwd_notsrc_or_dst,
371 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
372};
373
374static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
375 cirrus_bitblt_rop_bkwd_0,
376 cirrus_bitblt_rop_bkwd_src_and_dst,
377 cirrus_bitblt_rop_nop,
378 cirrus_bitblt_rop_bkwd_src_and_notdst,
379 cirrus_bitblt_rop_bkwd_notdst,
380 cirrus_bitblt_rop_bkwd_src,
381 cirrus_bitblt_rop_bkwd_1,
382 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
383 cirrus_bitblt_rop_bkwd_src_xor_dst,
384 cirrus_bitblt_rop_bkwd_src_or_dst,
385 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
386 cirrus_bitblt_rop_bkwd_src_notxor_dst,
387 cirrus_bitblt_rop_bkwd_src_or_notdst,
388 cirrus_bitblt_rop_bkwd_notsrc,
389 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
390 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
391};
96cf2df8
TS		 392
393#define TRANSP_ROP(name) {\
394 name ## _8,\
395 name ## _16,\
396 }
397#define TRANSP_NOP(func) {\
398 func,\
399 func,\
400 }
401
402static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
403 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
404 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
405 TRANSP_NOP(cirrus_bitblt_rop_nop),
406 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
407 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
408 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
409 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
410 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
411 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
412 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
413 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
414 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
415 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
416 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
417 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
418 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
419};
420
421static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
422 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
423 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
424 TRANSP_NOP(cirrus_bitblt_rop_nop),
425 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
426 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
427 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
428 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
429 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
430 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
431 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
432 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
433 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
434 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
435 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
436 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
437 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
438};
439
a5082316
FB		 440#define ROP2(name) {\
441 name ## _8,\
442 name ## _16,\
443 name ## _24,\
444 name ## _32,\
445 }
446
447#define ROP_NOP2(func) {\
448 func,\
449 func,\
450 func,\
451 func,\
452 }
453
e69390ce
FB		 454static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
455 ROP2(cirrus_patternfill_0),
456 ROP2(cirrus_patternfill_src_and_dst),
457 ROP_NOP2(cirrus_bitblt_rop_nop),
458 ROP2(cirrus_patternfill_src_and_notdst),
459 ROP2(cirrus_patternfill_notdst),
460 ROP2(cirrus_patternfill_src),
461 ROP2(cirrus_patternfill_1),
462 ROP2(cirrus_patternfill_notsrc_and_dst),
463 ROP2(cirrus_patternfill_src_xor_dst),
464 ROP2(cirrus_patternfill_src_or_dst),
465 ROP2(cirrus_patternfill_notsrc_or_notdst),
466 ROP2(cirrus_patternfill_src_notxor_dst),
467 ROP2(cirrus_patternfill_src_or_notdst),
468 ROP2(cirrus_patternfill_notsrc),
469 ROP2(cirrus_patternfill_notsrc_or_dst),
470 ROP2(cirrus_patternfill_notsrc_and_notdst),
471};
472
a5082316
FB		 473static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
474 ROP2(cirrus_colorexpand_transp_0),
475 ROP2(cirrus_colorexpand_transp_src_and_dst),
476 ROP_NOP2(cirrus_bitblt_rop_nop),
477 ROP2(cirrus_colorexpand_transp_src_and_notdst),
478 ROP2(cirrus_colorexpand_transp_notdst),
479 ROP2(cirrus_colorexpand_transp_src),
480 ROP2(cirrus_colorexpand_transp_1),
481 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
482 ROP2(cirrus_colorexpand_transp_src_xor_dst),
483 ROP2(cirrus_colorexpand_transp_src_or_dst),
484 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
485 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
486 ROP2(cirrus_colorexpand_transp_src_or_notdst),
487 ROP2(cirrus_colorexpand_transp_notsrc),
488 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
489 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
490};
491
492static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
493 ROP2(cirrus_colorexpand_0),
494 ROP2(cirrus_colorexpand_src_and_dst),
495 ROP_NOP2(cirrus_bitblt_rop_nop),
496 ROP2(cirrus_colorexpand_src_and_notdst),
497 ROP2(cirrus_colorexpand_notdst),
498 ROP2(cirrus_colorexpand_src),
499 ROP2(cirrus_colorexpand_1),
500 ROP2(cirrus_colorexpand_notsrc_and_dst),
501 ROP2(cirrus_colorexpand_src_xor_dst),
502 ROP2(cirrus_colorexpand_src_or_dst),
503 ROP2(cirrus_colorexpand_notsrc_or_notdst),
504 ROP2(cirrus_colorexpand_src_notxor_dst),
505 ROP2(cirrus_colorexpand_src_or_notdst),
506 ROP2(cirrus_colorexpand_notsrc),
507 ROP2(cirrus_colorexpand_notsrc_or_dst),
508 ROP2(cirrus_colorexpand_notsrc_and_notdst),
509};
510
b30d4608
FB		 511static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
512 ROP2(cirrus_colorexpand_pattern_transp_0),
513 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
514 ROP_NOP2(cirrus_bitblt_rop_nop),
515 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
516 ROP2(cirrus_colorexpand_pattern_transp_notdst),
517 ROP2(cirrus_colorexpand_pattern_transp_src),
518 ROP2(cirrus_colorexpand_pattern_transp_1),
519 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
520 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
521 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
522 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
523 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
524 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
525 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
526 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
527 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
528};
529
530static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
531 ROP2(cirrus_colorexpand_pattern_0),
532 ROP2(cirrus_colorexpand_pattern_src_and_dst),
533 ROP_NOP2(cirrus_bitblt_rop_nop),
534 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
535 ROP2(cirrus_colorexpand_pattern_notdst),
536 ROP2(cirrus_colorexpand_pattern_src),
537 ROP2(cirrus_colorexpand_pattern_1),
538 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
539 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
540 ROP2(cirrus_colorexpand_pattern_src_or_dst),
541 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
542 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
543 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
544 ROP2(cirrus_colorexpand_pattern_notsrc),
545 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
546 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
547};
548
a5082316
FB		 549static const cirrus_fill_t cirrus_fill[16][4] = {
550 ROP2(cirrus_fill_0),
551 ROP2(cirrus_fill_src_and_dst),
552 ROP_NOP2(cirrus_bitblt_fill_nop),
553 ROP2(cirrus_fill_src_and_notdst),
554 ROP2(cirrus_fill_notdst),
555 ROP2(cirrus_fill_src),
556 ROP2(cirrus_fill_1),
557 ROP2(cirrus_fill_notsrc_and_dst),
558 ROP2(cirrus_fill_src_xor_dst),
559 ROP2(cirrus_fill_src_or_dst),
560 ROP2(cirrus_fill_notsrc_or_notdst),
561 ROP2(cirrus_fill_src_notxor_dst),
562 ROP2(cirrus_fill_src_or_notdst),
563 ROP2(cirrus_fill_notsrc),
564 ROP2(cirrus_fill_notsrc_or_dst),
565 ROP2(cirrus_fill_notsrc_and_notdst),
566};
567
568static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
e6e5ad80 569{
a5082316
FB		 570 unsigned int color;
571 switch (s->cirrus_blt_pixelwidth) {
572 case 1:
573 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
574 break;
575 case 2:
4e12cd94 576 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
a5082316
FB		 577 s->cirrus_blt_fgcol = le16_to_cpu(color);
578 break;
579 case 3:
5fafdf24 580 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
4e12cd94 581 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
a5082316
FB		 582 break;
583 default:
584 case 4:
4e12cd94
AK		 585 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
586 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
a5082316
FB		 587 s->cirrus_blt_fgcol = le32_to_cpu(color);
588 break;
e6e5ad80
FB		 589 }
590}
591
a5082316 592static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
e6e5ad80 593{
a5082316 594 unsigned int color;
e6e5ad80
FB		 595 switch (s->cirrus_blt_pixelwidth) {
596 case 1:
a5082316
FB		 597 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
598 break;
e6e5ad80 599 case 2:
4e12cd94 600 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
a5082316
FB		 601 s->cirrus_blt_bgcol = le16_to_cpu(color);
602 break;
e6e5ad80 603 case 3:
5fafdf24 604 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
4e12cd94 605 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
a5082316 606 break;
e6e5ad80 607 default:
a5082316 608 case 4:
4e12cd94
AK		 609 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
610 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
a5082316
FB		 611 s->cirrus_blt_bgcol = le32_to_cpu(color);
612 break;
e6e5ad80
FB		 613 }
614}
615
616static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
617 int off_pitch, int bytesperline,
618 int lines)
619{
620 int y;
621 int off_cur;
622 int off_cur_end;
623
624 for (y = 0; y < lines; y++) {
625 off_cur = off_begin;
b2eb849d 626 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
fd4aa979 627 memory_region_set_dirty(&s->vga.vram, off_cur, off_cur_end - off_cur);
e6e5ad80
FB		 628 off_begin += off_pitch;
629 }
630}
631
e6e5ad80
FB		 632static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
633 const uint8_t * src)
634{
e6e5ad80 635 uint8_t *dst;
e6e5ad80 636
4e12cd94 637 dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
b2eb849d
AJ		 638
639 if (BLTUNSAFE(s))
640 return 0;
641
e69390ce 642 (*s->cirrus_rop) (s, dst, src,
5fafdf24 643 s->cirrus_blt_dstpitch, 0,
e69390ce 644 s->cirrus_blt_width, s->cirrus_blt_height);
e6e5ad80 645 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
e69390ce
FB		 646 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
647 s->cirrus_blt_height);
e6e5ad80
FB		 648 return 1;
649}
650
a21ae81d
FB		 651/* fill */
652
a5082316 653static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
a21ae81d 654{
a5082316 655 cirrus_fill_t rop_func;
a21ae81d 656
b2eb849d
AJ		 657 if (BLTUNSAFE(s))
658 return 0;
a5082316 659 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
4e12cd94 660 rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
a5082316
FB		 661 s->cirrus_blt_dstpitch,
662 s->cirrus_blt_width, s->cirrus_blt_height);
a21ae81d
FB		 663 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
664 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
665 s->cirrus_blt_height);
666 cirrus_bitblt_reset(s);
667 return 1;
668}
669
e6e5ad80
FB		 670/***************************************
671 *
672 * bitblt (video-to-video)
673 *
674 ***************************************/
675
676static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
677{
678 return cirrus_bitblt_common_patterncopy(s,
4e12cd94 679 s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
b2eb849d 680 s->cirrus_addr_mask));
e6e5ad80
FB		 681}
682
24236869 683static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
e6e5ad80 684{
78935c4a
AJ		 685 int sx = 0, sy = 0;
686 int dx = 0, dy = 0;
687 int depth = 0;
24236869
FB		 688 int notify = 0;
689
92d675d1
AJ		 690 /* make sure to only copy if it's a plain copy ROP */
691 if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
692 *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {
24236869 693
92d675d1
AJ		 694 int width, height;
695
696 depth = s->vga.get_bpp(&s->vga) / 8;
697 s->vga.get_resolution(&s->vga, &width, &height);
698
699 /* extra x, y */
700 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
701 sy = (src / ABS(s->cirrus_blt_srcpitch));
702 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
703 dy = (dst / ABS(s->cirrus_blt_dstpitch));
24236869 704
92d675d1
AJ		 705 /* normalize width */
706 w /= depth;
24236869 707
92d675d1
AJ		 708 /* if we're doing a backward copy, we have to adjust
709 our x/y to be the upper left corner (instead of the lower
710 right corner) */
711 if (s->cirrus_blt_dstpitch < 0) {
712 sx -= (s->cirrus_blt_width / depth) - 1;
713 dx -= (s->cirrus_blt_width / depth) - 1;
714 sy -= s->cirrus_blt_height - 1;
715 dy -= s->cirrus_blt_height - 1;
716 }
717
718 /* are we in the visible portion of memory? */
719 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
720 (sx + w) <= width && (sy + h) <= height &&
721 (dx + w) <= width && (dy + h) <= height) {
722 notify = 1;
723 }
724 }
24236869
FB		 725
726 /* we have to flush all pending changes so that the copy
727 is generated at the appropriate moment in time */
728 if (notify)
1dbfa005 729 graphic_hw_update(s->vga.con);
24236869 730
4e12cd94 731 (*s->cirrus_rop) (s, s->vga.vram_ptr +
b2eb849d 732 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
4e12cd94 733 s->vga.vram_ptr +
b2eb849d 734 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
e6e5ad80
FB		 735 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
736 s->cirrus_blt_width, s->cirrus_blt_height);
24236869 737
c78f7137
GH		 738 if (notify) {
739 qemu_console_copy(s->vga.con,
38334f76
AZ		 740 sx, sy, dx, dy,
741 s->cirrus_blt_width / depth,
742 s->cirrus_blt_height);
c78f7137 743 }
24236869
FB		 744
745 /* we don't have to notify the display that this portion has
38334f76 746 changed since qemu_console_copy implies this */
24236869 747
31c05501
AL		 748 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
749 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
750 s->cirrus_blt_height);
24236869
FB		 751}
752
753static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
754{
65d35a09
AJ		 755 if (BLTUNSAFE(s))
756 return 0;
757
4e12cd94
AK		 758 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
759 s->cirrus_blt_srcaddr - s->vga.start_addr,
7d957bd8 760 s->cirrus_blt_width, s->cirrus_blt_height);
24236869 761
e6e5ad80
FB		 762 return 1;
763}
764
765/***************************************
766 *
767 * bitblt (cpu-to-video)
768 *
769 ***************************************/
770
e6e5ad80
FB		 771static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
772{
773 int copy_count;
a5082316 774 uint8_t *end_ptr;
3b46e624 775
e6e5ad80 776 if (s->cirrus_srccounter > 0) {
a5082316
FB		 777 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
778 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
779 the_end:
780 s->cirrus_srccounter = 0;
781 cirrus_bitblt_reset(s);
782 } else {
783 /* at least one scan line */
784 do {
4e12cd94 785 (*s->cirrus_rop)(s, s->vga.vram_ptr +
b2eb849d
AJ		 786 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
787 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
a5082316
FB		 788 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
789 s->cirrus_blt_width, 1);
790 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
791 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
792 if (s->cirrus_srccounter <= 0)
793 goto the_end;
66a0a2cb 794 /* more bytes than needed can be transferred because of
a5082316
FB		 795 word alignment, so we keep them for the next line */
796 /* XXX: keep alignment to speed up transfer */
797 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
798 copy_count = s->cirrus_srcptr_end - end_ptr;
799 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
800 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
801 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
802 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
803 }
e6e5ad80
FB		 804 }
805}
806
807/***************************************
808 *
809 * bitblt wrapper
810 *
811 ***************************************/
812
813static void cirrus_bitblt_reset(CirrusVGAState * s)
814{
f8b237af
AL		 815 int need_update;
816
4e12cd94 817 s->vga.gr[0x31] &=
e6e5ad80 818 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
f8b237af
AL		 819 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
820 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
e6e5ad80
FB		 821 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
822 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
823 s->cirrus_srccounter = 0;
f8b237af
AL		 824 if (!need_update)
825 return;
8926b517 826 cirrus_update_memory_access(s);
e6e5ad80
FB		 827}
828
829static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
830{
a5082316
FB		 831 int w;
832
e6e5ad80
FB		 833 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
834 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
835 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
836
837 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
838 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 839 s->cirrus_blt_srcpitch = 8;
e6e5ad80 840 } else {
b30d4608 841 /* XXX: check for 24 bpp */
a5082316 842 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
e6e5ad80 843 }
a5082316 844 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
e6e5ad80
FB		 845 } else {
846 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 847 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
5fafdf24 848 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
a5082316
FB		 849 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
850 else
851 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
e6e5ad80 852 } else {
c9c0eae8
FB		 853 /* always align input size to 32 bits */
854 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
e6e5ad80 855 }
a5082316 856 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
e6e5ad80 857 }
a5082316
FB		 858 s->cirrus_srcptr = s->cirrus_bltbuf;
859 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
8926b517 860 cirrus_update_memory_access(s);
e6e5ad80
FB		 861 return 1;
862}
863
864static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
865{
866 /* XXX */
a5082316 867#ifdef DEBUG_BITBLT
e6e5ad80
FB		 868 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
869#endif
870 return 0;
871}
872
873static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
874{
875 int ret;
876
877 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
878 ret = cirrus_bitblt_videotovideo_patterncopy(s);
879 } else {
880 ret = cirrus_bitblt_videotovideo_copy(s);
881 }
e6e5ad80
FB		 882 if (ret)
883 cirrus_bitblt_reset(s);
884 return ret;
885}
886
887static void cirrus_bitblt_start(CirrusVGAState * s)
888{
889 uint8_t blt_rop;
890
4e12cd94 891 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
a5082316 892
4e12cd94
AK		 893 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
894 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
895 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
896 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
e6e5ad80 897 s->cirrus_blt_dstaddr =
4e12cd94 898 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
e6e5ad80 899 s->cirrus_blt_srcaddr =
4e12cd94
AK		 900 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
901 s->cirrus_blt_mode = s->vga.gr[0x30];
902 s->cirrus_blt_modeext = s->vga.gr[0x33];
903 blt_rop = s->vga.gr[0x32];
e6e5ad80 904
a21ae81d 905#ifdef DEBUG_BITBLT
0b74ed78 906 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
5fafdf24 907 blt_rop,
a21ae81d 908 s->cirrus_blt_mode,
a5082316 909 s->cirrus_blt_modeext,
a21ae81d
FB		 910 s->cirrus_blt_width,
911 s->cirrus_blt_height,
912 s->cirrus_blt_dstpitch,
913 s->cirrus_blt_srcpitch,
914 s->cirrus_blt_dstaddr,
a5082316 915 s->cirrus_blt_srcaddr,
4e12cd94 916 s->vga.gr[0x2f]);
a21ae81d
FB		 917#endif
918
e6e5ad80
FB		 919 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
920 case CIRRUS_BLTMODE_PIXELWIDTH8:
921 s->cirrus_blt_pixelwidth = 1;
922 break;
923 case CIRRUS_BLTMODE_PIXELWIDTH16:
924 s->cirrus_blt_pixelwidth = 2;
925 break;
926 case CIRRUS_BLTMODE_PIXELWIDTH24:
927 s->cirrus_blt_pixelwidth = 3;
928 break;
929 case CIRRUS_BLTMODE_PIXELWIDTH32:
930 s->cirrus_blt_pixelwidth = 4;
931 break;
932 default:
a5082316 933#ifdef DEBUG_BITBLT
e6e5ad80
FB		 934 printf("cirrus: bitblt - pixel width is unknown\n");
935#endif
936 goto bitblt_ignore;
937 }
938 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
939
940 if ((s->
941 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
942 CIRRUS_BLTMODE_MEMSYSDEST))
943 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
a5082316 944#ifdef DEBUG_BITBLT
e6e5ad80
FB		 945 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
946#endif
947 goto bitblt_ignore;
948 }
949
a5082316 950 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
5fafdf24 951 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
a21ae81d 952 CIRRUS_BLTMODE_TRANSPARENTCOMP |
5fafdf24
TS		 953 CIRRUS_BLTMODE_PATTERNCOPY |
954 CIRRUS_BLTMODE_COLOREXPAND)) ==
a21ae81d 955 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
a5082316
FB		 956 cirrus_bitblt_fgcol(s);
957 cirrus_bitblt_solidfill(s, blt_rop);
e6e5ad80 958 } else {
5fafdf24
TS		 959 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
960 CIRRUS_BLTMODE_PATTERNCOPY)) ==
a5082316
FB		 961 CIRRUS_BLTMODE_COLOREXPAND) {
962
963 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
b30d4608 964 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
4c8732d7 965 cirrus_bitblt_bgcol(s);
b30d4608 966 else
4c8732d7 967 cirrus_bitblt_fgcol(s);
b30d4608 968 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
a5082316
FB		 969 } else {
970 cirrus_bitblt_fgcol(s);
971 cirrus_bitblt_bgcol(s);
972 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
973 }
e69390ce 974 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
b30d4608
FB		 975 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
976 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
977 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
978 cirrus_bitblt_bgcol(s);
979 else
980 cirrus_bitblt_fgcol(s);
981 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
982 } else {
983 cirrus_bitblt_fgcol(s);
984 cirrus_bitblt_bgcol(s);
985 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
986 }
987 } else {
988 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
989 }
a21ae81d 990 } else {
96cf2df8
TS		 991 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
992 if (s->cirrus_blt_pixelwidth > 2) {
993 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
994 goto bitblt_ignore;
995 }
996 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
997 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
998 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
999 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1000 } else {
1001 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1002 }
1003 } else {
1004 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1005 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1006 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1007 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1008 } else {
1009 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1010 }
1011 }
1012 }
a21ae81d
FB		 1013 // setup bitblt engine.
1014 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1015 if (!cirrus_bitblt_cputovideo(s))
1016 goto bitblt_ignore;
1017 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1018 if (!cirrus_bitblt_videotocpu(s))
1019 goto bitblt_ignore;
1020 } else {
1021 if (!cirrus_bitblt_videotovideo(s))
1022 goto bitblt_ignore;
1023 }
e6e5ad80 1024 }
e6e5ad80
FB		 1025 return;
1026 bitblt_ignore:;
1027 cirrus_bitblt_reset(s);
1028}
1029
1030static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1031{
1032 unsigned old_value;
1033
4e12cd94
AK		 1034 old_value = s->vga.gr[0x31];
1035 s->vga.gr[0x31] = reg_value;
e6e5ad80
FB		 1036
1037 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1038 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1039 cirrus_bitblt_reset(s);
1040 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1041 ((reg_value & CIRRUS_BLT_START) != 0)) {
e6e5ad80
FB		 1042 cirrus_bitblt_start(s);
1043 }
1044}
1045
1046
1047/***************************************
1048 *
1049 * basic parameters
1050 *
1051 ***************************************/
1052
a4a2f59c 1053static void cirrus_get_offsets(VGACommonState *s1,
83acc96b
FB		 1054 uint32_t *pline_offset,
1055 uint32_t *pstart_addr,
1056 uint32_t *pline_compare)
e6e5ad80 1057{
4e12cd94 1058 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
83acc96b 1059 uint32_t start_addr, line_offset, line_compare;
e6e5ad80 1060
4e12cd94
AK		 1061 line_offset = s->vga.cr[0x13]
1062 | ((s->vga.cr[0x1b] & 0x10) << 4);
e6e5ad80
FB		 1063 line_offset <<= 3;
1064 *pline_offset = line_offset;
1065
4e12cd94
AK		 1066 start_addr = (s->vga.cr[0x0c] << 8)
1067 | s->vga.cr[0x0d]
1068 | ((s->vga.cr[0x1b] & 0x01) << 16)
1069 | ((s->vga.cr[0x1b] & 0x0c) << 15)
1070 | ((s->vga.cr[0x1d] & 0x80) << 12);
e6e5ad80 1071 *pstart_addr = start_addr;
83acc96b 1072
4e12cd94
AK		 1073 line_compare = s->vga.cr[0x18] |
1074 ((s->vga.cr[0x07] & 0x10) << 4) |
1075 ((s->vga.cr[0x09] & 0x40) << 3);
83acc96b 1076 *pline_compare = line_compare;
e6e5ad80
FB		 1077}
1078
1079static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1080{
1081 uint32_t ret = 16;
1082
1083 switch (s->cirrus_hidden_dac_data & 0xf) {
1084 case 0:
1085 ret = 15;
1086 break; /* Sierra HiColor */
1087 case 1:
1088 ret = 16;
1089 break; /* XGA HiColor */
1090 default:
1091#ifdef DEBUG_CIRRUS
1092 printf("cirrus: invalid DAC value %x in 16bpp\n",
1093 (s->cirrus_hidden_dac_data & 0xf));
1094#endif
1095 ret = 15; /* XXX */
1096 break;
1097 }
1098 return ret;
1099}
1100
a4a2f59c 1101static int cirrus_get_bpp(VGACommonState *s1)
e6e5ad80 1102{
4e12cd94 1103 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
e6e5ad80
FB		 1104 uint32_t ret = 8;
1105
4e12cd94 1106 if ((s->vga.sr[0x07] & 0x01) != 0) {
e6e5ad80 1107 /* Cirrus SVGA */
4e12cd94 1108 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
e6e5ad80
FB		 1109 case CIRRUS_SR7_BPP_8:
1110 ret = 8;
1111 break;
1112 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1113 ret = cirrus_get_bpp16_depth(s);
1114 break;
1115 case CIRRUS_SR7_BPP_24:
1116 ret = 24;
1117 break;
1118 case CIRRUS_SR7_BPP_16:
1119 ret = cirrus_get_bpp16_depth(s);
1120 break;
1121 case CIRRUS_SR7_BPP_32:
1122 ret = 32;
1123 break;
1124 default:
1125#ifdef DEBUG_CIRRUS
4e12cd94 1126 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
e6e5ad80
FB		 1127#endif
1128 ret = 8;
1129 break;
1130 }
1131 } else {
1132 /* VGA */
aeb3c85f 1133 ret = 0;
e6e5ad80
FB		 1134 }
1135
1136 return ret;
1137}
1138
a4a2f59c 1139static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
78e127ef
FB		 1140{
1141 int width, height;
3b46e624 1142
78e127ef 1143 width = (s->cr[0x01] + 1) * 8;
5fafdf24
TS		 1144 height = s->cr[0x12] |
1145 ((s->cr[0x07] & 0x02) << 7) |
78e127ef
FB		 1146 ((s->cr[0x07] & 0x40) << 3);
1147 height = (height + 1);
1148 /* interlace support */
1149 if (s->cr[0x1a] & 0x01)
1150 height = height * 2;
1151 *pwidth = width;
1152 *pheight = height;
1153}
1154
e6e5ad80
FB		 1155/***************************************
1156 *
1157 * bank memory
1158 *
1159 ***************************************/
1160
1161static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1162{
1163 unsigned offset;
1164 unsigned limit;
1165
4e12cd94
AK		 1166 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */
1167 offset = s->vga.gr[0x09 + bank_index];
e6e5ad80 1168 else /* single bank */
4e12cd94 1169 offset = s->vga.gr[0x09];
e6e5ad80 1170
4e12cd94 1171 if ((s->vga.gr[0x0b] & 0x20) != 0)
e6e5ad80
FB		 1172 offset <<= 14;
1173 else
1174 offset <<= 12;
1175
e3a4e4b6 1176 if (s->real_vram_size <= offset)
e6e5ad80
FB		 1177 limit = 0;
1178 else
e3a4e4b6 1179 limit = s->real_vram_size - offset;
e6e5ad80 1180
4e12cd94 1181 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
e6e5ad80
FB		 1182 if (limit > 0x8000) {
1183 offset += 0x8000;
1184 limit -= 0x8000;
1185 } else {
1186 limit = 0;
1187 }
1188 }
1189
1190 if (limit > 0) {
1191 s->cirrus_bank_base[bank_index] = offset;
1192 s->cirrus_bank_limit[bank_index] = limit;
1193 } else {
1194 s->cirrus_bank_base[bank_index] = 0;
1195 s->cirrus_bank_limit[bank_index] = 0;
1196 }
1197}
1198
1199/***************************************
1200 *
1201 * I/O access between 0x3c4-0x3c5
1202 *
1203 ***************************************/
1204
8a82c322 1205static int cirrus_vga_read_sr(CirrusVGAState * s)
e6e5ad80 1206{
8a82c322 1207 switch (s->vga.sr_index) {
e6e5ad80
FB		 1208 case 0x00: // Standard VGA
1209 case 0x01: // Standard VGA
1210 case 0x02: // Standard VGA
1211 case 0x03: // Standard VGA
1212 case 0x04: // Standard VGA
8a82c322 1213 return s->vga.sr[s->vga.sr_index];
e6e5ad80 1214 case 0x06: // Unlock Cirrus extensions
8a82c322 1215 return s->vga.sr[s->vga.sr_index];
e6e5ad80
FB		 1216 case 0x10:
1217 case 0x30:
1218 case 0x50:
1219 case 0x70: // Graphics Cursor X
1220 case 0x90:
1221 case 0xb0:
1222 case 0xd0:
1223 case 0xf0: // Graphics Cursor X
8a82c322 1224 return s->vga.sr[0x10];
e6e5ad80
FB		 1225 case 0x11:
1226 case 0x31:
1227 case 0x51:
1228 case 0x71: // Graphics Cursor Y
1229 case 0x91:
1230 case 0xb1:
1231 case 0xd1:
a5082316 1232 case 0xf1: // Graphics Cursor Y
8a82c322 1233 return s->vga.sr[0x11];
aeb3c85f
FB		 1234 case 0x05: // ???
1235 case 0x07: // Extended Sequencer Mode
1236 case 0x08: // EEPROM Control
1237 case 0x09: // Scratch Register 0
1238 case 0x0a: // Scratch Register 1
1239 case 0x0b: // VCLK 0
1240 case 0x0c: // VCLK 1
1241 case 0x0d: // VCLK 2
1242 case 0x0e: // VCLK 3
1243 case 0x0f: // DRAM Control
e6e5ad80
FB		 1244 case 0x12: // Graphics Cursor Attribute
1245 case 0x13: // Graphics Cursor Pattern Address
1246 case 0x14: // Scratch Register 2
1247 case 0x15: // Scratch Register 3
1248 case 0x16: // Performance Tuning Register
1249 case 0x17: // Configuration Readback and Extended Control
1250 case 0x18: // Signature Generator Control
1251 case 0x19: // Signal Generator Result
1252 case 0x1a: // Signal Generator Result
1253 case 0x1b: // VCLK 0 Denominator & Post
1254 case 0x1c: // VCLK 1 Denominator & Post
1255 case 0x1d: // VCLK 2 Denominator & Post
1256 case 0x1e: // VCLK 3 Denominator & Post
1257 case 0x1f: // BIOS Write Enable and MCLK select
1258#ifdef DEBUG_CIRRUS
8a82c322 1259 printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
e6e5ad80 1260#endif
8a82c322 1261 return s->vga.sr[s->vga.sr_index];
e6e5ad80
FB		 1262 default:
1263#ifdef DEBUG_CIRRUS
8a82c322 1264 printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
e6e5ad80 1265#endif
8a82c322 1266 return 0xff;
e6e5ad80
FB		 1267 break;
1268 }
e6e5ad80
FB		 1269}
1270
31c63201 1271static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
e6e5ad80 1272{
31c63201 1273 switch (s->vga.sr_index) {
e6e5ad80
FB		 1274 case 0x00: // Standard VGA
1275 case 0x01: // Standard VGA
1276 case 0x02: // Standard VGA
1277 case 0x03: // Standard VGA
1278 case 0x04: // Standard VGA
31c63201
JQ		 1279 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
1280 if (s->vga.sr_index == 1)
1281 s->vga.update_retrace_info(&s->vga);
1282 break;
e6e5ad80 1283 case 0x06: // Unlock Cirrus extensions
31c63201
JQ		 1284 val &= 0x17;
1285 if (val == 0x12) {
1286 s->vga.sr[s->vga.sr_index] = 0x12;
e6e5ad80 1287 } else {
31c63201 1288 s->vga.sr[s->vga.sr_index] = 0x0f;
e6e5ad80
FB		 1289 }
1290 break;
1291 case 0x10:
1292 case 0x30:
1293 case 0x50:
1294 case 0x70: // Graphics Cursor X
1295 case 0x90:
1296 case 0xb0:
1297 case 0xd0:
1298 case 0xf0: // Graphics Cursor X
31c63201
JQ		 1299 s->vga.sr[0x10] = val;
1300 s->hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1301 break;
1302 case 0x11:
1303 case 0x31:
1304 case 0x51:
1305 case 0x71: // Graphics Cursor Y
1306 case 0x91:
1307 case 0xb1:
1308 case 0xd1:
1309 case 0xf1: // Graphics Cursor Y
31c63201
JQ		 1310 s->vga.sr[0x11] = val;
1311 s->hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1312 break;
1313 case 0x07: // Extended Sequencer Mode
2bec46dc 1314 cirrus_update_memory_access(s);
e6e5ad80
FB		 1315 case 0x08: // EEPROM Control
1316 case 0x09: // Scratch Register 0
1317 case 0x0a: // Scratch Register 1
1318 case 0x0b: // VCLK 0
1319 case 0x0c: // VCLK 1
1320 case 0x0d: // VCLK 2
1321 case 0x0e: // VCLK 3
1322 case 0x0f: // DRAM Control
1323 case 0x12: // Graphics Cursor Attribute
1324 case 0x13: // Graphics Cursor Pattern Address
1325 case 0x14: // Scratch Register 2
1326 case 0x15: // Scratch Register 3
1327 case 0x16: // Performance Tuning Register
e6e5ad80
FB		 1328 case 0x18: // Signature Generator Control
1329 case 0x19: // Signature Generator Result
1330 case 0x1a: // Signature Generator Result
1331 case 0x1b: // VCLK 0 Denominator & Post
1332 case 0x1c: // VCLK 1 Denominator & Post
1333 case 0x1d: // VCLK 2 Denominator & Post
1334 case 0x1e: // VCLK 3 Denominator & Post
1335 case 0x1f: // BIOS Write Enable and MCLK select
31c63201 1336 s->vga.sr[s->vga.sr_index] = val;
e6e5ad80
FB		 1337#ifdef DEBUG_CIRRUS
1338 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
31c63201 1339 s->vga.sr_index, val);
e6e5ad80
FB		 1340#endif
1341 break;
8926b517 1342 case 0x17: // Configuration Readback and Extended Control
31c63201
JQ		 1343 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
1344 | (val & 0xc7);
8926b517
FB		 1345 cirrus_update_memory_access(s);
1346 break;
e6e5ad80
FB		 1347 default:
1348#ifdef DEBUG_CIRRUS
31c63201
JQ		 1349 printf("cirrus: outport sr_index %02x, sr_value %02x\n",
1350 s->vga.sr_index, val);
e6e5ad80
FB		 1351#endif
1352 break;
1353 }
e6e5ad80
FB		 1354}
1355
1356/***************************************
1357 *
1358 * I/O access at 0x3c6
1359 *
1360 ***************************************/
1361
957c9db5 1362static int cirrus_read_hidden_dac(CirrusVGAState * s)
e6e5ad80 1363{
a21ae81d 1364 if (++s->cirrus_hidden_dac_lockindex == 5) {
957c9db5
JQ		 1365 s->cirrus_hidden_dac_lockindex = 0;
1366 return s->cirrus_hidden_dac_data;
e6e5ad80 1367 }
957c9db5 1368 return 0xff;
e6e5ad80
FB		 1369}
1370
1371static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1372{
1373 if (s->cirrus_hidden_dac_lockindex == 4) {
1374 s->cirrus_hidden_dac_data = reg_value;
a21ae81d 1375#if defined(DEBUG_CIRRUS)
e6e5ad80
FB		 1376 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1377#endif
1378 }
1379 s->cirrus_hidden_dac_lockindex = 0;
1380}
1381
1382/***************************************
1383 *
1384 * I/O access at 0x3c9
1385 *
1386 ***************************************/
1387
5deaeee3 1388static int cirrus_vga_read_palette(CirrusVGAState * s)
e6e5ad80 1389{
5deaeee3
JQ		 1390 int val;
1391
1392 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1393 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1394 s->vga.dac_sub_index];
1395 } else {
1396 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
1397 }
4e12cd94
AK		 1398 if (++s->vga.dac_sub_index == 3) {
1399 s->vga.dac_sub_index = 0;
1400 s->vga.dac_read_index++;
e6e5ad80 1401 }
5deaeee3 1402 return val;
e6e5ad80
FB		 1403}
1404
86948bb1 1405static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value)
e6e5ad80 1406{
4e12cd94
AK		 1407 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1408 if (++s->vga.dac_sub_index == 3) {
86948bb1
JQ		 1409 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1410 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1411 s->vga.dac_cache, 3);
1412 } else {
1413 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
1414 }
a5082316 1415 /* XXX update cursor */
4e12cd94
AK		 1416 s->vga.dac_sub_index = 0;
1417 s->vga.dac_write_index++;
e6e5ad80 1418 }
e6e5ad80
FB		 1419}
1420
1421/***************************************
1422 *
1423 * I/O access between 0x3ce-0x3cf
1424 *
1425 ***************************************/
1426
f705db9d 1427static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1428{
1429 switch (reg_index) {
aeb3c85f 1430 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
f705db9d 1431 return s->cirrus_shadow_gr0;
aeb3c85f 1432 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
f705db9d 1433 return s->cirrus_shadow_gr1;
e6e5ad80
FB		 1434 case 0x02: // Standard VGA
1435 case 0x03: // Standard VGA
1436 case 0x04: // Standard VGA
1437 case 0x06: // Standard VGA
1438 case 0x07: // Standard VGA
1439 case 0x08: // Standard VGA
f705db9d 1440 return s->vga.gr[s->vga.gr_index];
e6e5ad80
FB		 1441 case 0x05: // Standard VGA, Cirrus extended mode
1442 default:
1443 break;
1444 }
1445
1446 if (reg_index < 0x3a) {
f705db9d 1447 return s->vga.gr[reg_index];
e6e5ad80
FB		 1448 } else {
1449#ifdef DEBUG_CIRRUS
1450 printf("cirrus: inport gr_index %02x\n", reg_index);
1451#endif
f705db9d 1452 return 0xff;
e6e5ad80 1453 }
e6e5ad80
FB		 1454}
1455
22286bc6
JQ		 1456static void
1457cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
e6e5ad80 1458{
a5082316
FB		 1459#if defined(DEBUG_BITBLT) && 0
1460 printf("gr%02x: %02x\n", reg_index, reg_value);
1461#endif
e6e5ad80
FB		 1462 switch (reg_index) {
1463 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
f22f5b07 1464 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
aeb3c85f 1465 s->cirrus_shadow_gr0 = reg_value;
22286bc6 1466 break;
e6e5ad80 1467 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
f22f5b07 1468 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
aeb3c85f 1469 s->cirrus_shadow_gr1 = reg_value;
22286bc6 1470 break;
e6e5ad80
FB		 1471 case 0x02: // Standard VGA
1472 case 0x03: // Standard VGA
1473 case 0x04: // Standard VGA
1474 case 0x06: // Standard VGA
1475 case 0x07: // Standard VGA
1476 case 0x08: // Standard VGA
22286bc6
JQ		 1477 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1478 break;
e6e5ad80 1479 case 0x05: // Standard VGA, Cirrus extended mode
4e12cd94 1480 s->vga.gr[reg_index] = reg_value & 0x7f;
8926b517 1481 cirrus_update_memory_access(s);
e6e5ad80
FB		 1482 break;
1483 case 0x09: // bank offset #0
1484 case 0x0A: // bank offset #1
4e12cd94 1485 s->vga.gr[reg_index] = reg_value;
8926b517
FB		 1486 cirrus_update_bank_ptr(s, 0);
1487 cirrus_update_bank_ptr(s, 1);
2bec46dc 1488 cirrus_update_memory_access(s);
8926b517 1489 break;
e6e5ad80 1490 case 0x0B:
4e12cd94 1491 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1492 cirrus_update_bank_ptr(s, 0);
1493 cirrus_update_bank_ptr(s, 1);
8926b517 1494 cirrus_update_memory_access(s);
e6e5ad80
FB		 1495 break;
1496 case 0x10: // BGCOLOR 0x0000ff00
1497 case 0x11: // FGCOLOR 0x0000ff00
1498 case 0x12: // BGCOLOR 0x00ff0000
1499 case 0x13: // FGCOLOR 0x00ff0000
1500 case 0x14: // BGCOLOR 0xff000000
1501 case 0x15: // FGCOLOR 0xff000000
1502 case 0x20: // BLT WIDTH 0x0000ff
1503 case 0x22: // BLT HEIGHT 0x0000ff
1504 case 0x24: // BLT DEST PITCH 0x0000ff
1505 case 0x26: // BLT SRC PITCH 0x0000ff
1506 case 0x28: // BLT DEST ADDR 0x0000ff
1507 case 0x29: // BLT DEST ADDR 0x00ff00
1508 case 0x2c: // BLT SRC ADDR 0x0000ff
1509 case 0x2d: // BLT SRC ADDR 0x00ff00
a5082316 1510 case 0x2f: // BLT WRITEMASK
e6e5ad80
FB		 1511 case 0x30: // BLT MODE
1512 case 0x32: // RASTER OP
a21ae81d 1513 case 0x33: // BLT MODEEXT
e6e5ad80
FB		 1514 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1515 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1516 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1517 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
4e12cd94 1518 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1519 break;
1520 case 0x21: // BLT WIDTH 0x001f00
1521 case 0x23: // BLT HEIGHT 0x001f00
1522 case 0x25: // BLT DEST PITCH 0x001f00
1523 case 0x27: // BLT SRC PITCH 0x001f00
4e12cd94 1524 s->vga.gr[reg_index] = reg_value & 0x1f;
e6e5ad80
FB		 1525 break;
1526 case 0x2a: // BLT DEST ADDR 0x3f0000
4e12cd94 1527 s->vga.gr[reg_index] = reg_value & 0x3f;
a5082316 1528 /* if auto start mode, starts bit blt now */
4e12cd94 1529 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
a5082316
FB		 1530 cirrus_bitblt_start(s);
1531 }
1532 break;
e6e5ad80 1533 case 0x2e: // BLT SRC ADDR 0x3f0000
4e12cd94 1534 s->vga.gr[reg_index] = reg_value & 0x3f;
e6e5ad80
FB		 1535 break;
1536 case 0x31: // BLT STATUS/START
1537 cirrus_write_bitblt(s, reg_value);
1538 break;
1539 default:
1540#ifdef DEBUG_CIRRUS
1541 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1542 reg_value);
1543#endif
1544 break;
1545 }
e6e5ad80
FB		 1546}
1547
1548/***************************************
1549 *
1550 * I/O access between 0x3d4-0x3d5
1551 *
1552 ***************************************/
1553
b863d514 1554static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1555{
1556 switch (reg_index) {
1557 case 0x00: // Standard VGA
1558 case 0x01: // Standard VGA
1559 case 0x02: // Standard VGA
1560 case 0x03: // Standard VGA
1561 case 0x04: // Standard VGA
1562 case 0x05: // Standard VGA
1563 case 0x06: // Standard VGA
1564 case 0x07: // Standard VGA
1565 case 0x08: // Standard VGA
1566 case 0x09: // Standard VGA
1567 case 0x0a: // Standard VGA
1568 case 0x0b: // Standard VGA
1569 case 0x0c: // Standard VGA
1570 case 0x0d: // Standard VGA
1571 case 0x0e: // Standard VGA
1572 case 0x0f: // Standard VGA
1573 case 0x10: // Standard VGA
1574 case 0x11: // Standard VGA
1575 case 0x12: // Standard VGA
1576 case 0x13: // Standard VGA
1577 case 0x14: // Standard VGA
1578 case 0x15: // Standard VGA
1579 case 0x16: // Standard VGA
1580 case 0x17: // Standard VGA
1581 case 0x18: // Standard VGA
b863d514 1582 return s->vga.cr[s->vga.cr_index];
ca896ef3 1583 case 0x24: // Attribute Controller Toggle Readback (R)
b863d514 1584 return (s->vga.ar_flip_flop << 7);
e6e5ad80
FB		 1585 case 0x19: // Interlace End
1586 case 0x1a: // Miscellaneous Control
1587 case 0x1b: // Extended Display Control
1588 case 0x1c: // Sync Adjust and Genlock
1589 case 0x1d: // Overlay Extended Control
1590 case 0x22: // Graphics Data Latches Readback (R)
e6e5ad80
FB		 1591 case 0x25: // Part Status
1592 case 0x27: // Part ID (R)
b863d514 1593 return s->vga.cr[s->vga.cr_index];
e6e5ad80 1594 case 0x26: // Attribute Controller Index Readback (R)
b863d514 1595 return s->vga.ar_index & 0x3f;
e6e5ad80
FB		 1596 break;
1597 default:
1598#ifdef DEBUG_CIRRUS
1599 printf("cirrus: inport cr_index %02x\n", reg_index);
e6e5ad80 1600#endif
b863d514 1601 return 0xff;
e6e5ad80 1602 }
e6e5ad80
FB		 1603}
1604
4ec1ce04 1605static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
e6e5ad80 1606{
4ec1ce04 1607 switch (s->vga.cr_index) {
e6e5ad80
FB		 1608 case 0x00: // Standard VGA
1609 case 0x01: // Standard VGA
1610 case 0x02: // Standard VGA
1611 case 0x03: // Standard VGA
1612 case 0x04: // Standard VGA
1613 case 0x05: // Standard VGA
1614 case 0x06: // Standard VGA
1615 case 0x07: // Standard VGA
1616 case 0x08: // Standard VGA
1617 case 0x09: // Standard VGA
1618 case 0x0a: // Standard VGA
1619 case 0x0b: // Standard VGA
1620 case 0x0c: // Standard VGA
1621 case 0x0d: // Standard VGA
1622 case 0x0e: // Standard VGA
1623 case 0x0f: // Standard VGA
1624 case 0x10: // Standard VGA
1625 case 0x11: // Standard VGA
1626 case 0x12: // Standard VGA
1627 case 0x13: // Standard VGA
1628 case 0x14: // Standard VGA
1629 case 0x15: // Standard VGA
1630 case 0x16: // Standard VGA
1631 case 0x17: // Standard VGA
1632 case 0x18: // Standard VGA
4ec1ce04
JQ		 1633 /* handle CR0-7 protection */
1634 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
1635 /* can always write bit 4 of CR7 */
1636 if (s->vga.cr_index == 7)
1637 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10);
1638 return;
1639 }
1640 s->vga.cr[s->vga.cr_index] = reg_value;
1641 switch(s->vga.cr_index) {
1642 case 0x00:
1643 case 0x04:
1644 case 0x05:
1645 case 0x06:
1646 case 0x07:
1647 case 0x11:
1648 case 0x17:
1649 s->vga.update_retrace_info(&s->vga);
1650 break;
1651 }
1652 break;
e6e5ad80
FB		 1653 case 0x19: // Interlace End
1654 case 0x1a: // Miscellaneous Control
1655 case 0x1b: // Extended Display Control
1656 case 0x1c: // Sync Adjust and Genlock
ae184e4a 1657 case 0x1d: // Overlay Extended Control
4ec1ce04 1658 s->vga.cr[s->vga.cr_index] = reg_value;
e6e5ad80
FB		 1659#ifdef DEBUG_CIRRUS
1660 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
4ec1ce04 1661 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1662#endif
1663 break;
1664 case 0x22: // Graphics Data Latches Readback (R)
1665 case 0x24: // Attribute Controller Toggle Readback (R)
1666 case 0x26: // Attribute Controller Index Readback (R)
1667 case 0x27: // Part ID (R)
1668 break;
e6e5ad80
FB		 1669 case 0x25: // Part Status
1670 default:
1671#ifdef DEBUG_CIRRUS
4ec1ce04
JQ		 1672 printf("cirrus: outport cr_index %02x, cr_value %02x\n",
1673 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1674#endif
1675 break;
1676 }
e6e5ad80
FB		 1677}
1678
1679/***************************************
1680 *
1681 * memory-mapped I/O (bitblt)
1682 *
1683 ***************************************/
1684
1685static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1686{
1687 int value = 0xff;
1688
1689 switch (address) {
1690 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
f705db9d 1691 value = cirrus_vga_read_gr(s, 0x00);
e6e5ad80
FB		 1692 break;
1693 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
f705db9d 1694 value = cirrus_vga_read_gr(s, 0x10);
e6e5ad80
FB		 1695 break;
1696 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
f705db9d 1697 value = cirrus_vga_read_gr(s, 0x12);
e6e5ad80
FB		 1698 break;
1699 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
f705db9d 1700 value = cirrus_vga_read_gr(s, 0x14);
e6e5ad80
FB		 1701 break;
1702 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
f705db9d 1703 value = cirrus_vga_read_gr(s, 0x01);
e6e5ad80
FB		 1704 break;
1705 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
f705db9d 1706 value = cirrus_vga_read_gr(s, 0x11);
e6e5ad80
FB		 1707 break;
1708 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
f705db9d 1709 value = cirrus_vga_read_gr(s, 0x13);
e6e5ad80
FB		 1710 break;
1711 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
f705db9d 1712 value = cirrus_vga_read_gr(s, 0x15);
e6e5ad80
FB		 1713 break;
1714 case (CIRRUS_MMIO_BLTWIDTH + 0):
f705db9d 1715 value = cirrus_vga_read_gr(s, 0x20);
e6e5ad80
FB		 1716 break;
1717 case (CIRRUS_MMIO_BLTWIDTH + 1):
f705db9d 1718 value = cirrus_vga_read_gr(s, 0x21);
e6e5ad80
FB		 1719 break;
1720 case (CIRRUS_MMIO_BLTHEIGHT + 0):
f705db9d 1721 value = cirrus_vga_read_gr(s, 0x22);
e6e5ad80
FB		 1722 break;
1723 case (CIRRUS_MMIO_BLTHEIGHT + 1):
f705db9d 1724 value = cirrus_vga_read_gr(s, 0x23);
e6e5ad80
FB		 1725 break;
1726 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
f705db9d 1727 value = cirrus_vga_read_gr(s, 0x24);
e6e5ad80
FB		 1728 break;
1729 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
f705db9d 1730 value = cirrus_vga_read_gr(s, 0x25);
e6e5ad80
FB		 1731 break;
1732 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
f705db9d 1733 value = cirrus_vga_read_gr(s, 0x26);
e6e5ad80
FB		 1734 break;
1735 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
f705db9d 1736 value = cirrus_vga_read_gr(s, 0x27);
e6e5ad80
FB		 1737 break;
1738 case (CIRRUS_MMIO_BLTDESTADDR + 0):
f705db9d 1739 value = cirrus_vga_read_gr(s, 0x28);
e6e5ad80
FB		 1740 break;
1741 case (CIRRUS_MMIO_BLTDESTADDR + 1):
f705db9d 1742 value = cirrus_vga_read_gr(s, 0x29);
e6e5ad80
FB		 1743 break;
1744 case (CIRRUS_MMIO_BLTDESTADDR + 2):
f705db9d 1745 value = cirrus_vga_read_gr(s, 0x2a);
e6e5ad80
FB		 1746 break;
1747 case (CIRRUS_MMIO_BLTSRCADDR + 0):
f705db9d 1748 value = cirrus_vga_read_gr(s, 0x2c);
e6e5ad80
FB		 1749 break;
1750 case (CIRRUS_MMIO_BLTSRCADDR + 1):
f705db9d 1751 value = cirrus_vga_read_gr(s, 0x2d);
e6e5ad80
FB		 1752 break;
1753 case (CIRRUS_MMIO_BLTSRCADDR + 2):
f705db9d 1754 value = cirrus_vga_read_gr(s, 0x2e);
e6e5ad80
FB		 1755 break;
1756 case CIRRUS_MMIO_BLTWRITEMASK:
f705db9d 1757 value = cirrus_vga_read_gr(s, 0x2f);
e6e5ad80
FB		 1758 break;
1759 case CIRRUS_MMIO_BLTMODE:
f705db9d 1760 value = cirrus_vga_read_gr(s, 0x30);
e6e5ad80
FB		 1761 break;
1762 case CIRRUS_MMIO_BLTROP:
f705db9d 1763 value = cirrus_vga_read_gr(s, 0x32);
e6e5ad80 1764 break;
a21ae81d 1765 case CIRRUS_MMIO_BLTMODEEXT:
f705db9d 1766 value = cirrus_vga_read_gr(s, 0x33);
a21ae81d 1767 break;
e6e5ad80 1768 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
f705db9d 1769 value = cirrus_vga_read_gr(s, 0x34);
e6e5ad80
FB		 1770 break;
1771 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
f705db9d 1772 value = cirrus_vga_read_gr(s, 0x35);
e6e5ad80
FB		 1773 break;
1774 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
f705db9d 1775 value = cirrus_vga_read_gr(s, 0x38);
e6e5ad80
FB		 1776 break;
1777 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
f705db9d 1778 value = cirrus_vga_read_gr(s, 0x39);
e6e5ad80
FB		 1779 break;
1780 case CIRRUS_MMIO_BLTSTATUS:
f705db9d 1781 value = cirrus_vga_read_gr(s, 0x31);
e6e5ad80
FB		 1782 break;
1783 default:
1784#ifdef DEBUG_CIRRUS
1785 printf("cirrus: mmio read - address 0x%04x\n", address);
1786#endif
1787 break;
1788 }
1789
1790 return (uint8_t) value;
1791}
1792
1793static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1794 uint8_t value)
1795{
1796 switch (address) {
1797 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
22286bc6 1798 cirrus_vga_write_gr(s, 0x00, value);
e6e5ad80
FB		 1799 break;
1800 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
22286bc6 1801 cirrus_vga_write_gr(s, 0x10, value);
e6e5ad80
FB		 1802 break;
1803 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
22286bc6 1804 cirrus_vga_write_gr(s, 0x12, value);
e6e5ad80
FB		 1805 break;
1806 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
22286bc6 1807 cirrus_vga_write_gr(s, 0x14, value);
e6e5ad80
FB		 1808 break;
1809 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
22286bc6 1810 cirrus_vga_write_gr(s, 0x01, value);
e6e5ad80
FB		 1811 break;
1812 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
22286bc6 1813 cirrus_vga_write_gr(s, 0x11, value);
e6e5ad80
FB		 1814 break;
1815 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
22286bc6 1816 cirrus_vga_write_gr(s, 0x13, value);
e6e5ad80
FB		 1817 break;
1818 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
22286bc6 1819 cirrus_vga_write_gr(s, 0x15, value);
e6e5ad80
FB		 1820 break;
1821 case (CIRRUS_MMIO_BLTWIDTH + 0):
22286bc6 1822 cirrus_vga_write_gr(s, 0x20, value);
e6e5ad80
FB		 1823 break;
1824 case (CIRRUS_MMIO_BLTWIDTH + 1):
22286bc6 1825 cirrus_vga_write_gr(s, 0x21, value);
e6e5ad80
FB		 1826 break;
1827 case (CIRRUS_MMIO_BLTHEIGHT + 0):
22286bc6 1828 cirrus_vga_write_gr(s, 0x22, value);
e6e5ad80
FB		 1829 break;
1830 case (CIRRUS_MMIO_BLTHEIGHT + 1):
22286bc6 1831 cirrus_vga_write_gr(s, 0x23, value);
e6e5ad80
FB		 1832 break;
1833 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
22286bc6 1834 cirrus_vga_write_gr(s, 0x24, value);
e6e5ad80
FB		 1835 break;
1836 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
22286bc6 1837 cirrus_vga_write_gr(s, 0x25, value);
e6e5ad80
FB		 1838 break;
1839 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
22286bc6 1840 cirrus_vga_write_gr(s, 0x26, value);
e6e5ad80
FB		 1841 break;
1842 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
22286bc6 1843 cirrus_vga_write_gr(s, 0x27, value);
e6e5ad80
FB		 1844 break;
1845 case (CIRRUS_MMIO_BLTDESTADDR + 0):
22286bc6 1846 cirrus_vga_write_gr(s, 0x28, value);
e6e5ad80
FB		 1847 break;
1848 case (CIRRUS_MMIO_BLTDESTADDR + 1):
22286bc6 1849 cirrus_vga_write_gr(s, 0x29, value);
e6e5ad80
FB		 1850 break;
1851 case (CIRRUS_MMIO_BLTDESTADDR + 2):
22286bc6 1852 cirrus_vga_write_gr(s, 0x2a, value);
e6e5ad80
FB		 1853 break;
1854 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1855 /* ignored */
1856 break;
1857 case (CIRRUS_MMIO_BLTSRCADDR + 0):
22286bc6 1858 cirrus_vga_write_gr(s, 0x2c, value);
e6e5ad80
FB		 1859 break;
1860 case (CIRRUS_MMIO_BLTSRCADDR + 1):
22286bc6 1861 cirrus_vga_write_gr(s, 0x2d, value);
e6e5ad80
FB		 1862 break;
1863 case (CIRRUS_MMIO_BLTSRCADDR + 2):
22286bc6 1864 cirrus_vga_write_gr(s, 0x2e, value);
e6e5ad80
FB		 1865 break;
1866 case CIRRUS_MMIO_BLTWRITEMASK:
22286bc6 1867 cirrus_vga_write_gr(s, 0x2f, value);
e6e5ad80
FB		 1868 break;
1869 case CIRRUS_MMIO_BLTMODE:
22286bc6 1870 cirrus_vga_write_gr(s, 0x30, value);
e6e5ad80
FB		 1871 break;
1872 case CIRRUS_MMIO_BLTROP:
22286bc6 1873 cirrus_vga_write_gr(s, 0x32, value);
e6e5ad80 1874 break;
a21ae81d 1875 case CIRRUS_MMIO_BLTMODEEXT:
22286bc6 1876 cirrus_vga_write_gr(s, 0x33, value);
a21ae81d 1877 break;
e6e5ad80 1878 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
22286bc6 1879 cirrus_vga_write_gr(s, 0x34, value);
e6e5ad80
FB		 1880 break;
1881 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
22286bc6 1882 cirrus_vga_write_gr(s, 0x35, value);
e6e5ad80
FB		 1883 break;
1884 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
22286bc6 1885 cirrus_vga_write_gr(s, 0x38, value);
e6e5ad80
FB		 1886 break;
1887 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
22286bc6 1888 cirrus_vga_write_gr(s, 0x39, value);
e6e5ad80
FB		 1889 break;
1890 case CIRRUS_MMIO_BLTSTATUS:
22286bc6 1891 cirrus_vga_write_gr(s, 0x31, value);
e6e5ad80
FB		 1892 break;
1893 default:
1894#ifdef DEBUG_CIRRUS
1895 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1896 address, value);
1897#endif
1898 break;
1899 }
1900}
1901
e6e5ad80
FB		 1902/***************************************
1903 *
1904 * write mode 4/5
1905 *
e6e5ad80
FB		 1906 ***************************************/
1907
1908static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1909 unsigned mode,
1910 unsigned offset,
1911 uint32_t mem_value)
1912{
1913 int x;
1914 unsigned val = mem_value;
1915 uint8_t *dst;
1916
4e12cd94 1917 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1918 for (x = 0; x < 8; x++) {
1919 if (val & 0x80) {
0b74ed78 1920 *dst = s->cirrus_shadow_gr1;
e6e5ad80 1921 } else if (mode == 5) {
0b74ed78 1922 *dst = s->cirrus_shadow_gr0;
e6e5ad80
FB		 1923 }
1924 val <<= 1;
0b74ed78 1925 dst++;
e6e5ad80 1926 }
fd4aa979 1927 memory_region_set_dirty(&s->vga.vram, offset, 8);
e6e5ad80
FB		 1928}
1929
1930static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1931 unsigned mode,
1932 unsigned offset,
1933 uint32_t mem_value)
1934{
1935 int x;
1936 unsigned val = mem_value;
1937 uint8_t *dst;
1938
4e12cd94 1939 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1940 for (x = 0; x < 8; x++) {
1941 if (val & 0x80) {
0b74ed78 1942 *dst = s->cirrus_shadow_gr1;
4e12cd94 1943 *(dst + 1) = s->vga.gr[0x11];
e6e5ad80 1944 } else if (mode == 5) {
0b74ed78 1945 *dst = s->cirrus_shadow_gr0;
4e12cd94 1946 *(dst + 1) = s->vga.gr[0x10];
e6e5ad80
FB		 1947 }
1948 val <<= 1;
0b74ed78 1949 dst += 2;
e6e5ad80 1950 }
fd4aa979 1951 memory_region_set_dirty(&s->vga.vram, offset, 16);
e6e5ad80
FB		 1952}
1953
1954/***************************************
1955 *
1956 * memory access between 0xa0000-0xbffff
1957 *
1958 ***************************************/
1959
a815b166 1960static uint64_t cirrus_vga_mem_read(void *opaque,
a8170e5e 1961 hwaddr addr,
a815b166 1962 uint32_t size)
e6e5ad80
FB		 1963{
1964 CirrusVGAState *s = opaque;
1965 unsigned bank_index;
1966 unsigned bank_offset;
1967 uint32_t val;
1968
4e12cd94 1969 if ((s->vga.sr[0x07] & 0x01) == 0) {
b2a5e761 1970 return vga_mem_readb(&s->vga, addr);
e6e5ad80
FB		 1971 }
1972
1973 if (addr < 0x10000) {
1974 /* XXX handle bitblt */
1975 /* video memory */
1976 bank_index = addr >> 15;
1977 bank_offset = addr & 0x7fff;
1978 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
1979 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 1980 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 1981 bank_offset <<= 4;
4e12cd94 1982 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 1983 bank_offset <<= 3;
1984 }
1985 bank_offset &= s->cirrus_addr_mask;
4e12cd94 1986 val = *(s->vga.vram_ptr + bank_offset);
e6e5ad80
FB		 1987 } else
1988 val = 0xff;
1989 } else if (addr >= 0x18000 && addr < 0x18100) {
1990 /* memory-mapped I/O */
1991 val = 0xff;
4e12cd94 1992 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 1993 val = cirrus_mmio_blt_read(s, addr & 0xff);
1994 }
1995 } else {
1996 val = 0xff;
1997#ifdef DEBUG_CIRRUS
0bf9e31a 1998 printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
e6e5ad80
FB		 1999#endif
2000 }
2001 return val;
2002}
2003
a815b166 2004static void cirrus_vga_mem_write(void *opaque,
a8170e5e 2005 hwaddr addr,
a815b166
AK		 2006 uint64_t mem_value,
2007 uint32_t size)
e6e5ad80
FB		 2008{
2009 CirrusVGAState *s = opaque;
2010 unsigned bank_index;
2011 unsigned bank_offset;
2012 unsigned mode;
2013
4e12cd94 2014 if ((s->vga.sr[0x07] & 0x01) == 0) {
b2a5e761 2015 vga_mem_writeb(&s->vga, addr, mem_value);
e6e5ad80
FB		 2016 return;
2017 }
2018
2019 if (addr < 0x10000) {
2020 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2021 /* bitblt */
2022 *s->cirrus_srcptr++ = (uint8_t) mem_value;
a5082316 2023 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2024 cirrus_bitblt_cputovideo_next(s);
2025 }
2026 } else {
2027 /* video memory */
2028 bank_index = addr >> 15;
2029 bank_offset = addr & 0x7fff;
2030 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2031 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 2032 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2033 bank_offset <<= 4;
4e12cd94 2034 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2035 bank_offset <<= 3;
2036 }
2037 bank_offset &= s->cirrus_addr_mask;
4e12cd94
AK		 2038 mode = s->vga.gr[0x05] & 0x7;
2039 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2040 *(s->vga.vram_ptr + bank_offset) = mem_value;
fd4aa979
BS		 2041 memory_region_set_dirty(&s->vga.vram, bank_offset,
2042 sizeof(mem_value));
e6e5ad80 2043 } else {
4e12cd94 2044 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2045 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2046 bank_offset,
2047 mem_value);
2048 } else {
2049 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2050 bank_offset,
2051 mem_value);
2052 }
2053 }
2054 }
2055 }
2056 } else if (addr >= 0x18000 && addr < 0x18100) {
2057 /* memory-mapped I/O */
4e12cd94 2058 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 2059 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2060 }
2061 } else {
2062#ifdef DEBUG_CIRRUS
e8ee4b68 2063 printf("cirrus: mem_writeb " TARGET_FMT_plx " value 0x%02" PRIu64 "\n", addr,
08406b03 2064 mem_value);
e6e5ad80
FB		 2065#endif
2066 }
2067}
2068
b1950430
AK		 2069static const MemoryRegionOps cirrus_vga_mem_ops = {
2070 .read = cirrus_vga_mem_read,
2071 .write = cirrus_vga_mem_write,
2072 .endianness = DEVICE_LITTLE_ENDIAN,
a815b166
AK		 2073 .impl = {
2074 .min_access_size = 1,
2075 .max_access_size = 1,
2076 },
e6e5ad80
FB		 2077};
2078
a5082316
FB		 2079/***************************************
2080 *
2081 * hardware cursor
2082 *
2083 ***************************************/
2084
2085static inline void invalidate_cursor1(CirrusVGAState *s)
2086{
2087 if (s->last_hw_cursor_size) {
4e12cd94 2088 vga_invalidate_scanlines(&s->vga,
a5082316
FB		 2089 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2090 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2091 }
2092}
2093
2094static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2095{
2096 const uint8_t *src;
2097 uint32_t content;
2098 int y, y_min, y_max;
2099
4e12cd94
AK		 2100 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2101 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2102 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2103 y_min = 64;
2104 y_max = -1;
2105 for(y = 0; y < 64; y++) {
2106 content = ((uint32_t *)src)[0] |
2107 ((uint32_t *)src)[1] |
2108 ((uint32_t *)src)[2] |
2109 ((uint32_t *)src)[3];
2110 if (content) {
2111 if (y < y_min)
2112 y_min = y;
2113 if (y > y_max)
2114 y_max = y;
2115 }
2116 src += 16;
2117 }
2118 } else {
4e12cd94 2119 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316
FB		 2120 y_min = 32;
2121 y_max = -1;
2122 for(y = 0; y < 32; y++) {
2123 content = ((uint32_t *)src)[0] |
2124 ((uint32_t *)(src + 128))[0];
2125 if (content) {
2126 if (y < y_min)
2127 y_min = y;
2128 if (y > y_max)
2129 y_max = y;
2130 }
2131 src += 4;
2132 }
2133 }
2134 if (y_min > y_max) {
2135 s->last_hw_cursor_y_start = 0;
2136 s->last_hw_cursor_y_end = 0;
2137 } else {
2138 s->last_hw_cursor_y_start = y_min;
2139 s->last_hw_cursor_y_end = y_max + 1;
2140 }
2141}
2142
2143/* NOTE: we do not currently handle the cursor bitmap change, so we
2144 update the cursor only if it moves. */
a4a2f59c 2145static void cirrus_cursor_invalidate(VGACommonState *s1)
a5082316 2146{
4e12cd94 2147 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
a5082316
FB		 2148 int size;
2149
4e12cd94 2150 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
a5082316
FB		 2151 size = 0;
2152 } else {
4e12cd94 2153 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
a5082316
FB		 2154 size = 64;
2155 else
2156 size = 32;
2157 }
2158 /* invalidate last cursor and new cursor if any change */
2159 if (s->last_hw_cursor_size != size ||
2160 s->last_hw_cursor_x != s->hw_cursor_x ||
2161 s->last_hw_cursor_y != s->hw_cursor_y) {
2162
2163 invalidate_cursor1(s);
3b46e624 2164
a5082316
FB		 2165 s->last_hw_cursor_size = size;
2166 s->last_hw_cursor_x = s->hw_cursor_x;
2167 s->last_hw_cursor_y = s->hw_cursor_y;
2168 /* compute the real cursor min and max y */
2169 cirrus_cursor_compute_yrange(s);
2170 invalidate_cursor1(s);
2171 }
2172}
2173
94d7b483 2174#define DEPTH 8
47b43a1f 2175#include "cirrus_vga_template.h"
94d7b483
BS		 2176
2177#define DEPTH 16
47b43a1f 2178#include "cirrus_vga_template.h"
94d7b483
BS		 2179
2180#define DEPTH 32
47b43a1f 2181#include "cirrus_vga_template.h"
94d7b483 2182
a4a2f59c 2183static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
a5082316 2184{
4e12cd94 2185 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
c78f7137 2186 DisplaySurface *surface = qemu_console_surface(s->vga.con);
a5082316
FB		 2187 int w, h, bpp, x1, x2, poffset;
2188 unsigned int color0, color1;
2189 const uint8_t *palette, *src;
2190 uint32_t content;
3b46e624 2191
4e12cd94 2192 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
a5082316
FB		 2193 return;
2194 /* fast test to see if the cursor intersects with the scan line */
4e12cd94 2195 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
a5082316
FB		 2196 h = 64;
2197 } else {
2198 h = 32;
2199 }
2200 if (scr_y < s->hw_cursor_y ||
2201 scr_y >= (s->hw_cursor_y + h))
2202 return;
3b46e624 2203
4e12cd94
AK		 2204 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2205 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2206 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2207 src += (scr_y - s->hw_cursor_y) * 16;
2208 poffset = 8;
2209 content = ((uint32_t *)src)[0] |
2210 ((uint32_t *)src)[1] |
2211 ((uint32_t *)src)[2] |
2212 ((uint32_t *)src)[3];
2213 } else {
4e12cd94 2214 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316 2215 src += (scr_y - s->hw_cursor_y) * 4;
d3c2343a
BH		 2216
2217
a5082316
FB		 2218 poffset = 128;
2219 content = ((uint32_t *)src)[0] |
2220 ((uint32_t *)(src + 128))[0];
2221 }
2222 /* if nothing to draw, no need to continue */
2223 if (!content)
2224 return;
2225 w = h;
2226
2227 x1 = s->hw_cursor_x;
4e12cd94 2228 if (x1 >= s->vga.last_scr_width)
a5082316
FB		 2229 return;
2230 x2 = s->hw_cursor_x + w;
4e12cd94
AK		 2231 if (x2 > s->vga.last_scr_width)
2232 x2 = s->vga.last_scr_width;
a5082316
FB		 2233 w = x2 - x1;
2234 palette = s->cirrus_hidden_palette;
d3c2343a
BH		 2235 color0 = rgb_to_pixel32(c6_to_8(palette[0x0 * 3]),
2236 c6_to_8(palette[0x0 * 3 + 1]),
2237 c6_to_8(palette[0x0 * 3 + 2]));
2238 color1 = rgb_to_pixel32(c6_to_8(palette[0xf * 3]),
2239 c6_to_8(palette[0xf * 3 + 1]),
2240 c6_to_8(palette[0xf * 3 + 2]));
c78f7137 2241 bpp = surface_bytes_per_pixel(surface);
a5082316 2242 d1 += x1 * bpp;
c78f7137 2243 switch (surface_bits_per_pixel(surface)) {
a5082316
FB		 2244 default:
2245 break;
2246 case 8:
2247 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2248 break;
2249 case 15:
2250 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2251 break;
2252 case 16:
2253 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2254 break;
2255 case 32:
2256 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2257 break;
2258 }
2259}
2260
e6e5ad80
FB		 2261/***************************************
2262 *
2263 * LFB memory access
2264 *
2265 ***************************************/
2266
a8170e5e 2267static uint64_t cirrus_linear_read(void *opaque, hwaddr addr,
899adf81 2268 unsigned size)
e6e5ad80 2269{
e05587e8 2270 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2271 uint32_t ret;
2272
e6e5ad80
FB		 2273 addr &= s->cirrus_addr_mask;
2274
4e12cd94 2275 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2276 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2277 /* memory-mapped I/O */
2278 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2279 } else if (0) {
2280 /* XXX handle bitblt */
2281 ret = 0xff;
2282 } else {
2283 /* video memory */
4e12cd94 2284 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2285 addr <<= 4;
4e12cd94 2286 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2287 addr <<= 3;
2288 }
2289 addr &= s->cirrus_addr_mask;
4e12cd94 2290 ret = *(s->vga.vram_ptr + addr);
e6e5ad80
FB		 2291 }
2292
2293 return ret;
2294}
2295
a8170e5e 2296static void cirrus_linear_write(void *opaque, hwaddr addr,
899adf81 2297 uint64_t val, unsigned size)
e6e5ad80 2298{
e05587e8 2299 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2300 unsigned mode;
2301
2302 addr &= s->cirrus_addr_mask;
3b46e624 2303
4e12cd94 2304 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2305 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2306 /* memory-mapped I/O */
2307 cirrus_mmio_blt_write(s, addr & 0xff, val);
2308 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2309 /* bitblt */
2310 *s->cirrus_srcptr++ = (uint8_t) val;
a5082316 2311 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2312 cirrus_bitblt_cputovideo_next(s);
2313 }
2314 } else {
2315 /* video memory */
4e12cd94 2316 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2317 addr <<= 4;
4e12cd94 2318 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2319 addr <<= 3;
2320 }
2321 addr &= s->cirrus_addr_mask;
2322
4e12cd94
AK		 2323 mode = s->vga.gr[0x05] & 0x7;
2324 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2325 *(s->vga.vram_ptr + addr) = (uint8_t) val;
fd4aa979 2326 memory_region_set_dirty(&s->vga.vram, addr, 1);
e6e5ad80 2327 } else {
4e12cd94 2328 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2329 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2330 } else {
2331 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2332 }
2333 }
2334 }
2335}
2336
a5082316
FB		 2337/***************************************
2338 *
2339 * system to screen memory access
2340 *
2341 ***************************************/
2342
2343
4e56f089 2344static uint64_t cirrus_linear_bitblt_read(void *opaque,
a8170e5e 2345 hwaddr addr,
4e56f089 2346 unsigned size)
a5082316 2347{
4e56f089 2348 CirrusVGAState *s = opaque;
a5082316
FB		 2349 uint32_t ret;
2350
2351 /* XXX handle bitblt */
4e56f089 2352 (void)s;
a5082316
FB		 2353 ret = 0xff;
2354 return ret;
2355}
2356
4e56f089 2357static void cirrus_linear_bitblt_write(void *opaque,
a8170e5e 2358 hwaddr addr,
4e56f089
AK		 2359 uint64_t val,
2360 unsigned size)
a5082316 2361{
e05587e8 2362 CirrusVGAState *s = opaque;
a5082316
FB		 2363
2364 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2365 /* bitblt */
2366 *s->cirrus_srcptr++ = (uint8_t) val;
2367 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2368 cirrus_bitblt_cputovideo_next(s);
2369 }
2370 }
2371}
2372
b1950430
AK		 2373static const MemoryRegionOps cirrus_linear_bitblt_io_ops = {
2374 .read = cirrus_linear_bitblt_read,
2375 .write = cirrus_linear_bitblt_write,
2376 .endianness = DEVICE_LITTLE_ENDIAN,
4e56f089
AK		 2377 .impl = {
2378 .min_access_size = 1,
2379 .max_access_size = 1,
2380 },
a5082316
FB		 2381};
2382
b1950430
AK		 2383static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank)
2384{
7969d9ed
AK		 2385 MemoryRegion *mr = &s->cirrus_bank[bank];
2386 bool enabled = !(s->cirrus_srcptr != s->cirrus_srcptr_end)
4e12cd94
AK		 2387 && !((s->vga.sr[0x07] & 0x01) == 0)
2388 && !((s->vga.gr[0x0B] & 0x14) == 0x14)
7969d9ed
AK		 2389 && !(s->vga.gr[0x0B] & 0x02);
2390
2391 memory_region_set_enabled(mr, enabled);
2392 memory_region_set_alias_offset(mr, s->cirrus_bank_base[bank]);
b1950430 2393}
2bec46dc 2394
b1950430
AK		 2395static void map_linear_vram(CirrusVGAState *s)
2396{
4c08fd1e 2397 if (s->bustype == CIRRUS_BUSTYPE_PCI && !s->linear_vram) {
b1950430
AK		 2398 s->linear_vram = true;
2399 memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1);
2400 }
2401 map_linear_vram_bank(s, 0);
2402 map_linear_vram_bank(s, 1);
2bec46dc
AL		 2403}
2404
2405static void unmap_linear_vram(CirrusVGAState *s)
2406{
4c08fd1e 2407 if (s->bustype == CIRRUS_BUSTYPE_PCI && s->linear_vram) {
b1950430
AK		 2408 s->linear_vram = false;
2409 memory_region_del_subregion(&s->pci_bar, &s->vga.vram);
4516e45f 2410 }
7969d9ed
AK		 2411 memory_region_set_enabled(&s->cirrus_bank[0], false);
2412 memory_region_set_enabled(&s->cirrus_bank[1], false);
2bec46dc
AL		 2413}
2414
8926b517
FB		 2415/* Compute the memory access functions */
2416static void cirrus_update_memory_access(CirrusVGAState *s)
2417{
2418 unsigned mode;
2419
64c048f4 2420 memory_region_transaction_begin();
4e12cd94 2421 if ((s->vga.sr[0x17] & 0x44) == 0x44) {
8926b517
FB		 2422 goto generic_io;
2423 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2424 goto generic_io;
2425 } else {
4e12cd94 2426 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
8926b517 2427 goto generic_io;
4e12cd94 2428 } else if (s->vga.gr[0x0B] & 0x02) {
8926b517
FB		 2429 goto generic_io;
2430 }
3b46e624 2431
4e12cd94
AK		 2432 mode = s->vga.gr[0x05] & 0x7;
2433 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2bec46dc 2434 map_linear_vram(s);
8926b517
FB		 2435 } else {
2436 generic_io:
2bec46dc 2437 unmap_linear_vram(s);
8926b517
FB		 2438 }
2439 }
64c048f4 2440 memory_region_transaction_commit();
8926b517
FB		 2441}
2442
2443
e6e5ad80
FB		 2444/* I/O ports */
2445
c75e6d8e
JG		 2446static uint64_t cirrus_vga_ioport_read(void *opaque, hwaddr addr,
2447 unsigned size)
e6e5ad80 2448{
b6343073
JQ		 2449 CirrusVGAState *c = opaque;
2450 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2451 int val, index;
2452
c75e6d8e 2453 addr += 0x3b0;
bd8f2f5d 2454
b6343073 2455 if (vga_ioport_invalid(s, addr)) {
e6e5ad80
FB		 2456 val = 0xff;
2457 } else {
2458 switch (addr) {
2459 case 0x3c0:
b6343073
JQ		 2460 if (s->ar_flip_flop == 0) {
2461 val = s->ar_index;
e6e5ad80
FB		 2462 } else {
2463 val = 0;
2464 }
2465 break;
2466 case 0x3c1:
b6343073 2467 index = s->ar_index & 0x1f;
e6e5ad80 2468 if (index < 21)
b6343073 2469 val = s->ar[index];
e6e5ad80
FB		 2470 else
2471 val = 0;
2472 break;
2473 case 0x3c2:
b6343073 2474 val = s->st00;
e6e5ad80
FB		 2475 break;
2476 case 0x3c4:
b6343073 2477 val = s->sr_index;
e6e5ad80
FB		 2478 break;
2479 case 0x3c5:
8a82c322
JQ		 2480 val = cirrus_vga_read_sr(c);
2481 break;
e6e5ad80 2482#ifdef DEBUG_VGA_REG
b6343073 2483 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
e6e5ad80
FB		 2484#endif
2485 break;
2486 case 0x3c6:
957c9db5 2487 val = cirrus_read_hidden_dac(c);
e6e5ad80
FB		 2488 break;
2489 case 0x3c7:
b6343073 2490 val = s->dac_state;
e6e5ad80 2491 break;
ae184e4a 2492 case 0x3c8:
b6343073
JQ		 2493 val = s->dac_write_index;
2494 c->cirrus_hidden_dac_lockindex = 0;
ae184e4a
FB		 2495 break;
2496 case 0x3c9:
5deaeee3
JQ		 2497 val = cirrus_vga_read_palette(c);
2498 break;
e6e5ad80 2499 case 0x3ca:
b6343073 2500 val = s->fcr;
e6e5ad80
FB		 2501 break;
2502 case 0x3cc:
b6343073 2503 val = s->msr;
e6e5ad80
FB		 2504 break;
2505 case 0x3ce:
b6343073 2506 val = s->gr_index;
e6e5ad80
FB		 2507 break;
2508 case 0x3cf:
f705db9d 2509 val = cirrus_vga_read_gr(c, s->gr_index);
e6e5ad80 2510#ifdef DEBUG_VGA_REG
b6343073 2511 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
e6e5ad80
FB		 2512#endif
2513 break;
2514 case 0x3b4:
2515 case 0x3d4:
b6343073 2516 val = s->cr_index;
e6e5ad80
FB		 2517 break;
2518 case 0x3b5:
2519 case 0x3d5:
b863d514 2520 val = cirrus_vga_read_cr(c, s->cr_index);
e6e5ad80 2521#ifdef DEBUG_VGA_REG
b6343073 2522 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80
FB		 2523#endif
2524 break;
2525 case 0x3ba:
2526 case 0x3da:
2527 /* just toggle to fool polling */
b6343073
JQ		 2528 val = s->st01 = s->retrace(s);
2529 s->ar_flip_flop = 0;
e6e5ad80
FB		 2530 break;
2531 default:
2532 val = 0x00;
2533 break;
2534 }
2535 }
2536#if defined(DEBUG_VGA)
2537 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2538#endif
2539 return val;
2540}
2541
c75e6d8e
JG		 2542static void cirrus_vga_ioport_write(void *opaque, hwaddr addr, uint64_t val,
2543 unsigned size)
e6e5ad80 2544{
b6343073
JQ		 2545 CirrusVGAState *c = opaque;
2546 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2547 int index;
2548
c75e6d8e 2549 addr += 0x3b0;
bd8f2f5d 2550
e6e5ad80 2551 /* check port range access depending on color/monochrome mode */
b6343073 2552 if (vga_ioport_invalid(s, addr)) {
e6e5ad80 2553 return;
25a18cbd 2554 }
e6e5ad80
FB		 2555#ifdef DEBUG_VGA
2556 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2557#endif
2558
2559 switch (addr) {
2560 case 0x3c0:
b6343073 2561 if (s->ar_flip_flop == 0) {
e6e5ad80 2562 val &= 0x3f;
b6343073 2563 s->ar_index = val;
e6e5ad80 2564 } else {
b6343073 2565 index = s->ar_index & 0x1f;
e6e5ad80
FB		 2566 switch (index) {
2567 case 0x00 ... 0x0f:
b6343073 2568 s->ar[index] = val & 0x3f;
e6e5ad80
FB		 2569 break;
2570 case 0x10:
b6343073 2571 s->ar[index] = val & ~0x10;
e6e5ad80
FB		 2572 break;
2573 case 0x11:
b6343073 2574 s->ar[index] = val;
e6e5ad80
FB		 2575 break;
2576 case 0x12:
b6343073 2577 s->ar[index] = val & ~0xc0;
e6e5ad80
FB		 2578 break;
2579 case 0x13:
b6343073 2580 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2581 break;
2582 case 0x14:
b6343073 2583 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2584 break;
2585 default:
2586 break;
2587 }
2588 }
b6343073 2589 s->ar_flip_flop ^= 1;
e6e5ad80
FB		 2590 break;
2591 case 0x3c2:
b6343073
JQ		 2592 s->msr = val & ~0x10;
2593 s->update_retrace_info(s);
e6e5ad80
FB		 2594 break;
2595 case 0x3c4:
b6343073 2596 s->sr_index = val;
e6e5ad80
FB		 2597 break;
2598 case 0x3c5:
e6e5ad80 2599#ifdef DEBUG_VGA_REG
e8ee4b68 2600 printf("vga: write SR%x = 0x%02" PRIu64 "\n", s->sr_index, val);
e6e5ad80 2601#endif
31c63201
JQ		 2602 cirrus_vga_write_sr(c, val);
2603 break;
e6e5ad80 2604 case 0x3c6:
b6343073 2605 cirrus_write_hidden_dac(c, val);
e6e5ad80
FB		 2606 break;
2607 case 0x3c7:
b6343073
JQ		 2608 s->dac_read_index = val;
2609 s->dac_sub_index = 0;
2610 s->dac_state = 3;
e6e5ad80
FB		 2611 break;
2612 case 0x3c8:
b6343073
JQ		 2613 s->dac_write_index = val;
2614 s->dac_sub_index = 0;
2615 s->dac_state = 0;
e6e5ad80
FB		 2616 break;
2617 case 0x3c9:
86948bb1
JQ		 2618 cirrus_vga_write_palette(c, val);
2619 break;
e6e5ad80 2620 case 0x3ce:
b6343073 2621 s->gr_index = val;
e6e5ad80
FB		 2622 break;
2623 case 0x3cf:
e6e5ad80 2624#ifdef DEBUG_VGA_REG
e8ee4b68 2625 printf("vga: write GR%x = 0x%02" PRIu64 "\n", s->gr_index, val);
e6e5ad80 2626#endif
22286bc6 2627 cirrus_vga_write_gr(c, s->gr_index, val);
e6e5ad80
FB		 2628 break;
2629 case 0x3b4:
2630 case 0x3d4:
b6343073 2631 s->cr_index = val;
e6e5ad80
FB		 2632 break;
2633 case 0x3b5:
2634 case 0x3d5:
e6e5ad80 2635#ifdef DEBUG_VGA_REG
e8ee4b68 2636 printf("vga: write CR%x = 0x%02"PRIu64"\n", s->cr_index, val);
e6e5ad80 2637#endif
4ec1ce04 2638 cirrus_vga_write_cr(c, val);
e6e5ad80
FB		 2639 break;
2640 case 0x3ba:
2641 case 0x3da:
b6343073 2642 s->fcr = val & 0x10;
e6e5ad80
FB		 2643 break;
2644 }
2645}
2646
e36f36e1
FB		 2647/***************************************
2648 *
2649 * memory-mapped I/O access
2650 *
2651 ***************************************/
2652
a8170e5e 2653static uint64_t cirrus_mmio_read(void *opaque, hwaddr addr,
1e04d4d6 2654 unsigned size)
e36f36e1 2655{
e05587e8 2656 CirrusVGAState *s = opaque;
e36f36e1 2657
e36f36e1
FB		 2658 if (addr >= 0x100) {
2659 return cirrus_mmio_blt_read(s, addr - 0x100);
2660 } else {
c75e6d8e 2661 return cirrus_vga_ioport_read(s, addr + 0x10, size);
e36f36e1
FB		 2662 }
2663}
2664
a8170e5e 2665static void cirrus_mmio_write(void *opaque, hwaddr addr,
1e04d4d6 2666 uint64_t val, unsigned size)
e36f36e1 2667{
e05587e8 2668 CirrusVGAState *s = opaque;
e36f36e1 2669
e36f36e1
FB		 2670 if (addr >= 0x100) {
2671 cirrus_mmio_blt_write(s, addr - 0x100, val);
2672 } else {
c75e6d8e 2673 cirrus_vga_ioport_write(s, addr + 0x10, val, size);
e36f36e1
FB		 2674 }
2675}
2676
b1950430
AK		 2677static const MemoryRegionOps cirrus_mmio_io_ops = {
2678 .read = cirrus_mmio_read,
2679 .write = cirrus_mmio_write,
2680 .endianness = DEVICE_LITTLE_ENDIAN,
1e04d4d6
AK		 2681 .impl = {
2682 .min_access_size = 1,
2683 .max_access_size = 1,
2684 },
e36f36e1
FB		 2685};
2686
2c6ab832
FB		 2687/* load/save state */
2688
e59fb374 2689static int cirrus_post_load(void *opaque, int version_id)
2c6ab832
FB		 2690{
2691 CirrusVGAState *s = opaque;
2692
4e12cd94
AK		 2693 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
2694 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
2c6ab832 2695
2bec46dc 2696 cirrus_update_memory_access(s);
2c6ab832 2697 /* force refresh */
4e12cd94 2698 s->vga.graphic_mode = -1;
2c6ab832
FB		 2699 cirrus_update_bank_ptr(s, 0);
2700 cirrus_update_bank_ptr(s, 1);
2701 return 0;
2702}
2703
7e72abc3
JQ		 2704static const VMStateDescription vmstate_cirrus_vga = {
2705 .name = "cirrus_vga",
2706 .version_id = 2,
2707 .minimum_version_id = 1,
7e72abc3 2708 .post_load = cirrus_post_load,
d49805ae 2709 .fields = (VMStateField[]) {
7e72abc3
JQ		 2710 VMSTATE_UINT32(vga.latch, CirrusVGAState),
2711 VMSTATE_UINT8(vga.sr_index, CirrusVGAState),
2712 VMSTATE_BUFFER(vga.sr, CirrusVGAState),
2713 VMSTATE_UINT8(vga.gr_index, CirrusVGAState),
2714 VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState),
2715 VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState),
2716 VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
2717 VMSTATE_UINT8(vga.ar_index, CirrusVGAState),
2718 VMSTATE_BUFFER(vga.ar, CirrusVGAState),
2719 VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState),
2720 VMSTATE_UINT8(vga.cr_index, CirrusVGAState),
2721 VMSTATE_BUFFER(vga.cr, CirrusVGAState),
2722 VMSTATE_UINT8(vga.msr, CirrusVGAState),
2723 VMSTATE_UINT8(vga.fcr, CirrusVGAState),
2724 VMSTATE_UINT8(vga.st00, CirrusVGAState),
2725 VMSTATE_UINT8(vga.st01, CirrusVGAState),
2726 VMSTATE_UINT8(vga.dac_state, CirrusVGAState),
2727 VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState),
2728 VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState),
2729 VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState),
2730 VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState),
2731 VMSTATE_BUFFER(vga.palette, CirrusVGAState),
2732 VMSTATE_INT32(vga.bank_offset, CirrusVGAState),
2733 VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState),
2734 VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState),
2735 VMSTATE_UINT32(hw_cursor_x, CirrusVGAState),
2736 VMSTATE_UINT32(hw_cursor_y, CirrusVGAState),
2737 /* XXX: we do not save the bitblt state - we assume we do not save
2738 the state when the blitter is active */
2739 VMSTATE_END_OF_LIST()
4f335feb 2740 }
7e72abc3 2741};
4f335feb 2742
7e72abc3
JQ		 2743static const VMStateDescription vmstate_pci_cirrus_vga = {
2744 .name = "cirrus_vga",
2745 .version_id = 2,
2746 .minimum_version_id = 2,
d49805ae 2747 .fields = (VMStateField[]) {
7e72abc3
JQ		 2748 VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState),
2749 VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
2750 vmstate_cirrus_vga, CirrusVGAState),
2751 VMSTATE_END_OF_LIST()
2752 }
2753};
4f335feb 2754
e6e5ad80
FB		 2755/***************************************
2756 *
2757 * initialize
2758 *
2759 ***************************************/
2760
4abc796d 2761static void cirrus_reset(void *opaque)
e6e5ad80 2762{
4abc796d 2763 CirrusVGAState *s = opaque;
e6e5ad80 2764
03a3e7ba 2765 vga_common_reset(&s->vga);
ee50c6bc 2766 unmap_linear_vram(s);
4e12cd94 2767 s->vga.sr[0x06] = 0x0f;
4abc796d 2768 if (s->device_id == CIRRUS_ID_CLGD5446) {
78e127ef 2769 /* 4MB 64 bit memory config, always PCI */
4e12cd94
AK		 2770 s->vga.sr[0x1F] = 0x2d; // MemClock
2771 s->vga.gr[0x18] = 0x0f; // fastest memory configuration
2772 s->vga.sr[0x0f] = 0x98;
2773 s->vga.sr[0x17] = 0x20;
2774 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
78e127ef 2775 } else {
4e12cd94
AK		 2776 s->vga.sr[0x1F] = 0x22; // MemClock
2777 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
2778 s->vga.sr[0x17] = s->bustype;
2779 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
78e127ef 2780 }
4e12cd94 2781 s->vga.cr[0x27] = s->device_id;
e6e5ad80
FB		 2782
2783 s->cirrus_hidden_dac_lockindex = 5;
2784 s->cirrus_hidden_dac_data = 0;
4abc796d
BS		 2785}
2786
b1950430
AK		 2787static const MemoryRegionOps cirrus_linear_io_ops = {
2788 .read = cirrus_linear_read,
2789 .write = cirrus_linear_write,
2790 .endianness = DEVICE_LITTLE_ENDIAN,
899adf81
AK		 2791 .impl = {
2792 .min_access_size = 1,
2793 .max_access_size = 1,
2794 },
b1950430
AK		 2795};
2796
c75e6d8e
JG		 2797static const MemoryRegionOps cirrus_vga_io_ops = {
2798 .read = cirrus_vga_ioport_read,
2799 .write = cirrus_vga_ioport_write,
2800 .endianness = DEVICE_LITTLE_ENDIAN,
2801 .impl = {
2802 .min_access_size = 1,
2803 .max_access_size = 1,
2804 },
2805};
2806
9eb58a47
PB		 2807static void cirrus_init_common(CirrusVGAState *s, Object *owner,
2808 int device_id, int is_pci,
c75e6d8e
JG		 2809 MemoryRegion *system_memory,
2810 MemoryRegion *system_io)
4abc796d
BS		 2811{
2812 int i;
2813 static int inited;
2814
2815 if (!inited) {
2816 inited = 1;
2817 for(i = 0;i < 256; i++)
2818 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
2819 rop_to_index[CIRRUS_ROP_0] = 0;
2820 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
2821 rop_to_index[CIRRUS_ROP_NOP] = 2;
2822 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
2823 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
2824 rop_to_index[CIRRUS_ROP_SRC] = 5;
2825 rop_to_index[CIRRUS_ROP_1] = 6;
2826 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
2827 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
2828 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
2829 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
2830 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
2831 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
2832 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
2833 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
2834 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
2835 s->device_id = device_id;
2836 if (is_pci)
2837 s->bustype = CIRRUS_BUSTYPE_PCI;
2838 else
2839 s->bustype = CIRRUS_BUSTYPE_ISA;
2840 }
2841
c75e6d8e 2842 /* Register ioport 0x3b0 - 0x3df */
9eb58a47 2843 memory_region_init_io(&s->cirrus_vga_io, owner, &cirrus_vga_io_ops, s,
c75e6d8e 2844 "cirrus-io", 0x30);
eb25a1d9 2845 memory_region_set_flush_coalesced(&s->cirrus_vga_io);
c75e6d8e 2846 memory_region_add_subregion(system_io, 0x3b0, &s->cirrus_vga_io);
4abc796d 2847
9eb58a47 2848 memory_region_init(&s->low_mem_container, owner,
b1950430
AK		 2849 "cirrus-lowmem-container",
2850 0x20000);
2851
9eb58a47 2852 memory_region_init_io(&s->low_mem, owner, &cirrus_vga_mem_ops, s,
b1950430
AK		 2853 "cirrus-low-memory", 0x20000);
2854 memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
7969d9ed
AK		 2855 for (i = 0; i < 2; ++i) {
2856 static const char *names[] = { "vga.bank0", "vga.bank1" };
2857 MemoryRegion *bank = &s->cirrus_bank[i];
9eb58a47
PB		 2858 memory_region_init_alias(bank, owner, names[i], &s->vga.vram,
2859 0, 0x8000);
7969d9ed
AK		 2860 memory_region_set_enabled(bank, false);
2861 memory_region_add_subregion_overlap(&s->low_mem_container, i * 0x8000,
2862 bank, 1);
2863 }
be20f9e9 2864 memory_region_add_subregion_overlap(system_memory,
b1950430
AK		 2865 isa_mem_base + 0x000a0000,
2866 &s->low_mem_container,
2867 1);
2868 memory_region_set_coalescing(&s->low_mem);
2c6ab832 2869
fefe54e3 2870 /* I/O handler for LFB */
9eb58a47 2871 memory_region_init_io(&s->cirrus_linear_io, owner, &cirrus_linear_io_ops, s,
19403a68
MT		 2872 "cirrus-linear-io", s->vga.vram_size_mb
2873 * 1024 * 1024);
bd8f2f5d 2874 memory_region_set_flush_coalesced(&s->cirrus_linear_io);
fefe54e3
AL		 2875
2876 /* I/O handler for LFB */
9eb58a47 2877 memory_region_init_io(&s->cirrus_linear_bitblt_io, owner,
b1950430
AK		 2878 &cirrus_linear_bitblt_io_ops,
2879 s,
2880 "cirrus-bitblt-mmio",
2881 0x400000);
bd8f2f5d 2882 memory_region_set_flush_coalesced(&s->cirrus_linear_bitblt_io);
fefe54e3
AL		 2883
2884 /* I/O handler for memory-mapped I/O */
9eb58a47 2885 memory_region_init_io(&s->cirrus_mmio_io, owner, &cirrus_mmio_io_ops, s,
b1950430 2886 "cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
bd8f2f5d 2887 memory_region_set_flush_coalesced(&s->cirrus_mmio_io);
fefe54e3
AL		 2888
2889 s->real_vram_size =
2890 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
2891
4e12cd94 2892 /* XXX: s->vga.vram_size must be a power of two */
fefe54e3
AL		 2893 s->cirrus_addr_mask = s->real_vram_size - 1;
2894 s->linear_mmio_mask = s->real_vram_size - 256;
2895
4e12cd94
AK		 2896 s->vga.get_bpp = cirrus_get_bpp;
2897 s->vga.get_offsets = cirrus_get_offsets;
2898 s->vga.get_resolution = cirrus_get_resolution;
2899 s->vga.cursor_invalidate = cirrus_cursor_invalidate;
2900 s->vga.cursor_draw_line = cirrus_cursor_draw_line;
fefe54e3 2901
a08d4367 2902 qemu_register_reset(cirrus_reset, s);
e6e5ad80
FB		 2903}
2904
2905/***************************************
2906 *
2907 * ISA bus support
2908 *
2909 ***************************************/
2910
db895a1e 2911static void isa_cirrus_vga_realizefn(DeviceState *dev, Error **errp)
e6e5ad80 2912{
db895a1e 2913 ISADevice *isadev = ISA_DEVICE(dev);
6d4c2f17 2914 ISACirrusVGAState *d = ISA_CIRRUS_VGA(dev);
3d402831
BS		 2915 VGACommonState *s = &d->cirrus_vga.vga;
2916
f61d82c2
GA		 2917 /* follow real hardware, cirrus card emulated has 4 MB video memory.
2918 Also accept 8 MB/16 MB for backward compatibility. */
2919 if (s->vram_size_mb != 4 && s->vram_size_mb != 8 &&
2920 s->vram_size_mb != 16) {
2921 error_setg(errp, "Invalid cirrus_vga ram size '%u'",
2922 s->vram_size_mb);
2923 return;
2924 }
e2bbfc8e 2925 vga_common_init(s, OBJECT(dev), true);
9eb58a47 2926 cirrus_init_common(&d->cirrus_vga, OBJECT(dev), CIRRUS_ID_CLGD5430, 0,
db895a1e
AF		 2927 isa_address_space(isadev),
2928 isa_address_space_io(isadev));
5643706a 2929 s->con = graphic_console_init(dev, 0, s->hw_ops, s);
5245d57a 2930 rom_add_vga(VGABIOS_CIRRUS_FILENAME);
e6e5ad80 2931 /* XXX ISA-LFB support */
ad6d45fa 2932 /* FIXME not qdev yet */
3d402831
BS		 2933}
2934
6d4c2f17 2935static Property isa_cirrus_vga_properties[] = {
19403a68
MT		 2936 DEFINE_PROP_UINT32("vgamem_mb", struct ISACirrusVGAState,
2937 cirrus_vga.vga.vram_size_mb, 8),
2938 DEFINE_PROP_END_OF_LIST(),
2939};
2940
8f04ee08
AL		 2941static void isa_cirrus_vga_class_init(ObjectClass *klass, void *data)
2942{
39bffca2 2943 DeviceClass *dc = DEVICE_CLASS(klass);
8f04ee08 2944
39bffca2 2945 dc->vmsd = &vmstate_cirrus_vga;
db895a1e 2946 dc->realize = isa_cirrus_vga_realizefn;
6d4c2f17 2947 dc->props = isa_cirrus_vga_properties;
125ee0ed 2948 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
8f04ee08
AL		 2949}
2950
8c43a6f0 2951static const TypeInfo isa_cirrus_vga_info = {
6d4c2f17 2952 .name = TYPE_ISA_CIRRUS_VGA,
39bffca2
AL		 2953 .parent = TYPE_ISA_DEVICE,
2954 .instance_size = sizeof(ISACirrusVGAState),
8f04ee08 2955 .class_init = isa_cirrus_vga_class_init,
3d402831
BS		 2956};
2957
e6e5ad80
FB		 2958/***************************************
2959 *
2960 * PCI bus support
2961 *
2962 ***************************************/
2963
81a322d4 2964static int pci_cirrus_vga_initfn(PCIDevice *dev)
a414c306
GH		 2965{
2966 PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev);
2967 CirrusVGAState *s = &d->cirrus_vga;
40021f08
AL		 2968 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2969 int16_t device_id = pc->device_id;
a414c306 2970
f61d82c2
GA		 2971 /* follow real hardware, cirrus card emulated has 4 MB video memory.
2972 Also accept 8 MB/16 MB for backward compatibility. */
2973 if (s->vga.vram_size_mb != 4 && s->vga.vram_size_mb != 8 &&
2974 s->vga.vram_size_mb != 16) {
2975 error_report("Invalid cirrus_vga ram size '%u'",
2976 s->vga.vram_size_mb);
2977 return -1;
2978 }
a414c306 2979 /* setup VGA */
e2bbfc8e 2980 vga_common_init(&s->vga, OBJECT(dev), true);
9eb58a47 2981 cirrus_init_common(s, OBJECT(dev), device_id, 1, pci_address_space(dev),
c75e6d8e 2982 pci_address_space_io(dev));
5643706a 2983 s->vga.con = graphic_console_init(DEVICE(dev), 0, s->vga.hw_ops, &s->vga);
a414c306
GH		 2984
2985 /* setup PCI */
a414c306 2986
3eadad55 2987 memory_region_init(&s->pci_bar, OBJECT(dev), "cirrus-pci-bar0", 0x2000000);
b1950430
AK		 2988
2989 /* XXX: add byte swapping apertures */
2990 memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io);
2991 memory_region_add_subregion(&s->pci_bar, 0x1000000,
2992 &s->cirrus_linear_bitblt_io);
2993
a414c306
GH		 2994 /* setup memory space */
2995 /* memory #0 LFB */
2996 /* memory #1 memory-mapped I/O */
2997 /* XXX: s->vga.vram_size must be a power of two */
e824b2cc 2998 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar);
a414c306 2999 if (device_id == CIRRUS_ID_CLGD5446) {
e824b2cc 3000 pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io);
a414c306 3001 }
81a322d4 3002 return 0;
a414c306
GH		 3003}
3004
19403a68
MT		 3005static Property pci_vga_cirrus_properties[] = {
3006 DEFINE_PROP_UINT32("vgamem_mb", struct PCICirrusVGAState,
3007 cirrus_vga.vga.vram_size_mb, 8),
3008 DEFINE_PROP_END_OF_LIST(),
3009};
3010
40021f08
AL		 3011static void cirrus_vga_class_init(ObjectClass *klass, void *data)
3012{
39bffca2 3013 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 3014 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3015
40021f08
AL		 3016 k->init = pci_cirrus_vga_initfn;
3017 k->romfile = VGABIOS_CIRRUS_FILENAME;
3018 k->vendor_id = PCI_VENDOR_ID_CIRRUS;
3019 k->device_id = CIRRUS_ID_CLGD5446;
3020 k->class_id = PCI_CLASS_DISPLAY_VGA;
125ee0ed 3021 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
39bffca2
AL		 3022 dc->desc = "Cirrus CLGD 54xx VGA";
3023 dc->vmsd = &vmstate_pci_cirrus_vga;
19403a68 3024 dc->props = pci_vga_cirrus_properties;
2897ae02 3025 dc->hotpluggable = false;
40021f08
AL		 3026}
3027
8c43a6f0 3028static const TypeInfo cirrus_vga_info = {
39bffca2
AL		 3029 .name = "cirrus-vga",
3030 .parent = TYPE_PCI_DEVICE,
3031 .instance_size = sizeof(PCICirrusVGAState),
3032 .class_init = cirrus_vga_class_init,
a414c306 3033};
e6e5ad80 3034
83f7d43a 3035static void cirrus_vga_register_types(void)
a414c306 3036{
83f7d43a 3037 type_register_static(&isa_cirrus_vga_info);
39bffca2 3038 type_register_static(&cirrus_vga_info);
e6e5ad80 3039}
83f7d43a
AF		 3040
3041type_init(cirrus_vga_register_types)
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