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hw/display/cirrus_vga: Convert debug printf() to trace event
[mirror_qemu.git] / hw / display / cirrus_vga.c
CommitLineData
e6e5ad80 1/*
aeb3c85f 2 * QEMU Cirrus CLGD 54xx VGA Emulator.
5fafdf24 3 *
e6e5ad80 4 * Copyright (c) 2004 Fabrice Bellard
aeb3c85f 5 * Copyright (c) 2004 Makoto Suzuki (suzu)
5fafdf24 6 *
e6e5ad80
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
aeb3c85f 25/*
29585468
PMD		 26 * Reference: Finn Thogersons' VGADOC4b:
27 *
28 * http://web.archive.org/web/20021019054927/http://home.worldonline.dk/finth/
29 *
30 * VGADOC4b.ZIP content available at:
31 *
32 * https://pdos.csail.mit.edu/6.828/2005/readings/hardware/vgadoc
aeb3c85f 33 */
0b8fa32f 34
47df5154 35#include "qemu/osdep.h"
0b8fa32f 36#include "qemu/module.h"
f0353b0d 37#include "qemu/units.h"
71e8a915 38#include "sysemu/reset.h"
da34e65c 39#include "qapi/error.h"
ec87f206 40#include "trace.h"
83c9f4ca 41#include "hw/pci/pci.h"
a27bd6c7 42#include "hw/qdev-properties.h"
d6454270 43#include "migration/vmstate.h"
d3c2343a 44#include "ui/pixel_ops.h"
ce3cf70e 45#include "cirrus_vga_internal.h"
e6e5ad80 46
a5082316
FB		 47/*
48 * TODO:
ad81218e 49 * - destination write mask support not complete (bits 5..7)
a5082316
FB		 50 * - optimize linear mappings
51 * - optimize bitblt functions
52 */
53
e36f36e1 54//#define DEBUG_CIRRUS
a21ae81d 55//#define DEBUG_BITBLT
e36f36e1 56
e6e5ad80
FB		 57/***************************************
58 *
59 * definitions
60 *
61 ***************************************/
62
e6e5ad80
FB		 63// sequencer 0x07
64#define CIRRUS_SR7_BPP_VGA 0x00
65#define CIRRUS_SR7_BPP_SVGA 0x01
66#define CIRRUS_SR7_BPP_MASK 0x0e
67#define CIRRUS_SR7_BPP_8 0x00
68#define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
69#define CIRRUS_SR7_BPP_24 0x04
70#define CIRRUS_SR7_BPP_16 0x06
71#define CIRRUS_SR7_BPP_32 0x08
72#define CIRRUS_SR7_ISAADDR_MASK 0xe0
73
74// sequencer 0x0f
75#define CIRRUS_MEMSIZE_512k 0x08
76#define CIRRUS_MEMSIZE_1M 0x10
77#define CIRRUS_MEMSIZE_2M 0x18
78#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
79
80// sequencer 0x12
81#define CIRRUS_CURSOR_SHOW 0x01
82#define CIRRUS_CURSOR_HIDDENPEL 0x02
83#define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
84
85// sequencer 0x17
86#define CIRRUS_BUSTYPE_VLBFAST 0x10
87#define CIRRUS_BUSTYPE_PCI 0x20
88#define CIRRUS_BUSTYPE_VLBSLOW 0x30
89#define CIRRUS_BUSTYPE_ISA 0x38
90#define CIRRUS_MMIO_ENABLE 0x04
91#define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
92#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
93
94// control 0x0b
95#define CIRRUS_BANKING_DUAL 0x01
96#define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
97
98// control 0x30
99#define CIRRUS_BLTMODE_BACKWARDS 0x01
100#define CIRRUS_BLTMODE_MEMSYSDEST 0x02
101#define CIRRUS_BLTMODE_MEMSYSSRC 0x04
102#define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
103#define CIRRUS_BLTMODE_PATTERNCOPY 0x40
104#define CIRRUS_BLTMODE_COLOREXPAND 0x80
105#define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
106#define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
107#define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
108#define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
109#define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
110
111// control 0x31
112#define CIRRUS_BLT_BUSY 0x01
113#define CIRRUS_BLT_START 0x02
114#define CIRRUS_BLT_RESET 0x04
115#define CIRRUS_BLT_FIFOUSED 0x10
a5082316 116#define CIRRUS_BLT_AUTOSTART 0x80
e6e5ad80
FB		 117
118// control 0x32
119#define CIRRUS_ROP_0 0x00
120#define CIRRUS_ROP_SRC_AND_DST 0x05
121#define CIRRUS_ROP_NOP 0x06
122#define CIRRUS_ROP_SRC_AND_NOTDST 0x09
123#define CIRRUS_ROP_NOTDST 0x0b
124#define CIRRUS_ROP_SRC 0x0d
125#define CIRRUS_ROP_1 0x0e
126#define CIRRUS_ROP_NOTSRC_AND_DST 0x50
127#define CIRRUS_ROP_SRC_XOR_DST 0x59
128#define CIRRUS_ROP_SRC_OR_DST 0x6d
129#define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
130#define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
131#define CIRRUS_ROP_SRC_OR_NOTDST 0xad
132#define CIRRUS_ROP_NOTSRC 0xd0
133#define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
134#define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
135
a5082316
FB		 136#define CIRRUS_ROP_NOP_INDEX 2
137#define CIRRUS_ROP_SRC_INDEX 5
138
a21ae81d 139// control 0x33
a5082316 140#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
4c8732d7 141#define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
a5082316 142#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
a21ae81d 143
e6e5ad80
FB		 144// memory-mapped IO
145#define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
146#define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
147#define CIRRUS_MMIO_BLTWIDTH 0x08 // word
148#define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
149#define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
150#define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
151#define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
152#define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
153#define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
154#define CIRRUS_MMIO_BLTMODE 0x18 // byte
155#define CIRRUS_MMIO_BLTROP 0x1a // byte
156#define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
157#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
158#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
159#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
160#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
161#define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
162#define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
163#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
164#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
165#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
166#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
167#define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
168#define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
169#define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
170#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
171#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
172#define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
173#define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
174
a21ae81d 175#define CIRRUS_PNPMMIO_SIZE 0x1000
e6e5ad80 176
a5082316 177typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
026aeffc
GH		 178 uint32_t dstaddr, int dst_pitch,
179 int width, int height);
e6e5ad80 180
e6e5ad80
FB		 181typedef struct PCICirrusVGAState {
182 PCIDevice dev;
183 CirrusVGAState cirrus_vga;
184} PCICirrusVGAState;
185
d338bae3
GA		 186#define TYPE_PCI_CIRRUS_VGA "cirrus-vga"
187#define PCI_CIRRUS_VGA(obj) \
188 OBJECT_CHECK(PCICirrusVGAState, (obj), TYPE_PCI_CIRRUS_VGA)
189
a5082316 190static uint8_t rop_to_index[256];
3b46e624 191
e6e5ad80
FB		 192/***************************************
193 *
194 * prototypes.
195 *
196 ***************************************/
197
198
8926b517
FB		 199static void cirrus_bitblt_reset(CirrusVGAState *s);
200static void cirrus_update_memory_access(CirrusVGAState *s);
e6e5ad80
FB		 201
202/***************************************
203 *
204 * raster operations
205 *
206 ***************************************/
207
d3532a0d
GH		 208static bool blit_region_is_unsafe(struct CirrusVGAState *s,
209 int32_t pitch, int32_t addr)
210{
12e97ec3
GH		 211 if (!pitch) {
212 return true;
213 }
d3532a0d
GH		 214 if (pitch < 0) {
215 int64_t min = addr
62d4c6bd
LQ		 216 + ((int64_t)s->cirrus_blt_height - 1) * pitch
217 - s->cirrus_blt_width;
218 if (min < -1 || addr >= s->vga.vram_size) {
d3532a0d
GH		 219 return true;
220 }
221 } else {
222 int64_t max = addr
223 + ((int64_t)s->cirrus_blt_height-1) * pitch
224 + s->cirrus_blt_width;
d2ba7ecb 225 if (max > s->vga.vram_size) {
d3532a0d
GH		 226 return true;
227 }
228 }
229 return false;
230}
231
12e97ec3 232static bool blit_is_unsafe(struct CirrusVGAState *s, bool dst_only)
d3532a0d
GH		 233{
234 /* should be the case, see cirrus_bitblt_start */
235 assert(s->cirrus_blt_width > 0);
236 assert(s->cirrus_blt_height > 0);
237
bf259833
GH		 238 if (s->cirrus_blt_width > CIRRUS_BLTBUFSIZE) {
239 return true;
240 }
241
d3532a0d 242 if (blit_region_is_unsafe(s, s->cirrus_blt_dstpitch,
60cd23e8 243 s->cirrus_blt_dstaddr)) {
d3532a0d
GH		 244 return true;
245 }
913a8788
BR		 246 if (dst_only) {
247 return false;
248 }
12e97ec3 249 if (blit_region_is_unsafe(s, s->cirrus_blt_srcpitch,
60cd23e8 250 s->cirrus_blt_srcaddr)) {
d3532a0d
GH		 251 return true;
252 }
253
254 return false;
255}
256
a5082316 257static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
ffaf8577 258 uint32_t dstaddr, uint32_t srcaddr,
a5082316
FB		 259 int dstpitch,int srcpitch,
260 int bltwidth,int bltheight)
261{
e6e5ad80
FB		 262}
263
a5082316 264static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
026aeffc 265 uint32_t dstaddr,
a5082316 266 int dstpitch, int bltwidth,int bltheight)
e6e5ad80 267{
a5082316 268}
e6e5ad80 269
ffaf8577
GH		 270static inline uint8_t cirrus_src(CirrusVGAState *s, uint32_t srcaddr)
271{
272 if (s->cirrus_srccounter) {
273 /* cputovideo */
274 return s->cirrus_bltbuf[srcaddr & (CIRRUS_BLTBUFSIZE - 1)];
275 } else {
276 /* videotovideo */
277 return s->vga.vram_ptr[srcaddr & s->cirrus_addr_mask];
278 }
279}
280
281static inline uint16_t cirrus_src16(CirrusVGAState *s, uint32_t srcaddr)
282{
283 uint16_t *src;
284
285 if (s->cirrus_srccounter) {
286 /* cputovideo */
287 src = (void *)&s->cirrus_bltbuf[srcaddr & (CIRRUS_BLTBUFSIZE - 1) & ~1];
288 } else {
289 /* videotovideo */
290 src = (void *)&s->vga.vram_ptr[srcaddr & s->cirrus_addr_mask & ~1];
291 }
292 return *src;
293}
294
295static inline uint32_t cirrus_src32(CirrusVGAState *s, uint32_t srcaddr)
296{
297 uint32_t *src;
298
299 if (s->cirrus_srccounter) {
300 /* cputovideo */
301 src = (void *)&s->cirrus_bltbuf[srcaddr & (CIRRUS_BLTBUFSIZE - 1) & ~3];
302 } else {
303 /* videotovideo */
304 src = (void *)&s->vga.vram_ptr[srcaddr & s->cirrus_addr_mask & ~3];
305 }
306 return *src;
307}
308
a5082316 309#define ROP_NAME 0
8c78881f 310#define ROP_FN(d, s) 0
47b43a1f 311#include "cirrus_vga_rop.h"
e6e5ad80 312
a5082316 313#define ROP_NAME src_and_dst
8c78881f 314#define ROP_FN(d, s) (s) & (d)
47b43a1f 315#include "cirrus_vga_rop.h"
e6e5ad80 316
a5082316 317#define ROP_NAME src_and_notdst
8c78881f 318#define ROP_FN(d, s) (s) & (~(d))
47b43a1f 319#include "cirrus_vga_rop.h"
e6e5ad80 320
a5082316 321#define ROP_NAME notdst
8c78881f 322#define ROP_FN(d, s) ~(d)
47b43a1f 323#include "cirrus_vga_rop.h"
e6e5ad80 324
a5082316 325#define ROP_NAME src
8c78881f 326#define ROP_FN(d, s) s
47b43a1f 327#include "cirrus_vga_rop.h"
e6e5ad80 328
a5082316 329#define ROP_NAME 1
8c78881f 330#define ROP_FN(d, s) ~0
47b43a1f 331#include "cirrus_vga_rop.h"
a5082316
FB		 332
333#define ROP_NAME notsrc_and_dst
8c78881f 334#define ROP_FN(d, s) (~(s)) & (d)
47b43a1f 335#include "cirrus_vga_rop.h"
a5082316
FB		 336
337#define ROP_NAME src_xor_dst
8c78881f 338#define ROP_FN(d, s) (s) ^ (d)
47b43a1f 339#include "cirrus_vga_rop.h"
a5082316
FB		 340
341#define ROP_NAME src_or_dst
8c78881f 342#define ROP_FN(d, s) (s) | (d)
47b43a1f 343#include "cirrus_vga_rop.h"
a5082316
FB		 344
345#define ROP_NAME notsrc_or_notdst
8c78881f 346#define ROP_FN(d, s) (~(s)) | (~(d))
47b43a1f 347#include "cirrus_vga_rop.h"
a5082316
FB		 348
349#define ROP_NAME src_notxor_dst
8c78881f 350#define ROP_FN(d, s) ~((s) ^ (d))
47b43a1f 351#include "cirrus_vga_rop.h"
e6e5ad80 352
a5082316 353#define ROP_NAME src_or_notdst
8c78881f 354#define ROP_FN(d, s) (s) | (~(d))
47b43a1f 355#include "cirrus_vga_rop.h"
a5082316
FB		 356
357#define ROP_NAME notsrc
8c78881f 358#define ROP_FN(d, s) (~(s))
47b43a1f 359#include "cirrus_vga_rop.h"
a5082316
FB		 360
361#define ROP_NAME notsrc_or_dst
8c78881f 362#define ROP_FN(d, s) (~(s)) | (d)
47b43a1f 363#include "cirrus_vga_rop.h"
a5082316
FB		 364
365#define ROP_NAME notsrc_and_notdst
8c78881f 366#define ROP_FN(d, s) (~(s)) & (~(d))
47b43a1f 367#include "cirrus_vga_rop.h"
a5082316
FB		 368
369static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
370 cirrus_bitblt_rop_fwd_0,
371 cirrus_bitblt_rop_fwd_src_and_dst,
372 cirrus_bitblt_rop_nop,
373 cirrus_bitblt_rop_fwd_src_and_notdst,
374 cirrus_bitblt_rop_fwd_notdst,
375 cirrus_bitblt_rop_fwd_src,
376 cirrus_bitblt_rop_fwd_1,
377 cirrus_bitblt_rop_fwd_notsrc_and_dst,
378 cirrus_bitblt_rop_fwd_src_xor_dst,
379 cirrus_bitblt_rop_fwd_src_or_dst,
380 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
381 cirrus_bitblt_rop_fwd_src_notxor_dst,
382 cirrus_bitblt_rop_fwd_src_or_notdst,
383 cirrus_bitblt_rop_fwd_notsrc,
384 cirrus_bitblt_rop_fwd_notsrc_or_dst,
385 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
386};
387
388static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
389 cirrus_bitblt_rop_bkwd_0,
390 cirrus_bitblt_rop_bkwd_src_and_dst,
391 cirrus_bitblt_rop_nop,
392 cirrus_bitblt_rop_bkwd_src_and_notdst,
393 cirrus_bitblt_rop_bkwd_notdst,
394 cirrus_bitblt_rop_bkwd_src,
395 cirrus_bitblt_rop_bkwd_1,
396 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
397 cirrus_bitblt_rop_bkwd_src_xor_dst,
398 cirrus_bitblt_rop_bkwd_src_or_dst,
399 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
400 cirrus_bitblt_rop_bkwd_src_notxor_dst,
401 cirrus_bitblt_rop_bkwd_src_or_notdst,
402 cirrus_bitblt_rop_bkwd_notsrc,
403 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
404 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
405};
96cf2df8
TS		 406
407#define TRANSP_ROP(name) {\
408 name ## _8,\
409 name ## _16,\
410 }
411#define TRANSP_NOP(func) {\
412 func,\
413 func,\
414 }
415
416static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
417 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
418 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
419 TRANSP_NOP(cirrus_bitblt_rop_nop),
420 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
421 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
422 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
423 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
424 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
425 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
426 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
427 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
428 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
429 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
430 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
431 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
432 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
433};
434
435static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
436 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
437 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
438 TRANSP_NOP(cirrus_bitblt_rop_nop),
439 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
440 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
441 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
442 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
443 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
444 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
445 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
446 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
447 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
448 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
449 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
450 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
451 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
452};
453
a5082316
FB		 454#define ROP2(name) {\
455 name ## _8,\
456 name ## _16,\
457 name ## _24,\
458 name ## _32,\
459 }
460
461#define ROP_NOP2(func) {\
462 func,\
463 func,\
464 func,\
465 func,\
466 }
467
e69390ce
FB		 468static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
469 ROP2(cirrus_patternfill_0),
470 ROP2(cirrus_patternfill_src_and_dst),
471 ROP_NOP2(cirrus_bitblt_rop_nop),
472 ROP2(cirrus_patternfill_src_and_notdst),
473 ROP2(cirrus_patternfill_notdst),
474 ROP2(cirrus_patternfill_src),
475 ROP2(cirrus_patternfill_1),
476 ROP2(cirrus_patternfill_notsrc_and_dst),
477 ROP2(cirrus_patternfill_src_xor_dst),
478 ROP2(cirrus_patternfill_src_or_dst),
479 ROP2(cirrus_patternfill_notsrc_or_notdst),
480 ROP2(cirrus_patternfill_src_notxor_dst),
481 ROP2(cirrus_patternfill_src_or_notdst),
482 ROP2(cirrus_patternfill_notsrc),
483 ROP2(cirrus_patternfill_notsrc_or_dst),
484 ROP2(cirrus_patternfill_notsrc_and_notdst),
485};
486
a5082316
FB		 487static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
488 ROP2(cirrus_colorexpand_transp_0),
489 ROP2(cirrus_colorexpand_transp_src_and_dst),
490 ROP_NOP2(cirrus_bitblt_rop_nop),
491 ROP2(cirrus_colorexpand_transp_src_and_notdst),
492 ROP2(cirrus_colorexpand_transp_notdst),
493 ROP2(cirrus_colorexpand_transp_src),
494 ROP2(cirrus_colorexpand_transp_1),
495 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
496 ROP2(cirrus_colorexpand_transp_src_xor_dst),
497 ROP2(cirrus_colorexpand_transp_src_or_dst),
498 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
499 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
500 ROP2(cirrus_colorexpand_transp_src_or_notdst),
501 ROP2(cirrus_colorexpand_transp_notsrc),
502 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
503 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
504};
505
506static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
507 ROP2(cirrus_colorexpand_0),
508 ROP2(cirrus_colorexpand_src_and_dst),
509 ROP_NOP2(cirrus_bitblt_rop_nop),
510 ROP2(cirrus_colorexpand_src_and_notdst),
511 ROP2(cirrus_colorexpand_notdst),
512 ROP2(cirrus_colorexpand_src),
513 ROP2(cirrus_colorexpand_1),
514 ROP2(cirrus_colorexpand_notsrc_and_dst),
515 ROP2(cirrus_colorexpand_src_xor_dst),
516 ROP2(cirrus_colorexpand_src_or_dst),
517 ROP2(cirrus_colorexpand_notsrc_or_notdst),
518 ROP2(cirrus_colorexpand_src_notxor_dst),
519 ROP2(cirrus_colorexpand_src_or_notdst),
520 ROP2(cirrus_colorexpand_notsrc),
521 ROP2(cirrus_colorexpand_notsrc_or_dst),
522 ROP2(cirrus_colorexpand_notsrc_and_notdst),
523};
524
b30d4608
FB		 525static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
526 ROP2(cirrus_colorexpand_pattern_transp_0),
527 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
528 ROP_NOP2(cirrus_bitblt_rop_nop),
529 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
530 ROP2(cirrus_colorexpand_pattern_transp_notdst),
531 ROP2(cirrus_colorexpand_pattern_transp_src),
532 ROP2(cirrus_colorexpand_pattern_transp_1),
533 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
534 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
535 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
536 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
537 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
538 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
539 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
540 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
541 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
542};
543
544static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
545 ROP2(cirrus_colorexpand_pattern_0),
546 ROP2(cirrus_colorexpand_pattern_src_and_dst),
547 ROP_NOP2(cirrus_bitblt_rop_nop),
548 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
549 ROP2(cirrus_colorexpand_pattern_notdst),
550 ROP2(cirrus_colorexpand_pattern_src),
551 ROP2(cirrus_colorexpand_pattern_1),
552 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
553 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
554 ROP2(cirrus_colorexpand_pattern_src_or_dst),
555 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
556 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
557 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
558 ROP2(cirrus_colorexpand_pattern_notsrc),
559 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
560 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
561};
562
a5082316
FB		 563static const cirrus_fill_t cirrus_fill[16][4] = {
564 ROP2(cirrus_fill_0),
565 ROP2(cirrus_fill_src_and_dst),
566 ROP_NOP2(cirrus_bitblt_fill_nop),
567 ROP2(cirrus_fill_src_and_notdst),
568 ROP2(cirrus_fill_notdst),
569 ROP2(cirrus_fill_src),
570 ROP2(cirrus_fill_1),
571 ROP2(cirrus_fill_notsrc_and_dst),
572 ROP2(cirrus_fill_src_xor_dst),
573 ROP2(cirrus_fill_src_or_dst),
574 ROP2(cirrus_fill_notsrc_or_notdst),
575 ROP2(cirrus_fill_src_notxor_dst),
576 ROP2(cirrus_fill_src_or_notdst),
577 ROP2(cirrus_fill_notsrc),
578 ROP2(cirrus_fill_notsrc_or_dst),
579 ROP2(cirrus_fill_notsrc_and_notdst),
580};
581
582static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
e6e5ad80 583{
a5082316
FB		 584 unsigned int color;
585 switch (s->cirrus_blt_pixelwidth) {
586 case 1:
587 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
588 break;
589 case 2:
4e12cd94 590 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
a5082316
FB		 591 s->cirrus_blt_fgcol = le16_to_cpu(color);
592 break;
593 case 3:
5fafdf24 594 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
4e12cd94 595 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
a5082316
FB		 596 break;
597 default:
598 case 4:
4e12cd94
AK		 599 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
600 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
a5082316
FB		 601 s->cirrus_blt_fgcol = le32_to_cpu(color);
602 break;
e6e5ad80
FB		 603 }
604}
605
a5082316 606static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
e6e5ad80 607{
a5082316 608 unsigned int color;
e6e5ad80
FB		 609 switch (s->cirrus_blt_pixelwidth) {
610 case 1:
a5082316
FB		 611 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
612 break;
e6e5ad80 613 case 2:
4e12cd94 614 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
a5082316
FB		 615 s->cirrus_blt_bgcol = le16_to_cpu(color);
616 break;
e6e5ad80 617 case 3:
5fafdf24 618 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
4e12cd94 619 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
a5082316 620 break;
e6e5ad80 621 default:
a5082316 622 case 4:
4e12cd94
AK		 623 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
624 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
a5082316
FB		 625 s->cirrus_blt_bgcol = le32_to_cpu(color);
626 break;
e6e5ad80
FB		 627 }
628}
629
630static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
631 int off_pitch, int bytesperline,
632 int lines)
633{
634 int y;
635 int off_cur;
636 int off_cur_end;
637
f153b563
WB		 638 if (off_pitch < 0) {
639 off_begin -= bytesperline - 1;
640 }
641
e6e5ad80 642 for (y = 0; y < lines; y++) {
e048dac6
GH		 643 off_cur = off_begin;
644 off_cur_end = ((off_cur + bytesperline - 1) & s->cirrus_addr_mask) + 1;
f153b563 645 assert(off_cur_end >= off_cur);
fd4aa979 646 memory_region_set_dirty(&s->vga.vram, off_cur, off_cur_end - off_cur);
e048dac6 647 off_begin += off_pitch;
e6e5ad80
FB		 648 }
649}
650
ffaf8577 651static int cirrus_bitblt_common_patterncopy(CirrusVGAState *s)
e6e5ad80 652{
95280c31 653 uint32_t patternsize;
ffaf8577 654 bool videosrc = !s->cirrus_srccounter;
e6e5ad80 655
95280c31
GH		 656 if (videosrc) {
657 switch (s->vga.get_bpp(&s->vga)) {
658 case 8:
659 patternsize = 64;
660 break;
661 case 15:
662 case 16:
663 patternsize = 128;
664 break;
665 case 24:
666 case 32:
667 default:
668 patternsize = 256;
669 break;
670 }
671 s->cirrus_blt_srcaddr &= ~(patternsize - 1);
672 if (s->cirrus_blt_srcaddr + patternsize > s->vga.vram_size) {
673 return 0;
674 }
95280c31
GH		 675 }
676
12e97ec3 677 if (blit_is_unsafe(s, true)) {
b2eb849d 678 return 0;
5858dd18 679 }
b2eb849d 680
ffaf8577
GH		 681 (*s->cirrus_rop) (s, s->cirrus_blt_dstaddr,
682 videosrc ? s->cirrus_blt_srcaddr : 0,
5fafdf24 683 s->cirrus_blt_dstpitch, 0,
e69390ce 684 s->cirrus_blt_width, s->cirrus_blt_height);
e6e5ad80 685 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
e69390ce
FB		 686 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
687 s->cirrus_blt_height);
e6e5ad80
FB		 688 return 1;
689}
690
a21ae81d
FB		 691/* fill */
692
a5082316 693static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
a21ae81d 694{
a5082316 695 cirrus_fill_t rop_func;
a21ae81d 696
12e97ec3 697 if (blit_is_unsafe(s, true)) {
b2eb849d 698 return 0;
d3532a0d 699 }
a5082316 700 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
026aeffc 701 rop_func(s, s->cirrus_blt_dstaddr,
a5082316
FB		 702 s->cirrus_blt_dstpitch,
703 s->cirrus_blt_width, s->cirrus_blt_height);
a21ae81d
FB		 704 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
705 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
706 s->cirrus_blt_height);
707 cirrus_bitblt_reset(s);
708 return 1;
709}
710
e6e5ad80
FB		 711/***************************************
712 *
713 * bitblt (video-to-video)
714 *
715 ***************************************/
716
717static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
718{
ffaf8577 719 return cirrus_bitblt_common_patterncopy(s);
e6e5ad80
FB		 720}
721
4299b90e 722static int cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
e6e5ad80 723{
78935c4a
AJ		 724 int sx = 0, sy = 0;
725 int dx = 0, dy = 0;
726 int depth = 0;
24236869
FB		 727 int notify = 0;
728
92d675d1
AJ		 729 /* make sure to only copy if it's a plain copy ROP */
730 if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
731 *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {
24236869 732
92d675d1
AJ		 733 int width, height;
734
735 depth = s->vga.get_bpp(&s->vga) / 8;
4299b90e
PP		 736 if (!depth) {
737 return 0;
738 }
92d675d1
AJ		 739 s->vga.get_resolution(&s->vga, &width, &height);
740
741 /* extra x, y */
742 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
743 sy = (src / ABS(s->cirrus_blt_srcpitch));
744 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
745 dy = (dst / ABS(s->cirrus_blt_dstpitch));
24236869 746
92d675d1
AJ		 747 /* normalize width */
748 w /= depth;
24236869 749
92d675d1
AJ		 750 /* if we're doing a backward copy, we have to adjust
751 our x/y to be the upper left corner (instead of the lower
752 right corner) */
753 if (s->cirrus_blt_dstpitch < 0) {
754 sx -= (s->cirrus_blt_width / depth) - 1;
755 dx -= (s->cirrus_blt_width / depth) - 1;
756 sy -= s->cirrus_blt_height - 1;
757 dy -= s->cirrus_blt_height - 1;
758 }
759
760 /* are we in the visible portion of memory? */
761 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
762 (sx + w) <= width && (sy + h) <= height &&
763 (dx + w) <= width && (dy + h) <= height) {
764 notify = 1;
765 }
766 }
24236869 767
026aeffc 768 (*s->cirrus_rop) (s, s->cirrus_blt_dstaddr,
ffaf8577 769 s->cirrus_blt_srcaddr,
e6e5ad80
FB		 770 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
771 s->cirrus_blt_width, s->cirrus_blt_height);
24236869 772
c78f7137 773 if (notify) {
50628d34
GH		 774 dpy_gfx_update(s->vga.con, dx, dy,
775 s->cirrus_blt_width / depth,
776 s->cirrus_blt_height);
c78f7137 777 }
24236869
FB		 778
779 /* we don't have to notify the display that this portion has
38334f76 780 changed since qemu_console_copy implies this */
24236869 781
31c05501
AL		 782 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
783 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
784 s->cirrus_blt_height);
4299b90e
PP		 785
786 return 1;
24236869
FB		 787}
788
789static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
790{
12e97ec3 791 if (blit_is_unsafe(s, false))
65d35a09
AJ		 792 return 0;
793
4299b90e 794 return cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
4e12cd94 795 s->cirrus_blt_srcaddr - s->vga.start_addr,
7d957bd8 796 s->cirrus_blt_width, s->cirrus_blt_height);
e6e5ad80
FB		 797}
798
799/***************************************
800 *
801 * bitblt (cpu-to-video)
802 *
803 ***************************************/
804
e6e5ad80
FB		 805static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
806{
807 int copy_count;
a5082316 808 uint8_t *end_ptr;
3b46e624 809
e6e5ad80 810 if (s->cirrus_srccounter > 0) {
a5082316 811 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
ffaf8577 812 cirrus_bitblt_common_patterncopy(s);
a5082316
FB		 813 the_end:
814 s->cirrus_srccounter = 0;
815 cirrus_bitblt_reset(s);
816 } else {
817 /* at least one scan line */
818 do {
026aeffc 819 (*s->cirrus_rop)(s, s->cirrus_blt_dstaddr,
ffaf8577 820 0, 0, 0, s->cirrus_blt_width, 1);
a5082316
FB		 821 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
822 s->cirrus_blt_width, 1);
823 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
824 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
825 if (s->cirrus_srccounter <= 0)
826 goto the_end;
66a0a2cb 827 /* more bytes than needed can be transferred because of
a5082316
FB		 828 word alignment, so we keep them for the next line */
829 /* XXX: keep alignment to speed up transfer */
830 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
831 copy_count = s->cirrus_srcptr_end - end_ptr;
832 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
833 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
834 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
835 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
836 }
e6e5ad80
FB		 837 }
838}
839
840/***************************************
841 *
842 * bitblt wrapper
843 *
844 ***************************************/
845
846static void cirrus_bitblt_reset(CirrusVGAState * s)
847{
f8b237af
AL		 848 int need_update;
849
4e12cd94 850 s->vga.gr[0x31] &=
e6e5ad80 851 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
f8b237af
AL		 852 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
853 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
e6e5ad80
FB		 854 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
855 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
856 s->cirrus_srccounter = 0;
f8b237af
AL		 857 if (!need_update)
858 return;
8926b517 859 cirrus_update_memory_access(s);
e6e5ad80
FB		 860}
861
862static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
863{
a5082316
FB		 864 int w;
865
92f2b88c
GH		 866 if (blit_is_unsafe(s, true)) {
867 return 0;
868 }
869
e6e5ad80
FB		 870 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
871 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
872 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
873
874 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
875 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 876 s->cirrus_blt_srcpitch = 8;
e6e5ad80 877 } else {
b30d4608 878 /* XXX: check for 24 bpp */
a5082316 879 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
e6e5ad80 880 }
a5082316 881 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
e6e5ad80
FB		 882 } else {
883 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 884 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
5fafdf24 885 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
a5082316
FB		 886 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
887 else
888 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
e6e5ad80 889 } else {
c9c0eae8
FB		 890 /* always align input size to 32 bits */
891 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
e6e5ad80 892 }
a5082316 893 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
e6e5ad80 894 }
92f2b88c
GH		 895
896 /* the blit_is_unsafe call above should catch this */
897 assert(s->cirrus_blt_srcpitch <= CIRRUS_BLTBUFSIZE);
898
a5082316
FB		 899 s->cirrus_srcptr = s->cirrus_bltbuf;
900 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
8926b517 901 cirrus_update_memory_access(s);
e6e5ad80
FB		 902 return 1;
903}
904
905static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
906{
907 /* XXX */
a5082316 908#ifdef DEBUG_BITBLT
e6e5ad80
FB		 909 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
910#endif
911 return 0;
912}
913
914static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
915{
916 int ret;
917
918 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
919 ret = cirrus_bitblt_videotovideo_patterncopy(s);
920 } else {
921 ret = cirrus_bitblt_videotovideo_copy(s);
922 }
e6e5ad80
FB		 923 if (ret)
924 cirrus_bitblt_reset(s);
925 return ret;
926}
927
928static void cirrus_bitblt_start(CirrusVGAState * s)
929{
930 uint8_t blt_rop;
931
827bd517
GH		 932 if (!s->enable_blitter) {
933 goto bitblt_ignore;
934 }
935
4e12cd94 936 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
a5082316 937
4e12cd94
AK		 938 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
939 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
940 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
941 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
e6e5ad80 942 s->cirrus_blt_dstaddr =
4e12cd94 943 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
e6e5ad80 944 s->cirrus_blt_srcaddr =
4e12cd94
AK		 945 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
946 s->cirrus_blt_mode = s->vga.gr[0x30];
947 s->cirrus_blt_modeext = s->vga.gr[0x33];
948 blt_rop = s->vga.gr[0x32];
e6e5ad80 949
60cd23e8
GH		 950 s->cirrus_blt_dstaddr &= s->cirrus_addr_mask;
951 s->cirrus_blt_srcaddr &= s->cirrus_addr_mask;
952
a21ae81d 953#ifdef DEBUG_BITBLT
0b74ed78 954 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
5fafdf24 955 blt_rop,
a21ae81d 956 s->cirrus_blt_mode,
a5082316 957 s->cirrus_blt_modeext,
a21ae81d
FB		 958 s->cirrus_blt_width,
959 s->cirrus_blt_height,
960 s->cirrus_blt_dstpitch,
961 s->cirrus_blt_srcpitch,
962 s->cirrus_blt_dstaddr,
a5082316 963 s->cirrus_blt_srcaddr,
4e12cd94 964 s->vga.gr[0x2f]);
a21ae81d
FB		 965#endif
966
e6e5ad80
FB		 967 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
968 case CIRRUS_BLTMODE_PIXELWIDTH8:
969 s->cirrus_blt_pixelwidth = 1;
970 break;
971 case CIRRUS_BLTMODE_PIXELWIDTH16:
972 s->cirrus_blt_pixelwidth = 2;
973 break;
974 case CIRRUS_BLTMODE_PIXELWIDTH24:
975 s->cirrus_blt_pixelwidth = 3;
976 break;
977 case CIRRUS_BLTMODE_PIXELWIDTH32:
978 s->cirrus_blt_pixelwidth = 4;
979 break;
980 default:
a5082316 981#ifdef DEBUG_BITBLT
e6e5ad80
FB		 982 printf("cirrus: bitblt - pixel width is unknown\n");
983#endif
984 goto bitblt_ignore;
985 }
986 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
987
988 if ((s->
989 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
990 CIRRUS_BLTMODE_MEMSYSDEST))
991 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
a5082316 992#ifdef DEBUG_BITBLT
e6e5ad80
FB		 993 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
994#endif
995 goto bitblt_ignore;
996 }
997
a5082316 998 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
5fafdf24 999 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
a21ae81d 1000 CIRRUS_BLTMODE_TRANSPARENTCOMP |
5fafdf24
TS		 1001 CIRRUS_BLTMODE_PATTERNCOPY |
1002 CIRRUS_BLTMODE_COLOREXPAND)) ==
a21ae81d 1003 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
a5082316
FB		 1004 cirrus_bitblt_fgcol(s);
1005 cirrus_bitblt_solidfill(s, blt_rop);
e6e5ad80 1006 } else {
5fafdf24
TS		 1007 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
1008 CIRRUS_BLTMODE_PATTERNCOPY)) ==
a5082316
FB		 1009 CIRRUS_BLTMODE_COLOREXPAND) {
1010
1011 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
b30d4608 1012 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
4c8732d7 1013 cirrus_bitblt_bgcol(s);
b30d4608 1014 else
4c8732d7 1015 cirrus_bitblt_fgcol(s);
b30d4608 1016 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
a5082316
FB		 1017 } else {
1018 cirrus_bitblt_fgcol(s);
1019 cirrus_bitblt_bgcol(s);
1020 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1021 }
e69390ce 1022 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
b30d4608
FB		 1023 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1024 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1025 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1026 cirrus_bitblt_bgcol(s);
1027 else
1028 cirrus_bitblt_fgcol(s);
1029 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1030 } else {
1031 cirrus_bitblt_fgcol(s);
1032 cirrus_bitblt_bgcol(s);
1033 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1034 }
1035 } else {
1036 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1037 }
a21ae81d 1038 } else {
96cf2df8
TS		 1039 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1040 if (s->cirrus_blt_pixelwidth > 2) {
1041 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1042 goto bitblt_ignore;
1043 }
1044 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1045 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1046 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1047 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1048 } else {
1049 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1050 }
1051 } else {
1052 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1053 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1054 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1055 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1056 } else {
1057 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1058 }
1059 }
1060 }
a21ae81d
FB		 1061 // setup bitblt engine.
1062 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1063 if (!cirrus_bitblt_cputovideo(s))
1064 goto bitblt_ignore;
1065 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1066 if (!cirrus_bitblt_videotocpu(s))
1067 goto bitblt_ignore;
1068 } else {
1069 if (!cirrus_bitblt_videotovideo(s))
1070 goto bitblt_ignore;
1071 }
e6e5ad80 1072 }
e6e5ad80
FB		 1073 return;
1074 bitblt_ignore:;
1075 cirrus_bitblt_reset(s);
1076}
1077
1078static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1079{
1080 unsigned old_value;
1081
4e12cd94
AK		 1082 old_value = s->vga.gr[0x31];
1083 s->vga.gr[0x31] = reg_value;
e6e5ad80
FB		 1084
1085 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1086 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1087 cirrus_bitblt_reset(s);
1088 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1089 ((reg_value & CIRRUS_BLT_START) != 0)) {
e6e5ad80
FB		 1090 cirrus_bitblt_start(s);
1091 }
1092}
1093
1094
1095/***************************************
1096 *
1097 * basic parameters
1098 *
1099 ***************************************/
1100
a4a2f59c 1101static void cirrus_get_offsets(VGACommonState *s1,
83acc96b
FB		 1102 uint32_t *pline_offset,
1103 uint32_t *pstart_addr,
1104 uint32_t *pline_compare)
e6e5ad80 1105{
4e12cd94 1106 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
83acc96b 1107 uint32_t start_addr, line_offset, line_compare;
e6e5ad80 1108
4e12cd94
AK		 1109 line_offset = s->vga.cr[0x13]
1110 | ((s->vga.cr[0x1b] & 0x10) << 4);
e6e5ad80
FB		 1111 line_offset <<= 3;
1112 *pline_offset = line_offset;
1113
4e12cd94
AK		 1114 start_addr = (s->vga.cr[0x0c] << 8)
1115 | s->vga.cr[0x0d]
1116 | ((s->vga.cr[0x1b] & 0x01) << 16)
1117 | ((s->vga.cr[0x1b] & 0x0c) << 15)
1118 | ((s->vga.cr[0x1d] & 0x80) << 12);
e6e5ad80 1119 *pstart_addr = start_addr;
83acc96b 1120
4e12cd94
AK		 1121 line_compare = s->vga.cr[0x18] |
1122 ((s->vga.cr[0x07] & 0x10) << 4) |
1123 ((s->vga.cr[0x09] & 0x40) << 3);
83acc96b 1124 *pline_compare = line_compare;
e6e5ad80
FB		 1125}
1126
1127static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1128{
1129 uint32_t ret = 16;
1130
1131 switch (s->cirrus_hidden_dac_data & 0xf) {
1132 case 0:
1133 ret = 15;
1134 break; /* Sierra HiColor */
1135 case 1:
1136 ret = 16;
1137 break; /* XGA HiColor */
1138 default:
1139#ifdef DEBUG_CIRRUS
1140 printf("cirrus: invalid DAC value %x in 16bpp\n",
1141 (s->cirrus_hidden_dac_data & 0xf));
1142#endif
1143 ret = 15; /* XXX */
1144 break;
1145 }
1146 return ret;
1147}
1148
a4a2f59c 1149static int cirrus_get_bpp(VGACommonState *s1)
e6e5ad80 1150{
4e12cd94 1151 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
e6e5ad80
FB		 1152 uint32_t ret = 8;
1153
4e12cd94 1154 if ((s->vga.sr[0x07] & 0x01) != 0) {
e6e5ad80 1155 /* Cirrus SVGA */
4e12cd94 1156 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
e6e5ad80
FB		 1157 case CIRRUS_SR7_BPP_8:
1158 ret = 8;
1159 break;
1160 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1161 ret = cirrus_get_bpp16_depth(s);
1162 break;
1163 case CIRRUS_SR7_BPP_24:
1164 ret = 24;
1165 break;
1166 case CIRRUS_SR7_BPP_16:
1167 ret = cirrus_get_bpp16_depth(s);
1168 break;
1169 case CIRRUS_SR7_BPP_32:
1170 ret = 32;
1171 break;
1172 default:
1173#ifdef DEBUG_CIRRUS
4e12cd94 1174 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
e6e5ad80
FB		 1175#endif
1176 ret = 8;
1177 break;
1178 }
1179 } else {
1180 /* VGA */
aeb3c85f 1181 ret = 0;
e6e5ad80
FB		 1182 }
1183
1184 return ret;
1185}
1186
a4a2f59c 1187static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
78e127ef
FB		 1188{
1189 int width, height;
3b46e624 1190
78e127ef 1191 width = (s->cr[0x01] + 1) * 8;
5fafdf24
TS		 1192 height = s->cr[0x12] |
1193 ((s->cr[0x07] & 0x02) << 7) |
78e127ef
FB		 1194 ((s->cr[0x07] & 0x40) << 3);
1195 height = (height + 1);
1196 /* interlace support */
1197 if (s->cr[0x1a] & 0x01)
1198 height = height * 2;
1199 *pwidth = width;
1200 *pheight = height;
1201}
1202
e6e5ad80
FB		 1203/***************************************
1204 *
1205 * bank memory
1206 *
1207 ***************************************/
1208
1209static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1210{
1211 unsigned offset;
1212 unsigned limit;
1213
4e12cd94
AK		 1214 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */
1215 offset = s->vga.gr[0x09 + bank_index];
e6e5ad80 1216 else /* single bank */
4e12cd94 1217 offset = s->vga.gr[0x09];
e6e5ad80 1218
4e12cd94 1219 if ((s->vga.gr[0x0b] & 0x20) != 0)
e6e5ad80
FB		 1220 offset <<= 14;
1221 else
1222 offset <<= 12;
1223
e3a4e4b6 1224 if (s->real_vram_size <= offset)
e6e5ad80
FB		 1225 limit = 0;
1226 else
e3a4e4b6 1227 limit = s->real_vram_size - offset;
e6e5ad80 1228
4e12cd94 1229 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
e6e5ad80
FB		 1230 if (limit > 0x8000) {
1231 offset += 0x8000;
1232 limit -= 0x8000;
1233 } else {
1234 limit = 0;
1235 }
1236 }
1237
1238 if (limit > 0) {
1239 s->cirrus_bank_base[bank_index] = offset;
1240 s->cirrus_bank_limit[bank_index] = limit;
1241 } else {
1242 s->cirrus_bank_base[bank_index] = 0;
1243 s->cirrus_bank_limit[bank_index] = 0;
1244 }
1245}
1246
1247/***************************************
1248 *
1249 * I/O access between 0x3c4-0x3c5
1250 *
1251 ***************************************/
1252
8a82c322 1253static int cirrus_vga_read_sr(CirrusVGAState * s)
e6e5ad80 1254{
8a82c322 1255 switch (s->vga.sr_index) {
e6e5ad80
FB		 1256 case 0x00: // Standard VGA
1257 case 0x01: // Standard VGA
1258 case 0x02: // Standard VGA
1259 case 0x03: // Standard VGA
1260 case 0x04: // Standard VGA
8a82c322 1261 return s->vga.sr[s->vga.sr_index];
e6e5ad80 1262 case 0x06: // Unlock Cirrus extensions
8a82c322 1263 return s->vga.sr[s->vga.sr_index];
e6e5ad80
FB		 1264 case 0x10:
1265 case 0x30:
1266 case 0x50:
1267 case 0x70: // Graphics Cursor X
1268 case 0x90:
1269 case 0xb0:
1270 case 0xd0:
1271 case 0xf0: // Graphics Cursor X
8a82c322 1272 return s->vga.sr[0x10];
e6e5ad80
FB		 1273 case 0x11:
1274 case 0x31:
1275 case 0x51:
1276 case 0x71: // Graphics Cursor Y
1277 case 0x91:
1278 case 0xb1:
1279 case 0xd1:
a5082316 1280 case 0xf1: // Graphics Cursor Y
8a82c322 1281 return s->vga.sr[0x11];
aeb3c85f
FB		 1282 case 0x05: // ???
1283 case 0x07: // Extended Sequencer Mode
1284 case 0x08: // EEPROM Control
1285 case 0x09: // Scratch Register 0
1286 case 0x0a: // Scratch Register 1
1287 case 0x0b: // VCLK 0
1288 case 0x0c: // VCLK 1
1289 case 0x0d: // VCLK 2
1290 case 0x0e: // VCLK 3
1291 case 0x0f: // DRAM Control
e6e5ad80
FB		 1292 case 0x12: // Graphics Cursor Attribute
1293 case 0x13: // Graphics Cursor Pattern Address
1294 case 0x14: // Scratch Register 2
1295 case 0x15: // Scratch Register 3
1296 case 0x16: // Performance Tuning Register
1297 case 0x17: // Configuration Readback and Extended Control
1298 case 0x18: // Signature Generator Control
1299 case 0x19: // Signal Generator Result
1300 case 0x1a: // Signal Generator Result
1301 case 0x1b: // VCLK 0 Denominator & Post
1302 case 0x1c: // VCLK 1 Denominator & Post
1303 case 0x1d: // VCLK 2 Denominator & Post
1304 case 0x1e: // VCLK 3 Denominator & Post
1305 case 0x1f: // BIOS Write Enable and MCLK select
1306#ifdef DEBUG_CIRRUS
8a82c322 1307 printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
e6e5ad80 1308#endif
8a82c322 1309 return s->vga.sr[s->vga.sr_index];
e6e5ad80
FB		 1310 default:
1311#ifdef DEBUG_CIRRUS
8a82c322 1312 printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
e6e5ad80 1313#endif
8a82c322 1314 return 0xff;
e6e5ad80
FB		 1315 break;
1316 }
e6e5ad80
FB		 1317}
1318
31c63201 1319static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
e6e5ad80 1320{
31c63201 1321 switch (s->vga.sr_index) {
e6e5ad80
FB		 1322 case 0x00: // Standard VGA
1323 case 0x01: // Standard VGA
1324 case 0x02: // Standard VGA
1325 case 0x03: // Standard VGA
1326 case 0x04: // Standard VGA
31c63201
JQ		 1327 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
1328 if (s->vga.sr_index == 1)
1329 s->vga.update_retrace_info(&s->vga);
1330 break;
e6e5ad80 1331 case 0x06: // Unlock Cirrus extensions
31c63201
JQ		 1332 val &= 0x17;
1333 if (val == 0x12) {
1334 s->vga.sr[s->vga.sr_index] = 0x12;
e6e5ad80 1335 } else {
31c63201 1336 s->vga.sr[s->vga.sr_index] = 0x0f;
e6e5ad80
FB		 1337 }
1338 break;
1339 case 0x10:
1340 case 0x30:
1341 case 0x50:
1342 case 0x70: // Graphics Cursor X
1343 case 0x90:
1344 case 0xb0:
1345 case 0xd0:
1346 case 0xf0: // Graphics Cursor X
31c63201 1347 s->vga.sr[0x10] = val;
22382bb9 1348 s->vga.hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1349 break;
1350 case 0x11:
1351 case 0x31:
1352 case 0x51:
1353 case 0x71: // Graphics Cursor Y
1354 case 0x91:
1355 case 0xb1:
1356 case 0xd1:
1357 case 0xf1: // Graphics Cursor Y
31c63201 1358 s->vga.sr[0x11] = val;
22382bb9 1359 s->vga.hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1360 break;
1361 case 0x07: // Extended Sequencer Mode
edd7541b
PB		 1362 cirrus_update_memory_access(s);
1363 /* fall through */
e6e5ad80
FB		 1364 case 0x08: // EEPROM Control
1365 case 0x09: // Scratch Register 0
1366 case 0x0a: // Scratch Register 1
1367 case 0x0b: // VCLK 0
1368 case 0x0c: // VCLK 1
1369 case 0x0d: // VCLK 2
1370 case 0x0e: // VCLK 3
1371 case 0x0f: // DRAM Control
e6e5ad80
FB		 1372 case 0x13: // Graphics Cursor Pattern Address
1373 case 0x14: // Scratch Register 2
1374 case 0x15: // Scratch Register 3
1375 case 0x16: // Performance Tuning Register
e6e5ad80
FB		 1376 case 0x18: // Signature Generator Control
1377 case 0x19: // Signature Generator Result
1378 case 0x1a: // Signature Generator Result
1379 case 0x1b: // VCLK 0 Denominator & Post
1380 case 0x1c: // VCLK 1 Denominator & Post
1381 case 0x1d: // VCLK 2 Denominator & Post
1382 case 0x1e: // VCLK 3 Denominator & Post
1383 case 0x1f: // BIOS Write Enable and MCLK select
31c63201 1384 s->vga.sr[s->vga.sr_index] = val;
e6e5ad80
FB		 1385#ifdef DEBUG_CIRRUS
1386 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
31c63201 1387 s->vga.sr_index, val);
e6e5ad80
FB		 1388#endif
1389 break;
b9fd11b8
BH		 1390 case 0x12: // Graphics Cursor Attribute
1391 s->vga.sr[0x12] = val;
1392 s->vga.force_shadow = !!(val & CIRRUS_CURSOR_SHOW);
1393#ifdef DEBUG_CIRRUS
1394 printf("cirrus: cursor ctl SR12=%02x (force shadow: %d)\n",
1395 val, s->vga.force_shadow);
1396#endif
1397 break;
8926b517 1398 case 0x17: // Configuration Readback and Extended Control
31c63201
JQ		 1399 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
1400 | (val & 0xc7);
8926b517
FB		 1401 cirrus_update_memory_access(s);
1402 break;
e6e5ad80
FB		 1403 default:
1404#ifdef DEBUG_CIRRUS
31c63201
JQ		 1405 printf("cirrus: outport sr_index %02x, sr_value %02x\n",
1406 s->vga.sr_index, val);
e6e5ad80
FB		 1407#endif
1408 break;
1409 }
e6e5ad80
FB		 1410}
1411
1412/***************************************
1413 *
1414 * I/O access at 0x3c6
1415 *
1416 ***************************************/
1417
957c9db5 1418static int cirrus_read_hidden_dac(CirrusVGAState * s)
e6e5ad80 1419{
a21ae81d 1420 if (++s->cirrus_hidden_dac_lockindex == 5) {
957c9db5
JQ		 1421 s->cirrus_hidden_dac_lockindex = 0;
1422 return s->cirrus_hidden_dac_data;
e6e5ad80 1423 }
957c9db5 1424 return 0xff;
e6e5ad80
FB		 1425}
1426
1427static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1428{
1429 if (s->cirrus_hidden_dac_lockindex == 4) {
1430 s->cirrus_hidden_dac_data = reg_value;
a21ae81d 1431#if defined(DEBUG_CIRRUS)
e6e5ad80
FB		 1432 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1433#endif
1434 }
1435 s->cirrus_hidden_dac_lockindex = 0;
1436}
1437
1438/***************************************
1439 *
1440 * I/O access at 0x3c9
1441 *
1442 ***************************************/
1443
5deaeee3 1444static int cirrus_vga_read_palette(CirrusVGAState * s)
e6e5ad80 1445{
5deaeee3
JQ		 1446 int val;
1447
1448 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1449 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1450 s->vga.dac_sub_index];
1451 } else {
1452 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
1453 }
4e12cd94
AK		 1454 if (++s->vga.dac_sub_index == 3) {
1455 s->vga.dac_sub_index = 0;
1456 s->vga.dac_read_index++;
e6e5ad80 1457 }
5deaeee3 1458 return val;
e6e5ad80
FB		 1459}
1460
86948bb1 1461static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value)
e6e5ad80 1462{
4e12cd94
AK		 1463 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1464 if (++s->vga.dac_sub_index == 3) {
86948bb1
JQ		 1465 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1466 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1467 s->vga.dac_cache, 3);
1468 } else {
1469 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
1470 }
a5082316 1471 /* XXX update cursor */
4e12cd94
AK		 1472 s->vga.dac_sub_index = 0;
1473 s->vga.dac_write_index++;
e6e5ad80 1474 }
e6e5ad80
FB		 1475}
1476
1477/***************************************
1478 *
1479 * I/O access between 0x3ce-0x3cf
1480 *
1481 ***************************************/
1482
f705db9d 1483static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1484{
1485 switch (reg_index) {
aeb3c85f 1486 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
f705db9d 1487 return s->cirrus_shadow_gr0;
aeb3c85f 1488 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
f705db9d 1489 return s->cirrus_shadow_gr1;
e6e5ad80
FB		 1490 case 0x02: // Standard VGA
1491 case 0x03: // Standard VGA
1492 case 0x04: // Standard VGA
1493 case 0x06: // Standard VGA
1494 case 0x07: // Standard VGA
1495 case 0x08: // Standard VGA
f705db9d 1496 return s->vga.gr[s->vga.gr_index];
e6e5ad80
FB		 1497 case 0x05: // Standard VGA, Cirrus extended mode
1498 default:
1499 break;
1500 }
1501
1502 if (reg_index < 0x3a) {
f705db9d 1503 return s->vga.gr[reg_index];
e6e5ad80
FB		 1504 } else {
1505#ifdef DEBUG_CIRRUS
1506 printf("cirrus: inport gr_index %02x\n", reg_index);
1507#endif
f705db9d 1508 return 0xff;
e6e5ad80 1509 }
e6e5ad80
FB		 1510}
1511
22286bc6
JQ		 1512static void
1513cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
e6e5ad80 1514{
bee61ca2 1515 trace_vga_cirrus_write_gr(reg_index, reg_value);
e6e5ad80
FB		 1516 switch (reg_index) {
1517 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
f22f5b07 1518 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
aeb3c85f 1519 s->cirrus_shadow_gr0 = reg_value;
22286bc6 1520 break;
e6e5ad80 1521 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
f22f5b07 1522 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
aeb3c85f 1523 s->cirrus_shadow_gr1 = reg_value;
22286bc6 1524 break;
e6e5ad80
FB		 1525 case 0x02: // Standard VGA
1526 case 0x03: // Standard VGA
1527 case 0x04: // Standard VGA
1528 case 0x06: // Standard VGA
1529 case 0x07: // Standard VGA
1530 case 0x08: // Standard VGA
22286bc6
JQ		 1531 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1532 break;
e6e5ad80 1533 case 0x05: // Standard VGA, Cirrus extended mode
4e12cd94 1534 s->vga.gr[reg_index] = reg_value & 0x7f;
8926b517 1535 cirrus_update_memory_access(s);
e6e5ad80
FB		 1536 break;
1537 case 0x09: // bank offset #0
1538 case 0x0A: // bank offset #1
4e12cd94 1539 s->vga.gr[reg_index] = reg_value;
8926b517
FB		 1540 cirrus_update_bank_ptr(s, 0);
1541 cirrus_update_bank_ptr(s, 1);
2bec46dc 1542 cirrus_update_memory_access(s);
8926b517 1543 break;
e6e5ad80 1544 case 0x0B:
4e12cd94 1545 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1546 cirrus_update_bank_ptr(s, 0);
1547 cirrus_update_bank_ptr(s, 1);
8926b517 1548 cirrus_update_memory_access(s);
e6e5ad80
FB		 1549 break;
1550 case 0x10: // BGCOLOR 0x0000ff00
1551 case 0x11: // FGCOLOR 0x0000ff00
1552 case 0x12: // BGCOLOR 0x00ff0000
1553 case 0x13: // FGCOLOR 0x00ff0000
1554 case 0x14: // BGCOLOR 0xff000000
1555 case 0x15: // FGCOLOR 0xff000000
1556 case 0x20: // BLT WIDTH 0x0000ff
1557 case 0x22: // BLT HEIGHT 0x0000ff
1558 case 0x24: // BLT DEST PITCH 0x0000ff
1559 case 0x26: // BLT SRC PITCH 0x0000ff
1560 case 0x28: // BLT DEST ADDR 0x0000ff
1561 case 0x29: // BLT DEST ADDR 0x00ff00
1562 case 0x2c: // BLT SRC ADDR 0x0000ff
1563 case 0x2d: // BLT SRC ADDR 0x00ff00
a5082316 1564 case 0x2f: // BLT WRITEMASK
e6e5ad80
FB		 1565 case 0x30: // BLT MODE
1566 case 0x32: // RASTER OP
a21ae81d 1567 case 0x33: // BLT MODEEXT
e6e5ad80
FB		 1568 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1569 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1570 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1571 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
4e12cd94 1572 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1573 break;
1574 case 0x21: // BLT WIDTH 0x001f00
1575 case 0x23: // BLT HEIGHT 0x001f00
1576 case 0x25: // BLT DEST PITCH 0x001f00
1577 case 0x27: // BLT SRC PITCH 0x001f00
4e12cd94 1578 s->vga.gr[reg_index] = reg_value & 0x1f;
e6e5ad80
FB		 1579 break;
1580 case 0x2a: // BLT DEST ADDR 0x3f0000
4e12cd94 1581 s->vga.gr[reg_index] = reg_value & 0x3f;
a5082316 1582 /* if auto start mode, starts bit blt now */
4e12cd94 1583 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
a5082316
FB		 1584 cirrus_bitblt_start(s);
1585 }
1586 break;
e6e5ad80 1587 case 0x2e: // BLT SRC ADDR 0x3f0000
4e12cd94 1588 s->vga.gr[reg_index] = reg_value & 0x3f;
e6e5ad80
FB		 1589 break;
1590 case 0x31: // BLT STATUS/START
1591 cirrus_write_bitblt(s, reg_value);
1592 break;
1593 default:
1594#ifdef DEBUG_CIRRUS
1595 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1596 reg_value);
1597#endif
1598 break;
1599 }
e6e5ad80
FB		 1600}
1601
1602/***************************************
1603 *
1604 * I/O access between 0x3d4-0x3d5
1605 *
1606 ***************************************/
1607
b863d514 1608static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1609{
1610 switch (reg_index) {
1611 case 0x00: // Standard VGA
1612 case 0x01: // Standard VGA
1613 case 0x02: // Standard VGA
1614 case 0x03: // Standard VGA
1615 case 0x04: // Standard VGA
1616 case 0x05: // Standard VGA
1617 case 0x06: // Standard VGA
1618 case 0x07: // Standard VGA
1619 case 0x08: // Standard VGA
1620 case 0x09: // Standard VGA
1621 case 0x0a: // Standard VGA
1622 case 0x0b: // Standard VGA
1623 case 0x0c: // Standard VGA
1624 case 0x0d: // Standard VGA
1625 case 0x0e: // Standard VGA
1626 case 0x0f: // Standard VGA
1627 case 0x10: // Standard VGA
1628 case 0x11: // Standard VGA
1629 case 0x12: // Standard VGA
1630 case 0x13: // Standard VGA
1631 case 0x14: // Standard VGA
1632 case 0x15: // Standard VGA
1633 case 0x16: // Standard VGA
1634 case 0x17: // Standard VGA
1635 case 0x18: // Standard VGA
b863d514 1636 return s->vga.cr[s->vga.cr_index];
ca896ef3 1637 case 0x24: // Attribute Controller Toggle Readback (R)
b863d514 1638 return (s->vga.ar_flip_flop << 7);
e6e5ad80
FB		 1639 case 0x19: // Interlace End
1640 case 0x1a: // Miscellaneous Control
1641 case 0x1b: // Extended Display Control
1642 case 0x1c: // Sync Adjust and Genlock
1643 case 0x1d: // Overlay Extended Control
1644 case 0x22: // Graphics Data Latches Readback (R)
e6e5ad80
FB		 1645 case 0x25: // Part Status
1646 case 0x27: // Part ID (R)
b863d514 1647 return s->vga.cr[s->vga.cr_index];
e6e5ad80 1648 case 0x26: // Attribute Controller Index Readback (R)
b863d514 1649 return s->vga.ar_index & 0x3f;
e6e5ad80
FB		 1650 break;
1651 default:
1652#ifdef DEBUG_CIRRUS
1653 printf("cirrus: inport cr_index %02x\n", reg_index);
e6e5ad80 1654#endif
b863d514 1655 return 0xff;
e6e5ad80 1656 }
e6e5ad80
FB		 1657}
1658
4ec1ce04 1659static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
e6e5ad80 1660{
4ec1ce04 1661 switch (s->vga.cr_index) {
e6e5ad80
FB		 1662 case 0x00: // Standard VGA
1663 case 0x01: // Standard VGA
1664 case 0x02: // Standard VGA
1665 case 0x03: // Standard VGA
1666 case 0x04: // Standard VGA
1667 case 0x05: // Standard VGA
1668 case 0x06: // Standard VGA
1669 case 0x07: // Standard VGA
1670 case 0x08: // Standard VGA
1671 case 0x09: // Standard VGA
1672 case 0x0a: // Standard VGA
1673 case 0x0b: // Standard VGA
1674 case 0x0c: // Standard VGA
1675 case 0x0d: // Standard VGA
1676 case 0x0e: // Standard VGA
1677 case 0x0f: // Standard VGA
1678 case 0x10: // Standard VGA
1679 case 0x11: // Standard VGA
1680 case 0x12: // Standard VGA
1681 case 0x13: // Standard VGA
1682 case 0x14: // Standard VGA
1683 case 0x15: // Standard VGA
1684 case 0x16: // Standard VGA
1685 case 0x17: // Standard VGA
1686 case 0x18: // Standard VGA
4ec1ce04
JQ		 1687 /* handle CR0-7 protection */
1688 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
1689 /* can always write bit 4 of CR7 */
1690 if (s->vga.cr_index == 7)
1691 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10);
1692 return;
1693 }
1694 s->vga.cr[s->vga.cr_index] = reg_value;
1695 switch(s->vga.cr_index) {
1696 case 0x00:
1697 case 0x04:
1698 case 0x05:
1699 case 0x06:
1700 case 0x07:
1701 case 0x11:
1702 case 0x17:
1703 s->vga.update_retrace_info(&s->vga);
1704 break;
1705 }
1706 break;
e6e5ad80
FB		 1707 case 0x19: // Interlace End
1708 case 0x1a: // Miscellaneous Control
1709 case 0x1b: // Extended Display Control
1710 case 0x1c: // Sync Adjust and Genlock
ae184e4a 1711 case 0x1d: // Overlay Extended Control
4ec1ce04 1712 s->vga.cr[s->vga.cr_index] = reg_value;
e6e5ad80
FB		 1713#ifdef DEBUG_CIRRUS
1714 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
4ec1ce04 1715 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1716#endif
1717 break;
1718 case 0x22: // Graphics Data Latches Readback (R)
1719 case 0x24: // Attribute Controller Toggle Readback (R)
1720 case 0x26: // Attribute Controller Index Readback (R)
1721 case 0x27: // Part ID (R)
1722 break;
e6e5ad80
FB		 1723 case 0x25: // Part Status
1724 default:
1725#ifdef DEBUG_CIRRUS
4ec1ce04
JQ		 1726 printf("cirrus: outport cr_index %02x, cr_value %02x\n",
1727 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1728#endif
1729 break;
1730 }
e6e5ad80
FB		 1731}
1732
1733/***************************************
1734 *
1735 * memory-mapped I/O (bitblt)
1736 *
1737 ***************************************/
1738
1739static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1740{
1741 int value = 0xff;
1742
1743 switch (address) {
1744 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
f705db9d 1745 value = cirrus_vga_read_gr(s, 0x00);
e6e5ad80
FB		 1746 break;
1747 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
f705db9d 1748 value = cirrus_vga_read_gr(s, 0x10);
e6e5ad80
FB		 1749 break;
1750 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
f705db9d 1751 value = cirrus_vga_read_gr(s, 0x12);
e6e5ad80
FB		 1752 break;
1753 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
f705db9d 1754 value = cirrus_vga_read_gr(s, 0x14);
e6e5ad80
FB		 1755 break;
1756 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
f705db9d 1757 value = cirrus_vga_read_gr(s, 0x01);
e6e5ad80
FB		 1758 break;
1759 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
f705db9d 1760 value = cirrus_vga_read_gr(s, 0x11);
e6e5ad80
FB		 1761 break;
1762 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
f705db9d 1763 value = cirrus_vga_read_gr(s, 0x13);
e6e5ad80
FB		 1764 break;
1765 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
f705db9d 1766 value = cirrus_vga_read_gr(s, 0x15);
e6e5ad80
FB		 1767 break;
1768 case (CIRRUS_MMIO_BLTWIDTH + 0):
f705db9d 1769 value = cirrus_vga_read_gr(s, 0x20);
e6e5ad80
FB		 1770 break;
1771 case (CIRRUS_MMIO_BLTWIDTH + 1):
f705db9d 1772 value = cirrus_vga_read_gr(s, 0x21);
e6e5ad80
FB		 1773 break;
1774 case (CIRRUS_MMIO_BLTHEIGHT + 0):
f705db9d 1775 value = cirrus_vga_read_gr(s, 0x22);
e6e5ad80
FB		 1776 break;
1777 case (CIRRUS_MMIO_BLTHEIGHT + 1):
f705db9d 1778 value = cirrus_vga_read_gr(s, 0x23);
e6e5ad80
FB		 1779 break;
1780 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
f705db9d 1781 value = cirrus_vga_read_gr(s, 0x24);
e6e5ad80
FB		 1782 break;
1783 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
f705db9d 1784 value = cirrus_vga_read_gr(s, 0x25);
e6e5ad80
FB		 1785 break;
1786 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
f705db9d 1787 value = cirrus_vga_read_gr(s, 0x26);
e6e5ad80
FB		 1788 break;
1789 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
f705db9d 1790 value = cirrus_vga_read_gr(s, 0x27);
e6e5ad80
FB		 1791 break;
1792 case (CIRRUS_MMIO_BLTDESTADDR + 0):
f705db9d 1793 value = cirrus_vga_read_gr(s, 0x28);
e6e5ad80
FB		 1794 break;
1795 case (CIRRUS_MMIO_BLTDESTADDR + 1):
f705db9d 1796 value = cirrus_vga_read_gr(s, 0x29);
e6e5ad80
FB		 1797 break;
1798 case (CIRRUS_MMIO_BLTDESTADDR + 2):
f705db9d 1799 value = cirrus_vga_read_gr(s, 0x2a);
e6e5ad80
FB		 1800 break;
1801 case (CIRRUS_MMIO_BLTSRCADDR + 0):
f705db9d 1802 value = cirrus_vga_read_gr(s, 0x2c);
e6e5ad80
FB		 1803 break;
1804 case (CIRRUS_MMIO_BLTSRCADDR + 1):
f705db9d 1805 value = cirrus_vga_read_gr(s, 0x2d);
e6e5ad80
FB		 1806 break;
1807 case (CIRRUS_MMIO_BLTSRCADDR + 2):
f705db9d 1808 value = cirrus_vga_read_gr(s, 0x2e);
e6e5ad80
FB		 1809 break;
1810 case CIRRUS_MMIO_BLTWRITEMASK:
f705db9d 1811 value = cirrus_vga_read_gr(s, 0x2f);
e6e5ad80
FB		 1812 break;
1813 case CIRRUS_MMIO_BLTMODE:
f705db9d 1814 value = cirrus_vga_read_gr(s, 0x30);
e6e5ad80
FB		 1815 break;
1816 case CIRRUS_MMIO_BLTROP:
f705db9d 1817 value = cirrus_vga_read_gr(s, 0x32);
e6e5ad80 1818 break;
a21ae81d 1819 case CIRRUS_MMIO_BLTMODEEXT:
f705db9d 1820 value = cirrus_vga_read_gr(s, 0x33);
a21ae81d 1821 break;
e6e5ad80 1822 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
f705db9d 1823 value = cirrus_vga_read_gr(s, 0x34);
e6e5ad80
FB		 1824 break;
1825 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
f705db9d 1826 value = cirrus_vga_read_gr(s, 0x35);
e6e5ad80
FB		 1827 break;
1828 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
f705db9d 1829 value = cirrus_vga_read_gr(s, 0x38);
e6e5ad80
FB		 1830 break;
1831 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
f705db9d 1832 value = cirrus_vga_read_gr(s, 0x39);
e6e5ad80
FB		 1833 break;
1834 case CIRRUS_MMIO_BLTSTATUS:
f705db9d 1835 value = cirrus_vga_read_gr(s, 0x31);
e6e5ad80
FB		 1836 break;
1837 default:
1838#ifdef DEBUG_CIRRUS
1839 printf("cirrus: mmio read - address 0x%04x\n", address);
1840#endif
1841 break;
1842 }
1843
ec87f206 1844 trace_vga_cirrus_write_blt(address, value);
e6e5ad80
FB		 1845 return (uint8_t) value;
1846}
1847
1848static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1849 uint8_t value)
1850{
ec87f206 1851 trace_vga_cirrus_write_blt(address, value);
e6e5ad80
FB		 1852 switch (address) {
1853 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
22286bc6 1854 cirrus_vga_write_gr(s, 0x00, value);
e6e5ad80
FB		 1855 break;
1856 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
22286bc6 1857 cirrus_vga_write_gr(s, 0x10, value);
e6e5ad80
FB		 1858 break;
1859 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
22286bc6 1860 cirrus_vga_write_gr(s, 0x12, value);
e6e5ad80
FB		 1861 break;
1862 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
22286bc6 1863 cirrus_vga_write_gr(s, 0x14, value);
e6e5ad80
FB		 1864 break;
1865 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
22286bc6 1866 cirrus_vga_write_gr(s, 0x01, value);
e6e5ad80
FB		 1867 break;
1868 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
22286bc6 1869 cirrus_vga_write_gr(s, 0x11, value);
e6e5ad80
FB		 1870 break;
1871 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
22286bc6 1872 cirrus_vga_write_gr(s, 0x13, value);
e6e5ad80
FB		 1873 break;
1874 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
22286bc6 1875 cirrus_vga_write_gr(s, 0x15, value);
e6e5ad80
FB		 1876 break;
1877 case (CIRRUS_MMIO_BLTWIDTH + 0):
22286bc6 1878 cirrus_vga_write_gr(s, 0x20, value);
e6e5ad80
FB		 1879 break;
1880 case (CIRRUS_MMIO_BLTWIDTH + 1):
22286bc6 1881 cirrus_vga_write_gr(s, 0x21, value);
e6e5ad80
FB		 1882 break;
1883 case (CIRRUS_MMIO_BLTHEIGHT + 0):
22286bc6 1884 cirrus_vga_write_gr(s, 0x22, value);
e6e5ad80
FB		 1885 break;
1886 case (CIRRUS_MMIO_BLTHEIGHT + 1):
22286bc6 1887 cirrus_vga_write_gr(s, 0x23, value);
e6e5ad80
FB		 1888 break;
1889 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
22286bc6 1890 cirrus_vga_write_gr(s, 0x24, value);
e6e5ad80
FB		 1891 break;
1892 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
22286bc6 1893 cirrus_vga_write_gr(s, 0x25, value);
e6e5ad80
FB		 1894 break;
1895 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
22286bc6 1896 cirrus_vga_write_gr(s, 0x26, value);
e6e5ad80
FB		 1897 break;
1898 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
22286bc6 1899 cirrus_vga_write_gr(s, 0x27, value);
e6e5ad80
FB		 1900 break;
1901 case (CIRRUS_MMIO_BLTDESTADDR + 0):
22286bc6 1902 cirrus_vga_write_gr(s, 0x28, value);
e6e5ad80
FB		 1903 break;
1904 case (CIRRUS_MMIO_BLTDESTADDR + 1):
22286bc6 1905 cirrus_vga_write_gr(s, 0x29, value);
e6e5ad80
FB		 1906 break;
1907 case (CIRRUS_MMIO_BLTDESTADDR + 2):
22286bc6 1908 cirrus_vga_write_gr(s, 0x2a, value);
e6e5ad80
FB		 1909 break;
1910 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1911 /* ignored */
1912 break;
1913 case (CIRRUS_MMIO_BLTSRCADDR + 0):
22286bc6 1914 cirrus_vga_write_gr(s, 0x2c, value);
e6e5ad80
FB		 1915 break;
1916 case (CIRRUS_MMIO_BLTSRCADDR + 1):
22286bc6 1917 cirrus_vga_write_gr(s, 0x2d, value);
e6e5ad80
FB		 1918 break;
1919 case (CIRRUS_MMIO_BLTSRCADDR + 2):
22286bc6 1920 cirrus_vga_write_gr(s, 0x2e, value);
e6e5ad80
FB		 1921 break;
1922 case CIRRUS_MMIO_BLTWRITEMASK:
22286bc6 1923 cirrus_vga_write_gr(s, 0x2f, value);
e6e5ad80
FB		 1924 break;
1925 case CIRRUS_MMIO_BLTMODE:
22286bc6 1926 cirrus_vga_write_gr(s, 0x30, value);
e6e5ad80
FB		 1927 break;
1928 case CIRRUS_MMIO_BLTROP:
22286bc6 1929 cirrus_vga_write_gr(s, 0x32, value);
e6e5ad80 1930 break;
a21ae81d 1931 case CIRRUS_MMIO_BLTMODEEXT:
22286bc6 1932 cirrus_vga_write_gr(s, 0x33, value);
a21ae81d 1933 break;
e6e5ad80 1934 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
22286bc6 1935 cirrus_vga_write_gr(s, 0x34, value);
e6e5ad80
FB		 1936 break;
1937 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
22286bc6 1938 cirrus_vga_write_gr(s, 0x35, value);
e6e5ad80
FB		 1939 break;
1940 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
22286bc6 1941 cirrus_vga_write_gr(s, 0x38, value);
e6e5ad80
FB		 1942 break;
1943 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
22286bc6 1944 cirrus_vga_write_gr(s, 0x39, value);
e6e5ad80
FB		 1945 break;
1946 case CIRRUS_MMIO_BLTSTATUS:
22286bc6 1947 cirrus_vga_write_gr(s, 0x31, value);
e6e5ad80
FB		 1948 break;
1949 default:
1950#ifdef DEBUG_CIRRUS
1951 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1952 address, value);
1953#endif
1954 break;
1955 }
1956}
1957
e6e5ad80
FB		 1958/***************************************
1959 *
1960 * write mode 4/5
1961 *
e6e5ad80
FB		 1962 ***************************************/
1963
1964static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1965 unsigned mode,
1966 unsigned offset,
1967 uint32_t mem_value)
1968{
1969 int x;
1970 unsigned val = mem_value;
1971 uint8_t *dst;
1972
e6e5ad80 1973 for (x = 0; x < 8; x++) {
eb38e1bc 1974 dst = s->vga.vram_ptr + ((offset + x) & s->cirrus_addr_mask);
e6e5ad80 1975 if (val & 0x80) {
0b74ed78 1976 *dst = s->cirrus_shadow_gr1;
e6e5ad80 1977 } else if (mode == 5) {
0b74ed78 1978 *dst = s->cirrus_shadow_gr0;
e6e5ad80
FB		 1979 }
1980 val <<= 1;
1981 }
fd4aa979 1982 memory_region_set_dirty(&s->vga.vram, offset, 8);
e6e5ad80
FB		 1983}
1984
1985static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1986 unsigned mode,
1987 unsigned offset,
1988 uint32_t mem_value)
1989{
1990 int x;
1991 unsigned val = mem_value;
1992 uint8_t *dst;
1993
e6e5ad80 1994 for (x = 0; x < 8; x++) {
eb38e1bc 1995 dst = s->vga.vram_ptr + ((offset + 2 * x) & s->cirrus_addr_mask & ~1);
e6e5ad80 1996 if (val & 0x80) {
0b74ed78 1997 *dst = s->cirrus_shadow_gr1;
4e12cd94 1998 *(dst + 1) = s->vga.gr[0x11];
e6e5ad80 1999 } else if (mode == 5) {
0b74ed78 2000 *dst = s->cirrus_shadow_gr0;
4e12cd94 2001 *(dst + 1) = s->vga.gr[0x10];
e6e5ad80
FB		 2002 }
2003 val <<= 1;
2004 }
fd4aa979 2005 memory_region_set_dirty(&s->vga.vram, offset, 16);
e6e5ad80
FB		 2006}
2007
2008/***************************************
2009 *
2010 * memory access between 0xa0000-0xbffff
2011 *
2012 ***************************************/
2013
a815b166 2014static uint64_t cirrus_vga_mem_read(void *opaque,
a8170e5e 2015 hwaddr addr,
a815b166 2016 uint32_t size)
e6e5ad80
FB		 2017{
2018 CirrusVGAState *s = opaque;
2019 unsigned bank_index;
2020 unsigned bank_offset;
2021 uint32_t val;
2022
4e12cd94 2023 if ((s->vga.sr[0x07] & 0x01) == 0) {
b2a5e761 2024 return vga_mem_readb(&s->vga, addr);
e6e5ad80
FB		 2025 }
2026
2027 if (addr < 0x10000) {
2028 /* XXX handle bitblt */
2029 /* video memory */
2030 bank_index = addr >> 15;
2031 bank_offset = addr & 0x7fff;
2032 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2033 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 2034 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2035 bank_offset <<= 4;
4e12cd94 2036 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2037 bank_offset <<= 3;
2038 }
2039 bank_offset &= s->cirrus_addr_mask;
4e12cd94 2040 val = *(s->vga.vram_ptr + bank_offset);
e6e5ad80
FB		 2041 } else
2042 val = 0xff;
2043 } else if (addr >= 0x18000 && addr < 0x18100) {
2044 /* memory-mapped I/O */
2045 val = 0xff;
4e12cd94 2046 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 2047 val = cirrus_mmio_blt_read(s, addr & 0xff);
2048 }
2049 } else {
2050 val = 0xff;
2051#ifdef DEBUG_CIRRUS
0bf9e31a 2052 printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
e6e5ad80
FB		 2053#endif
2054 }
2055 return val;
2056}
2057
a815b166 2058static void cirrus_vga_mem_write(void *opaque,
a8170e5e 2059 hwaddr addr,
a815b166
AK		 2060 uint64_t mem_value,
2061 uint32_t size)
e6e5ad80
FB		 2062{
2063 CirrusVGAState *s = opaque;
2064 unsigned bank_index;
2065 unsigned bank_offset;
2066 unsigned mode;
2067
4e12cd94 2068 if ((s->vga.sr[0x07] & 0x01) == 0) {
b2a5e761 2069 vga_mem_writeb(&s->vga, addr, mem_value);
e6e5ad80
FB		 2070 return;
2071 }
2072
2073 if (addr < 0x10000) {
2074 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2075 /* bitblt */
2076 *s->cirrus_srcptr++ = (uint8_t) mem_value;
a5082316 2077 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2078 cirrus_bitblt_cputovideo_next(s);
2079 }
2080 } else {
2081 /* video memory */
2082 bank_index = addr >> 15;
2083 bank_offset = addr & 0x7fff;
2084 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2085 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 2086 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2087 bank_offset <<= 4;
4e12cd94 2088 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2089 bank_offset <<= 3;
2090 }
2091 bank_offset &= s->cirrus_addr_mask;
4e12cd94
AK		 2092 mode = s->vga.gr[0x05] & 0x7;
2093 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2094 *(s->vga.vram_ptr + bank_offset) = mem_value;
fd4aa979
BS		 2095 memory_region_set_dirty(&s->vga.vram, bank_offset,
2096 sizeof(mem_value));
e6e5ad80 2097 } else {
4e12cd94 2098 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2099 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2100 bank_offset,
2101 mem_value);
2102 } else {
2103 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2104 bank_offset,
2105 mem_value);
2106 }
2107 }
2108 }
2109 }
2110 } else if (addr >= 0x18000 && addr < 0x18100) {
2111 /* memory-mapped I/O */
4e12cd94 2112 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 2113 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2114 }
2115 } else {
2116#ifdef DEBUG_CIRRUS
e8ee4b68 2117 printf("cirrus: mem_writeb " TARGET_FMT_plx " value 0x%02" PRIu64 "\n", addr,
08406b03 2118 mem_value);
e6e5ad80
FB		 2119#endif
2120 }
2121}
2122
b1950430
AK		 2123static const MemoryRegionOps cirrus_vga_mem_ops = {
2124 .read = cirrus_vga_mem_read,
2125 .write = cirrus_vga_mem_write,
2126 .endianness = DEVICE_LITTLE_ENDIAN,
a815b166
AK		 2127 .impl = {
2128 .min_access_size = 1,
2129 .max_access_size = 1,
2130 },
e6e5ad80
FB		 2131};
2132
a5082316
FB		 2133/***************************************
2134 *
2135 * hardware cursor
2136 *
2137 ***************************************/
2138
2139static inline void invalidate_cursor1(CirrusVGAState *s)
2140{
2141 if (s->last_hw_cursor_size) {
4e12cd94 2142 vga_invalidate_scanlines(&s->vga,
a5082316
FB		 2143 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2144 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2145 }
2146}
2147
2148static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2149{
2150 const uint8_t *src;
2151 uint32_t content;
2152 int y, y_min, y_max;
2153
f0353b0d 2154 src = s->vga.vram_ptr + s->real_vram_size - 16 * KiB;
4e12cd94
AK		 2155 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2156 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2157 y_min = 64;
2158 y_max = -1;
2159 for(y = 0; y < 64; y++) {
2160 content = ((uint32_t *)src)[0] |
2161 ((uint32_t *)src)[1] |
2162 ((uint32_t *)src)[2] |
2163 ((uint32_t *)src)[3];
2164 if (content) {
2165 if (y < y_min)
2166 y_min = y;
2167 if (y > y_max)
2168 y_max = y;
2169 }
2170 src += 16;
2171 }
2172 } else {
4e12cd94 2173 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316
FB		 2174 y_min = 32;
2175 y_max = -1;
2176 for(y = 0; y < 32; y++) {
2177 content = ((uint32_t *)src)[0] |
2178 ((uint32_t *)(src + 128))[0];
2179 if (content) {
2180 if (y < y_min)
2181 y_min = y;
2182 if (y > y_max)
2183 y_max = y;
2184 }
2185 src += 4;
2186 }
2187 }
2188 if (y_min > y_max) {
2189 s->last_hw_cursor_y_start = 0;
2190 s->last_hw_cursor_y_end = 0;
2191 } else {
2192 s->last_hw_cursor_y_start = y_min;
2193 s->last_hw_cursor_y_end = y_max + 1;
2194 }
2195}
2196
2197/* NOTE: we do not currently handle the cursor bitmap change, so we
2198 update the cursor only if it moves. */
a4a2f59c 2199static void cirrus_cursor_invalidate(VGACommonState *s1)
a5082316 2200{
4e12cd94 2201 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
a5082316
FB		 2202 int size;
2203
4e12cd94 2204 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
a5082316
FB		 2205 size = 0;
2206 } else {
4e12cd94 2207 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
a5082316
FB		 2208 size = 64;
2209 else
2210 size = 32;
2211 }
2212 /* invalidate last cursor and new cursor if any change */
2213 if (s->last_hw_cursor_size != size ||
22382bb9
GH		 2214 s->last_hw_cursor_x != s->vga.hw_cursor_x ||
2215 s->last_hw_cursor_y != s->vga.hw_cursor_y) {
a5082316
FB		 2216
2217 invalidate_cursor1(s);
3b46e624 2218
a5082316 2219 s->last_hw_cursor_size = size;
22382bb9
GH		 2220 s->last_hw_cursor_x = s->vga.hw_cursor_x;
2221 s->last_hw_cursor_y = s->vga.hw_cursor_y;
a5082316
FB		 2222 /* compute the real cursor min and max y */
2223 cirrus_cursor_compute_yrange(s);
2224 invalidate_cursor1(s);
2225 }
2226}
2227
70a041fe
BH		 2228static void vga_draw_cursor_line(uint8_t *d1,
2229 const uint8_t *src1,
2230 int poffset, int w,
2231 unsigned int color0,
2232 unsigned int color1,
2233 unsigned int color_xor)
2234{
2235 const uint8_t *plane0, *plane1;
2236 int x, b0, b1;
2237 uint8_t *d;
2238
2239 d = d1;
2240 plane0 = src1;
2241 plane1 = src1 + poffset;
2242 for (x = 0; x < w; x++) {
2243 b0 = (plane0[x >> 3] >> (7 - (x & 7))) & 1;
2244 b1 = (plane1[x >> 3] >> (7 - (x & 7))) & 1;
2245 switch (b0 | (b1 << 1)) {
2246 case 0:
2247 break;
2248 case 1:
2249 ((uint32_t *)d)[0] ^= color_xor;
2250 break;
2251 case 2:
2252 ((uint32_t *)d)[0] = color0;
2253 break;
2254 case 3:
2255 ((uint32_t *)d)[0] = color1;
2256 break;
2257 }
2258 d += 4;
2259 }
2260}
94d7b483 2261
a4a2f59c 2262static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
a5082316 2263{
4e12cd94 2264 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
70a041fe 2265 int w, h, x1, x2, poffset;
a5082316
FB		 2266 unsigned int color0, color1;
2267 const uint8_t *palette, *src;
2268 uint32_t content;
3b46e624 2269
4e12cd94 2270 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
a5082316
FB		 2271 return;
2272 /* fast test to see if the cursor intersects with the scan line */
4e12cd94 2273 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
a5082316
FB		 2274 h = 64;
2275 } else {
2276 h = 32;
2277 }
22382bb9
GH		 2278 if (scr_y < s->vga.hw_cursor_y ||
2279 scr_y >= (s->vga.hw_cursor_y + h)) {
a5082316 2280 return;
22382bb9 2281 }
3b46e624 2282
f0353b0d 2283 src = s->vga.vram_ptr + s->real_vram_size - 16 * KiB;
4e12cd94
AK		 2284 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2285 src += (s->vga.sr[0x13] & 0x3c) * 256;
22382bb9 2286 src += (scr_y - s->vga.hw_cursor_y) * 16;
a5082316
FB		 2287 poffset = 8;
2288 content = ((uint32_t *)src)[0] |
2289 ((uint32_t *)src)[1] |
2290 ((uint32_t *)src)[2] |
2291 ((uint32_t *)src)[3];
2292 } else {
4e12cd94 2293 src += (s->vga.sr[0x13] & 0x3f) * 256;
22382bb9 2294 src += (scr_y - s->vga.hw_cursor_y) * 4;
d3c2343a
BH		 2295
2296
a5082316
FB		 2297 poffset = 128;
2298 content = ((uint32_t *)src)[0] |
2299 ((uint32_t *)(src + 128))[0];
2300 }
2301 /* if nothing to draw, no need to continue */
2302 if (!content)
2303 return;
2304 w = h;
2305
22382bb9 2306 x1 = s->vga.hw_cursor_x;
4e12cd94 2307 if (x1 >= s->vga.last_scr_width)
a5082316 2308 return;
22382bb9 2309 x2 = s->vga.hw_cursor_x + w;
4e12cd94
AK		 2310 if (x2 > s->vga.last_scr_width)
2311 x2 = s->vga.last_scr_width;
a5082316
FB		 2312 w = x2 - x1;
2313 palette = s->cirrus_hidden_palette;
d3c2343a
BH		 2314 color0 = rgb_to_pixel32(c6_to_8(palette[0x0 * 3]),
2315 c6_to_8(palette[0x0 * 3 + 1]),
2316 c6_to_8(palette[0x0 * 3 + 2]));
2317 color1 = rgb_to_pixel32(c6_to_8(palette[0xf * 3]),
2318 c6_to_8(palette[0xf * 3 + 1]),
2319 c6_to_8(palette[0xf * 3 + 2]));
70a041fe
BH		 2320 d1 += x1 * 4;
2321 vga_draw_cursor_line(d1, src, poffset, w, color0, color1, 0xffffff);
a5082316
FB		 2322}
2323
e6e5ad80
FB		 2324/***************************************
2325 *
2326 * LFB memory access
2327 *
2328 ***************************************/
2329
a8170e5e 2330static uint64_t cirrus_linear_read(void *opaque, hwaddr addr,
899adf81 2331 unsigned size)
e6e5ad80 2332{
e05587e8 2333 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2334 uint32_t ret;
2335
e6e5ad80
FB		 2336 addr &= s->cirrus_addr_mask;
2337
4e12cd94 2338 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2339 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2340 /* memory-mapped I/O */
2341 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2342 } else if (0) {
2343 /* XXX handle bitblt */
2344 ret = 0xff;
2345 } else {
2346 /* video memory */
4e12cd94 2347 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2348 addr <<= 4;
4e12cd94 2349 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2350 addr <<= 3;
2351 }
2352 addr &= s->cirrus_addr_mask;
4e12cd94 2353 ret = *(s->vga.vram_ptr + addr);
e6e5ad80
FB		 2354 }
2355
2356 return ret;
2357}
2358
a8170e5e 2359static void cirrus_linear_write(void *opaque, hwaddr addr,
899adf81 2360 uint64_t val, unsigned size)
e6e5ad80 2361{
e05587e8 2362 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2363 unsigned mode;
2364
2365 addr &= s->cirrus_addr_mask;
3b46e624 2366
4e12cd94 2367 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2368 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2369 /* memory-mapped I/O */
2370 cirrus_mmio_blt_write(s, addr & 0xff, val);
2371 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2372 /* bitblt */
2373 *s->cirrus_srcptr++ = (uint8_t) val;
a5082316 2374 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2375 cirrus_bitblt_cputovideo_next(s);
2376 }
2377 } else {
2378 /* video memory */
4e12cd94 2379 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2380 addr <<= 4;
4e12cd94 2381 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2382 addr <<= 3;
2383 }
2384 addr &= s->cirrus_addr_mask;
2385
4e12cd94
AK		 2386 mode = s->vga.gr[0x05] & 0x7;
2387 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2388 *(s->vga.vram_ptr + addr) = (uint8_t) val;
fd4aa979 2389 memory_region_set_dirty(&s->vga.vram, addr, 1);
e6e5ad80 2390 } else {
4e12cd94 2391 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2392 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2393 } else {
2394 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2395 }
2396 }
2397 }
2398}
2399
a5082316
FB		 2400/***************************************
2401 *
2402 * system to screen memory access
2403 *
2404 ***************************************/
2405
2406
4e56f089 2407static uint64_t cirrus_linear_bitblt_read(void *opaque,
a8170e5e 2408 hwaddr addr,
4e56f089 2409 unsigned size)
a5082316 2410{
4e56f089 2411 CirrusVGAState *s = opaque;
a5082316
FB		 2412
2413 /* XXX handle bitblt */
4e56f089 2414 (void)s;
b3ac2b94 2415 return 0xff;
a5082316
FB		 2416}
2417
4e56f089 2418static void cirrus_linear_bitblt_write(void *opaque,
a8170e5e 2419 hwaddr addr,
4e56f089
AK		 2420 uint64_t val,
2421 unsigned size)
a5082316 2422{
e05587e8 2423 CirrusVGAState *s = opaque;
a5082316
FB		 2424
2425 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2426 /* bitblt */
2427 *s->cirrus_srcptr++ = (uint8_t) val;
2428 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2429 cirrus_bitblt_cputovideo_next(s);
2430 }
2431 }
2432}
2433
b1950430
AK		 2434static const MemoryRegionOps cirrus_linear_bitblt_io_ops = {
2435 .read = cirrus_linear_bitblt_read,
2436 .write = cirrus_linear_bitblt_write,
2437 .endianness = DEVICE_LITTLE_ENDIAN,
4e56f089
AK		 2438 .impl = {
2439 .min_access_size = 1,
2440 .max_access_size = 1,
2441 },
a5082316
FB		 2442};
2443
b1950430
AK		 2444static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank)
2445{
7969d9ed
AK		 2446 MemoryRegion *mr = &s->cirrus_bank[bank];
2447 bool enabled = !(s->cirrus_srcptr != s->cirrus_srcptr_end)
4e12cd94
AK		 2448 && !((s->vga.sr[0x07] & 0x01) == 0)
2449 && !((s->vga.gr[0x0B] & 0x14) == 0x14)
7969d9ed
AK		 2450 && !(s->vga.gr[0x0B] & 0x02);
2451
2452 memory_region_set_enabled(mr, enabled);
2453 memory_region_set_alias_offset(mr, s->cirrus_bank_base[bank]);
b1950430 2454}
2bec46dc 2455
b1950430
AK		 2456static void map_linear_vram(CirrusVGAState *s)
2457{
4c08fd1e 2458 if (s->bustype == CIRRUS_BUSTYPE_PCI && !s->linear_vram) {
b1950430
AK		 2459 s->linear_vram = true;
2460 memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1);
2461 }
2462 map_linear_vram_bank(s, 0);
2463 map_linear_vram_bank(s, 1);
2bec46dc
AL		 2464}
2465
2466static void unmap_linear_vram(CirrusVGAState *s)
2467{
4c08fd1e 2468 if (s->bustype == CIRRUS_BUSTYPE_PCI && s->linear_vram) {
b1950430
AK		 2469 s->linear_vram = false;
2470 memory_region_del_subregion(&s->pci_bar, &s->vga.vram);
4516e45f 2471 }
7969d9ed
AK		 2472 memory_region_set_enabled(&s->cirrus_bank[0], false);
2473 memory_region_set_enabled(&s->cirrus_bank[1], false);
2bec46dc
AL		 2474}
2475
8926b517
FB		 2476/* Compute the memory access functions */
2477static void cirrus_update_memory_access(CirrusVGAState *s)
2478{
2479 unsigned mode;
2480
64c048f4 2481 memory_region_transaction_begin();
4e12cd94 2482 if ((s->vga.sr[0x17] & 0x44) == 0x44) {
8926b517
FB		 2483 goto generic_io;
2484 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2485 goto generic_io;
2486 } else {
4e12cd94 2487 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
8926b517 2488 goto generic_io;
4e12cd94 2489 } else if (s->vga.gr[0x0B] & 0x02) {
8926b517
FB		 2490 goto generic_io;
2491 }
3b46e624 2492
4e12cd94
AK		 2493 mode = s->vga.gr[0x05] & 0x7;
2494 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2bec46dc 2495 map_linear_vram(s);
8926b517
FB		 2496 } else {
2497 generic_io:
2bec46dc 2498 unmap_linear_vram(s);
8926b517
FB		 2499 }
2500 }
64c048f4 2501 memory_region_transaction_commit();
8926b517
FB		 2502}
2503
2504
e6e5ad80
FB		 2505/* I/O ports */
2506
c75e6d8e
JG		 2507static uint64_t cirrus_vga_ioport_read(void *opaque, hwaddr addr,
2508 unsigned size)
e6e5ad80 2509{
b6343073
JQ		 2510 CirrusVGAState *c = opaque;
2511 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2512 int val, index;
2513
c75e6d8e 2514 addr += 0x3b0;
bd8f2f5d 2515
b6343073 2516 if (vga_ioport_invalid(s, addr)) {
e6e5ad80
FB		 2517 val = 0xff;
2518 } else {
2519 switch (addr) {
2520 case 0x3c0:
b6343073
JQ		 2521 if (s->ar_flip_flop == 0) {
2522 val = s->ar_index;
e6e5ad80
FB		 2523 } else {
2524 val = 0;
2525 }
2526 break;
2527 case 0x3c1:
b6343073 2528 index = s->ar_index & 0x1f;
e6e5ad80 2529 if (index < 21)
b6343073 2530 val = s->ar[index];
e6e5ad80
FB		 2531 else
2532 val = 0;
2533 break;
2534 case 0x3c2:
b6343073 2535 val = s->st00;
e6e5ad80
FB		 2536 break;
2537 case 0x3c4:
b6343073 2538 val = s->sr_index;
e6e5ad80
FB		 2539 break;
2540 case 0x3c5:
8a82c322
JQ		 2541 val = cirrus_vga_read_sr(c);
2542 break;
e6e5ad80 2543#ifdef DEBUG_VGA_REG
b6343073 2544 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
e6e5ad80
FB		 2545#endif
2546 break;
2547 case 0x3c6:
957c9db5 2548 val = cirrus_read_hidden_dac(c);
e6e5ad80
FB		 2549 break;
2550 case 0x3c7:
b6343073 2551 val = s->dac_state;
e6e5ad80 2552 break;
ae184e4a 2553 case 0x3c8:
b6343073
JQ		 2554 val = s->dac_write_index;
2555 c->cirrus_hidden_dac_lockindex = 0;
ae184e4a
FB		 2556 break;
2557 case 0x3c9:
5deaeee3
JQ		 2558 val = cirrus_vga_read_palette(c);
2559 break;
e6e5ad80 2560 case 0x3ca:
b6343073 2561 val = s->fcr;
e6e5ad80
FB		 2562 break;
2563 case 0x3cc:
b6343073 2564 val = s->msr;
e6e5ad80
FB		 2565 break;
2566 case 0x3ce:
b6343073 2567 val = s->gr_index;
e6e5ad80
FB		 2568 break;
2569 case 0x3cf:
f705db9d 2570 val = cirrus_vga_read_gr(c, s->gr_index);
e6e5ad80 2571#ifdef DEBUG_VGA_REG
b6343073 2572 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
e6e5ad80
FB		 2573#endif
2574 break;
2575 case 0x3b4:
2576 case 0x3d4:
b6343073 2577 val = s->cr_index;
e6e5ad80
FB		 2578 break;
2579 case 0x3b5:
2580 case 0x3d5:
b863d514 2581 val = cirrus_vga_read_cr(c, s->cr_index);
e6e5ad80 2582#ifdef DEBUG_VGA_REG
b6343073 2583 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80
FB		 2584#endif
2585 break;
2586 case 0x3ba:
2587 case 0x3da:
2588 /* just toggle to fool polling */
b6343073
JQ		 2589 val = s->st01 = s->retrace(s);
2590 s->ar_flip_flop = 0;
e6e5ad80
FB		 2591 break;
2592 default:
2593 val = 0x00;
2594 break;
2595 }
2596 }
ec87f206 2597 trace_vga_cirrus_read_io(addr, val);
e6e5ad80
FB		 2598 return val;
2599}
2600
c75e6d8e
JG		 2601static void cirrus_vga_ioport_write(void *opaque, hwaddr addr, uint64_t val,
2602 unsigned size)
e6e5ad80 2603{
b6343073
JQ		 2604 CirrusVGAState *c = opaque;
2605 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2606 int index;
2607
c75e6d8e 2608 addr += 0x3b0;
bd8f2f5d 2609
e6e5ad80 2610 /* check port range access depending on color/monochrome mode */
b6343073 2611 if (vga_ioport_invalid(s, addr)) {
e6e5ad80 2612 return;
25a18cbd 2613 }
ec87f206 2614 trace_vga_cirrus_write_io(addr, val);
e6e5ad80
FB		 2615
2616 switch (addr) {
2617 case 0x3c0:
b6343073 2618 if (s->ar_flip_flop == 0) {
e6e5ad80 2619 val &= 0x3f;
b6343073 2620 s->ar_index = val;
e6e5ad80 2621 } else {
b6343073 2622 index = s->ar_index & 0x1f;
e6e5ad80
FB		 2623 switch (index) {
2624 case 0x00 ... 0x0f:
b6343073 2625 s->ar[index] = val & 0x3f;
e6e5ad80
FB		 2626 break;
2627 case 0x10:
b6343073 2628 s->ar[index] = val & ~0x10;
e6e5ad80
FB		 2629 break;
2630 case 0x11:
b6343073 2631 s->ar[index] = val;
e6e5ad80
FB		 2632 break;
2633 case 0x12:
b6343073 2634 s->ar[index] = val & ~0xc0;
e6e5ad80
FB		 2635 break;
2636 case 0x13:
b6343073 2637 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2638 break;
2639 case 0x14:
b6343073 2640 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2641 break;
2642 default:
2643 break;
2644 }
2645 }
b6343073 2646 s->ar_flip_flop ^= 1;
e6e5ad80
FB		 2647 break;
2648 case 0x3c2:
b6343073
JQ		 2649 s->msr = val & ~0x10;
2650 s->update_retrace_info(s);
e6e5ad80
FB		 2651 break;
2652 case 0x3c4:
b6343073 2653 s->sr_index = val;
e6e5ad80
FB		 2654 break;
2655 case 0x3c5:
e6e5ad80 2656#ifdef DEBUG_VGA_REG
e8ee4b68 2657 printf("vga: write SR%x = 0x%02" PRIu64 "\n", s->sr_index, val);
e6e5ad80 2658#endif
31c63201
JQ		 2659 cirrus_vga_write_sr(c, val);
2660 break;
e6e5ad80 2661 case 0x3c6:
b6343073 2662 cirrus_write_hidden_dac(c, val);
e6e5ad80
FB		 2663 break;
2664 case 0x3c7:
b6343073
JQ		 2665 s->dac_read_index = val;
2666 s->dac_sub_index = 0;
2667 s->dac_state = 3;
e6e5ad80
FB		 2668 break;
2669 case 0x3c8:
b6343073
JQ		 2670 s->dac_write_index = val;
2671 s->dac_sub_index = 0;
2672 s->dac_state = 0;
e6e5ad80
FB		 2673 break;
2674 case 0x3c9:
86948bb1
JQ		 2675 cirrus_vga_write_palette(c, val);
2676 break;
e6e5ad80 2677 case 0x3ce:
b6343073 2678 s->gr_index = val;
e6e5ad80
FB		 2679 break;
2680 case 0x3cf:
e6e5ad80 2681#ifdef DEBUG_VGA_REG
e8ee4b68 2682 printf("vga: write GR%x = 0x%02" PRIu64 "\n", s->gr_index, val);
e6e5ad80 2683#endif
22286bc6 2684 cirrus_vga_write_gr(c, s->gr_index, val);
e6e5ad80
FB		 2685 break;
2686 case 0x3b4:
2687 case 0x3d4:
b6343073 2688 s->cr_index = val;
e6e5ad80
FB		 2689 break;
2690 case 0x3b5:
2691 case 0x3d5:
e6e5ad80 2692#ifdef DEBUG_VGA_REG
e8ee4b68 2693 printf("vga: write CR%x = 0x%02"PRIu64"\n", s->cr_index, val);
e6e5ad80 2694#endif
4ec1ce04 2695 cirrus_vga_write_cr(c, val);
e6e5ad80
FB		 2696 break;
2697 case 0x3ba:
2698 case 0x3da:
b6343073 2699 s->fcr = val & 0x10;
e6e5ad80
FB		 2700 break;
2701 }
2702}
2703
e36f36e1
FB		 2704/***************************************
2705 *
2706 * memory-mapped I/O access
2707 *
2708 ***************************************/
2709
a8170e5e 2710static uint64_t cirrus_mmio_read(void *opaque, hwaddr addr,
1e04d4d6 2711 unsigned size)
e36f36e1 2712{
e05587e8 2713 CirrusVGAState *s = opaque;
e36f36e1 2714
e36f36e1
FB		 2715 if (addr >= 0x100) {
2716 return cirrus_mmio_blt_read(s, addr - 0x100);
2717 } else {
c75e6d8e 2718 return cirrus_vga_ioport_read(s, addr + 0x10, size);
e36f36e1
FB		 2719 }
2720}
2721
a8170e5e 2722static void cirrus_mmio_write(void *opaque, hwaddr addr,
1e04d4d6 2723 uint64_t val, unsigned size)
e36f36e1 2724{
e05587e8 2725 CirrusVGAState *s = opaque;
e36f36e1 2726
e36f36e1
FB		 2727 if (addr >= 0x100) {
2728 cirrus_mmio_blt_write(s, addr - 0x100, val);
2729 } else {
c75e6d8e 2730 cirrus_vga_ioport_write(s, addr + 0x10, val, size);
e36f36e1
FB		 2731 }
2732}
2733
b1950430
AK		 2734static const MemoryRegionOps cirrus_mmio_io_ops = {
2735 .read = cirrus_mmio_read,
2736 .write = cirrus_mmio_write,
2737 .endianness = DEVICE_LITTLE_ENDIAN,
1e04d4d6
AK		 2738 .impl = {
2739 .min_access_size = 1,
2740 .max_access_size = 1,
2741 },
e36f36e1
FB		 2742};
2743
2c6ab832
FB		 2744/* load/save state */
2745
e59fb374 2746static int cirrus_post_load(void *opaque, int version_id)
2c6ab832
FB		 2747{
2748 CirrusVGAState *s = opaque;
2749
4e12cd94
AK		 2750 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
2751 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
2c6ab832 2752
b7ee9e49
WX		 2753 cirrus_update_bank_ptr(s, 0);
2754 cirrus_update_bank_ptr(s, 1);
2bec46dc 2755 cirrus_update_memory_access(s);
2c6ab832 2756 /* force refresh */
4e12cd94 2757 s->vga.graphic_mode = -1;
b7ee9e49 2758
2c6ab832
FB		 2759 return 0;
2760}
2761
ce3cf70e 2762const VMStateDescription vmstate_cirrus_vga = {
7e72abc3
JQ		 2763 .name = "cirrus_vga",
2764 .version_id = 2,
2765 .minimum_version_id = 1,
7e72abc3 2766 .post_load = cirrus_post_load,
d49805ae 2767 .fields = (VMStateField[]) {
7e72abc3
JQ		 2768 VMSTATE_UINT32(vga.latch, CirrusVGAState),
2769 VMSTATE_UINT8(vga.sr_index, CirrusVGAState),
2770 VMSTATE_BUFFER(vga.sr, CirrusVGAState),
2771 VMSTATE_UINT8(vga.gr_index, CirrusVGAState),
2772 VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState),
2773 VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState),
2774 VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
2775 VMSTATE_UINT8(vga.ar_index, CirrusVGAState),
2776 VMSTATE_BUFFER(vga.ar, CirrusVGAState),
2777 VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState),
2778 VMSTATE_UINT8(vga.cr_index, CirrusVGAState),
2779 VMSTATE_BUFFER(vga.cr, CirrusVGAState),
2780 VMSTATE_UINT8(vga.msr, CirrusVGAState),
2781 VMSTATE_UINT8(vga.fcr, CirrusVGAState),
2782 VMSTATE_UINT8(vga.st00, CirrusVGAState),
2783 VMSTATE_UINT8(vga.st01, CirrusVGAState),
2784 VMSTATE_UINT8(vga.dac_state, CirrusVGAState),
2785 VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState),
2786 VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState),
2787 VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState),
2788 VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState),
2789 VMSTATE_BUFFER(vga.palette, CirrusVGAState),
2790 VMSTATE_INT32(vga.bank_offset, CirrusVGAState),
2791 VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState),
2792 VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState),
22382bb9
GH		 2793 VMSTATE_UINT32(vga.hw_cursor_x, CirrusVGAState),
2794 VMSTATE_UINT32(vga.hw_cursor_y, CirrusVGAState),
7e72abc3
JQ		 2795 /* XXX: we do not save the bitblt state - we assume we do not save
2796 the state when the blitter is active */
2797 VMSTATE_END_OF_LIST()
4f335feb 2798 }
7e72abc3 2799};
4f335feb 2800
7e72abc3
JQ		 2801static const VMStateDescription vmstate_pci_cirrus_vga = {
2802 .name = "cirrus_vga",
2803 .version_id = 2,
2804 .minimum_version_id = 2,
d49805ae 2805 .fields = (VMStateField[]) {
7e72abc3
JQ		 2806 VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState),
2807 VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
2808 vmstate_cirrus_vga, CirrusVGAState),
2809 VMSTATE_END_OF_LIST()
2810 }
2811};
4f335feb 2812
e6e5ad80
FB		 2813/***************************************
2814 *
2815 * initialize
2816 *
2817 ***************************************/
2818
4abc796d 2819static void cirrus_reset(void *opaque)
e6e5ad80 2820{
4abc796d 2821 CirrusVGAState *s = opaque;
e6e5ad80 2822
03a3e7ba 2823 vga_common_reset(&s->vga);
ee50c6bc 2824 unmap_linear_vram(s);
4e12cd94 2825 s->vga.sr[0x06] = 0x0f;
4abc796d 2826 if (s->device_id == CIRRUS_ID_CLGD5446) {
78e127ef 2827 /* 4MB 64 bit memory config, always PCI */
4e12cd94
AK		 2828 s->vga.sr[0x1F] = 0x2d; // MemClock
2829 s->vga.gr[0x18] = 0x0f; // fastest memory configuration
2830 s->vga.sr[0x0f] = 0x98;
2831 s->vga.sr[0x17] = 0x20;
2832 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
78e127ef 2833 } else {
4e12cd94
AK		 2834 s->vga.sr[0x1F] = 0x22; // MemClock
2835 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
2836 s->vga.sr[0x17] = s->bustype;
2837 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
78e127ef 2838 }
4e12cd94 2839 s->vga.cr[0x27] = s->device_id;
e6e5ad80
FB		 2840
2841 s->cirrus_hidden_dac_lockindex = 5;
2842 s->cirrus_hidden_dac_data = 0;
4abc796d
BS		 2843}
2844
b1950430
AK		 2845static const MemoryRegionOps cirrus_linear_io_ops = {
2846 .read = cirrus_linear_read,
2847 .write = cirrus_linear_write,
2848 .endianness = DEVICE_LITTLE_ENDIAN,
899adf81
AK		 2849 .impl = {
2850 .min_access_size = 1,
2851 .max_access_size = 1,
2852 },
b1950430
AK		 2853};
2854
c75e6d8e
JG		 2855static const MemoryRegionOps cirrus_vga_io_ops = {
2856 .read = cirrus_vga_ioport_read,
2857 .write = cirrus_vga_ioport_write,
2858 .endianness = DEVICE_LITTLE_ENDIAN,
2859 .impl = {
2860 .min_access_size = 1,
2861 .max_access_size = 1,
2862 },
2863};
2864
ce3cf70e
TH		 2865void cirrus_init_common(CirrusVGAState *s, Object *owner,
2866 int device_id, int is_pci,
2867 MemoryRegion *system_memory, MemoryRegion *system_io)
4abc796d
BS		 2868{
2869 int i;
2870 static int inited;
2871
2872 if (!inited) {
2873 inited = 1;
2874 for(i = 0;i < 256; i++)
2875 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
2876 rop_to_index[CIRRUS_ROP_0] = 0;
2877 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
2878 rop_to_index[CIRRUS_ROP_NOP] = 2;
2879 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
2880 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
2881 rop_to_index[CIRRUS_ROP_SRC] = 5;
2882 rop_to_index[CIRRUS_ROP_1] = 6;
2883 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
2884 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
2885 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
2886 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
2887 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
2888 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
2889 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
2890 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
2891 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
2892 s->device_id = device_id;
2893 if (is_pci)
2894 s->bustype = CIRRUS_BUSTYPE_PCI;
2895 else
2896 s->bustype = CIRRUS_BUSTYPE_ISA;
2897 }
2898
c75e6d8e 2899 /* Register ioport 0x3b0 - 0x3df */
9eb58a47 2900 memory_region_init_io(&s->cirrus_vga_io, owner, &cirrus_vga_io_ops, s,
c75e6d8e 2901 "cirrus-io", 0x30);
eb25a1d9 2902 memory_region_set_flush_coalesced(&s->cirrus_vga_io);
c75e6d8e 2903 memory_region_add_subregion(system_io, 0x3b0, &s->cirrus_vga_io);
4abc796d 2904
9eb58a47 2905 memory_region_init(&s->low_mem_container, owner,
b1950430
AK		 2906 "cirrus-lowmem-container",
2907 0x20000);
2908
9eb58a47 2909 memory_region_init_io(&s->low_mem, owner, &cirrus_vga_mem_ops, s,
b1950430
AK		 2910 "cirrus-low-memory", 0x20000);
2911 memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
7969d9ed
AK		 2912 for (i = 0; i < 2; ++i) {
2913 static const char *names[] = { "vga.bank0", "vga.bank1" };
2914 MemoryRegion *bank = &s->cirrus_bank[i];
9eb58a47
PB		 2915 memory_region_init_alias(bank, owner, names[i], &s->vga.vram,
2916 0, 0x8000);
7969d9ed
AK		 2917 memory_region_set_enabled(bank, false);
2918 memory_region_add_subregion_overlap(&s->low_mem_container, i * 0x8000,
2919 bank, 1);
2920 }
be20f9e9 2921 memory_region_add_subregion_overlap(system_memory,
b19c1c08 2922 0x000a0000,
b1950430
AK		 2923 &s->low_mem_container,
2924 1);
2925 memory_region_set_coalescing(&s->low_mem);
2c6ab832 2926
fefe54e3 2927 /* I/O handler for LFB */
9eb58a47 2928 memory_region_init_io(&s->cirrus_linear_io, owner, &cirrus_linear_io_ops, s,
f0353b0d 2929 "cirrus-linear-io", s->vga.vram_size_mb * MiB);
bd8f2f5d 2930 memory_region_set_flush_coalesced(&s->cirrus_linear_io);
fefe54e3
AL		 2931
2932 /* I/O handler for LFB */
9eb58a47 2933 memory_region_init_io(&s->cirrus_linear_bitblt_io, owner,
b1950430
AK		 2934 &cirrus_linear_bitblt_io_ops,
2935 s,
2936 "cirrus-bitblt-mmio",
2937 0x400000);
bd8f2f5d 2938 memory_region_set_flush_coalesced(&s->cirrus_linear_bitblt_io);
fefe54e3
AL		 2939
2940 /* I/O handler for memory-mapped I/O */
9eb58a47 2941 memory_region_init_io(&s->cirrus_mmio_io, owner, &cirrus_mmio_io_ops, s,
b1950430 2942 "cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
bd8f2f5d 2943 memory_region_set_flush_coalesced(&s->cirrus_mmio_io);
fefe54e3
AL		 2944
2945 s->real_vram_size =
f0353b0d 2946 (s->device_id == CIRRUS_ID_CLGD5446) ? 4 * MiB : 2 * MiB;
fefe54e3 2947
4e12cd94 2948 /* XXX: s->vga.vram_size must be a power of two */
fefe54e3
AL		 2949 s->cirrus_addr_mask = s->real_vram_size - 1;
2950 s->linear_mmio_mask = s->real_vram_size - 256;
2951
4e12cd94
AK		 2952 s->vga.get_bpp = cirrus_get_bpp;
2953 s->vga.get_offsets = cirrus_get_offsets;
2954 s->vga.get_resolution = cirrus_get_resolution;
2955 s->vga.cursor_invalidate = cirrus_cursor_invalidate;
2956 s->vga.cursor_draw_line = cirrus_cursor_draw_line;
fefe54e3 2957
a08d4367 2958 qemu_register_reset(cirrus_reset, s);
e6e5ad80
FB		 2959}
2960
e6e5ad80
FB		 2961/***************************************
2962 *
2963 * PCI bus support
2964 *
2965 ***************************************/
2966
f409edf7 2967static void pci_cirrus_vga_realize(PCIDevice *dev, Error **errp)
a414c306 2968{
d338bae3 2969 PCICirrusVGAState *d = PCI_CIRRUS_VGA(dev);
a414c306 2970 CirrusVGAState *s = &d->cirrus_vga;
40021f08
AL		 2971 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2972 int16_t device_id = pc->device_id;
a414c306 2973
f61d82c2
GA		 2974 /* follow real hardware, cirrus card emulated has 4 MB video memory.
2975 Also accept 8 MB/16 MB for backward compatibility. */
2976 if (s->vga.vram_size_mb != 4 && s->vga.vram_size_mb != 8 &&
2977 s->vga.vram_size_mb != 16) {
f409edf7
MA		 2978 error_setg(errp, "Invalid cirrus_vga ram size '%u'",
2979 s->vga.vram_size_mb);
2980 return;
f61d82c2 2981 }
a414c306 2982 /* setup VGA */
1fcfdc43 2983 vga_common_init(&s->vga, OBJECT(dev));
9eb58a47 2984 cirrus_init_common(s, OBJECT(dev), device_id, 1, pci_address_space(dev),
c75e6d8e 2985 pci_address_space_io(dev));
5643706a 2986 s->vga.con = graphic_console_init(DEVICE(dev), 0, s->vga.hw_ops, &s->vga);
a414c306
GH		 2987
2988 /* setup PCI */
a414c306 2989
3eadad55 2990 memory_region_init(&s->pci_bar, OBJECT(dev), "cirrus-pci-bar0", 0x2000000);
b1950430
AK		 2991
2992 /* XXX: add byte swapping apertures */
2993 memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io);
2994 memory_region_add_subregion(&s->pci_bar, 0x1000000,
2995 &s->cirrus_linear_bitblt_io);
2996
a414c306
GH		 2997 /* setup memory space */
2998 /* memory #0 LFB */
2999 /* memory #1 memory-mapped I/O */
3000 /* XXX: s->vga.vram_size must be a power of two */
e824b2cc 3001 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar);
a414c306 3002 if (device_id == CIRRUS_ID_CLGD5446) {
e824b2cc 3003 pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io);
a414c306 3004 }
a414c306
GH		 3005}
3006
19403a68
MT		 3007static Property pci_vga_cirrus_properties[] = {
3008 DEFINE_PROP_UINT32("vgamem_mb", struct PCICirrusVGAState,
73c14813 3009 cirrus_vga.vga.vram_size_mb, 4),
827bd517
GH		 3010 DEFINE_PROP_BOOL("blitter", struct PCICirrusVGAState,
3011 cirrus_vga.enable_blitter, true),
1fcfdc43
GH		 3012 DEFINE_PROP_BOOL("global-vmstate", struct PCICirrusVGAState,
3013 cirrus_vga.vga.global_vmstate, false),
19403a68
MT		 3014 DEFINE_PROP_END_OF_LIST(),
3015};
3016
40021f08
AL		 3017static void cirrus_vga_class_init(ObjectClass *klass, void *data)
3018{
39bffca2 3019 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 3020 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3021
f409edf7 3022 k->realize = pci_cirrus_vga_realize;
40021f08
AL		 3023 k->romfile = VGABIOS_CIRRUS_FILENAME;
3024 k->vendor_id = PCI_VENDOR_ID_CIRRUS;
3025 k->device_id = CIRRUS_ID_CLGD5446;
3026 k->class_id = PCI_CLASS_DISPLAY_VGA;
125ee0ed 3027 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
39bffca2
AL		 3028 dc->desc = "Cirrus CLGD 54xx VGA";
3029 dc->vmsd = &vmstate_pci_cirrus_vga;
4f67d30b 3030 device_class_set_props(dc, pci_vga_cirrus_properties);
2897ae02 3031 dc->hotpluggable = false;
40021f08
AL		 3032}
3033
8c43a6f0 3034static const TypeInfo cirrus_vga_info = {
d338bae3 3035 .name = TYPE_PCI_CIRRUS_VGA,
39bffca2
AL		 3036 .parent = TYPE_PCI_DEVICE,
3037 .instance_size = sizeof(PCICirrusVGAState),
3038 .class_init = cirrus_vga_class_init,
fd3b02c8
EH		 3039 .interfaces = (InterfaceInfo[]) {
3040 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
3041 { },
3042 },
a414c306 3043};
e6e5ad80 3044
83f7d43a 3045static void cirrus_vga_register_types(void)
a414c306 3046{
39bffca2 3047 type_register_static(&cirrus_vga_info);
e6e5ad80 3048}
83f7d43a
AF		 3049
3050type_init(cirrus_vga_register_types)
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