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virtio-gpu: fix unmap the already mapped items
[mirror_qemu.git] / hw / display / cirrus_vga.c
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e6e5ad80 1/*
aeb3c85f 2 * QEMU Cirrus CLGD 54xx VGA Emulator.
5fafdf24 3 *
e6e5ad80 4 * Copyright (c) 2004 Fabrice Bellard
aeb3c85f 5 * Copyright (c) 2004 Makoto Suzuki (suzu)
5fafdf24 6 *
e6e5ad80
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
aeb3c85f 25/*
29585468
PMD		 26 * Reference: Finn Thogersons' VGADOC4b:
27 *
28 * http://web.archive.org/web/20021019054927/http://home.worldonline.dk/finth/
29 *
30 * VGADOC4b.ZIP content available at:
31 *
32 * https://pdos.csail.mit.edu/6.828/2005/readings/hardware/vgadoc
aeb3c85f 33 */
0b8fa32f 34
47df5154 35#include "qemu/osdep.h"
0b8fa32f 36#include "qemu/module.h"
f0353b0d 37#include "qemu/units.h"
bb6e9e94 38#include "qemu/log.h"
71e8a915 39#include "sysemu/reset.h"
da34e65c 40#include "qapi/error.h"
ec87f206 41#include "trace.h"
83c9f4ca 42#include "hw/pci/pci.h"
a27bd6c7 43#include "hw/qdev-properties.h"
d6454270 44#include "migration/vmstate.h"
d3c2343a 45#include "ui/pixel_ops.h"
ce3cf70e 46#include "cirrus_vga_internal.h"
e6e5ad80 47
a5082316
FB		 48/*
49 * TODO:
ad81218e 50 * - destination write mask support not complete (bits 5..7)
a5082316
FB		 51 * - optimize linear mappings
52 * - optimize bitblt functions
53 */
54
e36f36e1
FB		 55//#define DEBUG_CIRRUS
56
e6e5ad80
FB		 57/***************************************
58 *
59 * definitions
60 *
61 ***************************************/
62
e6e5ad80
FB		 63// sequencer 0x07
64#define CIRRUS_SR7_BPP_VGA 0x00
65#define CIRRUS_SR7_BPP_SVGA 0x01
66#define CIRRUS_SR7_BPP_MASK 0x0e
67#define CIRRUS_SR7_BPP_8 0x00
68#define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
69#define CIRRUS_SR7_BPP_24 0x04
70#define CIRRUS_SR7_BPP_16 0x06
71#define CIRRUS_SR7_BPP_32 0x08
72#define CIRRUS_SR7_ISAADDR_MASK 0xe0
73
74// sequencer 0x0f
75#define CIRRUS_MEMSIZE_512k 0x08
76#define CIRRUS_MEMSIZE_1M 0x10
77#define CIRRUS_MEMSIZE_2M 0x18
78#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
79
80// sequencer 0x12
81#define CIRRUS_CURSOR_SHOW 0x01
82#define CIRRUS_CURSOR_HIDDENPEL 0x02
83#define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
84
85// sequencer 0x17
86#define CIRRUS_BUSTYPE_VLBFAST 0x10
87#define CIRRUS_BUSTYPE_PCI 0x20
88#define CIRRUS_BUSTYPE_VLBSLOW 0x30
89#define CIRRUS_BUSTYPE_ISA 0x38
90#define CIRRUS_MMIO_ENABLE 0x04
91#define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
92#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
93
94// control 0x0b
95#define CIRRUS_BANKING_DUAL 0x01
96#define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
97
98// control 0x30
99#define CIRRUS_BLTMODE_BACKWARDS 0x01
100#define CIRRUS_BLTMODE_MEMSYSDEST 0x02
101#define CIRRUS_BLTMODE_MEMSYSSRC 0x04
102#define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
103#define CIRRUS_BLTMODE_PATTERNCOPY 0x40
104#define CIRRUS_BLTMODE_COLOREXPAND 0x80
105#define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
106#define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
107#define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
108#define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
109#define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
110
111// control 0x31
112#define CIRRUS_BLT_BUSY 0x01
113#define CIRRUS_BLT_START 0x02
114#define CIRRUS_BLT_RESET 0x04
115#define CIRRUS_BLT_FIFOUSED 0x10
a5082316 116#define CIRRUS_BLT_AUTOSTART 0x80
e6e5ad80
FB		 117
118// control 0x32
119#define CIRRUS_ROP_0 0x00
120#define CIRRUS_ROP_SRC_AND_DST 0x05
121#define CIRRUS_ROP_NOP 0x06
122#define CIRRUS_ROP_SRC_AND_NOTDST 0x09
123#define CIRRUS_ROP_NOTDST 0x0b
124#define CIRRUS_ROP_SRC 0x0d
125#define CIRRUS_ROP_1 0x0e
126#define CIRRUS_ROP_NOTSRC_AND_DST 0x50
127#define CIRRUS_ROP_SRC_XOR_DST 0x59
128#define CIRRUS_ROP_SRC_OR_DST 0x6d
129#define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
130#define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
131#define CIRRUS_ROP_SRC_OR_NOTDST 0xad
132#define CIRRUS_ROP_NOTSRC 0xd0
133#define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
134#define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
135
a5082316
FB		 136#define CIRRUS_ROP_NOP_INDEX 2
137#define CIRRUS_ROP_SRC_INDEX 5
138
a21ae81d 139// control 0x33
a5082316 140#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
4c8732d7 141#define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
a5082316 142#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
a21ae81d 143
e6e5ad80
FB		 144// memory-mapped IO
145#define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
146#define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
147#define CIRRUS_MMIO_BLTWIDTH 0x08 // word
148#define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
149#define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
150#define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
151#define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
152#define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
153#define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
154#define CIRRUS_MMIO_BLTMODE 0x18 // byte
155#define CIRRUS_MMIO_BLTROP 0x1a // byte
156#define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
157#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
158#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
159#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
160#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
161#define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
162#define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
163#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
164#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
165#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
166#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
167#define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
168#define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
169#define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
170#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
171#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
172#define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
173#define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
174
a21ae81d 175#define CIRRUS_PNPMMIO_SIZE 0x1000
e6e5ad80 176
a5082316 177typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
026aeffc
GH		 178 uint32_t dstaddr, int dst_pitch,
179 int width, int height);
e6e5ad80 180
e6e5ad80
FB		 181typedef struct PCICirrusVGAState {
182 PCIDevice dev;
183 CirrusVGAState cirrus_vga;
184} PCICirrusVGAState;
185
d338bae3
GA		 186#define TYPE_PCI_CIRRUS_VGA "cirrus-vga"
187#define PCI_CIRRUS_VGA(obj) \
188 OBJECT_CHECK(PCICirrusVGAState, (obj), TYPE_PCI_CIRRUS_VGA)
189
a5082316 190static uint8_t rop_to_index[256];
3b46e624 191
e6e5ad80
FB		 192/***************************************
193 *
194 * prototypes.
195 *
196 ***************************************/
197
198
8926b517
FB		 199static void cirrus_bitblt_reset(CirrusVGAState *s);
200static void cirrus_update_memory_access(CirrusVGAState *s);
e6e5ad80
FB		 201
202/***************************************
203 *
204 * raster operations
205 *
206 ***************************************/
207
d3532a0d
GH		 208static bool blit_region_is_unsafe(struct CirrusVGAState *s,
209 int32_t pitch, int32_t addr)
210{
12e97ec3
GH		 211 if (!pitch) {
212 return true;
213 }
d3532a0d
GH		 214 if (pitch < 0) {
215 int64_t min = addr
62d4c6bd
LQ		 216 + ((int64_t)s->cirrus_blt_height - 1) * pitch
217 - s->cirrus_blt_width;
218 if (min < -1 || addr >= s->vga.vram_size) {
d3532a0d
GH		 219 return true;
220 }
221 } else {
222 int64_t max = addr
223 + ((int64_t)s->cirrus_blt_height-1) * pitch
224 + s->cirrus_blt_width;
d2ba7ecb 225 if (max > s->vga.vram_size) {
d3532a0d
GH		 226 return true;
227 }
228 }
229 return false;
230}
231
12e97ec3 232static bool blit_is_unsafe(struct CirrusVGAState *s, bool dst_only)
d3532a0d
GH		 233{
234 /* should be the case, see cirrus_bitblt_start */
235 assert(s->cirrus_blt_width > 0);
236 assert(s->cirrus_blt_height > 0);
237
bf259833
GH		 238 if (s->cirrus_blt_width > CIRRUS_BLTBUFSIZE) {
239 return true;
240 }
241
d3532a0d 242 if (blit_region_is_unsafe(s, s->cirrus_blt_dstpitch,
60cd23e8 243 s->cirrus_blt_dstaddr)) {
d3532a0d
GH		 244 return true;
245 }
913a8788
BR		 246 if (dst_only) {
247 return false;
248 }
12e97ec3 249 if (blit_region_is_unsafe(s, s->cirrus_blt_srcpitch,
60cd23e8 250 s->cirrus_blt_srcaddr)) {
d3532a0d
GH		 251 return true;
252 }
253
254 return false;
255}
256
a5082316 257static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
ffaf8577 258 uint32_t dstaddr, uint32_t srcaddr,
a5082316
FB		 259 int dstpitch,int srcpitch,
260 int bltwidth,int bltheight)
261{
e6e5ad80
FB		 262}
263
a5082316 264static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
026aeffc 265 uint32_t dstaddr,
a5082316 266 int dstpitch, int bltwidth,int bltheight)
e6e5ad80 267{
a5082316 268}
e6e5ad80 269
ffaf8577
GH		 270static inline uint8_t cirrus_src(CirrusVGAState *s, uint32_t srcaddr)
271{
272 if (s->cirrus_srccounter) {
273 /* cputovideo */
274 return s->cirrus_bltbuf[srcaddr & (CIRRUS_BLTBUFSIZE - 1)];
275 } else {
276 /* videotovideo */
277 return s->vga.vram_ptr[srcaddr & s->cirrus_addr_mask];
278 }
279}
280
281static inline uint16_t cirrus_src16(CirrusVGAState *s, uint32_t srcaddr)
282{
283 uint16_t *src;
284
285 if (s->cirrus_srccounter) {
286 /* cputovideo */
287 src = (void *)&s->cirrus_bltbuf[srcaddr & (CIRRUS_BLTBUFSIZE - 1) & ~1];
288 } else {
289 /* videotovideo */
290 src = (void *)&s->vga.vram_ptr[srcaddr & s->cirrus_addr_mask & ~1];
291 }
292 return *src;
293}
294
295static inline uint32_t cirrus_src32(CirrusVGAState *s, uint32_t srcaddr)
296{
297 uint32_t *src;
298
299 if (s->cirrus_srccounter) {
300 /* cputovideo */
301 src = (void *)&s->cirrus_bltbuf[srcaddr & (CIRRUS_BLTBUFSIZE - 1) & ~3];
302 } else {
303 /* videotovideo */
304 src = (void *)&s->vga.vram_ptr[srcaddr & s->cirrus_addr_mask & ~3];
305 }
306 return *src;
307}
308
a5082316 309#define ROP_NAME 0
8c78881f 310#define ROP_FN(d, s) 0
47b43a1f 311#include "cirrus_vga_rop.h"
e6e5ad80 312
a5082316 313#define ROP_NAME src_and_dst
8c78881f 314#define ROP_FN(d, s) (s) & (d)
47b43a1f 315#include "cirrus_vga_rop.h"
e6e5ad80 316
a5082316 317#define ROP_NAME src_and_notdst
8c78881f 318#define ROP_FN(d, s) (s) & (~(d))
47b43a1f 319#include "cirrus_vga_rop.h"
e6e5ad80 320
a5082316 321#define ROP_NAME notdst
8c78881f 322#define ROP_FN(d, s) ~(d)
47b43a1f 323#include "cirrus_vga_rop.h"
e6e5ad80 324
a5082316 325#define ROP_NAME src
8c78881f 326#define ROP_FN(d, s) s
47b43a1f 327#include "cirrus_vga_rop.h"
e6e5ad80 328
a5082316 329#define ROP_NAME 1
8c78881f 330#define ROP_FN(d, s) ~0
47b43a1f 331#include "cirrus_vga_rop.h"
a5082316
FB		 332
333#define ROP_NAME notsrc_and_dst
8c78881f 334#define ROP_FN(d, s) (~(s)) & (d)
47b43a1f 335#include "cirrus_vga_rop.h"
a5082316
FB		 336
337#define ROP_NAME src_xor_dst
8c78881f 338#define ROP_FN(d, s) (s) ^ (d)
47b43a1f 339#include "cirrus_vga_rop.h"
a5082316
FB		 340
341#define ROP_NAME src_or_dst
8c78881f 342#define ROP_FN(d, s) (s) | (d)
47b43a1f 343#include "cirrus_vga_rop.h"
a5082316
FB		 344
345#define ROP_NAME notsrc_or_notdst
8c78881f 346#define ROP_FN(d, s) (~(s)) | (~(d))
47b43a1f 347#include "cirrus_vga_rop.h"
a5082316
FB		 348
349#define ROP_NAME src_notxor_dst
8c78881f 350#define ROP_FN(d, s) ~((s) ^ (d))
47b43a1f 351#include "cirrus_vga_rop.h"
e6e5ad80 352
a5082316 353#define ROP_NAME src_or_notdst
8c78881f 354#define ROP_FN(d, s) (s) | (~(d))
47b43a1f 355#include "cirrus_vga_rop.h"
a5082316
FB		 356
357#define ROP_NAME notsrc
8c78881f 358#define ROP_FN(d, s) (~(s))
47b43a1f 359#include "cirrus_vga_rop.h"
a5082316
FB		 360
361#define ROP_NAME notsrc_or_dst
8c78881f 362#define ROP_FN(d, s) (~(s)) | (d)
47b43a1f 363#include "cirrus_vga_rop.h"
a5082316
FB		 364
365#define ROP_NAME notsrc_and_notdst
8c78881f 366#define ROP_FN(d, s) (~(s)) & (~(d))
47b43a1f 367#include "cirrus_vga_rop.h"
a5082316
FB		 368
369static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
370 cirrus_bitblt_rop_fwd_0,
371 cirrus_bitblt_rop_fwd_src_and_dst,
372 cirrus_bitblt_rop_nop,
373 cirrus_bitblt_rop_fwd_src_and_notdst,
374 cirrus_bitblt_rop_fwd_notdst,
375 cirrus_bitblt_rop_fwd_src,
376 cirrus_bitblt_rop_fwd_1,
377 cirrus_bitblt_rop_fwd_notsrc_and_dst,
378 cirrus_bitblt_rop_fwd_src_xor_dst,
379 cirrus_bitblt_rop_fwd_src_or_dst,
380 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
381 cirrus_bitblt_rop_fwd_src_notxor_dst,
382 cirrus_bitblt_rop_fwd_src_or_notdst,
383 cirrus_bitblt_rop_fwd_notsrc,
384 cirrus_bitblt_rop_fwd_notsrc_or_dst,
385 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
386};
387
388static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
389 cirrus_bitblt_rop_bkwd_0,
390 cirrus_bitblt_rop_bkwd_src_and_dst,
391 cirrus_bitblt_rop_nop,
392 cirrus_bitblt_rop_bkwd_src_and_notdst,
393 cirrus_bitblt_rop_bkwd_notdst,
394 cirrus_bitblt_rop_bkwd_src,
395 cirrus_bitblt_rop_bkwd_1,
396 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
397 cirrus_bitblt_rop_bkwd_src_xor_dst,
398 cirrus_bitblt_rop_bkwd_src_or_dst,
399 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
400 cirrus_bitblt_rop_bkwd_src_notxor_dst,
401 cirrus_bitblt_rop_bkwd_src_or_notdst,
402 cirrus_bitblt_rop_bkwd_notsrc,
403 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
404 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
405};
96cf2df8
TS		 406
407#define TRANSP_ROP(name) {\
408 name ## _8,\
409 name ## _16,\
410 }
411#define TRANSP_NOP(func) {\
412 func,\
413 func,\
414 }
415
416static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
417 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
418 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
419 TRANSP_NOP(cirrus_bitblt_rop_nop),
420 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
421 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
422 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
423 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
424 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
425 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
426 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
427 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
428 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
429 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
430 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
431 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
432 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
433};
434
435static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
436 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
437 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
438 TRANSP_NOP(cirrus_bitblt_rop_nop),
439 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
440 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
441 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
442 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
443 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
444 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
445 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
446 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
447 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
448 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
449 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
450 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
451 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
452};
453
a5082316
FB		 454#define ROP2(name) {\
455 name ## _8,\
456 name ## _16,\
457 name ## _24,\
458 name ## _32,\
459 }
460
461#define ROP_NOP2(func) {\
462 func,\
463 func,\
464 func,\
465 func,\
466 }
467
e69390ce
FB		 468static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
469 ROP2(cirrus_patternfill_0),
470 ROP2(cirrus_patternfill_src_and_dst),
471 ROP_NOP2(cirrus_bitblt_rop_nop),
472 ROP2(cirrus_patternfill_src_and_notdst),
473 ROP2(cirrus_patternfill_notdst),
474 ROP2(cirrus_patternfill_src),
475 ROP2(cirrus_patternfill_1),
476 ROP2(cirrus_patternfill_notsrc_and_dst),
477 ROP2(cirrus_patternfill_src_xor_dst),
478 ROP2(cirrus_patternfill_src_or_dst),
479 ROP2(cirrus_patternfill_notsrc_or_notdst),
480 ROP2(cirrus_patternfill_src_notxor_dst),
481 ROP2(cirrus_patternfill_src_or_notdst),
482 ROP2(cirrus_patternfill_notsrc),
483 ROP2(cirrus_patternfill_notsrc_or_dst),
484 ROP2(cirrus_patternfill_notsrc_and_notdst),
485};
486
a5082316
FB		 487static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
488 ROP2(cirrus_colorexpand_transp_0),
489 ROP2(cirrus_colorexpand_transp_src_and_dst),
490 ROP_NOP2(cirrus_bitblt_rop_nop),
491 ROP2(cirrus_colorexpand_transp_src_and_notdst),
492 ROP2(cirrus_colorexpand_transp_notdst),
493 ROP2(cirrus_colorexpand_transp_src),
494 ROP2(cirrus_colorexpand_transp_1),
495 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
496 ROP2(cirrus_colorexpand_transp_src_xor_dst),
497 ROP2(cirrus_colorexpand_transp_src_or_dst),
498 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
499 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
500 ROP2(cirrus_colorexpand_transp_src_or_notdst),
501 ROP2(cirrus_colorexpand_transp_notsrc),
502 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
503 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
504};
505
506static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
507 ROP2(cirrus_colorexpand_0),
508 ROP2(cirrus_colorexpand_src_and_dst),
509 ROP_NOP2(cirrus_bitblt_rop_nop),
510 ROP2(cirrus_colorexpand_src_and_notdst),
511 ROP2(cirrus_colorexpand_notdst),
512 ROP2(cirrus_colorexpand_src),
513 ROP2(cirrus_colorexpand_1),
514 ROP2(cirrus_colorexpand_notsrc_and_dst),
515 ROP2(cirrus_colorexpand_src_xor_dst),
516 ROP2(cirrus_colorexpand_src_or_dst),
517 ROP2(cirrus_colorexpand_notsrc_or_notdst),
518 ROP2(cirrus_colorexpand_src_notxor_dst),
519 ROP2(cirrus_colorexpand_src_or_notdst),
520 ROP2(cirrus_colorexpand_notsrc),
521 ROP2(cirrus_colorexpand_notsrc_or_dst),
522 ROP2(cirrus_colorexpand_notsrc_and_notdst),
523};
524
b30d4608
FB		 525static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
526 ROP2(cirrus_colorexpand_pattern_transp_0),
527 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
528 ROP_NOP2(cirrus_bitblt_rop_nop),
529 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
530 ROP2(cirrus_colorexpand_pattern_transp_notdst),
531 ROP2(cirrus_colorexpand_pattern_transp_src),
532 ROP2(cirrus_colorexpand_pattern_transp_1),
533 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
534 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
535 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
536 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
537 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
538 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
539 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
540 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
541 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
542};
543
544static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
545 ROP2(cirrus_colorexpand_pattern_0),
546 ROP2(cirrus_colorexpand_pattern_src_and_dst),
547 ROP_NOP2(cirrus_bitblt_rop_nop),
548 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
549 ROP2(cirrus_colorexpand_pattern_notdst),
550 ROP2(cirrus_colorexpand_pattern_src),
551 ROP2(cirrus_colorexpand_pattern_1),
552 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
553 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
554 ROP2(cirrus_colorexpand_pattern_src_or_dst),
555 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
556 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
557 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
558 ROP2(cirrus_colorexpand_pattern_notsrc),
559 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
560 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
561};
562
a5082316
FB		 563static const cirrus_fill_t cirrus_fill[16][4] = {
564 ROP2(cirrus_fill_0),
565 ROP2(cirrus_fill_src_and_dst),
566 ROP_NOP2(cirrus_bitblt_fill_nop),
567 ROP2(cirrus_fill_src_and_notdst),
568 ROP2(cirrus_fill_notdst),
569 ROP2(cirrus_fill_src),
570 ROP2(cirrus_fill_1),
571 ROP2(cirrus_fill_notsrc_and_dst),
572 ROP2(cirrus_fill_src_xor_dst),
573 ROP2(cirrus_fill_src_or_dst),
574 ROP2(cirrus_fill_notsrc_or_notdst),
575 ROP2(cirrus_fill_src_notxor_dst),
576 ROP2(cirrus_fill_src_or_notdst),
577 ROP2(cirrus_fill_notsrc),
578 ROP2(cirrus_fill_notsrc_or_dst),
579 ROP2(cirrus_fill_notsrc_and_notdst),
580};
581
582static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
e6e5ad80 583{
a5082316
FB		 584 unsigned int color;
585 switch (s->cirrus_blt_pixelwidth) {
586 case 1:
587 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
588 break;
589 case 2:
4e12cd94 590 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
a5082316
FB		 591 s->cirrus_blt_fgcol = le16_to_cpu(color);
592 break;
593 case 3:
5fafdf24 594 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
4e12cd94 595 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
a5082316
FB		 596 break;
597 default:
598 case 4:
4e12cd94
AK		 599 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
600 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
a5082316
FB		 601 s->cirrus_blt_fgcol = le32_to_cpu(color);
602 break;
e6e5ad80
FB		 603 }
604}
605
a5082316 606static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
e6e5ad80 607{
a5082316 608 unsigned int color;
e6e5ad80
FB		 609 switch (s->cirrus_blt_pixelwidth) {
610 case 1:
a5082316
FB		 611 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
612 break;
e6e5ad80 613 case 2:
4e12cd94 614 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
a5082316
FB		 615 s->cirrus_blt_bgcol = le16_to_cpu(color);
616 break;
e6e5ad80 617 case 3:
5fafdf24 618 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
4e12cd94 619 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
a5082316 620 break;
e6e5ad80 621 default:
a5082316 622 case 4:
4e12cd94
AK		 623 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
624 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
a5082316
FB		 625 s->cirrus_blt_bgcol = le32_to_cpu(color);
626 break;
e6e5ad80
FB		 627 }
628}
629
630static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
631 int off_pitch, int bytesperline,
632 int lines)
633{
634 int y;
635 int off_cur;
636 int off_cur_end;
637
f153b563
WB		 638 if (off_pitch < 0) {
639 off_begin -= bytesperline - 1;
640 }
641
e6e5ad80 642 for (y = 0; y < lines; y++) {
e048dac6
GH		 643 off_cur = off_begin;
644 off_cur_end = ((off_cur + bytesperline - 1) & s->cirrus_addr_mask) + 1;
f153b563 645 assert(off_cur_end >= off_cur);
fd4aa979 646 memory_region_set_dirty(&s->vga.vram, off_cur, off_cur_end - off_cur);
e048dac6 647 off_begin += off_pitch;
e6e5ad80
FB		 648 }
649}
650
ffaf8577 651static int cirrus_bitblt_common_patterncopy(CirrusVGAState *s)
e6e5ad80 652{
95280c31 653 uint32_t patternsize;
ffaf8577 654 bool videosrc = !s->cirrus_srccounter;
e6e5ad80 655
95280c31
GH		 656 if (videosrc) {
657 switch (s->vga.get_bpp(&s->vga)) {
658 case 8:
659 patternsize = 64;
660 break;
661 case 15:
662 case 16:
663 patternsize = 128;
664 break;
665 case 24:
666 case 32:
667 default:
668 patternsize = 256;
669 break;
670 }
671 s->cirrus_blt_srcaddr &= ~(patternsize - 1);
672 if (s->cirrus_blt_srcaddr + patternsize > s->vga.vram_size) {
673 return 0;
674 }
95280c31
GH		 675 }
676
12e97ec3 677 if (blit_is_unsafe(s, true)) {
b2eb849d 678 return 0;
5858dd18 679 }
b2eb849d 680
ffaf8577
GH		 681 (*s->cirrus_rop) (s, s->cirrus_blt_dstaddr,
682 videosrc ? s->cirrus_blt_srcaddr : 0,
5fafdf24 683 s->cirrus_blt_dstpitch, 0,
e69390ce 684 s->cirrus_blt_width, s->cirrus_blt_height);
e6e5ad80 685 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
e69390ce
FB		 686 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
687 s->cirrus_blt_height);
e6e5ad80
FB		 688 return 1;
689}
690
a21ae81d
FB		 691/* fill */
692
a5082316 693static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
a21ae81d 694{
a5082316 695 cirrus_fill_t rop_func;
a21ae81d 696
12e97ec3 697 if (blit_is_unsafe(s, true)) {
b2eb849d 698 return 0;
d3532a0d 699 }
a5082316 700 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
026aeffc 701 rop_func(s, s->cirrus_blt_dstaddr,
a5082316
FB		 702 s->cirrus_blt_dstpitch,
703 s->cirrus_blt_width, s->cirrus_blt_height);
a21ae81d
FB		 704 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
705 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
706 s->cirrus_blt_height);
707 cirrus_bitblt_reset(s);
708 return 1;
709}
710
e6e5ad80
FB		 711/***************************************
712 *
713 * bitblt (video-to-video)
714 *
715 ***************************************/
716
717static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
718{
ffaf8577 719 return cirrus_bitblt_common_patterncopy(s);
e6e5ad80
FB		 720}
721
4299b90e 722static int cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
e6e5ad80 723{
78935c4a
AJ		 724 int sx = 0, sy = 0;
725 int dx = 0, dy = 0;
726 int depth = 0;
24236869
FB		 727 int notify = 0;
728
92d675d1
AJ		 729 /* make sure to only copy if it's a plain copy ROP */
730 if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
731 *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {
24236869 732
92d675d1
AJ		 733 int width, height;
734
735 depth = s->vga.get_bpp(&s->vga) / 8;
4299b90e
PP		 736 if (!depth) {
737 return 0;
738 }
92d675d1
AJ		 739 s->vga.get_resolution(&s->vga, &width, &height);
740
741 /* extra x, y */
742 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
743 sy = (src / ABS(s->cirrus_blt_srcpitch));
744 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
745 dy = (dst / ABS(s->cirrus_blt_dstpitch));
24236869 746
92d675d1
AJ		 747 /* normalize width */
748 w /= depth;
24236869 749
92d675d1
AJ		 750 /* if we're doing a backward copy, we have to adjust
751 our x/y to be the upper left corner (instead of the lower
752 right corner) */
753 if (s->cirrus_blt_dstpitch < 0) {
754 sx -= (s->cirrus_blt_width / depth) - 1;
755 dx -= (s->cirrus_blt_width / depth) - 1;
756 sy -= s->cirrus_blt_height - 1;
757 dy -= s->cirrus_blt_height - 1;
758 }
759
760 /* are we in the visible portion of memory? */
761 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
762 (sx + w) <= width && (sy + h) <= height &&
763 (dx + w) <= width && (dy + h) <= height) {
764 notify = 1;
765 }
766 }
24236869 767
026aeffc 768 (*s->cirrus_rop) (s, s->cirrus_blt_dstaddr,
ffaf8577 769 s->cirrus_blt_srcaddr,
e6e5ad80
FB		 770 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
771 s->cirrus_blt_width, s->cirrus_blt_height);
24236869 772
c78f7137 773 if (notify) {
50628d34
GH		 774 dpy_gfx_update(s->vga.con, dx, dy,
775 s->cirrus_blt_width / depth,
776 s->cirrus_blt_height);
c78f7137 777 }
24236869
FB		 778
779 /* we don't have to notify the display that this portion has
38334f76 780 changed since qemu_console_copy implies this */
24236869 781
31c05501
AL		 782 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
783 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
784 s->cirrus_blt_height);
4299b90e
PP		 785
786 return 1;
24236869
FB		 787}
788
789static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
790{
12e97ec3 791 if (blit_is_unsafe(s, false))
65d35a09
AJ		 792 return 0;
793
4299b90e 794 return cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
4e12cd94 795 s->cirrus_blt_srcaddr - s->vga.start_addr,
7d957bd8 796 s->cirrus_blt_width, s->cirrus_blt_height);
e6e5ad80
FB		 797}
798
799/***************************************
800 *
801 * bitblt (cpu-to-video)
802 *
803 ***************************************/
804
e6e5ad80
FB		 805static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
806{
807 int copy_count;
a5082316 808 uint8_t *end_ptr;
3b46e624 809
e6e5ad80 810 if (s->cirrus_srccounter > 0) {
a5082316 811 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
ffaf8577 812 cirrus_bitblt_common_patterncopy(s);
a5082316
FB		 813 the_end:
814 s->cirrus_srccounter = 0;
815 cirrus_bitblt_reset(s);
816 } else {
817 /* at least one scan line */
818 do {
026aeffc 819 (*s->cirrus_rop)(s, s->cirrus_blt_dstaddr,
ffaf8577 820 0, 0, 0, s->cirrus_blt_width, 1);
a5082316
FB		 821 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
822 s->cirrus_blt_width, 1);
823 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
824 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
825 if (s->cirrus_srccounter <= 0)
826 goto the_end;
66a0a2cb 827 /* more bytes than needed can be transferred because of
a5082316
FB		 828 word alignment, so we keep them for the next line */
829 /* XXX: keep alignment to speed up transfer */
830 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
831 copy_count = s->cirrus_srcptr_end - end_ptr;
832 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
833 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
834 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
835 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
836 }
e6e5ad80
FB		 837 }
838}
839
840/***************************************
841 *
842 * bitblt wrapper
843 *
844 ***************************************/
845
846static void cirrus_bitblt_reset(CirrusVGAState * s)
847{
f8b237af
AL		 848 int need_update;
849
4e12cd94 850 s->vga.gr[0x31] &=
e6e5ad80 851 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
f8b237af
AL		 852 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
853 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
e6e5ad80
FB		 854 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
855 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
856 s->cirrus_srccounter = 0;
f8b237af
AL		 857 if (!need_update)
858 return;
8926b517 859 cirrus_update_memory_access(s);
e6e5ad80
FB		 860}
861
862static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
863{
a5082316
FB		 864 int w;
865
92f2b88c
GH		 866 if (blit_is_unsafe(s, true)) {
867 return 0;
868 }
869
e6e5ad80
FB		 870 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
871 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
872 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
873
874 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
875 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 876 s->cirrus_blt_srcpitch = 8;
e6e5ad80 877 } else {
b30d4608 878 /* XXX: check for 24 bpp */
a5082316 879 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
e6e5ad80 880 }
a5082316 881 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
e6e5ad80
FB		 882 } else {
883 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 884 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
5fafdf24 885 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
a5082316
FB		 886 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
887 else
888 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
e6e5ad80 889 } else {
c9c0eae8
FB		 890 /* always align input size to 32 bits */
891 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
e6e5ad80 892 }
a5082316 893 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
e6e5ad80 894 }
92f2b88c
GH		 895
896 /* the blit_is_unsafe call above should catch this */
897 assert(s->cirrus_blt_srcpitch <= CIRRUS_BLTBUFSIZE);
898
a5082316
FB		 899 s->cirrus_srcptr = s->cirrus_bltbuf;
900 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
8926b517 901 cirrus_update_memory_access(s);
e6e5ad80
FB		 902 return 1;
903}
904
905static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
906{
907 /* XXX */
bb6e9e94
PMD		 908 qemu_log_mask(LOG_UNIMP,
909 "cirrus: bitblt (video to cpu) is not implemented\n");
e6e5ad80
FB		 910 return 0;
911}
912
913static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
914{
915 int ret;
916
917 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
918 ret = cirrus_bitblt_videotovideo_patterncopy(s);
919 } else {
920 ret = cirrus_bitblt_videotovideo_copy(s);
921 }
e6e5ad80
FB		 922 if (ret)
923 cirrus_bitblt_reset(s);
924 return ret;
925}
926
927static void cirrus_bitblt_start(CirrusVGAState * s)
928{
929 uint8_t blt_rop;
930
827bd517
GH		 931 if (!s->enable_blitter) {
932 goto bitblt_ignore;
933 }
934
4e12cd94 935 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
a5082316 936
4e12cd94
AK		 937 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
938 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
939 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
940 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
e6e5ad80 941 s->cirrus_blt_dstaddr =
4e12cd94 942 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
e6e5ad80 943 s->cirrus_blt_srcaddr =
4e12cd94
AK		 944 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
945 s->cirrus_blt_mode = s->vga.gr[0x30];
946 s->cirrus_blt_modeext = s->vga.gr[0x33];
947 blt_rop = s->vga.gr[0x32];
e6e5ad80 948
60cd23e8
GH		 949 s->cirrus_blt_dstaddr &= s->cirrus_addr_mask;
950 s->cirrus_blt_srcaddr &= s->cirrus_addr_mask;
951
61527721
PMD		 952 trace_vga_cirrus_bitblt_start(blt_rop,
953 s->cirrus_blt_mode,
954 s->cirrus_blt_modeext,
955 s->cirrus_blt_width,
956 s->cirrus_blt_height,
957 s->cirrus_blt_dstpitch,
958 s->cirrus_blt_srcpitch,
959 s->cirrus_blt_dstaddr,
960 s->cirrus_blt_srcaddr,
961 s->vga.gr[0x2f]);
a21ae81d 962
e6e5ad80
FB		 963 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
964 case CIRRUS_BLTMODE_PIXELWIDTH8:
965 s->cirrus_blt_pixelwidth = 1;
966 break;
967 case CIRRUS_BLTMODE_PIXELWIDTH16:
968 s->cirrus_blt_pixelwidth = 2;
969 break;
970 case CIRRUS_BLTMODE_PIXELWIDTH24:
971 s->cirrus_blt_pixelwidth = 3;
972 break;
973 case CIRRUS_BLTMODE_PIXELWIDTH32:
974 s->cirrus_blt_pixelwidth = 4;
975 break;
976 default:
2b55f4d3
PMD		 977 qemu_log_mask(LOG_GUEST_ERROR,
978 "cirrus: bitblt - pixel width is unknown\n");
e6e5ad80
FB		 979 goto bitblt_ignore;
980 }
981 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
982
983 if ((s->
984 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
985 CIRRUS_BLTMODE_MEMSYSDEST))
986 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
bb6e9e94
PMD		 987 qemu_log_mask(LOG_UNIMP,
988 "cirrus: bitblt - memory-to-memory copy requested\n");
e6e5ad80
FB		 989 goto bitblt_ignore;
990 }
991
a5082316 992 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
5fafdf24 993 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
a21ae81d 994 CIRRUS_BLTMODE_TRANSPARENTCOMP |
5fafdf24
TS		 995 CIRRUS_BLTMODE_PATTERNCOPY |
996 CIRRUS_BLTMODE_COLOREXPAND)) ==
a21ae81d 997 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
a5082316
FB		 998 cirrus_bitblt_fgcol(s);
999 cirrus_bitblt_solidfill(s, blt_rop);
e6e5ad80 1000 } else {
5fafdf24
TS		 1001 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
1002 CIRRUS_BLTMODE_PATTERNCOPY)) ==
a5082316
FB		 1003 CIRRUS_BLTMODE_COLOREXPAND) {
1004
1005 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
b30d4608 1006 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
4c8732d7 1007 cirrus_bitblt_bgcol(s);
b30d4608 1008 else
4c8732d7 1009 cirrus_bitblt_fgcol(s);
b30d4608 1010 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
a5082316
FB		 1011 } else {
1012 cirrus_bitblt_fgcol(s);
1013 cirrus_bitblt_bgcol(s);
1014 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1015 }
e69390ce 1016 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
b30d4608
FB		 1017 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1018 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1019 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1020 cirrus_bitblt_bgcol(s);
1021 else
1022 cirrus_bitblt_fgcol(s);
1023 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1024 } else {
1025 cirrus_bitblt_fgcol(s);
1026 cirrus_bitblt_bgcol(s);
1027 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1028 }
1029 } else {
1030 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1031 }
a21ae81d 1032 } else {
96cf2df8
TS		 1033 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1034 if (s->cirrus_blt_pixelwidth > 2) {
ae3887e6
PMD		 1035 qemu_log_mask(LOG_GUEST_ERROR,
1036 "cirrus: src transparent without colorexpand "
1037 "must be 8bpp or 16bpp\n");
96cf2df8
TS		 1038 goto bitblt_ignore;
1039 }
1040 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1041 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1042 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1043 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1044 } else {
1045 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1046 }
1047 } else {
1048 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1049 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1050 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1051 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1052 } else {
1053 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1054 }
1055 }
1056 }
a21ae81d
FB		 1057 // setup bitblt engine.
1058 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1059 if (!cirrus_bitblt_cputovideo(s))
1060 goto bitblt_ignore;
1061 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1062 if (!cirrus_bitblt_videotocpu(s))
1063 goto bitblt_ignore;
1064 } else {
1065 if (!cirrus_bitblt_videotovideo(s))
1066 goto bitblt_ignore;
1067 }
e6e5ad80 1068 }
e6e5ad80
FB		 1069 return;
1070 bitblt_ignore:;
1071 cirrus_bitblt_reset(s);
1072}
1073
1074static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1075{
1076 unsigned old_value;
1077
4e12cd94
AK		 1078 old_value = s->vga.gr[0x31];
1079 s->vga.gr[0x31] = reg_value;
e6e5ad80
FB		 1080
1081 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1082 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1083 cirrus_bitblt_reset(s);
1084 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1085 ((reg_value & CIRRUS_BLT_START) != 0)) {
e6e5ad80
FB		 1086 cirrus_bitblt_start(s);
1087 }
1088}
1089
1090
1091/***************************************
1092 *
1093 * basic parameters
1094 *
1095 ***************************************/
1096
a4a2f59c 1097static void cirrus_get_offsets(VGACommonState *s1,
83acc96b
FB		 1098 uint32_t *pline_offset,
1099 uint32_t *pstart_addr,
1100 uint32_t *pline_compare)
e6e5ad80 1101{
4e12cd94 1102 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
83acc96b 1103 uint32_t start_addr, line_offset, line_compare;
e6e5ad80 1104
4e12cd94
AK		 1105 line_offset = s->vga.cr[0x13]
1106 | ((s->vga.cr[0x1b] & 0x10) << 4);
e6e5ad80
FB		 1107 line_offset <<= 3;
1108 *pline_offset = line_offset;
1109
4e12cd94
AK		 1110 start_addr = (s->vga.cr[0x0c] << 8)
1111 | s->vga.cr[0x0d]
1112 | ((s->vga.cr[0x1b] & 0x01) << 16)
1113 | ((s->vga.cr[0x1b] & 0x0c) << 15)
1114 | ((s->vga.cr[0x1d] & 0x80) << 12);
e6e5ad80 1115 *pstart_addr = start_addr;
83acc96b 1116
4e12cd94
AK		 1117 line_compare = s->vga.cr[0x18] |
1118 ((s->vga.cr[0x07] & 0x10) << 4) |
1119 ((s->vga.cr[0x09] & 0x40) << 3);
83acc96b 1120 *pline_compare = line_compare;
e6e5ad80
FB		 1121}
1122
1123static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1124{
1125 uint32_t ret = 16;
1126
1127 switch (s->cirrus_hidden_dac_data & 0xf) {
1128 case 0:
1129 ret = 15;
1130 break; /* Sierra HiColor */
1131 case 1:
1132 ret = 16;
1133 break; /* XGA HiColor */
1134 default:
2b55f4d3
PMD		 1135 qemu_log_mask(LOG_GUEST_ERROR,
1136 "cirrus: invalid DAC value 0x%x in 16bpp\n",
1137 (s->cirrus_hidden_dac_data & 0xf));
e6e5ad80
FB		 1138 ret = 15; /* XXX */
1139 break;
1140 }
1141 return ret;
1142}
1143
a4a2f59c 1144static int cirrus_get_bpp(VGACommonState *s1)
e6e5ad80 1145{
4e12cd94 1146 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
e6e5ad80
FB		 1147 uint32_t ret = 8;
1148
4e12cd94 1149 if ((s->vga.sr[0x07] & 0x01) != 0) {
e6e5ad80 1150 /* Cirrus SVGA */
4e12cd94 1151 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
e6e5ad80
FB		 1152 case CIRRUS_SR7_BPP_8:
1153 ret = 8;
1154 break;
1155 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1156 ret = cirrus_get_bpp16_depth(s);
1157 break;
1158 case CIRRUS_SR7_BPP_24:
1159 ret = 24;
1160 break;
1161 case CIRRUS_SR7_BPP_16:
1162 ret = cirrus_get_bpp16_depth(s);
1163 break;
1164 case CIRRUS_SR7_BPP_32:
1165 ret = 32;
1166 break;
1167 default:
1168#ifdef DEBUG_CIRRUS
4e12cd94 1169 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
e6e5ad80
FB		 1170#endif
1171 ret = 8;
1172 break;
1173 }
1174 } else {
1175 /* VGA */
aeb3c85f 1176 ret = 0;
e6e5ad80
FB		 1177 }
1178
1179 return ret;
1180}
1181
a4a2f59c 1182static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
78e127ef
FB		 1183{
1184 int width, height;
3b46e624 1185
78e127ef 1186 width = (s->cr[0x01] + 1) * 8;
5fafdf24
TS		 1187 height = s->cr[0x12] |
1188 ((s->cr[0x07] & 0x02) << 7) |
78e127ef
FB		 1189 ((s->cr[0x07] & 0x40) << 3);
1190 height = (height + 1);
1191 /* interlace support */
1192 if (s->cr[0x1a] & 0x01)
1193 height = height * 2;
1194 *pwidth = width;
1195 *pheight = height;
1196}
1197
e6e5ad80
FB		 1198/***************************************
1199 *
1200 * bank memory
1201 *
1202 ***************************************/
1203
1204static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1205{
1206 unsigned offset;
1207 unsigned limit;
1208
4e12cd94
AK		 1209 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */
1210 offset = s->vga.gr[0x09 + bank_index];
e6e5ad80 1211 else /* single bank */
4e12cd94 1212 offset = s->vga.gr[0x09];
e6e5ad80 1213
4e12cd94 1214 if ((s->vga.gr[0x0b] & 0x20) != 0)
e6e5ad80
FB		 1215 offset <<= 14;
1216 else
1217 offset <<= 12;
1218
e3a4e4b6 1219 if (s->real_vram_size <= offset)
e6e5ad80
FB		 1220 limit = 0;
1221 else
e3a4e4b6 1222 limit = s->real_vram_size - offset;
e6e5ad80 1223
4e12cd94 1224 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
e6e5ad80
FB		 1225 if (limit > 0x8000) {
1226 offset += 0x8000;
1227 limit -= 0x8000;
1228 } else {
1229 limit = 0;
1230 }
1231 }
1232
1233 if (limit > 0) {
1234 s->cirrus_bank_base[bank_index] = offset;
1235 s->cirrus_bank_limit[bank_index] = limit;
1236 } else {
1237 s->cirrus_bank_base[bank_index] = 0;
1238 s->cirrus_bank_limit[bank_index] = 0;
1239 }
1240}
1241
1242/***************************************
1243 *
1244 * I/O access between 0x3c4-0x3c5
1245 *
1246 ***************************************/
1247
8a82c322 1248static int cirrus_vga_read_sr(CirrusVGAState * s)
e6e5ad80 1249{
8a82c322 1250 switch (s->vga.sr_index) {
e6e5ad80
FB		 1251 case 0x00: // Standard VGA
1252 case 0x01: // Standard VGA
1253 case 0x02: // Standard VGA
1254 case 0x03: // Standard VGA
1255 case 0x04: // Standard VGA
8a82c322 1256 return s->vga.sr[s->vga.sr_index];
e6e5ad80 1257 case 0x06: // Unlock Cirrus extensions
8a82c322 1258 return s->vga.sr[s->vga.sr_index];
e6e5ad80
FB		 1259 case 0x10:
1260 case 0x30:
1261 case 0x50:
1262 case 0x70: // Graphics Cursor X
1263 case 0x90:
1264 case 0xb0:
1265 case 0xd0:
1266 case 0xf0: // Graphics Cursor X
8a82c322 1267 return s->vga.sr[0x10];
e6e5ad80
FB		 1268 case 0x11:
1269 case 0x31:
1270 case 0x51:
1271 case 0x71: // Graphics Cursor Y
1272 case 0x91:
1273 case 0xb1:
1274 case 0xd1:
a5082316 1275 case 0xf1: // Graphics Cursor Y
8a82c322 1276 return s->vga.sr[0x11];
aeb3c85f
FB		 1277 case 0x05: // ???
1278 case 0x07: // Extended Sequencer Mode
1279 case 0x08: // EEPROM Control
1280 case 0x09: // Scratch Register 0
1281 case 0x0a: // Scratch Register 1
1282 case 0x0b: // VCLK 0
1283 case 0x0c: // VCLK 1
1284 case 0x0d: // VCLK 2
1285 case 0x0e: // VCLK 3
1286 case 0x0f: // DRAM Control
e6e5ad80
FB		 1287 case 0x12: // Graphics Cursor Attribute
1288 case 0x13: // Graphics Cursor Pattern Address
1289 case 0x14: // Scratch Register 2
1290 case 0x15: // Scratch Register 3
1291 case 0x16: // Performance Tuning Register
1292 case 0x17: // Configuration Readback and Extended Control
1293 case 0x18: // Signature Generator Control
1294 case 0x19: // Signal Generator Result
1295 case 0x1a: // Signal Generator Result
1296 case 0x1b: // VCLK 0 Denominator & Post
1297 case 0x1c: // VCLK 1 Denominator & Post
1298 case 0x1d: // VCLK 2 Denominator & Post
1299 case 0x1e: // VCLK 3 Denominator & Post
1300 case 0x1f: // BIOS Write Enable and MCLK select
1301#ifdef DEBUG_CIRRUS
8a82c322 1302 printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
e6e5ad80 1303#endif
8a82c322 1304 return s->vga.sr[s->vga.sr_index];
e6e5ad80 1305 default:
2b55f4d3
PMD		 1306 qemu_log_mask(LOG_GUEST_ERROR,
1307 "cirrus: inport sr_index 0x%02x\n", s->vga.sr_index);
8a82c322 1308 return 0xff;
e6e5ad80 1309 }
e6e5ad80
FB		 1310}
1311
31c63201 1312static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
e6e5ad80 1313{
31c63201 1314 switch (s->vga.sr_index) {
e6e5ad80
FB		 1315 case 0x00: // Standard VGA
1316 case 0x01: // Standard VGA
1317 case 0x02: // Standard VGA
1318 case 0x03: // Standard VGA
1319 case 0x04: // Standard VGA
31c63201
JQ		 1320 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
1321 if (s->vga.sr_index == 1)
1322 s->vga.update_retrace_info(&s->vga);
1323 break;
e6e5ad80 1324 case 0x06: // Unlock Cirrus extensions
31c63201
JQ		 1325 val &= 0x17;
1326 if (val == 0x12) {
1327 s->vga.sr[s->vga.sr_index] = 0x12;
e6e5ad80 1328 } else {
31c63201 1329 s->vga.sr[s->vga.sr_index] = 0x0f;
e6e5ad80
FB		 1330 }
1331 break;
1332 case 0x10:
1333 case 0x30:
1334 case 0x50:
1335 case 0x70: // Graphics Cursor X
1336 case 0x90:
1337 case 0xb0:
1338 case 0xd0:
1339 case 0xf0: // Graphics Cursor X
31c63201 1340 s->vga.sr[0x10] = val;
22382bb9 1341 s->vga.hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1342 break;
1343 case 0x11:
1344 case 0x31:
1345 case 0x51:
1346 case 0x71: // Graphics Cursor Y
1347 case 0x91:
1348 case 0xb1:
1349 case 0xd1:
1350 case 0xf1: // Graphics Cursor Y
31c63201 1351 s->vga.sr[0x11] = val;
22382bb9 1352 s->vga.hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1353 break;
1354 case 0x07: // Extended Sequencer Mode
edd7541b
PB		 1355 cirrus_update_memory_access(s);
1356 /* fall through */
e6e5ad80
FB		 1357 case 0x08: // EEPROM Control
1358 case 0x09: // Scratch Register 0
1359 case 0x0a: // Scratch Register 1
1360 case 0x0b: // VCLK 0
1361 case 0x0c: // VCLK 1
1362 case 0x0d: // VCLK 2
1363 case 0x0e: // VCLK 3
1364 case 0x0f: // DRAM Control
e6e5ad80
FB		 1365 case 0x13: // Graphics Cursor Pattern Address
1366 case 0x14: // Scratch Register 2
1367 case 0x15: // Scratch Register 3
1368 case 0x16: // Performance Tuning Register
e6e5ad80
FB		 1369 case 0x18: // Signature Generator Control
1370 case 0x19: // Signature Generator Result
1371 case 0x1a: // Signature Generator Result
1372 case 0x1b: // VCLK 0 Denominator & Post
1373 case 0x1c: // VCLK 1 Denominator & Post
1374 case 0x1d: // VCLK 2 Denominator & Post
1375 case 0x1e: // VCLK 3 Denominator & Post
1376 case 0x1f: // BIOS Write Enable and MCLK select
31c63201 1377 s->vga.sr[s->vga.sr_index] = val;
e6e5ad80
FB		 1378#ifdef DEBUG_CIRRUS
1379 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
31c63201 1380 s->vga.sr_index, val);
e6e5ad80
FB		 1381#endif
1382 break;
b9fd11b8
BH		 1383 case 0x12: // Graphics Cursor Attribute
1384 s->vga.sr[0x12] = val;
1385 s->vga.force_shadow = !!(val & CIRRUS_CURSOR_SHOW);
1386#ifdef DEBUG_CIRRUS
1387 printf("cirrus: cursor ctl SR12=%02x (force shadow: %d)\n",
1388 val, s->vga.force_shadow);
1389#endif
1390 break;
8926b517 1391 case 0x17: // Configuration Readback and Extended Control
31c63201
JQ		 1392 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
1393 | (val & 0xc7);
8926b517
FB		 1394 cirrus_update_memory_access(s);
1395 break;
e6e5ad80 1396 default:
2b55f4d3
PMD		 1397 qemu_log_mask(LOG_GUEST_ERROR,
1398 "cirrus: outport sr_index 0x%02x, sr_value 0x%02x\n",
1399 s->vga.sr_index, val);
e6e5ad80
FB		 1400 break;
1401 }
e6e5ad80
FB		 1402}
1403
1404/***************************************
1405 *
1406 * I/O access at 0x3c6
1407 *
1408 ***************************************/
1409
957c9db5 1410static int cirrus_read_hidden_dac(CirrusVGAState * s)
e6e5ad80 1411{
a21ae81d 1412 if (++s->cirrus_hidden_dac_lockindex == 5) {
957c9db5
JQ		 1413 s->cirrus_hidden_dac_lockindex = 0;
1414 return s->cirrus_hidden_dac_data;
e6e5ad80 1415 }
957c9db5 1416 return 0xff;
e6e5ad80
FB		 1417}
1418
1419static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1420{
1421 if (s->cirrus_hidden_dac_lockindex == 4) {
1422 s->cirrus_hidden_dac_data = reg_value;
a21ae81d 1423#if defined(DEBUG_CIRRUS)
e6e5ad80
FB		 1424 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1425#endif
1426 }
1427 s->cirrus_hidden_dac_lockindex = 0;
1428}
1429
1430/***************************************
1431 *
1432 * I/O access at 0x3c9
1433 *
1434 ***************************************/
1435
5deaeee3 1436static int cirrus_vga_read_palette(CirrusVGAState * s)
e6e5ad80 1437{
5deaeee3
JQ		 1438 int val;
1439
1440 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1441 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1442 s->vga.dac_sub_index];
1443 } else {
1444 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
1445 }
4e12cd94
AK		 1446 if (++s->vga.dac_sub_index == 3) {
1447 s->vga.dac_sub_index = 0;
1448 s->vga.dac_read_index++;
e6e5ad80 1449 }
5deaeee3 1450 return val;
e6e5ad80
FB		 1451}
1452
86948bb1 1453static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value)
e6e5ad80 1454{
4e12cd94
AK		 1455 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1456 if (++s->vga.dac_sub_index == 3) {
86948bb1
JQ		 1457 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1458 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1459 s->vga.dac_cache, 3);
1460 } else {
1461 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
1462 }
a5082316 1463 /* XXX update cursor */
4e12cd94
AK		 1464 s->vga.dac_sub_index = 0;
1465 s->vga.dac_write_index++;
e6e5ad80 1466 }
e6e5ad80
FB		 1467}
1468
1469/***************************************
1470 *
1471 * I/O access between 0x3ce-0x3cf
1472 *
1473 ***************************************/
1474
f705db9d 1475static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1476{
1477 switch (reg_index) {
aeb3c85f 1478 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
f705db9d 1479 return s->cirrus_shadow_gr0;
aeb3c85f 1480 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
f705db9d 1481 return s->cirrus_shadow_gr1;
e6e5ad80
FB		 1482 case 0x02: // Standard VGA
1483 case 0x03: // Standard VGA
1484 case 0x04: // Standard VGA
1485 case 0x06: // Standard VGA
1486 case 0x07: // Standard VGA
1487 case 0x08: // Standard VGA
f705db9d 1488 return s->vga.gr[s->vga.gr_index];
e6e5ad80
FB		 1489 case 0x05: // Standard VGA, Cirrus extended mode
1490 default:
1491 break;
1492 }
1493
1494 if (reg_index < 0x3a) {
f705db9d 1495 return s->vga.gr[reg_index];
e6e5ad80 1496 } else {
2b55f4d3
PMD		 1497 qemu_log_mask(LOG_GUEST_ERROR,
1498 "cirrus: inport gr_index 0x%02x\n", reg_index);
f705db9d 1499 return 0xff;
e6e5ad80 1500 }
e6e5ad80
FB		 1501}
1502
22286bc6
JQ		 1503static void
1504cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
e6e5ad80 1505{
bee61ca2 1506 trace_vga_cirrus_write_gr(reg_index, reg_value);
e6e5ad80
FB		 1507 switch (reg_index) {
1508 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
f22f5b07 1509 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
aeb3c85f 1510 s->cirrus_shadow_gr0 = reg_value;
22286bc6 1511 break;
e6e5ad80 1512 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
f22f5b07 1513 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
aeb3c85f 1514 s->cirrus_shadow_gr1 = reg_value;
22286bc6 1515 break;
e6e5ad80
FB		 1516 case 0x02: // Standard VGA
1517 case 0x03: // Standard VGA
1518 case 0x04: // Standard VGA
1519 case 0x06: // Standard VGA
1520 case 0x07: // Standard VGA
1521 case 0x08: // Standard VGA
22286bc6
JQ		 1522 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1523 break;
e6e5ad80 1524 case 0x05: // Standard VGA, Cirrus extended mode
4e12cd94 1525 s->vga.gr[reg_index] = reg_value & 0x7f;
8926b517 1526 cirrus_update_memory_access(s);
e6e5ad80
FB		 1527 break;
1528 case 0x09: // bank offset #0
1529 case 0x0A: // bank offset #1
4e12cd94 1530 s->vga.gr[reg_index] = reg_value;
8926b517
FB		 1531 cirrus_update_bank_ptr(s, 0);
1532 cirrus_update_bank_ptr(s, 1);
2bec46dc 1533 cirrus_update_memory_access(s);
8926b517 1534 break;
e6e5ad80 1535 case 0x0B:
4e12cd94 1536 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1537 cirrus_update_bank_ptr(s, 0);
1538 cirrus_update_bank_ptr(s, 1);
8926b517 1539 cirrus_update_memory_access(s);
e6e5ad80
FB		 1540 break;
1541 case 0x10: // BGCOLOR 0x0000ff00
1542 case 0x11: // FGCOLOR 0x0000ff00
1543 case 0x12: // BGCOLOR 0x00ff0000
1544 case 0x13: // FGCOLOR 0x00ff0000
1545 case 0x14: // BGCOLOR 0xff000000
1546 case 0x15: // FGCOLOR 0xff000000
1547 case 0x20: // BLT WIDTH 0x0000ff
1548 case 0x22: // BLT HEIGHT 0x0000ff
1549 case 0x24: // BLT DEST PITCH 0x0000ff
1550 case 0x26: // BLT SRC PITCH 0x0000ff
1551 case 0x28: // BLT DEST ADDR 0x0000ff
1552 case 0x29: // BLT DEST ADDR 0x00ff00
1553 case 0x2c: // BLT SRC ADDR 0x0000ff
1554 case 0x2d: // BLT SRC ADDR 0x00ff00
a5082316 1555 case 0x2f: // BLT WRITEMASK
e6e5ad80
FB		 1556 case 0x30: // BLT MODE
1557 case 0x32: // RASTER OP
a21ae81d 1558 case 0x33: // BLT MODEEXT
e6e5ad80
FB		 1559 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1560 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1561 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1562 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
4e12cd94 1563 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1564 break;
1565 case 0x21: // BLT WIDTH 0x001f00
1566 case 0x23: // BLT HEIGHT 0x001f00
1567 case 0x25: // BLT DEST PITCH 0x001f00
1568 case 0x27: // BLT SRC PITCH 0x001f00
4e12cd94 1569 s->vga.gr[reg_index] = reg_value & 0x1f;
e6e5ad80
FB		 1570 break;
1571 case 0x2a: // BLT DEST ADDR 0x3f0000
4e12cd94 1572 s->vga.gr[reg_index] = reg_value & 0x3f;
a5082316 1573 /* if auto start mode, starts bit blt now */
4e12cd94 1574 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
a5082316
FB		 1575 cirrus_bitblt_start(s);
1576 }
1577 break;
e6e5ad80 1578 case 0x2e: // BLT SRC ADDR 0x3f0000
4e12cd94 1579 s->vga.gr[reg_index] = reg_value & 0x3f;
e6e5ad80
FB		 1580 break;
1581 case 0x31: // BLT STATUS/START
1582 cirrus_write_bitblt(s, reg_value);
1583 break;
1584 default:
2b55f4d3
PMD		 1585 qemu_log_mask(LOG_GUEST_ERROR,
1586 "cirrus: outport gr_index 0x%02x, gr_value 0x%02x\n",
1587 reg_index, reg_value);
e6e5ad80
FB		 1588 break;
1589 }
e6e5ad80
FB		 1590}
1591
1592/***************************************
1593 *
1594 * I/O access between 0x3d4-0x3d5
1595 *
1596 ***************************************/
1597
b863d514 1598static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1599{
1600 switch (reg_index) {
1601 case 0x00: // Standard VGA
1602 case 0x01: // Standard VGA
1603 case 0x02: // Standard VGA
1604 case 0x03: // Standard VGA
1605 case 0x04: // Standard VGA
1606 case 0x05: // Standard VGA
1607 case 0x06: // Standard VGA
1608 case 0x07: // Standard VGA
1609 case 0x08: // Standard VGA
1610 case 0x09: // Standard VGA
1611 case 0x0a: // Standard VGA
1612 case 0x0b: // Standard VGA
1613 case 0x0c: // Standard VGA
1614 case 0x0d: // Standard VGA
1615 case 0x0e: // Standard VGA
1616 case 0x0f: // Standard VGA
1617 case 0x10: // Standard VGA
1618 case 0x11: // Standard VGA
1619 case 0x12: // Standard VGA
1620 case 0x13: // Standard VGA
1621 case 0x14: // Standard VGA
1622 case 0x15: // Standard VGA
1623 case 0x16: // Standard VGA
1624 case 0x17: // Standard VGA
1625 case 0x18: // Standard VGA
b863d514 1626 return s->vga.cr[s->vga.cr_index];
ca896ef3 1627 case 0x24: // Attribute Controller Toggle Readback (R)
b863d514 1628 return (s->vga.ar_flip_flop << 7);
e6e5ad80
FB		 1629 case 0x19: // Interlace End
1630 case 0x1a: // Miscellaneous Control
1631 case 0x1b: // Extended Display Control
1632 case 0x1c: // Sync Adjust and Genlock
1633 case 0x1d: // Overlay Extended Control
1634 case 0x22: // Graphics Data Latches Readback (R)
e6e5ad80
FB		 1635 case 0x25: // Part Status
1636 case 0x27: // Part ID (R)
b863d514 1637 return s->vga.cr[s->vga.cr_index];
e6e5ad80 1638 case 0x26: // Attribute Controller Index Readback (R)
b863d514 1639 return s->vga.ar_index & 0x3f;
e6e5ad80 1640 default:
2b55f4d3
PMD		 1641 qemu_log_mask(LOG_GUEST_ERROR,
1642 "cirrus: inport cr_index 0x%02x\n", reg_index);
b863d514 1643 return 0xff;
e6e5ad80 1644 }
e6e5ad80
FB		 1645}
1646
4ec1ce04 1647static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
e6e5ad80 1648{
4ec1ce04 1649 switch (s->vga.cr_index) {
e6e5ad80
FB		 1650 case 0x00: // Standard VGA
1651 case 0x01: // Standard VGA
1652 case 0x02: // Standard VGA
1653 case 0x03: // Standard VGA
1654 case 0x04: // Standard VGA
1655 case 0x05: // Standard VGA
1656 case 0x06: // Standard VGA
1657 case 0x07: // Standard VGA
1658 case 0x08: // Standard VGA
1659 case 0x09: // Standard VGA
1660 case 0x0a: // Standard VGA
1661 case 0x0b: // Standard VGA
1662 case 0x0c: // Standard VGA
1663 case 0x0d: // Standard VGA
1664 case 0x0e: // Standard VGA
1665 case 0x0f: // Standard VGA
1666 case 0x10: // Standard VGA
1667 case 0x11: // Standard VGA
1668 case 0x12: // Standard VGA
1669 case 0x13: // Standard VGA
1670 case 0x14: // Standard VGA
1671 case 0x15: // Standard VGA
1672 case 0x16: // Standard VGA
1673 case 0x17: // Standard VGA
1674 case 0x18: // Standard VGA
4ec1ce04
JQ		 1675 /* handle CR0-7 protection */
1676 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
1677 /* can always write bit 4 of CR7 */
1678 if (s->vga.cr_index == 7)
1679 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10);
1680 return;
1681 }
1682 s->vga.cr[s->vga.cr_index] = reg_value;
1683 switch(s->vga.cr_index) {
1684 case 0x00:
1685 case 0x04:
1686 case 0x05:
1687 case 0x06:
1688 case 0x07:
1689 case 0x11:
1690 case 0x17:
1691 s->vga.update_retrace_info(&s->vga);
1692 break;
1693 }
1694 break;
e6e5ad80
FB		 1695 case 0x19: // Interlace End
1696 case 0x1a: // Miscellaneous Control
1697 case 0x1b: // Extended Display Control
1698 case 0x1c: // Sync Adjust and Genlock
ae184e4a 1699 case 0x1d: // Overlay Extended Control
4ec1ce04 1700 s->vga.cr[s->vga.cr_index] = reg_value;
e6e5ad80
FB		 1701#ifdef DEBUG_CIRRUS
1702 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
4ec1ce04 1703 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1704#endif
1705 break;
1706 case 0x22: // Graphics Data Latches Readback (R)
1707 case 0x24: // Attribute Controller Toggle Readback (R)
1708 case 0x26: // Attribute Controller Index Readback (R)
1709 case 0x27: // Part ID (R)
1710 break;
e6e5ad80
FB		 1711 case 0x25: // Part Status
1712 default:
2b55f4d3
PMD		 1713 qemu_log_mask(LOG_GUEST_ERROR,
1714 "cirrus: outport cr_index 0x%02x, cr_value 0x%02x\n",
1715 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1716 break;
1717 }
e6e5ad80
FB		 1718}
1719
1720/***************************************
1721 *
1722 * memory-mapped I/O (bitblt)
1723 *
1724 ***************************************/
1725
1726static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1727{
1728 int value = 0xff;
1729
1730 switch (address) {
1731 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
f705db9d 1732 value = cirrus_vga_read_gr(s, 0x00);
e6e5ad80
FB		 1733 break;
1734 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
f705db9d 1735 value = cirrus_vga_read_gr(s, 0x10);
e6e5ad80
FB		 1736 break;
1737 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
f705db9d 1738 value = cirrus_vga_read_gr(s, 0x12);
e6e5ad80
FB		 1739 break;
1740 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
f705db9d 1741 value = cirrus_vga_read_gr(s, 0x14);
e6e5ad80
FB		 1742 break;
1743 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
f705db9d 1744 value = cirrus_vga_read_gr(s, 0x01);
e6e5ad80
FB		 1745 break;
1746 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
f705db9d 1747 value = cirrus_vga_read_gr(s, 0x11);
e6e5ad80
FB		 1748 break;
1749 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
f705db9d 1750 value = cirrus_vga_read_gr(s, 0x13);
e6e5ad80
FB		 1751 break;
1752 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
f705db9d 1753 value = cirrus_vga_read_gr(s, 0x15);
e6e5ad80
FB		 1754 break;
1755 case (CIRRUS_MMIO_BLTWIDTH + 0):
f705db9d 1756 value = cirrus_vga_read_gr(s, 0x20);
e6e5ad80
FB		 1757 break;
1758 case (CIRRUS_MMIO_BLTWIDTH + 1):
f705db9d 1759 value = cirrus_vga_read_gr(s, 0x21);
e6e5ad80
FB		 1760 break;
1761 case (CIRRUS_MMIO_BLTHEIGHT + 0):
f705db9d 1762 value = cirrus_vga_read_gr(s, 0x22);
e6e5ad80
FB		 1763 break;
1764 case (CIRRUS_MMIO_BLTHEIGHT + 1):
f705db9d 1765 value = cirrus_vga_read_gr(s, 0x23);
e6e5ad80
FB		 1766 break;
1767 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
f705db9d 1768 value = cirrus_vga_read_gr(s, 0x24);
e6e5ad80
FB		 1769 break;
1770 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
f705db9d 1771 value = cirrus_vga_read_gr(s, 0x25);
e6e5ad80
FB		 1772 break;
1773 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
f705db9d 1774 value = cirrus_vga_read_gr(s, 0x26);
e6e5ad80
FB		 1775 break;
1776 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
f705db9d 1777 value = cirrus_vga_read_gr(s, 0x27);
e6e5ad80
FB		 1778 break;
1779 case (CIRRUS_MMIO_BLTDESTADDR + 0):
f705db9d 1780 value = cirrus_vga_read_gr(s, 0x28);
e6e5ad80
FB		 1781 break;
1782 case (CIRRUS_MMIO_BLTDESTADDR + 1):
f705db9d 1783 value = cirrus_vga_read_gr(s, 0x29);
e6e5ad80
FB		 1784 break;
1785 case (CIRRUS_MMIO_BLTDESTADDR + 2):
f705db9d 1786 value = cirrus_vga_read_gr(s, 0x2a);
e6e5ad80
FB		 1787 break;
1788 case (CIRRUS_MMIO_BLTSRCADDR + 0):
f705db9d 1789 value = cirrus_vga_read_gr(s, 0x2c);
e6e5ad80
FB		 1790 break;
1791 case (CIRRUS_MMIO_BLTSRCADDR + 1):
f705db9d 1792 value = cirrus_vga_read_gr(s, 0x2d);
e6e5ad80
FB		 1793 break;
1794 case (CIRRUS_MMIO_BLTSRCADDR + 2):
f705db9d 1795 value = cirrus_vga_read_gr(s, 0x2e);
e6e5ad80
FB		 1796 break;
1797 case CIRRUS_MMIO_BLTWRITEMASK:
f705db9d 1798 value = cirrus_vga_read_gr(s, 0x2f);
e6e5ad80
FB		 1799 break;
1800 case CIRRUS_MMIO_BLTMODE:
f705db9d 1801 value = cirrus_vga_read_gr(s, 0x30);
e6e5ad80
FB		 1802 break;
1803 case CIRRUS_MMIO_BLTROP:
f705db9d 1804 value = cirrus_vga_read_gr(s, 0x32);
e6e5ad80 1805 break;
a21ae81d 1806 case CIRRUS_MMIO_BLTMODEEXT:
f705db9d 1807 value = cirrus_vga_read_gr(s, 0x33);
a21ae81d 1808 break;
e6e5ad80 1809 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
f705db9d 1810 value = cirrus_vga_read_gr(s, 0x34);
e6e5ad80
FB		 1811 break;
1812 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
f705db9d 1813 value = cirrus_vga_read_gr(s, 0x35);
e6e5ad80
FB		 1814 break;
1815 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
f705db9d 1816 value = cirrus_vga_read_gr(s, 0x38);
e6e5ad80
FB		 1817 break;
1818 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
f705db9d 1819 value = cirrus_vga_read_gr(s, 0x39);
e6e5ad80
FB		 1820 break;
1821 case CIRRUS_MMIO_BLTSTATUS:
f705db9d 1822 value = cirrus_vga_read_gr(s, 0x31);
e6e5ad80
FB		 1823 break;
1824 default:
2b55f4d3
PMD		 1825 qemu_log_mask(LOG_GUEST_ERROR,
1826 "cirrus: mmio read - address 0x%04x\n", address);
e6e5ad80
FB		 1827 break;
1828 }
1829
ec87f206 1830 trace_vga_cirrus_write_blt(address, value);
e6e5ad80
FB		 1831 return (uint8_t) value;
1832}
1833
1834static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1835 uint8_t value)
1836{
ec87f206 1837 trace_vga_cirrus_write_blt(address, value);
e6e5ad80
FB		 1838 switch (address) {
1839 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
22286bc6 1840 cirrus_vga_write_gr(s, 0x00, value);
e6e5ad80
FB		 1841 break;
1842 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
22286bc6 1843 cirrus_vga_write_gr(s, 0x10, value);
e6e5ad80
FB		 1844 break;
1845 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
22286bc6 1846 cirrus_vga_write_gr(s, 0x12, value);
e6e5ad80
FB		 1847 break;
1848 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
22286bc6 1849 cirrus_vga_write_gr(s, 0x14, value);
e6e5ad80
FB		 1850 break;
1851 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
22286bc6 1852 cirrus_vga_write_gr(s, 0x01, value);
e6e5ad80
FB		 1853 break;
1854 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
22286bc6 1855 cirrus_vga_write_gr(s, 0x11, value);
e6e5ad80
FB		 1856 break;
1857 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
22286bc6 1858 cirrus_vga_write_gr(s, 0x13, value);
e6e5ad80
FB		 1859 break;
1860 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
22286bc6 1861 cirrus_vga_write_gr(s, 0x15, value);
e6e5ad80
FB		 1862 break;
1863 case (CIRRUS_MMIO_BLTWIDTH + 0):
22286bc6 1864 cirrus_vga_write_gr(s, 0x20, value);
e6e5ad80
FB		 1865 break;
1866 case (CIRRUS_MMIO_BLTWIDTH + 1):
22286bc6 1867 cirrus_vga_write_gr(s, 0x21, value);
e6e5ad80
FB		 1868 break;
1869 case (CIRRUS_MMIO_BLTHEIGHT + 0):
22286bc6 1870 cirrus_vga_write_gr(s, 0x22, value);
e6e5ad80
FB		 1871 break;
1872 case (CIRRUS_MMIO_BLTHEIGHT + 1):
22286bc6 1873 cirrus_vga_write_gr(s, 0x23, value);
e6e5ad80
FB		 1874 break;
1875 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
22286bc6 1876 cirrus_vga_write_gr(s, 0x24, value);
e6e5ad80
FB		 1877 break;
1878 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
22286bc6 1879 cirrus_vga_write_gr(s, 0x25, value);
e6e5ad80
FB		 1880 break;
1881 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
22286bc6 1882 cirrus_vga_write_gr(s, 0x26, value);
e6e5ad80
FB		 1883 break;
1884 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
22286bc6 1885 cirrus_vga_write_gr(s, 0x27, value);
e6e5ad80
FB		 1886 break;
1887 case (CIRRUS_MMIO_BLTDESTADDR + 0):
22286bc6 1888 cirrus_vga_write_gr(s, 0x28, value);
e6e5ad80
FB		 1889 break;
1890 case (CIRRUS_MMIO_BLTDESTADDR + 1):
22286bc6 1891 cirrus_vga_write_gr(s, 0x29, value);
e6e5ad80
FB		 1892 break;
1893 case (CIRRUS_MMIO_BLTDESTADDR + 2):
22286bc6 1894 cirrus_vga_write_gr(s, 0x2a, value);
e6e5ad80
FB		 1895 break;
1896 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1897 /* ignored */
1898 break;
1899 case (CIRRUS_MMIO_BLTSRCADDR + 0):
22286bc6 1900 cirrus_vga_write_gr(s, 0x2c, value);
e6e5ad80
FB		 1901 break;
1902 case (CIRRUS_MMIO_BLTSRCADDR + 1):
22286bc6 1903 cirrus_vga_write_gr(s, 0x2d, value);
e6e5ad80
FB		 1904 break;
1905 case (CIRRUS_MMIO_BLTSRCADDR + 2):
22286bc6 1906 cirrus_vga_write_gr(s, 0x2e, value);
e6e5ad80
FB		 1907 break;
1908 case CIRRUS_MMIO_BLTWRITEMASK:
22286bc6 1909 cirrus_vga_write_gr(s, 0x2f, value);
e6e5ad80
FB		 1910 break;
1911 case CIRRUS_MMIO_BLTMODE:
22286bc6 1912 cirrus_vga_write_gr(s, 0x30, value);
e6e5ad80
FB		 1913 break;
1914 case CIRRUS_MMIO_BLTROP:
22286bc6 1915 cirrus_vga_write_gr(s, 0x32, value);
e6e5ad80 1916 break;
a21ae81d 1917 case CIRRUS_MMIO_BLTMODEEXT:
22286bc6 1918 cirrus_vga_write_gr(s, 0x33, value);
a21ae81d 1919 break;
e6e5ad80 1920 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
22286bc6 1921 cirrus_vga_write_gr(s, 0x34, value);
e6e5ad80
FB		 1922 break;
1923 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
22286bc6 1924 cirrus_vga_write_gr(s, 0x35, value);
e6e5ad80
FB		 1925 break;
1926 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
22286bc6 1927 cirrus_vga_write_gr(s, 0x38, value);
e6e5ad80
FB		 1928 break;
1929 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
22286bc6 1930 cirrus_vga_write_gr(s, 0x39, value);
e6e5ad80
FB		 1931 break;
1932 case CIRRUS_MMIO_BLTSTATUS:
22286bc6 1933 cirrus_vga_write_gr(s, 0x31, value);
e6e5ad80
FB		 1934 break;
1935 default:
2b55f4d3
PMD		 1936 qemu_log_mask(LOG_GUEST_ERROR,
1937 "cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1938 address, value);
e6e5ad80
FB		 1939 break;
1940 }
1941}
1942
e6e5ad80
FB		 1943/***************************************
1944 *
1945 * write mode 4/5
1946 *
e6e5ad80
FB		 1947 ***************************************/
1948
1949static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1950 unsigned mode,
1951 unsigned offset,
1952 uint32_t mem_value)
1953{
1954 int x;
1955 unsigned val = mem_value;
1956 uint8_t *dst;
1957
e6e5ad80 1958 for (x = 0; x < 8; x++) {
eb38e1bc 1959 dst = s->vga.vram_ptr + ((offset + x) & s->cirrus_addr_mask);
e6e5ad80 1960 if (val & 0x80) {
0b74ed78 1961 *dst = s->cirrus_shadow_gr1;
e6e5ad80 1962 } else if (mode == 5) {
0b74ed78 1963 *dst = s->cirrus_shadow_gr0;
e6e5ad80
FB		 1964 }
1965 val <<= 1;
1966 }
fd4aa979 1967 memory_region_set_dirty(&s->vga.vram, offset, 8);
e6e5ad80
FB		 1968}
1969
1970static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1971 unsigned mode,
1972 unsigned offset,
1973 uint32_t mem_value)
1974{
1975 int x;
1976 unsigned val = mem_value;
1977 uint8_t *dst;
1978
e6e5ad80 1979 for (x = 0; x < 8; x++) {
eb38e1bc 1980 dst = s->vga.vram_ptr + ((offset + 2 * x) & s->cirrus_addr_mask & ~1);
e6e5ad80 1981 if (val & 0x80) {
0b74ed78 1982 *dst = s->cirrus_shadow_gr1;
4e12cd94 1983 *(dst + 1) = s->vga.gr[0x11];
e6e5ad80 1984 } else if (mode == 5) {
0b74ed78 1985 *dst = s->cirrus_shadow_gr0;
4e12cd94 1986 *(dst + 1) = s->vga.gr[0x10];
e6e5ad80
FB		 1987 }
1988 val <<= 1;
1989 }
fd4aa979 1990 memory_region_set_dirty(&s->vga.vram, offset, 16);
e6e5ad80
FB		 1991}
1992
1993/***************************************
1994 *
1995 * memory access between 0xa0000-0xbffff
1996 *
1997 ***************************************/
1998
a815b166 1999static uint64_t cirrus_vga_mem_read(void *opaque,
a8170e5e 2000 hwaddr addr,
a815b166 2001 uint32_t size)
e6e5ad80
FB		 2002{
2003 CirrusVGAState *s = opaque;
2004 unsigned bank_index;
2005 unsigned bank_offset;
2006 uint32_t val;
2007
4e12cd94 2008 if ((s->vga.sr[0x07] & 0x01) == 0) {
b2a5e761 2009 return vga_mem_readb(&s->vga, addr);
e6e5ad80
FB		 2010 }
2011
2012 if (addr < 0x10000) {
2013 /* XXX handle bitblt */
2014 /* video memory */
2015 bank_index = addr >> 15;
2016 bank_offset = addr & 0x7fff;
2017 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2018 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 2019 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2020 bank_offset <<= 4;
4e12cd94 2021 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2022 bank_offset <<= 3;
2023 }
2024 bank_offset &= s->cirrus_addr_mask;
4e12cd94 2025 val = *(s->vga.vram_ptr + bank_offset);
e6e5ad80
FB		 2026 } else
2027 val = 0xff;
2028 } else if (addr >= 0x18000 && addr < 0x18100) {
2029 /* memory-mapped I/O */
2030 val = 0xff;
4e12cd94 2031 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 2032 val = cirrus_mmio_blt_read(s, addr & 0xff);
2033 }
2034 } else {
2035 val = 0xff;
2b55f4d3
PMD		 2036 qemu_log_mask(LOG_GUEST_ERROR,
2037 "cirrus: mem_readb 0x" TARGET_FMT_plx "\n", addr);
e6e5ad80
FB		 2038 }
2039 return val;
2040}
2041
a815b166 2042static void cirrus_vga_mem_write(void *opaque,
a8170e5e 2043 hwaddr addr,
a815b166
AK		 2044 uint64_t mem_value,
2045 uint32_t size)
e6e5ad80
FB		 2046{
2047 CirrusVGAState *s = opaque;
2048 unsigned bank_index;
2049 unsigned bank_offset;
2050 unsigned mode;
2051
4e12cd94 2052 if ((s->vga.sr[0x07] & 0x01) == 0) {
b2a5e761 2053 vga_mem_writeb(&s->vga, addr, mem_value);
e6e5ad80
FB		 2054 return;
2055 }
2056
2057 if (addr < 0x10000) {
2058 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2059 /* bitblt */
2060 *s->cirrus_srcptr++ = (uint8_t) mem_value;
a5082316 2061 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2062 cirrus_bitblt_cputovideo_next(s);
2063 }
2064 } else {
2065 /* video memory */
2066 bank_index = addr >> 15;
2067 bank_offset = addr & 0x7fff;
2068 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2069 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 2070 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2071 bank_offset <<= 4;
4e12cd94 2072 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2073 bank_offset <<= 3;
2074 }
2075 bank_offset &= s->cirrus_addr_mask;
4e12cd94
AK		 2076 mode = s->vga.gr[0x05] & 0x7;
2077 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2078 *(s->vga.vram_ptr + bank_offset) = mem_value;
fd4aa979
BS		 2079 memory_region_set_dirty(&s->vga.vram, bank_offset,
2080 sizeof(mem_value));
e6e5ad80 2081 } else {
4e12cd94 2082 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2083 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2084 bank_offset,
2085 mem_value);
2086 } else {
2087 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2088 bank_offset,
2089 mem_value);
2090 }
2091 }
2092 }
2093 }
2094 } else if (addr >= 0x18000 && addr < 0x18100) {
2095 /* memory-mapped I/O */
4e12cd94 2096 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 2097 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2098 }
2099 } else {
2b55f4d3
PMD		 2100 qemu_log_mask(LOG_GUEST_ERROR,
2101 "cirrus: mem_writeb 0x" TARGET_FMT_plx " "
2102 "value 0x%02" PRIu64 "\n", addr, mem_value);
e6e5ad80
FB		 2103 }
2104}
2105
b1950430
AK		 2106static const MemoryRegionOps cirrus_vga_mem_ops = {
2107 .read = cirrus_vga_mem_read,
2108 .write = cirrus_vga_mem_write,
2109 .endianness = DEVICE_LITTLE_ENDIAN,
a815b166
AK		 2110 .impl = {
2111 .min_access_size = 1,
2112 .max_access_size = 1,
2113 },
e6e5ad80
FB		 2114};
2115
a5082316
FB		 2116/***************************************
2117 *
2118 * hardware cursor
2119 *
2120 ***************************************/
2121
2122static inline void invalidate_cursor1(CirrusVGAState *s)
2123{
2124 if (s->last_hw_cursor_size) {
4e12cd94 2125 vga_invalidate_scanlines(&s->vga,
a5082316
FB		 2126 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2127 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2128 }
2129}
2130
2131static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2132{
2133 const uint8_t *src;
2134 uint32_t content;
2135 int y, y_min, y_max;
2136
f0353b0d 2137 src = s->vga.vram_ptr + s->real_vram_size - 16 * KiB;
4e12cd94
AK		 2138 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2139 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2140 y_min = 64;
2141 y_max = -1;
2142 for(y = 0; y < 64; y++) {
2143 content = ((uint32_t *)src)[0] |
2144 ((uint32_t *)src)[1] |
2145 ((uint32_t *)src)[2] |
2146 ((uint32_t *)src)[3];
2147 if (content) {
2148 if (y < y_min)
2149 y_min = y;
2150 if (y > y_max)
2151 y_max = y;
2152 }
2153 src += 16;
2154 }
2155 } else {
4e12cd94 2156 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316
FB		 2157 y_min = 32;
2158 y_max = -1;
2159 for(y = 0; y < 32; y++) {
2160 content = ((uint32_t *)src)[0] |
2161 ((uint32_t *)(src + 128))[0];
2162 if (content) {
2163 if (y < y_min)
2164 y_min = y;
2165 if (y > y_max)
2166 y_max = y;
2167 }
2168 src += 4;
2169 }
2170 }
2171 if (y_min > y_max) {
2172 s->last_hw_cursor_y_start = 0;
2173 s->last_hw_cursor_y_end = 0;
2174 } else {
2175 s->last_hw_cursor_y_start = y_min;
2176 s->last_hw_cursor_y_end = y_max + 1;
2177 }
2178}
2179
2180/* NOTE: we do not currently handle the cursor bitmap change, so we
2181 update the cursor only if it moves. */
a4a2f59c 2182static void cirrus_cursor_invalidate(VGACommonState *s1)
a5082316 2183{
4e12cd94 2184 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
a5082316
FB		 2185 int size;
2186
4e12cd94 2187 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
a5082316
FB		 2188 size = 0;
2189 } else {
4e12cd94 2190 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
a5082316
FB		 2191 size = 64;
2192 else
2193 size = 32;
2194 }
2195 /* invalidate last cursor and new cursor if any change */
2196 if (s->last_hw_cursor_size != size ||
22382bb9
GH		 2197 s->last_hw_cursor_x != s->vga.hw_cursor_x ||
2198 s->last_hw_cursor_y != s->vga.hw_cursor_y) {
a5082316
FB		 2199
2200 invalidate_cursor1(s);
3b46e624 2201
a5082316 2202 s->last_hw_cursor_size = size;
22382bb9
GH		 2203 s->last_hw_cursor_x = s->vga.hw_cursor_x;
2204 s->last_hw_cursor_y = s->vga.hw_cursor_y;
a5082316
FB		 2205 /* compute the real cursor min and max y */
2206 cirrus_cursor_compute_yrange(s);
2207 invalidate_cursor1(s);
2208 }
2209}
2210
70a041fe
BH		 2211static void vga_draw_cursor_line(uint8_t *d1,
2212 const uint8_t *src1,
2213 int poffset, int w,
2214 unsigned int color0,
2215 unsigned int color1,
2216 unsigned int color_xor)
2217{
2218 const uint8_t *plane0, *plane1;
2219 int x, b0, b1;
2220 uint8_t *d;
2221
2222 d = d1;
2223 plane0 = src1;
2224 plane1 = src1 + poffset;
2225 for (x = 0; x < w; x++) {
2226 b0 = (plane0[x >> 3] >> (7 - (x & 7))) & 1;
2227 b1 = (plane1[x >> 3] >> (7 - (x & 7))) & 1;
2228 switch (b0 | (b1 << 1)) {
2229 case 0:
2230 break;
2231 case 1:
2232 ((uint32_t *)d)[0] ^= color_xor;
2233 break;
2234 case 2:
2235 ((uint32_t *)d)[0] = color0;
2236 break;
2237 case 3:
2238 ((uint32_t *)d)[0] = color1;
2239 break;
2240 }
2241 d += 4;
2242 }
2243}
94d7b483 2244
a4a2f59c 2245static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
a5082316 2246{
4e12cd94 2247 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
70a041fe 2248 int w, h, x1, x2, poffset;
a5082316
FB		 2249 unsigned int color0, color1;
2250 const uint8_t *palette, *src;
2251 uint32_t content;
3b46e624 2252
4e12cd94 2253 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
a5082316
FB		 2254 return;
2255 /* fast test to see if the cursor intersects with the scan line */
4e12cd94 2256 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
a5082316
FB		 2257 h = 64;
2258 } else {
2259 h = 32;
2260 }
22382bb9
GH		 2261 if (scr_y < s->vga.hw_cursor_y ||
2262 scr_y >= (s->vga.hw_cursor_y + h)) {
a5082316 2263 return;
22382bb9 2264 }
3b46e624 2265
f0353b0d 2266 src = s->vga.vram_ptr + s->real_vram_size - 16 * KiB;
4e12cd94
AK		 2267 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2268 src += (s->vga.sr[0x13] & 0x3c) * 256;
22382bb9 2269 src += (scr_y - s->vga.hw_cursor_y) * 16;
a5082316
FB		 2270 poffset = 8;
2271 content = ((uint32_t *)src)[0] |
2272 ((uint32_t *)src)[1] |
2273 ((uint32_t *)src)[2] |
2274 ((uint32_t *)src)[3];
2275 } else {
4e12cd94 2276 src += (s->vga.sr[0x13] & 0x3f) * 256;
22382bb9 2277 src += (scr_y - s->vga.hw_cursor_y) * 4;
d3c2343a
BH		 2278
2279
a5082316
FB		 2280 poffset = 128;
2281 content = ((uint32_t *)src)[0] |
2282 ((uint32_t *)(src + 128))[0];
2283 }
2284 /* if nothing to draw, no need to continue */
2285 if (!content)
2286 return;
2287 w = h;
2288
22382bb9 2289 x1 = s->vga.hw_cursor_x;
4e12cd94 2290 if (x1 >= s->vga.last_scr_width)
a5082316 2291 return;
22382bb9 2292 x2 = s->vga.hw_cursor_x + w;
4e12cd94
AK		 2293 if (x2 > s->vga.last_scr_width)
2294 x2 = s->vga.last_scr_width;
a5082316
FB		 2295 w = x2 - x1;
2296 palette = s->cirrus_hidden_palette;
d3c2343a
BH		 2297 color0 = rgb_to_pixel32(c6_to_8(palette[0x0 * 3]),
2298 c6_to_8(palette[0x0 * 3 + 1]),
2299 c6_to_8(palette[0x0 * 3 + 2]));
2300 color1 = rgb_to_pixel32(c6_to_8(palette[0xf * 3]),
2301 c6_to_8(palette[0xf * 3 + 1]),
2302 c6_to_8(palette[0xf * 3 + 2]));
70a041fe
BH		 2303 d1 += x1 * 4;
2304 vga_draw_cursor_line(d1, src, poffset, w, color0, color1, 0xffffff);
a5082316
FB		 2305}
2306
e6e5ad80
FB		 2307/***************************************
2308 *
2309 * LFB memory access
2310 *
2311 ***************************************/
2312
a8170e5e 2313static uint64_t cirrus_linear_read(void *opaque, hwaddr addr,
899adf81 2314 unsigned size)
e6e5ad80 2315{
e05587e8 2316 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2317 uint32_t ret;
2318
e6e5ad80
FB		 2319 addr &= s->cirrus_addr_mask;
2320
4e12cd94 2321 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2322 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2323 /* memory-mapped I/O */
2324 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2325 } else if (0) {
2326 /* XXX handle bitblt */
2327 ret = 0xff;
2328 } else {
2329 /* video memory */
4e12cd94 2330 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2331 addr <<= 4;
4e12cd94 2332 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2333 addr <<= 3;
2334 }
2335 addr &= s->cirrus_addr_mask;
4e12cd94 2336 ret = *(s->vga.vram_ptr + addr);
e6e5ad80
FB		 2337 }
2338
2339 return ret;
2340}
2341
a8170e5e 2342static void cirrus_linear_write(void *opaque, hwaddr addr,
899adf81 2343 uint64_t val, unsigned size)
e6e5ad80 2344{
e05587e8 2345 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2346 unsigned mode;
2347
2348 addr &= s->cirrus_addr_mask;
3b46e624 2349
4e12cd94 2350 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2351 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2352 /* memory-mapped I/O */
2353 cirrus_mmio_blt_write(s, addr & 0xff, val);
2354 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2355 /* bitblt */
2356 *s->cirrus_srcptr++ = (uint8_t) val;
a5082316 2357 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2358 cirrus_bitblt_cputovideo_next(s);
2359 }
2360 } else {
2361 /* video memory */
4e12cd94 2362 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2363 addr <<= 4;
4e12cd94 2364 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2365 addr <<= 3;
2366 }
2367 addr &= s->cirrus_addr_mask;
2368
4e12cd94
AK		 2369 mode = s->vga.gr[0x05] & 0x7;
2370 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2371 *(s->vga.vram_ptr + addr) = (uint8_t) val;
fd4aa979 2372 memory_region_set_dirty(&s->vga.vram, addr, 1);
e6e5ad80 2373 } else {
4e12cd94 2374 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2375 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2376 } else {
2377 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2378 }
2379 }
2380 }
2381}
2382
a5082316
FB		 2383/***************************************
2384 *
2385 * system to screen memory access
2386 *
2387 ***************************************/
2388
2389
4e56f089 2390static uint64_t cirrus_linear_bitblt_read(void *opaque,
a8170e5e 2391 hwaddr addr,
4e56f089 2392 unsigned size)
a5082316 2393{
4e56f089 2394 CirrusVGAState *s = opaque;
a5082316
FB		 2395
2396 /* XXX handle bitblt */
4e56f089 2397 (void)s;
bb6e9e94
PMD		 2398 qemu_log_mask(LOG_UNIMP,
2399 "cirrus: linear bitblt is not implemented\n");
2400
b3ac2b94 2401 return 0xff;
a5082316
FB		 2402}
2403
4e56f089 2404static void cirrus_linear_bitblt_write(void *opaque,
a8170e5e 2405 hwaddr addr,
4e56f089
AK		 2406 uint64_t val,
2407 unsigned size)
a5082316 2408{
e05587e8 2409 CirrusVGAState *s = opaque;
a5082316
FB		 2410
2411 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2412 /* bitblt */
2413 *s->cirrus_srcptr++ = (uint8_t) val;
2414 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2415 cirrus_bitblt_cputovideo_next(s);
2416 }
2417 }
2418}
2419
b1950430
AK		 2420static const MemoryRegionOps cirrus_linear_bitblt_io_ops = {
2421 .read = cirrus_linear_bitblt_read,
2422 .write = cirrus_linear_bitblt_write,
2423 .endianness = DEVICE_LITTLE_ENDIAN,
4e56f089
AK		 2424 .impl = {
2425 .min_access_size = 1,
2426 .max_access_size = 1,
2427 },
a5082316
FB		 2428};
2429
b1950430
AK		 2430static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank)
2431{
7969d9ed
AK		 2432 MemoryRegion *mr = &s->cirrus_bank[bank];
2433 bool enabled = !(s->cirrus_srcptr != s->cirrus_srcptr_end)
4e12cd94
AK		 2434 && !((s->vga.sr[0x07] & 0x01) == 0)
2435 && !((s->vga.gr[0x0B] & 0x14) == 0x14)
7969d9ed
AK		 2436 && !(s->vga.gr[0x0B] & 0x02);
2437
2438 memory_region_set_enabled(mr, enabled);
2439 memory_region_set_alias_offset(mr, s->cirrus_bank_base[bank]);
b1950430 2440}
2bec46dc 2441
b1950430
AK		 2442static void map_linear_vram(CirrusVGAState *s)
2443{
4c08fd1e 2444 if (s->bustype == CIRRUS_BUSTYPE_PCI && !s->linear_vram) {
b1950430
AK		 2445 s->linear_vram = true;
2446 memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1);
2447 }
2448 map_linear_vram_bank(s, 0);
2449 map_linear_vram_bank(s, 1);
2bec46dc
AL		 2450}
2451
2452static void unmap_linear_vram(CirrusVGAState *s)
2453{
4c08fd1e 2454 if (s->bustype == CIRRUS_BUSTYPE_PCI && s->linear_vram) {
b1950430
AK		 2455 s->linear_vram = false;
2456 memory_region_del_subregion(&s->pci_bar, &s->vga.vram);
4516e45f 2457 }
7969d9ed
AK		 2458 memory_region_set_enabled(&s->cirrus_bank[0], false);
2459 memory_region_set_enabled(&s->cirrus_bank[1], false);
2bec46dc
AL		 2460}
2461
8926b517
FB		 2462/* Compute the memory access functions */
2463static void cirrus_update_memory_access(CirrusVGAState *s)
2464{
2465 unsigned mode;
2466
64c048f4 2467 memory_region_transaction_begin();
4e12cd94 2468 if ((s->vga.sr[0x17] & 0x44) == 0x44) {
8926b517
FB		 2469 goto generic_io;
2470 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2471 goto generic_io;
2472 } else {
4e12cd94 2473 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
8926b517 2474 goto generic_io;
4e12cd94 2475 } else if (s->vga.gr[0x0B] & 0x02) {
8926b517
FB		 2476 goto generic_io;
2477 }
3b46e624 2478
4e12cd94
AK		 2479 mode = s->vga.gr[0x05] & 0x7;
2480 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2bec46dc 2481 map_linear_vram(s);
8926b517
FB		 2482 } else {
2483 generic_io:
2bec46dc 2484 unmap_linear_vram(s);
8926b517
FB		 2485 }
2486 }
64c048f4 2487 memory_region_transaction_commit();
8926b517
FB		 2488}
2489
2490
e6e5ad80
FB		 2491/* I/O ports */
2492
c75e6d8e
JG		 2493static uint64_t cirrus_vga_ioport_read(void *opaque, hwaddr addr,
2494 unsigned size)
e6e5ad80 2495{
b6343073
JQ		 2496 CirrusVGAState *c = opaque;
2497 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2498 int val, index;
2499
c75e6d8e 2500 addr += 0x3b0;
bd8f2f5d 2501
b6343073 2502 if (vga_ioport_invalid(s, addr)) {
e6e5ad80
FB		 2503 val = 0xff;
2504 } else {
2505 switch (addr) {
2506 case 0x3c0:
b6343073
JQ		 2507 if (s->ar_flip_flop == 0) {
2508 val = s->ar_index;
e6e5ad80
FB		 2509 } else {
2510 val = 0;
2511 }
2512 break;
2513 case 0x3c1:
b6343073 2514 index = s->ar_index & 0x1f;
e6e5ad80 2515 if (index < 21)
b6343073 2516 val = s->ar[index];
e6e5ad80
FB		 2517 else
2518 val = 0;
2519 break;
2520 case 0x3c2:
b6343073 2521 val = s->st00;
e6e5ad80
FB		 2522 break;
2523 case 0x3c4:
b6343073 2524 val = s->sr_index;
e6e5ad80
FB		 2525 break;
2526 case 0x3c5:
8a82c322
JQ		 2527 val = cirrus_vga_read_sr(c);
2528 break;
e6e5ad80 2529#ifdef DEBUG_VGA_REG
b6343073 2530 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
e6e5ad80
FB		 2531#endif
2532 break;
2533 case 0x3c6:
957c9db5 2534 val = cirrus_read_hidden_dac(c);
e6e5ad80
FB		 2535 break;
2536 case 0x3c7:
b6343073 2537 val = s->dac_state;
e6e5ad80 2538 break;
ae184e4a 2539 case 0x3c8:
b6343073
JQ		 2540 val = s->dac_write_index;
2541 c->cirrus_hidden_dac_lockindex = 0;
ae184e4a
FB		 2542 break;
2543 case 0x3c9:
5deaeee3
JQ		 2544 val = cirrus_vga_read_palette(c);
2545 break;
e6e5ad80 2546 case 0x3ca:
b6343073 2547 val = s->fcr;
e6e5ad80
FB		 2548 break;
2549 case 0x3cc:
b6343073 2550 val = s->msr;
e6e5ad80
FB		 2551 break;
2552 case 0x3ce:
b6343073 2553 val = s->gr_index;
e6e5ad80
FB		 2554 break;
2555 case 0x3cf:
f705db9d 2556 val = cirrus_vga_read_gr(c, s->gr_index);
e6e5ad80 2557#ifdef DEBUG_VGA_REG
b6343073 2558 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
e6e5ad80
FB		 2559#endif
2560 break;
2561 case 0x3b4:
2562 case 0x3d4:
b6343073 2563 val = s->cr_index;
e6e5ad80
FB		 2564 break;
2565 case 0x3b5:
2566 case 0x3d5:
b863d514 2567 val = cirrus_vga_read_cr(c, s->cr_index);
e6e5ad80 2568#ifdef DEBUG_VGA_REG
b6343073 2569 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80
FB		 2570#endif
2571 break;
2572 case 0x3ba:
2573 case 0x3da:
2574 /* just toggle to fool polling */
b6343073
JQ		 2575 val = s->st01 = s->retrace(s);
2576 s->ar_flip_flop = 0;
e6e5ad80
FB		 2577 break;
2578 default:
2579 val = 0x00;
2580 break;
2581 }
2582 }
ec87f206 2583 trace_vga_cirrus_read_io(addr, val);
e6e5ad80
FB		 2584 return val;
2585}
2586
c75e6d8e
JG		 2587static void cirrus_vga_ioport_write(void *opaque, hwaddr addr, uint64_t val,
2588 unsigned size)
e6e5ad80 2589{
b6343073
JQ		 2590 CirrusVGAState *c = opaque;
2591 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2592 int index;
2593
c75e6d8e 2594 addr += 0x3b0;
bd8f2f5d 2595
e6e5ad80 2596 /* check port range access depending on color/monochrome mode */
b6343073 2597 if (vga_ioport_invalid(s, addr)) {
e6e5ad80 2598 return;
25a18cbd 2599 }
ec87f206 2600 trace_vga_cirrus_write_io(addr, val);
e6e5ad80
FB		 2601
2602 switch (addr) {
2603 case 0x3c0:
b6343073 2604 if (s->ar_flip_flop == 0) {
e6e5ad80 2605 val &= 0x3f;
b6343073 2606 s->ar_index = val;
e6e5ad80 2607 } else {
b6343073 2608 index = s->ar_index & 0x1f;
e6e5ad80
FB		 2609 switch (index) {
2610 case 0x00 ... 0x0f:
b6343073 2611 s->ar[index] = val & 0x3f;
e6e5ad80
FB		 2612 break;
2613 case 0x10:
b6343073 2614 s->ar[index] = val & ~0x10;
e6e5ad80
FB		 2615 break;
2616 case 0x11:
b6343073 2617 s->ar[index] = val;
e6e5ad80
FB		 2618 break;
2619 case 0x12:
b6343073 2620 s->ar[index] = val & ~0xc0;
e6e5ad80
FB		 2621 break;
2622 case 0x13:
b6343073 2623 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2624 break;
2625 case 0x14:
b6343073 2626 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2627 break;
2628 default:
2629 break;
2630 }
2631 }
b6343073 2632 s->ar_flip_flop ^= 1;
e6e5ad80
FB		 2633 break;
2634 case 0x3c2:
b6343073
JQ		 2635 s->msr = val & ~0x10;
2636 s->update_retrace_info(s);
e6e5ad80
FB		 2637 break;
2638 case 0x3c4:
b6343073 2639 s->sr_index = val;
e6e5ad80
FB		 2640 break;
2641 case 0x3c5:
e6e5ad80 2642#ifdef DEBUG_VGA_REG
e8ee4b68 2643 printf("vga: write SR%x = 0x%02" PRIu64 "\n", s->sr_index, val);
e6e5ad80 2644#endif
31c63201
JQ		 2645 cirrus_vga_write_sr(c, val);
2646 break;
e6e5ad80 2647 case 0x3c6:
b6343073 2648 cirrus_write_hidden_dac(c, val);
e6e5ad80
FB		 2649 break;
2650 case 0x3c7:
b6343073
JQ		 2651 s->dac_read_index = val;
2652 s->dac_sub_index = 0;
2653 s->dac_state = 3;
e6e5ad80
FB		 2654 break;
2655 case 0x3c8:
b6343073
JQ		 2656 s->dac_write_index = val;
2657 s->dac_sub_index = 0;
2658 s->dac_state = 0;
e6e5ad80
FB		 2659 break;
2660 case 0x3c9:
86948bb1
JQ		 2661 cirrus_vga_write_palette(c, val);
2662 break;
e6e5ad80 2663 case 0x3ce:
b6343073 2664 s->gr_index = val;
e6e5ad80
FB		 2665 break;
2666 case 0x3cf:
e6e5ad80 2667#ifdef DEBUG_VGA_REG
e8ee4b68 2668 printf("vga: write GR%x = 0x%02" PRIu64 "\n", s->gr_index, val);
e6e5ad80 2669#endif
22286bc6 2670 cirrus_vga_write_gr(c, s->gr_index, val);
e6e5ad80
FB		 2671 break;
2672 case 0x3b4:
2673 case 0x3d4:
b6343073 2674 s->cr_index = val;
e6e5ad80
FB		 2675 break;
2676 case 0x3b5:
2677 case 0x3d5:
e6e5ad80 2678#ifdef DEBUG_VGA_REG
e8ee4b68 2679 printf("vga: write CR%x = 0x%02"PRIu64"\n", s->cr_index, val);
e6e5ad80 2680#endif
4ec1ce04 2681 cirrus_vga_write_cr(c, val);
e6e5ad80
FB		 2682 break;
2683 case 0x3ba:
2684 case 0x3da:
b6343073 2685 s->fcr = val & 0x10;
e6e5ad80
FB		 2686 break;
2687 }
2688}
2689
e36f36e1
FB		 2690/***************************************
2691 *
2692 * memory-mapped I/O access
2693 *
2694 ***************************************/
2695
a8170e5e 2696static uint64_t cirrus_mmio_read(void *opaque, hwaddr addr,
1e04d4d6 2697 unsigned size)
e36f36e1 2698{
e05587e8 2699 CirrusVGAState *s = opaque;
e36f36e1 2700
e36f36e1
FB		 2701 if (addr >= 0x100) {
2702 return cirrus_mmio_blt_read(s, addr - 0x100);
2703 } else {
c75e6d8e 2704 return cirrus_vga_ioport_read(s, addr + 0x10, size);
e36f36e1
FB		 2705 }
2706}
2707
a8170e5e 2708static void cirrus_mmio_write(void *opaque, hwaddr addr,
1e04d4d6 2709 uint64_t val, unsigned size)
e36f36e1 2710{
e05587e8 2711 CirrusVGAState *s = opaque;
e36f36e1 2712
e36f36e1
FB		 2713 if (addr >= 0x100) {
2714 cirrus_mmio_blt_write(s, addr - 0x100, val);
2715 } else {
c75e6d8e 2716 cirrus_vga_ioport_write(s, addr + 0x10, val, size);
e36f36e1
FB		 2717 }
2718}
2719
b1950430
AK		 2720static const MemoryRegionOps cirrus_mmio_io_ops = {
2721 .read = cirrus_mmio_read,
2722 .write = cirrus_mmio_write,
2723 .endianness = DEVICE_LITTLE_ENDIAN,
1e04d4d6
AK		 2724 .impl = {
2725 .min_access_size = 1,
2726 .max_access_size = 1,
2727 },
e36f36e1
FB		 2728};
2729
2c6ab832
FB		 2730/* load/save state */
2731
e59fb374 2732static int cirrus_post_load(void *opaque, int version_id)
2c6ab832
FB		 2733{
2734 CirrusVGAState *s = opaque;
2735
4e12cd94
AK		 2736 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
2737 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
2c6ab832 2738
b7ee9e49
WX		 2739 cirrus_update_bank_ptr(s, 0);
2740 cirrus_update_bank_ptr(s, 1);
2bec46dc 2741 cirrus_update_memory_access(s);
2c6ab832 2742 /* force refresh */
4e12cd94 2743 s->vga.graphic_mode = -1;
b7ee9e49 2744
2c6ab832
FB		 2745 return 0;
2746}
2747
ce3cf70e 2748const VMStateDescription vmstate_cirrus_vga = {
7e72abc3
JQ		 2749 .name = "cirrus_vga",
2750 .version_id = 2,
2751 .minimum_version_id = 1,
7e72abc3 2752 .post_load = cirrus_post_load,
d49805ae 2753 .fields = (VMStateField[]) {
7e72abc3
JQ		 2754 VMSTATE_UINT32(vga.latch, CirrusVGAState),
2755 VMSTATE_UINT8(vga.sr_index, CirrusVGAState),
2756 VMSTATE_BUFFER(vga.sr, CirrusVGAState),
2757 VMSTATE_UINT8(vga.gr_index, CirrusVGAState),
2758 VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState),
2759 VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState),
2760 VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
2761 VMSTATE_UINT8(vga.ar_index, CirrusVGAState),
2762 VMSTATE_BUFFER(vga.ar, CirrusVGAState),
2763 VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState),
2764 VMSTATE_UINT8(vga.cr_index, CirrusVGAState),
2765 VMSTATE_BUFFER(vga.cr, CirrusVGAState),
2766 VMSTATE_UINT8(vga.msr, CirrusVGAState),
2767 VMSTATE_UINT8(vga.fcr, CirrusVGAState),
2768 VMSTATE_UINT8(vga.st00, CirrusVGAState),
2769 VMSTATE_UINT8(vga.st01, CirrusVGAState),
2770 VMSTATE_UINT8(vga.dac_state, CirrusVGAState),
2771 VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState),
2772 VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState),
2773 VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState),
2774 VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState),
2775 VMSTATE_BUFFER(vga.palette, CirrusVGAState),
2776 VMSTATE_INT32(vga.bank_offset, CirrusVGAState),
2777 VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState),
2778 VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState),
22382bb9
GH		 2779 VMSTATE_UINT32(vga.hw_cursor_x, CirrusVGAState),
2780 VMSTATE_UINT32(vga.hw_cursor_y, CirrusVGAState),
7e72abc3
JQ		 2781 /* XXX: we do not save the bitblt state - we assume we do not save
2782 the state when the blitter is active */
2783 VMSTATE_END_OF_LIST()
4f335feb 2784 }
7e72abc3 2785};
4f335feb 2786
7e72abc3
JQ		 2787static const VMStateDescription vmstate_pci_cirrus_vga = {
2788 .name = "cirrus_vga",
2789 .version_id = 2,
2790 .minimum_version_id = 2,
d49805ae 2791 .fields = (VMStateField[]) {
7e72abc3
JQ		 2792 VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState),
2793 VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
2794 vmstate_cirrus_vga, CirrusVGAState),
2795 VMSTATE_END_OF_LIST()
2796 }
2797};
4f335feb 2798
e6e5ad80
FB		 2799/***************************************
2800 *
2801 * initialize
2802 *
2803 ***************************************/
2804
4abc796d 2805static void cirrus_reset(void *opaque)
e6e5ad80 2806{
4abc796d 2807 CirrusVGAState *s = opaque;
e6e5ad80 2808
03a3e7ba 2809 vga_common_reset(&s->vga);
ee50c6bc 2810 unmap_linear_vram(s);
4e12cd94 2811 s->vga.sr[0x06] = 0x0f;
4abc796d 2812 if (s->device_id == CIRRUS_ID_CLGD5446) {
78e127ef 2813 /* 4MB 64 bit memory config, always PCI */
4e12cd94
AK		 2814 s->vga.sr[0x1F] = 0x2d; // MemClock
2815 s->vga.gr[0x18] = 0x0f; // fastest memory configuration
2816 s->vga.sr[0x0f] = 0x98;
2817 s->vga.sr[0x17] = 0x20;
2818 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
78e127ef 2819 } else {
4e12cd94
AK		 2820 s->vga.sr[0x1F] = 0x22; // MemClock
2821 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
2822 s->vga.sr[0x17] = s->bustype;
2823 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
78e127ef 2824 }
4e12cd94 2825 s->vga.cr[0x27] = s->device_id;
e6e5ad80
FB		 2826
2827 s->cirrus_hidden_dac_lockindex = 5;
2828 s->cirrus_hidden_dac_data = 0;
4abc796d
BS		 2829}
2830
b1950430
AK		 2831static const MemoryRegionOps cirrus_linear_io_ops = {
2832 .read = cirrus_linear_read,
2833 .write = cirrus_linear_write,
2834 .endianness = DEVICE_LITTLE_ENDIAN,
899adf81
AK		 2835 .impl = {
2836 .min_access_size = 1,
2837 .max_access_size = 1,
2838 },
b1950430
AK		 2839};
2840
c75e6d8e
JG		 2841static const MemoryRegionOps cirrus_vga_io_ops = {
2842 .read = cirrus_vga_ioport_read,
2843 .write = cirrus_vga_ioport_write,
2844 .endianness = DEVICE_LITTLE_ENDIAN,
2845 .impl = {
2846 .min_access_size = 1,
2847 .max_access_size = 1,
2848 },
2849};
2850
ce3cf70e
TH		 2851void cirrus_init_common(CirrusVGAState *s, Object *owner,
2852 int device_id, int is_pci,
2853 MemoryRegion *system_memory, MemoryRegion *system_io)
4abc796d
BS		 2854{
2855 int i;
2856 static int inited;
2857
2858 if (!inited) {
2859 inited = 1;
2860 for(i = 0;i < 256; i++)
2861 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
2862 rop_to_index[CIRRUS_ROP_0] = 0;
2863 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
2864 rop_to_index[CIRRUS_ROP_NOP] = 2;
2865 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
2866 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
2867 rop_to_index[CIRRUS_ROP_SRC] = 5;
2868 rop_to_index[CIRRUS_ROP_1] = 6;
2869 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
2870 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
2871 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
2872 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
2873 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
2874 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
2875 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
2876 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
2877 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
2878 s->device_id = device_id;
2879 if (is_pci)
2880 s->bustype = CIRRUS_BUSTYPE_PCI;
2881 else
2882 s->bustype = CIRRUS_BUSTYPE_ISA;
2883 }
2884
c75e6d8e 2885 /* Register ioport 0x3b0 - 0x3df */
9eb58a47 2886 memory_region_init_io(&s->cirrus_vga_io, owner, &cirrus_vga_io_ops, s,
c75e6d8e 2887 "cirrus-io", 0x30);
eb25a1d9 2888 memory_region_set_flush_coalesced(&s->cirrus_vga_io);
c75e6d8e 2889 memory_region_add_subregion(system_io, 0x3b0, &s->cirrus_vga_io);
4abc796d 2890
9eb58a47 2891 memory_region_init(&s->low_mem_container, owner,
b1950430
AK		 2892 "cirrus-lowmem-container",
2893 0x20000);
2894
9eb58a47 2895 memory_region_init_io(&s->low_mem, owner, &cirrus_vga_mem_ops, s,
b1950430
AK		 2896 "cirrus-low-memory", 0x20000);
2897 memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
7969d9ed
AK		 2898 for (i = 0; i < 2; ++i) {
2899 static const char *names[] = { "vga.bank0", "vga.bank1" };
2900 MemoryRegion *bank = &s->cirrus_bank[i];
9eb58a47
PB		 2901 memory_region_init_alias(bank, owner, names[i], &s->vga.vram,
2902 0, 0x8000);
7969d9ed
AK		 2903 memory_region_set_enabled(bank, false);
2904 memory_region_add_subregion_overlap(&s->low_mem_container, i * 0x8000,
2905 bank, 1);
2906 }
be20f9e9 2907 memory_region_add_subregion_overlap(system_memory,
b19c1c08 2908 0x000a0000,
b1950430
AK		 2909 &s->low_mem_container,
2910 1);
2911 memory_region_set_coalescing(&s->low_mem);
2c6ab832 2912
fefe54e3 2913 /* I/O handler for LFB */
9eb58a47 2914 memory_region_init_io(&s->cirrus_linear_io, owner, &cirrus_linear_io_ops, s,
f0353b0d 2915 "cirrus-linear-io", s->vga.vram_size_mb * MiB);
bd8f2f5d 2916 memory_region_set_flush_coalesced(&s->cirrus_linear_io);
fefe54e3
AL		 2917
2918 /* I/O handler for LFB */
9eb58a47 2919 memory_region_init_io(&s->cirrus_linear_bitblt_io, owner,
b1950430
AK		 2920 &cirrus_linear_bitblt_io_ops,
2921 s,
2922 "cirrus-bitblt-mmio",
2923 0x400000);
bd8f2f5d 2924 memory_region_set_flush_coalesced(&s->cirrus_linear_bitblt_io);
fefe54e3
AL		 2925
2926 /* I/O handler for memory-mapped I/O */
9eb58a47 2927 memory_region_init_io(&s->cirrus_mmio_io, owner, &cirrus_mmio_io_ops, s,
b1950430 2928 "cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
bd8f2f5d 2929 memory_region_set_flush_coalesced(&s->cirrus_mmio_io);
fefe54e3
AL		 2930
2931 s->real_vram_size =
f0353b0d 2932 (s->device_id == CIRRUS_ID_CLGD5446) ? 4 * MiB : 2 * MiB;
fefe54e3 2933
4e12cd94 2934 /* XXX: s->vga.vram_size must be a power of two */
fefe54e3
AL		 2935 s->cirrus_addr_mask = s->real_vram_size - 1;
2936 s->linear_mmio_mask = s->real_vram_size - 256;
2937
4e12cd94
AK		 2938 s->vga.get_bpp = cirrus_get_bpp;
2939 s->vga.get_offsets = cirrus_get_offsets;
2940 s->vga.get_resolution = cirrus_get_resolution;
2941 s->vga.cursor_invalidate = cirrus_cursor_invalidate;
2942 s->vga.cursor_draw_line = cirrus_cursor_draw_line;
fefe54e3 2943
a08d4367 2944 qemu_register_reset(cirrus_reset, s);
e6e5ad80
FB		 2945}
2946
e6e5ad80
FB		 2947/***************************************
2948 *
2949 * PCI bus support
2950 *
2951 ***************************************/
2952
f409edf7 2953static void pci_cirrus_vga_realize(PCIDevice *dev, Error **errp)
a414c306 2954{
d338bae3 2955 PCICirrusVGAState *d = PCI_CIRRUS_VGA(dev);
a414c306 2956 CirrusVGAState *s = &d->cirrus_vga;
40021f08
AL		 2957 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2958 int16_t device_id = pc->device_id;
a414c306 2959
f61d82c2
GA		 2960 /* follow real hardware, cirrus card emulated has 4 MB video memory.
2961 Also accept 8 MB/16 MB for backward compatibility. */
2962 if (s->vga.vram_size_mb != 4 && s->vga.vram_size_mb != 8 &&
2963 s->vga.vram_size_mb != 16) {
f409edf7
MA		 2964 error_setg(errp, "Invalid cirrus_vga ram size '%u'",
2965 s->vga.vram_size_mb);
2966 return;
f61d82c2 2967 }
a414c306 2968 /* setup VGA */
1fcfdc43 2969 vga_common_init(&s->vga, OBJECT(dev));
9eb58a47 2970 cirrus_init_common(s, OBJECT(dev), device_id, 1, pci_address_space(dev),
c75e6d8e 2971 pci_address_space_io(dev));
5643706a 2972 s->vga.con = graphic_console_init(DEVICE(dev), 0, s->vga.hw_ops, &s->vga);
a414c306
GH		 2973
2974 /* setup PCI */
a414c306 2975
3eadad55 2976 memory_region_init(&s->pci_bar, OBJECT(dev), "cirrus-pci-bar0", 0x2000000);
b1950430
AK		 2977
2978 /* XXX: add byte swapping apertures */
2979 memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io);
2980 memory_region_add_subregion(&s->pci_bar, 0x1000000,
2981 &s->cirrus_linear_bitblt_io);
2982
a414c306
GH		 2983 /* setup memory space */
2984 /* memory #0 LFB */
2985 /* memory #1 memory-mapped I/O */
2986 /* XXX: s->vga.vram_size must be a power of two */
e824b2cc 2987 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar);
a414c306 2988 if (device_id == CIRRUS_ID_CLGD5446) {
e824b2cc 2989 pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io);
a414c306 2990 }
a414c306
GH		 2991}
2992
19403a68
MT		 2993static Property pci_vga_cirrus_properties[] = {
2994 DEFINE_PROP_UINT32("vgamem_mb", struct PCICirrusVGAState,
73c14813 2995 cirrus_vga.vga.vram_size_mb, 4),
827bd517
GH		 2996 DEFINE_PROP_BOOL("blitter", struct PCICirrusVGAState,
2997 cirrus_vga.enable_blitter, true),
1fcfdc43
GH		 2998 DEFINE_PROP_BOOL("global-vmstate", struct PCICirrusVGAState,
2999 cirrus_vga.vga.global_vmstate, false),
19403a68
MT		 3000 DEFINE_PROP_END_OF_LIST(),
3001};
3002
40021f08
AL		 3003static void cirrus_vga_class_init(ObjectClass *klass, void *data)
3004{
39bffca2 3005 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 3006 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3007
f409edf7 3008 k->realize = pci_cirrus_vga_realize;
40021f08
AL		 3009 k->romfile = VGABIOS_CIRRUS_FILENAME;
3010 k->vendor_id = PCI_VENDOR_ID_CIRRUS;
3011 k->device_id = CIRRUS_ID_CLGD5446;
3012 k->class_id = PCI_CLASS_DISPLAY_VGA;
125ee0ed 3013 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
39bffca2
AL		 3014 dc->desc = "Cirrus CLGD 54xx VGA";
3015 dc->vmsd = &vmstate_pci_cirrus_vga;
4f67d30b 3016 device_class_set_props(dc, pci_vga_cirrus_properties);
2897ae02 3017 dc->hotpluggable = false;
40021f08
AL		 3018}
3019
8c43a6f0 3020static const TypeInfo cirrus_vga_info = {
d338bae3 3021 .name = TYPE_PCI_CIRRUS_VGA,
39bffca2
AL		 3022 .parent = TYPE_PCI_DEVICE,
3023 .instance_size = sizeof(PCICirrusVGAState),
3024 .class_init = cirrus_vga_class_init,
fd3b02c8
EH		 3025 .interfaces = (InterfaceInfo[]) {
3026 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
3027 { },
3028 },
a414c306 3029};
e6e5ad80 3030
83f7d43a 3031static void cirrus_vga_register_types(void)
a414c306 3032{
39bffca2 3033 type_register_static(&cirrus_vga_info);
e6e5ad80 3034}
83f7d43a
AF		 3035
3036type_init(cirrus_vga_register_types)
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