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a5082316 FB |
1 | /* |
2 | * QEMU Cirrus CLGD 54xx VGA Emulator. | |
5fafdf24 | 3 | * |
a5082316 | 4 | * Copyright (c) 2004 Fabrice Bellard |
5fafdf24 | 5 | * |
a5082316 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
026aeffc GH |
25 | static inline void glue(rop_8_, ROP_NAME)(CirrusVGAState *s, |
26 | uint32_t dstaddr, uint8_t src) | |
8c78881f | 27 | { |
026aeffc | 28 | uint8_t *dst = &s->vga.vram_ptr[dstaddr & s->cirrus_addr_mask]; |
8c78881f BS |
29 | *dst = ROP_FN(*dst, src); |
30 | } | |
31 | ||
026aeffc GH |
32 | static inline void glue(rop_tr_8_, ROP_NAME)(CirrusVGAState *s, |
33 | uint32_t dstaddr, uint8_t src, | |
34 | uint8_t transp) | |
8c78881f | 35 | { |
026aeffc GH |
36 | uint8_t *dst = &s->vga.vram_ptr[dstaddr & s->cirrus_addr_mask]; |
37 | uint8_t pixel = ROP_FN(*dst, src); | |
38 | if (pixel != transp) { | |
39 | *dst = pixel; | |
40 | } | |
41 | } | |
42 | ||
43 | static inline void glue(rop_16_, ROP_NAME)(CirrusVGAState *s, | |
44 | uint32_t dstaddr, uint16_t src) | |
45 | { | |
46 | uint16_t *dst = (uint16_t *) | |
47 | (&s->vga.vram_ptr[dstaddr & s->cirrus_addr_mask & ~1]); | |
8c78881f BS |
48 | *dst = ROP_FN(*dst, src); |
49 | } | |
50 | ||
026aeffc GH |
51 | static inline void glue(rop_tr_16_, ROP_NAME)(CirrusVGAState *s, |
52 | uint32_t dstaddr, uint16_t src, | |
53 | uint16_t transp) | |
54 | { | |
55 | uint16_t *dst = (uint16_t *) | |
56 | (&s->vga.vram_ptr[dstaddr & s->cirrus_addr_mask & ~1]); | |
57 | uint16_t pixel = ROP_FN(*dst, src); | |
58 | if (pixel != transp) { | |
59 | *dst = pixel; | |
60 | } | |
61 | } | |
62 | ||
63 | static inline void glue(rop_32_, ROP_NAME)(CirrusVGAState *s, | |
64 | uint32_t dstaddr, uint32_t src) | |
8c78881f | 65 | { |
026aeffc GH |
66 | uint32_t *dst = (uint32_t *) |
67 | (&s->vga.vram_ptr[dstaddr & s->cirrus_addr_mask & ~3]); | |
8c78881f BS |
68 | *dst = ROP_FN(*dst, src); |
69 | } | |
70 | ||
026aeffc GH |
71 | #define ROP_OP(st, d, s) glue(rop_8_, ROP_NAME)(st, d, s) |
72 | #define ROP_OP_TR(st, d, s, t) glue(rop_tr_8_, ROP_NAME)(st, d, s, t) | |
73 | #define ROP_OP_16(st, d, s) glue(rop_16_, ROP_NAME)(st, d, s) | |
74 | #define ROP_OP_TR_16(st, d, s, t) glue(rop_tr_16_, ROP_NAME)(st, d, s, t) | |
75 | #define ROP_OP_32(st, d, s) glue(rop_32_, ROP_NAME)(st, d, s) | |
8c78881f BS |
76 | #undef ROP_FN |
77 | ||
a5082316 FB |
78 | static void |
79 | glue(cirrus_bitblt_rop_fwd_, ROP_NAME)(CirrusVGAState *s, | |
026aeffc | 80 | uint32_t dstaddr, |
ffaf8577 | 81 | uint32_t srcaddr, |
026aeffc GH |
82 | int dstpitch, int srcpitch, |
83 | int bltwidth, int bltheight) | |
a5082316 FB |
84 | { |
85 | int x,y; | |
86 | dstpitch -= bltwidth; | |
87 | srcpitch -= bltwidth; | |
b2eb849d | 88 | |
d16136d2 | 89 | if (bltheight > 1 && (dstpitch < 0 || srcpitch < 0)) { |
b2eb849d AJ |
90 | return; |
91 | } | |
92 | ||
a5082316 FB |
93 | for (y = 0; y < bltheight; y++) { |
94 | for (x = 0; x < bltwidth; x++) { | |
ffaf8577 | 95 | ROP_OP(s, dstaddr, cirrus_src(s, srcaddr)); |
026aeffc | 96 | dstaddr++; |
ffaf8577 | 97 | srcaddr++; |
a5082316 | 98 | } |
026aeffc | 99 | dstaddr += dstpitch; |
ffaf8577 | 100 | srcaddr += srcpitch; |
a5082316 FB |
101 | } |
102 | } | |
103 | ||
104 | static void | |
105 | glue(cirrus_bitblt_rop_bkwd_, ROP_NAME)(CirrusVGAState *s, | |
026aeffc | 106 | uint32_t dstaddr, |
ffaf8577 | 107 | uint32_t srcaddr, |
026aeffc GH |
108 | int dstpitch, int srcpitch, |
109 | int bltwidth, int bltheight) | |
a5082316 FB |
110 | { |
111 | int x,y; | |
112 | dstpitch += bltwidth; | |
113 | srcpitch += bltwidth; | |
114 | for (y = 0; y < bltheight; y++) { | |
115 | for (x = 0; x < bltwidth; x++) { | |
ffaf8577 | 116 | ROP_OP(s, dstaddr, cirrus_src(s, srcaddr)); |
026aeffc | 117 | dstaddr--; |
ffaf8577 | 118 | srcaddr--; |
a5082316 | 119 | } |
026aeffc | 120 | dstaddr += dstpitch; |
ffaf8577 | 121 | srcaddr += srcpitch; |
a5082316 FB |
122 | } |
123 | } | |
124 | ||
96cf2df8 TS |
125 | static void |
126 | glue(glue(cirrus_bitblt_rop_fwd_transp_, ROP_NAME),_8)(CirrusVGAState *s, | |
026aeffc | 127 | uint32_t dstaddr, |
ffaf8577 | 128 | uint32_t srcaddr, |
026aeffc GH |
129 | int dstpitch, |
130 | int srcpitch, | |
131 | int bltwidth, | |
132 | int bltheight) | |
96cf2df8 TS |
133 | { |
134 | int x,y; | |
026aeffc | 135 | uint8_t transp = s->vga.gr[0x34]; |
96cf2df8 TS |
136 | dstpitch -= bltwidth; |
137 | srcpitch -= bltwidth; | |
215902d7 | 138 | |
139 | if (bltheight > 1 && (dstpitch < 0 || srcpitch < 0)) { | |
140 | return; | |
141 | } | |
142 | ||
96cf2df8 TS |
143 | for (y = 0; y < bltheight; y++) { |
144 | for (x = 0; x < bltwidth; x++) { | |
ffaf8577 | 145 | ROP_OP_TR(s, dstaddr, cirrus_src(s, srcaddr), transp); |
026aeffc | 146 | dstaddr++; |
ffaf8577 | 147 | srcaddr++; |
96cf2df8 | 148 | } |
026aeffc | 149 | dstaddr += dstpitch; |
ffaf8577 | 150 | srcaddr += srcpitch; |
96cf2df8 TS |
151 | } |
152 | } | |
153 | ||
154 | static void | |
155 | glue(glue(cirrus_bitblt_rop_bkwd_transp_, ROP_NAME),_8)(CirrusVGAState *s, | |
026aeffc | 156 | uint32_t dstaddr, |
ffaf8577 | 157 | uint32_t srcaddr, |
026aeffc GH |
158 | int dstpitch, |
159 | int srcpitch, | |
160 | int bltwidth, | |
161 | int bltheight) | |
96cf2df8 TS |
162 | { |
163 | int x,y; | |
026aeffc | 164 | uint8_t transp = s->vga.gr[0x34]; |
96cf2df8 TS |
165 | dstpitch += bltwidth; |
166 | srcpitch += bltwidth; | |
167 | for (y = 0; y < bltheight; y++) { | |
168 | for (x = 0; x < bltwidth; x++) { | |
ffaf8577 | 169 | ROP_OP_TR(s, dstaddr, cirrus_src(s, srcaddr), transp); |
026aeffc | 170 | dstaddr--; |
ffaf8577 | 171 | srcaddr--; |
96cf2df8 | 172 | } |
026aeffc | 173 | dstaddr += dstpitch; |
ffaf8577 | 174 | srcaddr += srcpitch; |
96cf2df8 TS |
175 | } |
176 | } | |
177 | ||
178 | static void | |
179 | glue(glue(cirrus_bitblt_rop_fwd_transp_, ROP_NAME),_16)(CirrusVGAState *s, | |
026aeffc | 180 | uint32_t dstaddr, |
ffaf8577 | 181 | uint32_t srcaddr, |
026aeffc GH |
182 | int dstpitch, |
183 | int srcpitch, | |
184 | int bltwidth, | |
185 | int bltheight) | |
96cf2df8 TS |
186 | { |
187 | int x,y; | |
026aeffc | 188 | uint16_t transp = s->vga.gr[0x34] | (uint16_t)s->vga.gr[0x35] << 8; |
96cf2df8 TS |
189 | dstpitch -= bltwidth; |
190 | srcpitch -= bltwidth; | |
215902d7 | 191 | |
192 | if (bltheight > 1 && (dstpitch < 0 || srcpitch < 0)) { | |
193 | return; | |
194 | } | |
195 | ||
96cf2df8 TS |
196 | for (y = 0; y < bltheight; y++) { |
197 | for (x = 0; x < bltwidth; x+=2) { | |
ffaf8577 | 198 | ROP_OP_TR_16(s, dstaddr, cirrus_src16(s, srcaddr), transp); |
026aeffc | 199 | dstaddr += 2; |
ffaf8577 | 200 | srcaddr += 2; |
96cf2df8 | 201 | } |
026aeffc | 202 | dstaddr += dstpitch; |
ffaf8577 | 203 | srcaddr += srcpitch; |
96cf2df8 TS |
204 | } |
205 | } | |
206 | ||
207 | static void | |
208 | glue(glue(cirrus_bitblt_rop_bkwd_transp_, ROP_NAME),_16)(CirrusVGAState *s, | |
026aeffc | 209 | uint32_t dstaddr, |
ffaf8577 | 210 | uint32_t srcaddr, |
026aeffc GH |
211 | int dstpitch, |
212 | int srcpitch, | |
213 | int bltwidth, | |
214 | int bltheight) | |
96cf2df8 TS |
215 | { |
216 | int x,y; | |
026aeffc | 217 | uint16_t transp = s->vga.gr[0x34] | (uint16_t)s->vga.gr[0x35] << 8; |
96cf2df8 TS |
218 | dstpitch += bltwidth; |
219 | srcpitch += bltwidth; | |
220 | for (y = 0; y < bltheight; y++) { | |
221 | for (x = 0; x < bltwidth; x+=2) { | |
f019722c | 222 | ROP_OP_TR_16(s, dstaddr - 1, cirrus_src16(s, srcaddr - 1), transp); |
026aeffc | 223 | dstaddr -= 2; |
ffaf8577 | 224 | srcaddr -= 2; |
96cf2df8 | 225 | } |
026aeffc | 226 | dstaddr += dstpitch; |
ffaf8577 | 227 | srcaddr += srcpitch; |
96cf2df8 TS |
228 | } |
229 | } | |
230 | ||
a5082316 | 231 | #define DEPTH 8 |
47b43a1f | 232 | #include "cirrus_vga_rop2.h" |
a5082316 FB |
233 | |
234 | #define DEPTH 16 | |
47b43a1f | 235 | #include "cirrus_vga_rop2.h" |
a5082316 FB |
236 | |
237 | #define DEPTH 24 | |
47b43a1f | 238 | #include "cirrus_vga_rop2.h" |
a5082316 FB |
239 | |
240 | #define DEPTH 32 | |
47b43a1f | 241 | #include "cirrus_vga_rop2.h" |
a5082316 FB |
242 | |
243 | #undef ROP_NAME | |
244 | #undef ROP_OP | |
8c78881f BS |
245 | #undef ROP_OP_16 |
246 | #undef ROP_OP_32 |