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a19cbfb3
GH		 1/*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
47df5154 21#include "qemu/osdep.h"
a639ab04
AL		 22#include <zlib.h>
23
a19cbfb3 24#include "qemu-common.h"
1de7afc9
PB		 25#include "qemu/timer.h"
26#include "qemu/queue.h"
5444e768 27#include "qemu/atomic.h"
9c17d615 28#include "sysemu/sysemu.h"
c480bb7d 29#include "trace.h"
a19cbfb3 30
47b43a1f 31#include "qxl.h"
a19cbfb3 32
0b81c478
AL		 33/*
34 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as
35 * such can be changed by the guest, so to avoid a guest trigerrable
0a530548 36 * abort we just qxl_set_guest_bug and set the return to NULL. Still
0b81c478
AL		 37 * it may happen as a result of emulator bug as well.
38 */
a19cbfb3 39#undef SPICE_RING_PROD_ITEM
0b81c478 40#define SPICE_RING_PROD_ITEM(qxl, r, ret) { \
a19cbfb3 41 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
bc5f92e5 42 if (prod >= ARRAY_SIZE((r)->items)) { \
0a530548 43 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
bc5f92e5 44 "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \
0b81c478
AL		 45 ret = NULL; \
46 } else { \
bc5f92e5 47 ret = &(r)->items[prod].el; \
a19cbfb3 48 } \
a19cbfb3
GH		 49 }
50
51#undef SPICE_RING_CONS_ITEM
0b81c478 52#define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
a19cbfb3 53 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
bc5f92e5 54 if (cons >= ARRAY_SIZE((r)->items)) { \
0a530548 55 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
bc5f92e5 56 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \
0b81c478
AL		 57 ret = NULL; \
58 } else { \
bc5f92e5 59 ret = &(r)->items[cons].el; \
a19cbfb3 60 } \
a19cbfb3
GH		 61 }
62
63#undef ALIGN
64#define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
65
66#define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
67
68#define QXL_MODE(_x, _y, _b, _o) \
69 { .x_res = _x, \
70 .y_res = _y, \
71 .bits = _b, \
72 .stride = (_x) * (_b) / 8, \
73 .x_mili = PIXEL_SIZE * (_x), \
74 .y_mili = PIXEL_SIZE * (_y), \
75 .orientation = _o, \
76 }
77
78#define QXL_MODE_16_32(x_res, y_res, orientation) \
79 QXL_MODE(x_res, y_res, 16, orientation), \
80 QXL_MODE(x_res, y_res, 32, orientation)
81
82#define QXL_MODE_EX(x_res, y_res) \
83 QXL_MODE_16_32(x_res, y_res, 0), \
038c1879 84 QXL_MODE_16_32(x_res, y_res, 1)
a19cbfb3
GH		 85
86static QXLMode qxl_modes[] = {
87 QXL_MODE_EX(640, 480),
88 QXL_MODE_EX(800, 480),
89 QXL_MODE_EX(800, 600),
90 QXL_MODE_EX(832, 624),
91 QXL_MODE_EX(960, 640),
92 QXL_MODE_EX(1024, 600),
93 QXL_MODE_EX(1024, 768),
94 QXL_MODE_EX(1152, 864),
95 QXL_MODE_EX(1152, 870),
96 QXL_MODE_EX(1280, 720),
97 QXL_MODE_EX(1280, 760),
98 QXL_MODE_EX(1280, 768),
99 QXL_MODE_EX(1280, 800),
100 QXL_MODE_EX(1280, 960),
101 QXL_MODE_EX(1280, 1024),
102 QXL_MODE_EX(1360, 768),
103 QXL_MODE_EX(1366, 768),
104 QXL_MODE_EX(1400, 1050),
105 QXL_MODE_EX(1440, 900),
106 QXL_MODE_EX(1600, 900),
107 QXL_MODE_EX(1600, 1200),
108 QXL_MODE_EX(1680, 1050),
109 QXL_MODE_EX(1920, 1080),
a19cbfb3
GH		 110 /* these modes need more than 8 MB video memory */
111 QXL_MODE_EX(1920, 1200),
112 QXL_MODE_EX(1920, 1440),
5c74fb27 113 QXL_MODE_EX(2000, 2000),
a19cbfb3 114 QXL_MODE_EX(2048, 1536),
5c74fb27 115 QXL_MODE_EX(2048, 2048),
a19cbfb3
GH		 116 QXL_MODE_EX(2560, 1440),
117 QXL_MODE_EX(2560, 1600),
a19cbfb3
GH		 118 /* these modes need more than 16 MB video memory */
119 QXL_MODE_EX(2560, 2048),
120 QXL_MODE_EX(2800, 2100),
121 QXL_MODE_EX(3200, 2400),
03d9825d 122 /* these modes need more than 32 MB video memory */
d4bcb199
GH		 123 QXL_MODE_EX(3840, 2160), /* 4k mainstream */
124 QXL_MODE_EX(4096, 2160), /* 4k */
03d9825d 125 /* these modes need more than 64 MB video memory */
d4bcb199 126 QXL_MODE_EX(7680, 4320), /* 8k mainstream */
03d9825d 127 /* these modes need more than 128 MB video memory */
d4bcb199 128 QXL_MODE_EX(8192, 4320), /* 8k */
a19cbfb3
GH		 129};
130
a19cbfb3 131static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
5ff4e36c 132static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
a19cbfb3
GH		 133static void qxl_reset_memslots(PCIQXLDevice *d);
134static void qxl_reset_surfaces(PCIQXLDevice *d);
135static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
136
15162335
GH		 137static void qxl_hw_update(void *opaque);
138
0a530548 139void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
2bce0400 140{
917ae08c 141 trace_qxl_set_guest_bug(qxl->id);
2bce0400 142 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
087e6a42 143 qxl->guest_bug = 1;
2bce0400 144 if (qxl->guestdebug) {
7635392c
AL		 145 va_list ap;
146 va_start(ap, msg);
147 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
148 vfprintf(stderr, msg, ap);
149 fprintf(stderr, "\n");
150 va_end(ap);
2bce0400
GH		 151 }
152}
153
087e6a42
AL		 154static void qxl_clear_guest_bug(PCIQXLDevice *qxl)
155{
156 qxl->guest_bug = 0;
157}
aee32bf3
GH		 158
159void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
160 struct QXLRect *area, struct QXLRect *dirty_rects,
161 uint32_t num_dirty_rects,
5ff4e36c 162 uint32_t clear_dirty_region,
2e1a98c9 163 qxl_async_io async, struct QXLCookie *cookie)
aee32bf3 164{
c480bb7d
AL		 165 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
166 area->top, area->bottom);
167 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
168 clear_dirty_region);
5ff4e36c 169 if (async == QXL_SYNC) {
26defe81 170 spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area,
5ff4e36c
AL		 171 dirty_rects, num_dirty_rects, clear_dirty_region);
172 } else {
2e1a98c9 173 assert(cookie != NULL);
5ff4e36c 174 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
5dba0d45 175 clear_dirty_region, (uintptr_t)cookie);
5ff4e36c 176 }
aee32bf3
GH		 177}
178
5ff4e36c
AL		 179static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
180 uint32_t id)
aee32bf3 181{
c480bb7d 182 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
14898cf6 183 qemu_mutex_lock(&qxl->track_lock);
14898cf6
GH		 184 qxl->guest_surfaces.cmds[id] = 0;
185 qxl->guest_surfaces.count--;
186 qemu_mutex_unlock(&qxl->track_lock);
aee32bf3
GH		 187}
188
5ff4e36c
AL		 189static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
190 qxl_async_io async)
191{
2e1a98c9
AL		 192 QXLCookie *cookie;
193
c480bb7d 194 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
5ff4e36c 195 if (async) {
2e1a98c9
AL		 196 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
197 QXL_IO_DESTROY_SURFACE_ASYNC);
198 cookie->u.surface_id = id;
5dba0d45 199 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
5ff4e36c 200 } else {
26defe81 201 spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id);
753b8b0d 202 qxl_spice_destroy_surface_wait_complete(qxl, id);
5ff4e36c
AL		 203 }
204}
205
3e16b9c5
AL		 206static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
207{
c480bb7d
AL		 208 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
209 qxl->num_free_res);
2e1a98c9 210 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
5dba0d45
PM		 211 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
212 QXL_IO_FLUSH_SURFACES_ASYNC));
3e16b9c5 213}
3e16b9c5 214
aee32bf3
GH		 215void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
216 uint32_t count)
217{
c480bb7d 218 trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
26defe81 219 spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count);
aee32bf3
GH		 220}
221
222void qxl_spice_oom(PCIQXLDevice *qxl)
223{
c480bb7d 224 trace_qxl_spice_oom(qxl->id);
26defe81 225 spice_qxl_oom(&qxl->ssd.qxl);
aee32bf3
GH		 226}
227
228void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
229{
c480bb7d 230 trace_qxl_spice_reset_memslots(qxl->id);
26defe81 231 spice_qxl_reset_memslots(&qxl->ssd.qxl);
aee32bf3
GH		 232}
233
5ff4e36c 234static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
aee32bf3 235{
c480bb7d 236 trace_qxl_spice_destroy_surfaces_complete(qxl->id);
14898cf6 237 qemu_mutex_lock(&qxl->track_lock);
ddd8fdc7 238 memset(qxl->guest_surfaces.cmds, 0,
8bb9f51c 239 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces);
14898cf6
GH		 240 qxl->guest_surfaces.count = 0;
241 qemu_mutex_unlock(&qxl->track_lock);
aee32bf3
GH		 242}
243
5ff4e36c
AL		 244static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
245{
c480bb7d 246 trace_qxl_spice_destroy_surfaces(qxl->id, async);
5ff4e36c 247 if (async) {
2e1a98c9 248 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
5dba0d45
PM		 249 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
250 QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
5ff4e36c 251 } else {
26defe81 252 spice_qxl_destroy_surfaces(&qxl->ssd.qxl);
5ff4e36c
AL		 253 qxl_spice_destroy_surfaces_complete(qxl);
254 }
255}
256
020af1c4
AL		 257static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay)
258{
259 trace_qxl_spice_monitors_config(qxl->id);
020af1c4
AL		 260 if (replay) {
261 /*
262 * don't use QXL_COOKIE_TYPE_IO:
263 * - we are not running yet (post_load), we will assert
264 * in send_events
265 * - this is not a guest io, but a reply, so async_io isn't set.
266 */
267 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
268 qxl->guest_monitors_config,
269 MEMSLOT_GROUP_GUEST,
270 (uintptr_t)qxl_cookie_new(
271 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG,
272 0));
273 } else {
567161fd
FZ		 274#if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
275 if (qxl->max_outputs) {
a52b2cbf 276 spice_qxl_set_max_monitors(&qxl->ssd.qxl, qxl->max_outputs);
567161fd
FZ		 277 }
278#endif
020af1c4
AL		 279 qxl->guest_monitors_config = qxl->ram->monitors_config;
280 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
281 qxl->ram->monitors_config,
282 MEMSLOT_GROUP_GUEST,
283 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
284 QXL_IO_MONITORS_CONFIG_ASYNC));
285 }
020af1c4
AL		 286}
287
aee32bf3
GH		 288void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
289{
c480bb7d 290 trace_qxl_spice_reset_image_cache(qxl->id);
26defe81 291 spice_qxl_reset_image_cache(&qxl->ssd.qxl);
aee32bf3
GH		 292}
293
294void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
295{
c480bb7d 296 trace_qxl_spice_reset_cursor(qxl->id);
26defe81 297 spice_qxl_reset_cursor(&qxl->ssd.qxl);
30f6da66
YH		 298 qemu_mutex_lock(&qxl->track_lock);
299 qxl->guest_cursor = 0;
300 qemu_mutex_unlock(&qxl->track_lock);
958c2bce
GH		 301 if (qxl->ssd.cursor) {
302 cursor_put(qxl->ssd.cursor);
303 }
304 qxl->ssd.cursor = cursor_builtin_hidden();
aee32bf3
GH		 305}
306
a19cbfb3
GH		 307static ram_addr_t qxl_rom_size(void)
308{
038c1879
AL		 309 uint32_t required_rom_size = sizeof(QXLRom) + sizeof(QXLModes) +
310 sizeof(qxl_modes);
311 uint32_t rom_size = 8192; /* two pages */
13d1fd44 312
60b3b2a5 313 QEMU_BUILD_BUG_ON(required_rom_size > rom_size);
a19cbfb3
GH		 314 return rom_size;
315}
316
317static void init_qxl_rom(PCIQXLDevice *d)
318{
b1950430 319 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
a19cbfb3
GH		 320 QXLModes *modes = (QXLModes *)(rom + 1);
321 uint32_t ram_header_size;
322 uint32_t surface0_area_size;
323 uint32_t num_pages;
13d1fd44
AL		 324 uint32_t fb;
325 int i, n;
a19cbfb3
GH		 326
327 memset(rom, 0, d->rom_size);
328
329 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
330 rom->id = cpu_to_le32(d->id);
331 rom->log_level = cpu_to_le32(d->guestdebug);
332 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
333
334 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
335 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
336 rom->slots_start = 1;
337 rom->slots_end = NUM_MEMSLOTS - 1;
ddd8fdc7 338 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces);
a19cbfb3 339
13d1fd44 340 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) {
a19cbfb3 341 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
13d1fd44
AL		 342 if (fb > d->vgamem_size) {
343 continue;
a19cbfb3 344 }
13d1fd44
AL		 345 modes->modes[n].id = cpu_to_le32(i);
346 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res);
347 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res);
348 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits);
349 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride);
350 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
351 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
352 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation);
353 n++;
354 }
355 modes->n_modes = cpu_to_le32(n);
a19cbfb3
GH		 356
357 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
13d1fd44 358 surface0_area_size = ALIGN(d->vgamem_size, 4096);
a19cbfb3
GH		 359 num_pages = d->vga.vram_size;
360 num_pages -= ram_header_size;
361 num_pages -= surface0_area_size;
9efc2d8d 362 num_pages = num_pages / QXL_PAGE_SIZE;
a19cbfb3 363
876d5163
RK		 364 assert(ram_header_size + surface0_area_size <= d->vga.vram_size);
365
a19cbfb3
GH		 366 rom->draw_area_offset = cpu_to_le32(0);
367 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
368 rom->pages_offset = cpu_to_le32(surface0_area_size);
369 rom->num_pages = cpu_to_le32(num_pages);
370 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
371
372 d->shadow_rom = *rom;
373 d->rom = rom;
374 d->modes = modes;
375}
376
377static void init_qxl_ram(PCIQXLDevice *d)
378{
379 uint8_t *buf;
380 uint64_t *item;
381
382 buf = d->vga.vram_ptr;
383 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
384 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
385 d->ram->int_pending = cpu_to_le32(0);
386 d->ram->int_mask = cpu_to_le32(0);
9f0f352d 387 d->ram->update_surface = 0;
329f97fc 388 d->ram->monitors_config = 0;
a19cbfb3
GH		 389 SPICE_RING_INIT(&d->ram->cmd_ring);
390 SPICE_RING_INIT(&d->ram->cursor_ring);
391 SPICE_RING_INIT(&d->ram->release_ring);
0b81c478
AL		 392 SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item);
393 assert(item);
a19cbfb3
GH		 394 *item = 0;
395 qxl_ring_set_dirty(d);
396}
397
398/* can be called from spice server thread context */
b1950430 399static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
a19cbfb3 400{
fd4aa979 401 memory_region_set_dirty(mr, addr, end - addr);
a19cbfb3
GH		 402}
403
404static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
405{
b1950430 406 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
a19cbfb3
GH		 407}
408
409/* called from spice server thread context only */
410static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
411{
a19cbfb3
GH		 412 void *base = qxl->vga.vram_ptr;
413 intptr_t offset;
414
415 offset = ptr - base;
a19cbfb3 416 assert(offset < qxl->vga.vram_size);
b0297b4a 417 qxl_set_dirty(&qxl->vga.vram, offset, offset + 3);
a19cbfb3
GH		 418}
419
420/* can be called from spice server thread context */
421static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
422{
b1950430
AK		 423 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
424 ram_addr_t end = qxl->vga.vram_size;
425 qxl_set_dirty(&qxl->vga.vram, addr, end);
a19cbfb3
GH		 426}
427
428/*
429 * keep track of some command state, for savevm/loadvm.
430 * called from spice server thread context only
431 */
fae2afb1 432static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
a19cbfb3
GH		 433{
434 switch (le32_to_cpu(ext->cmd.type)) {
435 case QXL_CMD_SURFACE:
436 {
437 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
fae2afb1
AL		 438
439 if (!cmd) {
440 return 1;
441 }
a19cbfb3 442 uint32_t id = le32_to_cpu(cmd->surface_id);
47eddfbf 443
ddd8fdc7 444 if (id >= qxl->ssd.num_surfaces) {
0a530548 445 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id,
ddd8fdc7 446 qxl->ssd.num_surfaces);
47eddfbf
AL		 447 return 1;
448 }
48f4ba67
AL		 449 if (cmd->type == QXL_SURFACE_CMD_CREATE &&
450 (cmd->u.surface_create.stride & 0x03) != 0) {
451 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
452 cmd->u.surface_create.stride);
453 return 1;
454 }
14898cf6 455 qemu_mutex_lock(&qxl->track_lock);
a19cbfb3
GH		 456 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
457 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
458 qxl->guest_surfaces.count++;
459 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
460 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
461 }
462 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
463 qxl->guest_surfaces.cmds[id] = 0;
464 qxl->guest_surfaces.count--;
465 }
14898cf6 466 qemu_mutex_unlock(&qxl->track_lock);
a19cbfb3
GH		 467 break;
468 }
469 case QXL_CMD_CURSOR:
470 {
471 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
fae2afb1
AL		 472
473 if (!cmd) {
474 return 1;
475 }
a19cbfb3 476 if (cmd->type == QXL_CURSOR_SET) {
30f6da66 477 qemu_mutex_lock(&qxl->track_lock);
a19cbfb3 478 qxl->guest_cursor = ext->cmd.data;
30f6da66 479 qemu_mutex_unlock(&qxl->track_lock);
a19cbfb3
GH		 480 }
481 break;
482 }
483 }
fae2afb1 484 return 0;
a19cbfb3
GH		 485}
486
487/* spice display interface callbacks */
488
489static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
490{
491 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
492
c480bb7d 493 trace_qxl_interface_attach_worker(qxl->id);
a19cbfb3
GH		 494 qxl->ssd.worker = qxl_worker;
495}
496
497static void interface_set_compression_level(QXLInstance *sin, int level)
498{
499 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
500
c480bb7d 501 trace_qxl_interface_set_compression_level(qxl->id, level);
a19cbfb3
GH		 502 qxl->shadow_rom.compression_level = cpu_to_le32(level);
503 qxl->rom->compression_level = cpu_to_le32(level);
504 qxl_rom_set_dirty(qxl);
505}
506
507static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
508{
509 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
510
641381c1
GH		 511 if (!qemu_spice_display_is_running(&qxl->ssd)) {
512 return;
513 }
514
c480bb7d 515 trace_qxl_interface_set_mm_time(qxl->id, mm_time);
a19cbfb3
GH		 516 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
517 qxl->rom->mm_clock = cpu_to_le32(mm_time);
518 qxl_rom_set_dirty(qxl);
519}
520
521static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
522{
523 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
524
c480bb7d 525 trace_qxl_interface_get_init_info(qxl->id);
a19cbfb3
GH		 526 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
527 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
528 info->num_memslots = NUM_MEMSLOTS;
529 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
530 info->internal_groupslot_id = 0;
9efc2d8d
GH		 531 info->qxl_ram_size =
532 le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS;
ddd8fdc7 533 info->n_surfaces = qxl->ssd.num_surfaces;
a19cbfb3
GH		 534}
535
5b77870c
AL		 536static const char *qxl_mode_to_string(int mode)
537{
538 switch (mode) {
539 case QXL_MODE_COMPAT:
540 return "compat";
541 case QXL_MODE_NATIVE:
542 return "native";
543 case QXL_MODE_UNDEFINED:
544 return "undefined";
545 case QXL_MODE_VGA:
546 return "vga";
547 }
548 return "INVALID";
549}
550
8b92e298
AL		 551static const char *io_port_to_string(uint32_t io_port)
552{
553 if (io_port >= QXL_IO_RANGE_SIZE) {
554 return "out of range";
555 }
556 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
557 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
558 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
559 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
560 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
561 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
562 [QXL_IO_RESET] = "QXL_IO_RESET",
563 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
564 [QXL_IO_LOG] = "QXL_IO_LOG",
565 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
566 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
567 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
568 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
569 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
570 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
571 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
572 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
8b92e298
AL		 573 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
574 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
575 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
576 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
577 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
578 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
579 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
580 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
581 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
020af1c4 582 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC",
8b92e298
AL		 583 };
584 return io_port_to_string[io_port];
585}
586
a19cbfb3
GH		 587/* called from spice server thread context only */
588static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
589{
590 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
591 SimpleSpiceUpdate *update;
592 QXLCommandRing *ring;
593 QXLCommand *cmd;
e0c64d08 594 int notify, ret;
a19cbfb3 595
c480bb7d
AL		 596 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
597
a19cbfb3
GH		 598 switch (qxl->mode) {
599 case QXL_MODE_VGA:
e0c64d08
GH		 600 ret = false;
601 qemu_mutex_lock(&qxl->ssd.lock);
b1af98ba
GH		 602 update = QTAILQ_FIRST(&qxl->ssd.updates);
603 if (update != NULL) {
604 QTAILQ_REMOVE(&qxl->ssd.updates, update, next);
e0c64d08
GH		 605 *ext = update->ext;
606 ret = true;
a19cbfb3 607 }
e0c64d08 608 qemu_mutex_unlock(&qxl->ssd.lock);
212496c9 609 if (ret) {
c480bb7d 610 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
212496c9
AL		 611 qxl_log_command(qxl, "vga", ext);
612 }
e0c64d08 613 return ret;
a19cbfb3
GH		 614 case QXL_MODE_COMPAT:
615 case QXL_MODE_NATIVE:
616 case QXL_MODE_UNDEFINED:
a19cbfb3 617 ring = &qxl->ram->cmd_ring;
087e6a42 618 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) {
a19cbfb3
GH		 619 return false;
620 }
0b81c478
AL		 621 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
622 if (!cmd) {
623 return false;
624 }
a19cbfb3
GH		 625 ext->cmd = *cmd;
626 ext->group_id = MEMSLOT_GROUP_GUEST;
627 ext->flags = qxl->cmdflags;
628 SPICE_RING_POP(ring, notify);
629 qxl_ring_set_dirty(qxl);
630 if (notify) {
631 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
632 }
633 qxl->guest_primary.commands++;
634 qxl_track_command(qxl, ext);
635 qxl_log_command(qxl, "cmd", ext);
0b81c478 636 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
a19cbfb3
GH		 637 return true;
638 default:
639 return false;
640 }
641}
642
643/* called from spice server thread context only */
644static int interface_req_cmd_notification(QXLInstance *sin)
645{
646 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
647 int wait = 1;
648
c480bb7d 649 trace_qxl_ring_command_req_notification(qxl->id);
a19cbfb3
GH		 650 switch (qxl->mode) {
651 case QXL_MODE_COMPAT:
652 case QXL_MODE_NATIVE:
653 case QXL_MODE_UNDEFINED:
654 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
655 qxl_ring_set_dirty(qxl);
656 break;
657 default:
658 /* nothing */
659 break;
660 }
661 return wait;
662}
663
664/* called from spice server thread context only */
665static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
666{
667 QXLReleaseRing *ring = &d->ram->release_ring;
668 uint64_t *item;
669 int notify;
670
671#define QXL_FREE_BUNCH_SIZE 32
672
673 if (ring->prod - ring->cons + 1 == ring->num_items) {
674 /* ring full -- can't push */
675 return;
676 }
677 if (!flush && d->oom_running) {
678 /* collect everything from oom handler before pushing */
679 return;
680 }
681 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
682 /* collect a bit more before pushing */
683 return;
684 }
685
686 SPICE_RING_PUSH(ring, notify);
c480bb7d
AL		 687 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
688 d->guest_surfaces.count, d->num_free_res,
689 d->last_release, notify ? "yes" : "no");
690 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
691 ring->num_items, ring->prod, ring->cons);
a19cbfb3
GH		 692 if (notify) {
693 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
694 }
0b81c478
AL		 695 SPICE_RING_PROD_ITEM(d, ring, item);
696 if (!item) {
697 return;
698 }
a19cbfb3
GH		 699 *item = 0;
700 d->num_free_res = 0;
701 d->last_release = NULL;
702 qxl_ring_set_dirty(d);
703}
704
705/* called from spice server thread context only */
706static void interface_release_resource(QXLInstance *sin,
c9f88ce3 707 QXLReleaseInfoExt ext)
a19cbfb3
GH		 708{
709 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
710 QXLReleaseRing *ring;
711 uint64_t *item, id;
712
713 if (ext.group_id == MEMSLOT_GROUP_HOST) {
714 /* host group -> vga mode update request */
e8e23b7d 715 QXLCommandExt *cmdext = (void *)(intptr_t)(ext.info->id);
5643fc01
GH		 716 SimpleSpiceUpdate *update;
717 g_assert(cmdext->cmd.type == QXL_CMD_DRAW);
718 update = container_of(cmdext, SimpleSpiceUpdate, ext);
719 qemu_spice_destroy_update(&qxl->ssd, update);
a19cbfb3
GH		 720 return;
721 }
722
723 /*
724 * ext->info points into guest-visible memory
725 * pci bar 0, $command.release_info
726 */
727 ring = &qxl->ram->release_ring;
0b81c478
AL		 728 SPICE_RING_PROD_ITEM(qxl, ring, item);
729 if (!item) {
730 return;
731 }
a19cbfb3
GH		 732 if (*item == 0) {
733 /* stick head into the ring */
734 id = ext.info->id;
735 ext.info->next = 0;
736 qxl_ram_set_dirty(qxl, &ext.info->next);
737 *item = id;
738 qxl_ring_set_dirty(qxl);
739 } else {
740 /* append item to the list */
741 qxl->last_release->next = ext.info->id;
742 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
743 ext.info->next = 0;
744 qxl_ram_set_dirty(qxl, &ext.info->next);
745 }
746 qxl->last_release = ext.info;
747 qxl->num_free_res++;
c480bb7d 748 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
a19cbfb3
GH		 749 qxl_push_free_res(qxl, 0);
750}
751
752/* called from spice server thread context only */
753static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
754{
755 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
756 QXLCursorRing *ring;
757 QXLCommand *cmd;
758 int notify;
759
c480bb7d
AL		 760 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
761
a19cbfb3
GH		 762 switch (qxl->mode) {
763 case QXL_MODE_COMPAT:
764 case QXL_MODE_NATIVE:
765 case QXL_MODE_UNDEFINED:
766 ring = &qxl->ram->cursor_ring;
767 if (SPICE_RING_IS_EMPTY(ring)) {
768 return false;
769 }
0b81c478
AL		 770 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
771 if (!cmd) {
772 return false;
773 }
a19cbfb3
GH		 774 ext->cmd = *cmd;
775 ext->group_id = MEMSLOT_GROUP_GUEST;
776 ext->flags = qxl->cmdflags;
777 SPICE_RING_POP(ring, notify);
778 qxl_ring_set_dirty(qxl);
779 if (notify) {
780 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
781 }
782 qxl->guest_primary.commands++;
783 qxl_track_command(qxl, ext);
784 qxl_log_command(qxl, "csr", ext);
785 if (qxl->id == 0) {
786 qxl_render_cursor(qxl, ext);
787 }
c480bb7d 788 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
a19cbfb3
GH		 789 return true;
790 default:
791 return false;
792 }
793}
794
795/* called from spice server thread context only */
796static int interface_req_cursor_notification(QXLInstance *sin)
797{
798 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
799 int wait = 1;
800
c480bb7d 801 trace_qxl_ring_cursor_req_notification(qxl->id);
a19cbfb3
GH		 802 switch (qxl->mode) {
803 case QXL_MODE_COMPAT:
804 case QXL_MODE_NATIVE:
805 case QXL_MODE_UNDEFINED:
806 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
807 qxl_ring_set_dirty(qxl);
808 break;
809 default:
810 /* nothing */
811 break;
812 }
813 return wait;
814}
815
816/* called from spice server thread context */
817static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
818{
baeae407
AL		 819 /*
820 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
821 * use by xf86-video-qxl and is defined out in the qxl windows driver.
822 * Probably was at some earlier version that is prior to git start (2009),
823 * and is still guest trigerrable.
824 */
825 fprintf(stderr, "%s: deprecated\n", __func__);
a19cbfb3
GH		 826}
827
828/* called from spice server thread context only */
829static int interface_flush_resources(QXLInstance *sin)
830{
831 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
832 int ret;
833
a19cbfb3
GH		 834 ret = qxl->num_free_res;
835 if (ret) {
836 qxl_push_free_res(qxl, 1);
837 }
838 return ret;
839}
840
5ff4e36c
AL		 841static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
842
5ff4e36c 843/* called from spice server thread context only */
2e1a98c9 844static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
5ff4e36c 845{
5ff4e36c
AL		 846 uint32_t current_async;
847
848 qemu_mutex_lock(&qxl->async_lock);
849 current_async = qxl->current_async;
850 qxl->current_async = QXL_UNDEFINED_IO;
851 qemu_mutex_unlock(&qxl->async_lock);
852
c480bb7d 853 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
2e1a98c9
AL		 854 if (!cookie) {
855 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
856 return;
857 }
858 if (cookie && current_async != cookie->io) {
859 fprintf(stderr,
2fce7edf
AL		 860 "qxl: %s: error: current_async = %d != %"
861 PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
2e1a98c9 862 }
5ff4e36c 863 switch (current_async) {
81fb6f15
AL		 864 case QXL_IO_MEMSLOT_ADD_ASYNC:
865 case QXL_IO_DESTROY_PRIMARY_ASYNC:
866 case QXL_IO_UPDATE_AREA_ASYNC:
867 case QXL_IO_FLUSH_SURFACES_ASYNC:
020af1c4 868 case QXL_IO_MONITORS_CONFIG_ASYNC:
81fb6f15 869 break;
5ff4e36c
AL		 870 case QXL_IO_CREATE_PRIMARY_ASYNC:
871 qxl_create_guest_primary_complete(qxl);
872 break;
873 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
874 qxl_spice_destroy_surfaces_complete(qxl);
875 break;
876 case QXL_IO_DESTROY_SURFACE_ASYNC:
2e1a98c9 877 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
5ff4e36c 878 break;
81fb6f15
AL		 879 default:
880 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__,
881 current_async);
5ff4e36c
AL		 882 }
883 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
884}
885
81fb6f15
AL		 886/* called from spice server thread context only */
887static void interface_update_area_complete(QXLInstance *sin,
888 uint32_t surface_id,
889 QXLRect *dirty, uint32_t num_updated_rects)
890{
891 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
892 int i;
893 int qxl_i;
894
895 qemu_mutex_lock(&qxl->ssd.lock);
896 if (surface_id != 0 || !qxl->render_update_cookie_num) {
897 qemu_mutex_unlock(&qxl->ssd.lock);
898 return;
899 }
c480bb7d
AL		 900 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
901 dirty->right, dirty->top, dirty->bottom);
902 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
81fb6f15
AL		 903 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
904 /*
905 * overflow - treat this as a full update. Not expected to be common.
906 */
c480bb7d
AL		 907 trace_qxl_interface_update_area_complete_overflow(qxl->id,
908 QXL_NUM_DIRTY_RECTS);
81fb6f15
AL		 909 qxl->guest_primary.resized = 1;
910 }
911 if (qxl->guest_primary.resized) {
912 /*
913 * Don't bother copying or scheduling the bh since we will flip
914 * the whole area anyway on completion of the update_area async call
915 */
916 qemu_mutex_unlock(&qxl->ssd.lock);
917 return;
918 }
919 qxl_i = qxl->num_dirty_rects;
920 for (i = 0; i < num_updated_rects; i++) {
921 qxl->dirty[qxl_i++] = dirty[i];
922 }
923 qxl->num_dirty_rects += num_updated_rects;
c480bb7d
AL		 924 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
925 qxl->num_dirty_rects);
81fb6f15
AL		 926 qemu_bh_schedule(qxl->update_area_bh);
927 qemu_mutex_unlock(&qxl->ssd.lock);
928}
929
2e1a98c9
AL		 930/* called from spice server thread context only */
931static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
932{
933 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
5dba0d45 934 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
2e1a98c9
AL		 935
936 switch (cookie->type) {
937 case QXL_COOKIE_TYPE_IO:
938 interface_async_complete_io(qxl, cookie);
81fb6f15
AL		 939 g_free(cookie);
940 break;
941 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
942 qxl_render_update_area_done(qxl, cookie);
2e1a98c9 943 break;
020af1c4
AL		 944 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG:
945 break;
2e1a98c9
AL		 946 default:
947 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
948 __func__, cookie->type);
81fb6f15 949 g_free(cookie);
2e1a98c9 950 }
2e1a98c9
AL		 951}
952
c10018d6
SSP		 953/* called from spice server thread context only */
954static void interface_set_client_capabilities(QXLInstance *sin,
955 uint8_t client_present,
956 uint8_t caps[58])
957{
958 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
959
e0ac6097
AL		 960 if (qxl->revision < 4) {
961 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id,
962 qxl->revision);
963 return;
964 }
965
ab902981
HG		 966 if (runstate_check(RUN_STATE_INMIGRATE) ||
967 runstate_check(RUN_STATE_POSTMIGRATE)) {
968 return;
969 }
970
c10018d6 971 qxl->shadow_rom.client_present = client_present;
08688af0
MA		 972 memcpy(qxl->shadow_rom.client_capabilities, caps,
973 sizeof(qxl->shadow_rom.client_capabilities));
c10018d6 974 qxl->rom->client_present = client_present;
08688af0
MA		 975 memcpy(qxl->rom->client_capabilities, caps,
976 sizeof(qxl->rom->client_capabilities));
c10018d6
SSP		 977 qxl_rom_set_dirty(qxl);
978
979 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT);
980}
981
a639ab04
AL		 982static uint32_t qxl_crc32(const uint8_t *p, unsigned len)
983{
984 /*
985 * zlib xors the seed with 0xffffffff, and xors the result
986 * again with 0xffffffff; Both are not done with linux's crc32,
987 * which we want to be compatible with, so undo that.
988 */
989 return crc32(0xffffffff, p, len) ^ 0xffffffff;
990}
991
992/* called from main context only */
993static int interface_client_monitors_config(QXLInstance *sin,
994 VDAgentMonitorsConfig *monitors_config)
995{
996 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
997 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar);
998 int i;
567161fd 999 unsigned max_outputs = ARRAY_SIZE(rom->client_monitors_config.heads);
a639ab04 1000
e0ac6097
AL		 1001 if (qxl->revision < 4) {
1002 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id,
1003 qxl->revision);
1004 return 0;
1005 }
a639ab04
AL		 1006 /*
1007 * Older windows drivers set int_mask to 0 when their ISR is called,
1008 * then later set it to ~0. So it doesn't relate to the actual interrupts
1009 * handled. However, they are old, so clearly they don't support this
1010 * interrupt
1011 */
1012 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 ||
1013 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) {
1014 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id,
1015 qxl->ram->int_mask,
1016 monitors_config);
1017 return 0;
1018 }
1019 if (!monitors_config) {
1020 return 1;
1021 }
567161fd
FZ		 1022
1023#if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
1024 /* limit number of outputs based on setting limit */
1025 if (qxl->max_outputs && qxl->max_outputs <= max_outputs) {
1026 max_outputs = qxl->max_outputs;
1027 }
1028#endif
1029
a639ab04
AL		 1030 memset(&rom->client_monitors_config, 0,
1031 sizeof(rom->client_monitors_config));
1032 rom->client_monitors_config.count = monitors_config->num_of_monitors;
1033 /* monitors_config->flags ignored */
567161fd 1034 if (rom->client_monitors_config.count >= max_outputs) {
a639ab04
AL		 1035 trace_qxl_client_monitors_config_capped(qxl->id,
1036 monitors_config->num_of_monitors,
567161fd
FZ		 1037 max_outputs);
1038 rom->client_monitors_config.count = max_outputs;
a639ab04
AL		 1039 }
1040 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1041 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1042 QXLURect *rect = &rom->client_monitors_config.heads[i];
1043 /* monitor->depth ignored */
1044 rect->left = monitor->x;
1045 rect->top = monitor->y;
1046 rect->right = monitor->x + monitor->width;
1047 rect->bottom = monitor->y + monitor->height;
1048 }
1049 rom->client_monitors_config_crc = qxl_crc32(
1050 (const uint8_t *)&rom->client_monitors_config,
1051 sizeof(rom->client_monitors_config));
1052 trace_qxl_client_monitors_config_crc(qxl->id,
1053 sizeof(rom->client_monitors_config),
1054 rom->client_monitors_config_crc);
1055
1056 trace_qxl_interrupt_client_monitors_config(qxl->id,
1057 rom->client_monitors_config.count,
1058 rom->client_monitors_config.heads);
1059 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG);
1060 return 1;
1061}
a639ab04 1062
a19cbfb3
GH		 1063static const QXLInterface qxl_interface = {
1064 .base.type = SPICE_INTERFACE_QXL,
1065 .base.description = "qxl gpu",
1066 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
1067 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
1068
1069 .attache_worker = interface_attach_worker,
1070 .set_compression_level = interface_set_compression_level,
1071 .set_mm_time = interface_set_mm_time,
1072 .get_init_info = interface_get_init_info,
1073
1074 /* the callbacks below are called from spice server thread context */
1075 .get_command = interface_get_command,
1076 .req_cmd_notification = interface_req_cmd_notification,
1077 .release_resource = interface_release_resource,
1078 .get_cursor_command = interface_get_cursor_command,
1079 .req_cursor_notification = interface_req_cursor_notification,
1080 .notify_update = interface_notify_update,
1081 .flush_resources = interface_flush_resources,
5ff4e36c 1082 .async_complete = interface_async_complete,
81fb6f15 1083 .update_area_complete = interface_update_area_complete,
c10018d6 1084 .set_client_capabilities = interface_set_client_capabilities,
a639ab04 1085 .client_monitors_config = interface_client_monitors_config,
a19cbfb3
GH		 1086};
1087
15162335
GH		 1088static const GraphicHwOps qxl_ops = {
1089 .gfx_update = qxl_hw_update,
1090};
1091
a19cbfb3
GH		 1092static void qxl_enter_vga_mode(PCIQXLDevice *d)
1093{
1094 if (d->mode == QXL_MODE_VGA) {
1095 return;
1096 }
c480bb7d 1097 trace_qxl_enter_vga_mode(d->id);
0a2b5e3a
HG		 1098#if SPICE_SERVER_VERSION >= 0x000c03 /* release 0.12.3 */
1099 spice_qxl_driver_unload(&d->ssd.qxl);
1100#endif
15162335 1101 graphic_console_set_hwops(d->ssd.dcl.con, d->vga.hw_ops, &d->vga);
3dcadce5 1102 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_DEFAULT);
a19cbfb3
GH		 1103 qemu_spice_create_host_primary(&d->ssd);
1104 d->mode = QXL_MODE_VGA;
0f7bfd81 1105 vga_dirty_log_start(&d->vga);
1dbfa005 1106 graphic_hw_update(d->vga.con);
a19cbfb3
GH		 1107}
1108
1109static void qxl_exit_vga_mode(PCIQXLDevice *d)
1110{
1111 if (d->mode != QXL_MODE_VGA) {
1112 return;
1113 }
c480bb7d 1114 trace_qxl_exit_vga_mode(d->id);
15162335 1115 graphic_console_set_hwops(d->ssd.dcl.con, &qxl_ops, d);
3dcadce5 1116 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_IDLE);
0f7bfd81 1117 vga_dirty_log_stop(&d->vga);
5ff4e36c 1118 qxl_destroy_primary(d, QXL_SYNC);
a19cbfb3
GH		 1119}
1120
40010aea 1121static void qxl_update_irq(PCIQXLDevice *d)
a19cbfb3
GH		 1122{
1123 uint32_t pending = le32_to_cpu(d->ram->int_pending);
1124 uint32_t mask = le32_to_cpu(d->ram->int_mask);
1125 int level = !!(pending & mask);
9e64f8a3 1126 pci_set_irq(&d->pci, level);
a19cbfb3
GH		 1127 qxl_ring_set_dirty(d);
1128}
1129
a19cbfb3
GH		 1130static void qxl_check_state(PCIQXLDevice *d)
1131{
1132 QXLRam *ram = d->ram;
71d388d4 1133 int spice_display_running = qemu_spice_display_is_running(&d->ssd);
a19cbfb3 1134
71d388d4
YH		 1135 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
1136 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
a19cbfb3
GH		 1137}
1138
1139static void qxl_reset_state(PCIQXLDevice *d)
1140{
a19cbfb3
GH		 1141 QXLRom *rom = d->rom;
1142
be48e995 1143 qxl_check_state(d);
a19cbfb3
GH		 1144 d->shadow_rom.update_id = cpu_to_le32(0);
1145 *rom = d->shadow_rom;
1146 qxl_rom_set_dirty(d);
1147 init_qxl_ram(d);
1148 d->num_free_res = 0;
1149 d->last_release = NULL;
1150 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
f06b8521 1151 qxl_update_irq(d);
a19cbfb3
GH		 1152}
1153
1154static void qxl_soft_reset(PCIQXLDevice *d)
1155{
c480bb7d 1156 trace_qxl_soft_reset(d->id);
a19cbfb3 1157 qxl_check_state(d);
087e6a42 1158 qxl_clear_guest_bug(d);
05fa1c74 1159 qemu_mutex_lock(&d->async_lock);
a5f68c22 1160 d->current_async = QXL_UNDEFINED_IO;
05fa1c74 1161 qemu_mutex_unlock(&d->async_lock);
a19cbfb3
GH		 1162
1163 if (d->id == 0) {
1164 qxl_enter_vga_mode(d);
1165 } else {
1166 d->mode = QXL_MODE_UNDEFINED;
1167 }
1168}
1169
1170static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
1171{
75c70e37
GH		 1172 bool startstop = qemu_spice_display_is_running(&d->ssd);
1173
c480bb7d 1174 trace_qxl_hard_reset(d->id, loadvm);
a19cbfb3 1175
75c70e37
GH		 1176 if (startstop) {
1177 qemu_spice_display_stop();
1178 }
1179
aee32bf3
GH		 1180 qxl_spice_reset_cursor(d);
1181 qxl_spice_reset_image_cache(d);
a19cbfb3
GH		 1182 qxl_reset_surfaces(d);
1183 qxl_reset_memslots(d);
1184
1185 /* pre loadvm reset must not touch QXLRam. This lives in
1186 * device memory, is migrated together with RAM and thus
1187 * already loaded at this point */
1188 if (!loadvm) {
1189 qxl_reset_state(d);
1190 }
1191 qemu_spice_create_host_memslot(&d->ssd);
1192 qxl_soft_reset(d);
75c70e37
GH		 1193
1194 if (startstop) {
1195 qemu_spice_display_start();
1196 }
a19cbfb3
GH		 1197}
1198
1199static void qxl_reset_handler(DeviceState *dev)
1200{
c69f6c7d 1201 PCIQXLDevice *d = PCI_QXL(PCI_DEVICE(dev));
c480bb7d 1202
a19cbfb3
GH		 1203 qxl_hard_reset(d, 0);
1204}
1205
1206static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1207{
1208 VGACommonState *vga = opaque;
1209 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
1210
c480bb7d 1211 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
a19cbfb3 1212 if (qxl->mode != QXL_MODE_VGA) {
5ff4e36c 1213 qxl_destroy_primary(qxl, QXL_SYNC);
a19cbfb3
GH		 1214 qxl_soft_reset(qxl);
1215 }
1216 vga_ioport_write(opaque, addr, val);
1217}
1218
f67ab77a
GH		 1219static const MemoryRegionPortio qxl_vga_portio_list[] = {
1220 { 0x04, 2, 1, .read = vga_ioport_read,
1221 .write = qxl_vga_ioport_write }, /* 3b4 */
1222 { 0x0a, 1, 1, .read = vga_ioport_read,
1223 .write = qxl_vga_ioport_write }, /* 3ba */
1224 { 0x10, 16, 1, .read = vga_ioport_read,
1225 .write = qxl_vga_ioport_write }, /* 3c0 */
1226 { 0x24, 2, 1, .read = vga_ioport_read,
1227 .write = qxl_vga_ioport_write }, /* 3d4 */
1228 { 0x2a, 1, 1, .read = vga_ioport_read,
1229 .write = qxl_vga_ioport_write }, /* 3da */
1230 PORTIO_END_OF_LIST(),
1231};
1232
e954ea28
AL		 1233static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
1234 qxl_async_io async)
a19cbfb3
GH		 1235{
1236 static const int regions[] = {
1237 QXL_RAM_RANGE_INDEX,
1238 QXL_VRAM_RANGE_INDEX,
6f2b175a 1239 QXL_VRAM64_RANGE_INDEX,
a19cbfb3
GH		 1240 };
1241 uint64_t guest_start;
1242 uint64_t guest_end;
1243 int pci_region;
1244 pcibus_t pci_start;
1245 pcibus_t pci_end;
1246 intptr_t virt_start;
1247 QXLDevMemSlot memslot;
1248 int i;
1249
1250 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1251 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1252
c480bb7d 1253 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
a19cbfb3 1254
e954ea28 1255 if (slot_id >= NUM_MEMSLOTS) {
0a530548 1256 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
e954ea28
AL		 1257 slot_id, NUM_MEMSLOTS);
1258 return 1;
1259 }
1260 if (guest_start > guest_end) {
0a530548 1261 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64
e954ea28
AL		 1262 " > 0x%" PRIx64, __func__, guest_start, guest_end);
1263 return 1;
1264 }
a19cbfb3
GH		 1265
1266 for (i = 0; i < ARRAY_SIZE(regions); i++) {
1267 pci_region = regions[i];
1268 pci_start = d->pci.io_regions[pci_region].addr;
1269 pci_end = pci_start + d->pci.io_regions[pci_region].size;
1270 /* mapped? */
1271 if (pci_start == -1) {
1272 continue;
1273 }
1274 /* start address in range ? */
1275 if (guest_start < pci_start || guest_start > pci_end) {
1276 continue;
1277 }
1278 /* end address in range ? */
1279 if (guest_end > pci_end) {
1280 continue;
1281 }
1282 /* passed */
1283 break;
1284 }
e954ea28 1285 if (i == ARRAY_SIZE(regions)) {
0a530548 1286 qxl_set_guest_bug(d, "%s: finished loop without match", __func__);
e954ea28
AL		 1287 return 1;
1288 }
a19cbfb3
GH		 1289
1290 switch (pci_region) {
1291 case QXL_RAM_RANGE_INDEX:
b1950430 1292 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram);
a19cbfb3
GH		 1293 break;
1294 case QXL_VRAM_RANGE_INDEX:
6f2b175a 1295 case 4 /* vram 64bit */:
b1950430 1296 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar);
a19cbfb3
GH		 1297 break;
1298 default:
1299 /* should not happen */
0a530548 1300 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
e954ea28 1301 return 1;
a19cbfb3
GH		 1302 }
1303
1304 memslot.slot_id = slot_id;
1305 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
1306 memslot.virt_start = virt_start + (guest_start - pci_start);
1307 memslot.virt_end = virt_start + (guest_end - pci_start);
1308 memslot.addr_delta = memslot.virt_start - delta;
1309 memslot.generation = d->rom->slot_generation = 0;
1310 qxl_rom_set_dirty(d);
1311
5ff4e36c 1312 qemu_spice_add_memslot(&d->ssd, &memslot, async);
a19cbfb3
GH		 1313 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
1314 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1315 d->guest_slots[slot_id].delta = delta;
1316 d->guest_slots[slot_id].active = 1;
e954ea28 1317 return 0;
a19cbfb3
GH		 1318}
1319
1320static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1321{
5c59d118 1322 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
a19cbfb3
GH		 1323 d->guest_slots[slot_id].active = 0;
1324}
1325
1326static void qxl_reset_memslots(PCIQXLDevice *d)
1327{
aee32bf3 1328 qxl_spice_reset_memslots(d);
a19cbfb3
GH		 1329 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1330}
1331
1332static void qxl_reset_surfaces(PCIQXLDevice *d)
1333{
c480bb7d 1334 trace_qxl_reset_surfaces(d->id);
a19cbfb3 1335 d->mode = QXL_MODE_UNDEFINED;
5ff4e36c 1336 qxl_spice_destroy_surfaces(d, QXL_SYNC);
a19cbfb3
GH		 1337}
1338
e25139b3 1339/* can be also called from spice server thread context */
a19cbfb3
GH		 1340void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1341{
1342 uint64_t phys = le64_to_cpu(pqxl);
1343 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1344 uint64_t offset = phys & 0xffffffffffff;
1345
1346 switch (group_id) {
1347 case MEMSLOT_GROUP_HOST:
f4a8a424 1348 return (void *)(intptr_t)offset;
a19cbfb3 1349 case MEMSLOT_GROUP_GUEST:
4b635c59 1350 if (slot >= NUM_MEMSLOTS) {
0a530548
AL		 1351 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
1352 NUM_MEMSLOTS);
4b635c59
AL		 1353 return NULL;
1354 }
1355 if (!qxl->guest_slots[slot].active) {
0a530548 1356 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
4b635c59
AL		 1357 return NULL;
1358 }
1359 if (offset < qxl->guest_slots[slot].delta) {
0a530548
AL		 1360 qxl_set_guest_bug(qxl,
1361 "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
4b635c59
AL		 1362 slot, offset, qxl->guest_slots[slot].delta);
1363 return NULL;
1364 }
a19cbfb3 1365 offset -= qxl->guest_slots[slot].delta;
4b635c59 1366 if (offset > qxl->guest_slots[slot].size) {
0a530548
AL		 1367 qxl_set_guest_bug(qxl,
1368 "slot %d offset %"PRIu64" > size %"PRIu64"\n",
4b635c59
AL		 1369 slot, offset, qxl->guest_slots[slot].size);
1370 return NULL;
1371 }
a19cbfb3 1372 return qxl->guest_slots[slot].ptr + offset;
a19cbfb3 1373 }
4b635c59 1374 return NULL;
a19cbfb3
GH		 1375}
1376
5ff4e36c
AL		 1377static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1378{
1379 /* for local rendering */
1380 qxl_render_resize(qxl);
1381}
1382
1383static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1384 qxl_async_io async)
a19cbfb3
GH		 1385{
1386 QXLDevSurfaceCreate surface;
1387 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
3761abb1 1388 uint32_t requested_height = le32_to_cpu(sc->height);
13d1fd44
AL		 1389 int requested_stride = le32_to_cpu(sc->stride);
1390
3761abb1
AL		 1391 if (requested_stride == INT32_MIN ||
1392 abs(requested_stride) * (uint64_t)requested_height
1393 > qxl->vgamem_size) {
1394 qxl_set_guest_bug(qxl, "%s: requested primary larger than framebuffer"
1395 " stride %d x height %" PRIu32 " > %" PRIu32,
1396 __func__, requested_stride, requested_height,
1397 qxl->vgamem_size);
13d1fd44
AL		 1398 return;
1399 }
a19cbfb3 1400
ddf9f4b7 1401 if (qxl->mode == QXL_MODE_NATIVE) {
0a530548 1402 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
ddf9f4b7
AL		 1403 __func__);
1404 }
a19cbfb3
GH		 1405 qxl_exit_vga_mode(qxl);
1406
a19cbfb3
GH		 1407 surface.format = le32_to_cpu(sc->format);
1408 surface.height = le32_to_cpu(sc->height);
1409 surface.mem = le64_to_cpu(sc->mem);
1410 surface.position = le32_to_cpu(sc->position);
1411 surface.stride = le32_to_cpu(sc->stride);
1412 surface.width = le32_to_cpu(sc->width);
1413 surface.type = le32_to_cpu(sc->type);
1414 surface.flags = le32_to_cpu(sc->flags);
c480bb7d
AL		 1415 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1416 sc->format, sc->position);
1417 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1418 sc->flags);
a19cbfb3 1419
48f4ba67
AL		 1420 if ((surface.stride & 0x3) != 0) {
1421 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0",
1422 surface.stride);
1423 return;
1424 }
1425
a19cbfb3
GH		 1426 surface.mouse_mode = true;
1427 surface.group_id = MEMSLOT_GROUP_GUEST;
1428 if (loadvm) {
1429 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1430 }
1431
1432 qxl->mode = QXL_MODE_NATIVE;
1433 qxl->cmdflags = 0;
5ff4e36c 1434 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
a19cbfb3 1435
5ff4e36c
AL		 1436 if (async == QXL_SYNC) {
1437 qxl_create_guest_primary_complete(qxl);
1438 }
a19cbfb3
GH		 1439}
1440
5ff4e36c
AL		 1441/* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1442 * done (in QXL_SYNC case), 0 otherwise. */
1443static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
a19cbfb3
GH		 1444{
1445 if (d->mode == QXL_MODE_UNDEFINED) {
5ff4e36c 1446 return 0;
a19cbfb3 1447 }
c480bb7d 1448 trace_qxl_destroy_primary(d->id);
a19cbfb3 1449 d->mode = QXL_MODE_UNDEFINED;
5ff4e36c 1450 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
30f6da66 1451 qxl_spice_reset_cursor(d);
5ff4e36c 1452 return 1;
a19cbfb3
GH		 1453}
1454
9c70434f 1455static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm)
a19cbfb3
GH		 1456{
1457 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1458 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1459 QXLMode *mode = d->modes->modes + modenr;
1460 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1461 QXLMemSlot slot = {
1462 .mem_start = start,
1463 .mem_end = end
1464 };
9c70434f
GH		 1465
1466 if (modenr >= d->modes->n_modes) {
1467 qxl_set_guest_bug(d, "mode number out of range");
1468 return;
1469 }
1470
a19cbfb3
GH		 1471 QXLSurfaceCreate surface = {
1472 .width = mode->x_res,
1473 .height = mode->y_res,
1474 .stride = -mode->x_res * 4,
1475 .format = SPICE_SURFACE_FMT_32_xRGB,
1476 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1477 .mouse_mode = true,
1478 .mem = devmem + d->shadow_rom.draw_area_offset,
1479 };
1480
c480bb7d
AL		 1481 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1482 devmem);
a19cbfb3
GH		 1483 if (!loadvm) {
1484 qxl_hard_reset(d, 0);
1485 }
1486
1487 d->guest_slots[0].slot = slot;
e954ea28 1488 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0);
a19cbfb3
GH		 1489
1490 d->guest_primary.surface = surface;
5ff4e36c 1491 qxl_create_guest_primary(d, 0, QXL_SYNC);
a19cbfb3
GH		 1492
1493 d->mode = QXL_MODE_COMPAT;
1494 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
a19cbfb3
GH		 1495 if (mode->bits == 16) {
1496 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1497 }
a19cbfb3
GH		 1498 d->shadow_rom.mode = cpu_to_le32(modenr);
1499 d->rom->mode = cpu_to_le32(modenr);
1500 qxl_rom_set_dirty(d);
1501}
1502
a8170e5e 1503static void ioport_write(void *opaque, hwaddr addr,
b1950430 1504 uint64_t val, unsigned size)
a19cbfb3
GH		 1505{
1506 PCIQXLDevice *d = opaque;
b1950430 1507 uint32_t io_port = addr;
5ff4e36c 1508 qxl_async_io async = QXL_SYNC;
5ff4e36c 1509 uint32_t orig_io_port = io_port;
a19cbfb3 1510
d96aafca 1511 if (d->guest_bug && io_port != QXL_IO_RESET) {
087e6a42
AL		 1512 return;
1513 }
1514
020af1c4 1515 if (d->revision <= QXL_REVISION_STABLE_V10 &&
ffe01e59 1516 io_port > QXL_IO_FLUSH_RELEASE) {
020af1c4
AL		 1517 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n",
1518 io_port, d->revision);
1519 return;
1520 }
1521
a19cbfb3
GH		 1522 switch (io_port) {
1523 case QXL_IO_RESET:
1524 case QXL_IO_SET_MODE:
1525 case QXL_IO_MEMSLOT_ADD:
1526 case QXL_IO_MEMSLOT_DEL:
1527 case QXL_IO_CREATE_PRIMARY:
81144d1a 1528 case QXL_IO_UPDATE_IRQ:
a3d14054 1529 case QXL_IO_LOG:
5ff4e36c
AL		 1530 case QXL_IO_MEMSLOT_ADD_ASYNC:
1531 case QXL_IO_CREATE_PRIMARY_ASYNC:
a19cbfb3
GH		 1532 break;
1533 default:
e21a298a 1534 if (d->mode != QXL_MODE_VGA) {
a19cbfb3 1535 break;
e21a298a 1536 }
c480bb7d 1537 trace_qxl_io_unexpected_vga_mode(d->id,
917ae08c 1538 addr, val, io_port_to_string(io_port));
5ff4e36c
AL		 1539 /* be nice to buggy guest drivers */
1540 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
020af1c4 1541 io_port < QXL_IO_RANGE_SIZE) {
5ff4e36c
AL		 1542 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1543 }
a19cbfb3
GH		 1544 return;
1545 }
1546
5ff4e36c
AL		 1547 /* we change the io_port to avoid ifdeffery in the main switch */
1548 orig_io_port = io_port;
1549 switch (io_port) {
1550 case QXL_IO_UPDATE_AREA_ASYNC:
1551 io_port = QXL_IO_UPDATE_AREA;
1552 goto async_common;
1553 case QXL_IO_MEMSLOT_ADD_ASYNC:
1554 io_port = QXL_IO_MEMSLOT_ADD;
1555 goto async_common;
1556 case QXL_IO_CREATE_PRIMARY_ASYNC:
1557 io_port = QXL_IO_CREATE_PRIMARY;
1558 goto async_common;
1559 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1560 io_port = QXL_IO_DESTROY_PRIMARY;
1561 goto async_common;
1562 case QXL_IO_DESTROY_SURFACE_ASYNC:
1563 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1564 goto async_common;
1565 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1566 io_port = QXL_IO_DESTROY_ALL_SURFACES;
3e16b9c5
AL		 1567 goto async_common;
1568 case QXL_IO_FLUSH_SURFACES_ASYNC:
020af1c4 1569 case QXL_IO_MONITORS_CONFIG_ASYNC:
5ff4e36c
AL		 1570async_common:
1571 async = QXL_ASYNC;
1572 qemu_mutex_lock(&d->async_lock);
1573 if (d->current_async != QXL_UNDEFINED_IO) {
0a530548 1574 qxl_set_guest_bug(d, "%d async started before last (%d) complete",
5ff4e36c
AL		 1575 io_port, d->current_async);
1576 qemu_mutex_unlock(&d->async_lock);
1577 return;
1578 }
1579 d->current_async = orig_io_port;
1580 qemu_mutex_unlock(&d->async_lock);
5ff4e36c
AL		 1581 break;
1582 default:
1583 break;
1584 }
18b20385
GH		 1585 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode),
1586 addr, io_port_to_string(addr),
1587 val, size, async);
5ff4e36c 1588
a19cbfb3
GH		 1589 switch (io_port) {
1590 case QXL_IO_UPDATE_AREA:
1591 {
81fb6f15 1592 QXLCookie *cookie = NULL;
a19cbfb3 1593 QXLRect update = d->ram->update_area;
81fb6f15 1594
ddd8fdc7 1595 if (d->ram->update_surface > d->ssd.num_surfaces) {
511b13e2
AL		 1596 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1597 d->ram->update_surface);
36a03e0b 1598 break;
511b13e2 1599 }
36a03e0b
MT		 1600 if (update.left >= update.right || update.top >= update.bottom ||
1601 update.left < 0 || update.top < 0) {
511b13e2
AL		 1602 qxl_set_guest_bug(d,
1603 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1604 update.left, update.top, update.right, update.bottom);
9e5a25f1
MAL		 1605 if (update.left == update.right || update.top == update.bottom) {
1606 /* old drivers may provide empty area, keep going */
1607 qxl_clear_guest_bug(d);
1608 goto cancel_async;
1609 }
ccc2960d
DH		 1610 break;
1611 }
81fb6f15
AL		 1612 if (async == QXL_ASYNC) {
1613 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1614 QXL_IO_UPDATE_AREA_ASYNC);
1615 cookie->u.area = update;
1616 }
aee32bf3 1617 qxl_spice_update_area(d, d->ram->update_surface,
81fb6f15
AL		 1618 cookie ? &cookie->u.area : &update,
1619 NULL, 0, 0, async, cookie);
a19cbfb3
GH		 1620 break;
1621 }
1622 case QXL_IO_NOTIFY_CMD:
5c59d118 1623 qemu_spice_wakeup(&d->ssd);
a19cbfb3
GH		 1624 break;
1625 case QXL_IO_NOTIFY_CURSOR:
5c59d118 1626 qemu_spice_wakeup(&d->ssd);
a19cbfb3
GH		 1627 break;
1628 case QXL_IO_UPDATE_IRQ:
40010aea 1629 qxl_update_irq(d);
a19cbfb3
GH		 1630 break;
1631 case QXL_IO_NOTIFY_OOM:
a19cbfb3
GH		 1632 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1633 break;
1634 }
1635 d->oom_running = 1;
aee32bf3 1636 qxl_spice_oom(d);
a19cbfb3
GH		 1637 d->oom_running = 0;
1638 break;
1639 case QXL_IO_SET_MODE:
a19cbfb3
GH		 1640 qxl_set_mode(d, val, 0);
1641 break;
1642 case QXL_IO_LOG:
1a1bc085 1643 trace_qxl_io_log(d->id, d->ram->log_buf);
a19cbfb3 1644 if (d->guestdebug) {
a680f7e7 1645 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
bc72ad67 1646 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), d->ram->log_buf);
a19cbfb3
GH		 1647 }
1648 break;
1649 case QXL_IO_RESET:
a19cbfb3
GH		 1650 qxl_hard_reset(d, 0);
1651 break;
1652 case QXL_IO_MEMSLOT_ADD:
2bce0400 1653 if (val >= NUM_MEMSLOTS) {
0a530548 1654 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
2bce0400
GH		 1655 break;
1656 }
1657 if (d->guest_slots[val].active) {
0a530548
AL		 1658 qxl_set_guest_bug(d,
1659 "QXL_IO_MEMSLOT_ADD: memory slot already active");
2bce0400
GH		 1660 break;
1661 }
a19cbfb3 1662 d->guest_slots[val].slot = d->ram->mem_slot;
5ff4e36c 1663 qxl_add_memslot(d, val, 0, async);
a19cbfb3
GH		 1664 break;
1665 case QXL_IO_MEMSLOT_DEL:
2bce0400 1666 if (val >= NUM_MEMSLOTS) {
0a530548 1667 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
2bce0400
GH		 1668 break;
1669 }
a19cbfb3
GH		 1670 qxl_del_memslot(d, val);
1671 break;
1672 case QXL_IO_CREATE_PRIMARY:
2bce0400 1673 if (val != 0) {
0a530548 1674 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
5ff4e36c
AL		 1675 async);
1676 goto cancel_async;
2bce0400 1677 }
a19cbfb3 1678 d->guest_primary.surface = d->ram->create_surface;
5ff4e36c 1679 qxl_create_guest_primary(d, 0, async);
a19cbfb3
GH		 1680 break;
1681 case QXL_IO_DESTROY_PRIMARY:
2bce0400 1682 if (val != 0) {
0a530548 1683 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
5ff4e36c
AL		 1684 async);
1685 goto cancel_async;
1686 }
5ff4e36c 1687 if (!qxl_destroy_primary(d, async)) {
c480bb7d
AL		 1688 trace_qxl_io_destroy_primary_ignored(d->id,
1689 qxl_mode_to_string(d->mode));
5ff4e36c 1690 goto cancel_async;
2bce0400 1691 }
a19cbfb3
GH		 1692 break;
1693 case QXL_IO_DESTROY_SURFACE_WAIT:
ddd8fdc7 1694 if (val >= d->ssd.num_surfaces) {
0a530548 1695 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
5f8daf2e 1696 "%" PRIu64 " >= NUM_SURFACES", async, val);
5ff4e36c
AL		 1697 goto cancel_async;
1698 }
1699 qxl_spice_destroy_surface_wait(d, val, async);
a19cbfb3 1700 break;
3e16b9c5
AL		 1701 case QXL_IO_FLUSH_RELEASE: {
1702 QXLReleaseRing *ring = &d->ram->release_ring;
1703 if (ring->prod - ring->cons + 1 == ring->num_items) {
1704 fprintf(stderr,
1705 "ERROR: no flush, full release ring [p%d,%dc]\n",
1706 ring->prod, ring->cons);
1707 }
1708 qxl_push_free_res(d, 1 /* flush */);
3e16b9c5
AL		 1709 break;
1710 }
1711 case QXL_IO_FLUSH_SURFACES_ASYNC:
3e16b9c5
AL		 1712 qxl_spice_flush_surfaces_async(d);
1713 break;
a19cbfb3 1714 case QXL_IO_DESTROY_ALL_SURFACES:
5ff4e36c
AL		 1715 d->mode = QXL_MODE_UNDEFINED;
1716 qxl_spice_destroy_surfaces(d, async);
a19cbfb3 1717 break;
020af1c4
AL		 1718 case QXL_IO_MONITORS_CONFIG_ASYNC:
1719 qxl_spice_monitors_config_async(d, 0);
1720 break;
a19cbfb3 1721 default:
0a530548 1722 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
a19cbfb3 1723 }
5ff4e36c
AL		 1724 return;
1725cancel_async:
5ff4e36c
AL		 1726 if (async) {
1727 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1728 qemu_mutex_lock(&d->async_lock);
1729 d->current_async = QXL_UNDEFINED_IO;
1730 qemu_mutex_unlock(&d->async_lock);
1731 }
a19cbfb3
GH		 1732}
1733
a8170e5e 1734static uint64_t ioport_read(void *opaque, hwaddr addr,
b1950430 1735 unsigned size)
a19cbfb3 1736{
917ae08c 1737 PCIQXLDevice *qxl = opaque;
a19cbfb3 1738
917ae08c 1739 trace_qxl_io_read_unexpected(qxl->id);
a19cbfb3
GH		 1740 return 0xff;
1741}
1742
b1950430
AK		 1743static const MemoryRegionOps qxl_io_ops = {
1744 .read = ioport_read,
1745 .write = ioport_write,
1746 .valid = {
1747 .min_access_size = 1,
1748 .max_access_size = 1,
1749 },
1750};
a19cbfb3 1751
4a46c99c 1752static void qxl_update_irq_bh(void *opaque)
a19cbfb3
GH		 1753{
1754 PCIQXLDevice *d = opaque;
40010aea 1755 qxl_update_irq(d);
a19cbfb3
GH		 1756}
1757
a19cbfb3
GH		 1758static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1759{
1760 uint32_t old_pending;
1761 uint32_t le_events = cpu_to_le32(events);
1762
917ae08c 1763 trace_qxl_send_events(d->id, events);
511aefb0
AL		 1764 if (!qemu_spice_display_is_running(&d->ssd)) {
1765 /* spice-server tracks guest running state and should not do this */
1766 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n",
1767 __func__);
1768 trace_qxl_send_events_vm_stopped(d->id, events);
1769 return;
1770 }
5444e768 1771 old_pending = atomic_fetch_or(&d->ram->int_pending, le_events);
a19cbfb3
GH		 1772 if ((old_pending & le_events) == le_events) {
1773 return;
1774 }
4a46c99c 1775 qemu_bh_schedule(d->update_irq);
a19cbfb3
GH		 1776}
1777
1778/* graphics console */
1779
1780static void qxl_hw_update(void *opaque)
1781{
1782 PCIQXLDevice *qxl = opaque;
a19cbfb3 1783
15162335 1784 qxl_render_update(qxl);
a19cbfb3
GH		 1785}
1786
e25139b3
YH		 1787static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1788{
c5825ac6 1789 uintptr_t vram_start;
e25139b3
YH		 1790 int i;
1791
2aa9e85c 1792 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
e25139b3
YH		 1793 return;
1794 }
1795
1796 /* dirty the primary surface */
1797 qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset,
1798 qxl->shadow_rom.surface0_area_size);
1799
c5825ac6 1800 vram_start = (uintptr_t)memory_region_get_ram_ptr(&qxl->vram_bar);
e25139b3
YH		 1801
1802 /* dirty the off-screen surfaces */
ddd8fdc7 1803 for (i = 0; i < qxl->ssd.num_surfaces; i++) {
e25139b3
YH		 1804 QXLSurfaceCmd *cmd;
1805 intptr_t surface_offset;
1806 int surface_size;
1807
1808 if (qxl->guest_surfaces.cmds[i] == 0) {
1809 continue;
1810 }
1811
1812 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1813 MEMSLOT_GROUP_GUEST);
fae2afb1 1814 assert(cmd);
e25139b3
YH		 1815 assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1816 surface_offset = (intptr_t)qxl_phys2virt(qxl,
1817 cmd->u.surface_create.data,
1818 MEMSLOT_GROUP_GUEST);
fae2afb1 1819 assert(surface_offset);
e25139b3
YH		 1820 surface_offset -= vram_start;
1821 surface_size = cmd->u.surface_create.height *
1822 abs(cmd->u.surface_create.stride);
c480bb7d 1823 trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size);
e25139b3
YH		 1824 qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size);
1825 }
1826}
1827
1dfb4dd9
LC		 1828static void qxl_vm_change_state_handler(void *opaque, int running,
1829 RunState state)
a19cbfb3
GH		 1830{
1831 PCIQXLDevice *qxl = opaque;
a19cbfb3 1832
efbf2950
YH		 1833 if (running) {
1834 /*
1835 * if qxl_send_events was called from spice server context before
40010aea 1836 * migration ended, qxl_update_irq for these events might not have been
efbf2950
YH		 1837 * called
1838 */
40010aea 1839 qxl_update_irq(qxl);
e25139b3
YH		 1840 } else {
1841 /* make sure surfaces are saved before migration */
1842 qxl_dirty_surfaces(qxl);
a19cbfb3
GH		 1843 }
1844}
1845
1846/* display change listener */
1847
7c20b4a3 1848static void display_update(DisplayChangeListener *dcl,
7c20b4a3 1849 int x, int y, int w, int h)
a19cbfb3 1850{
c6c06853
GH		 1851 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1852
1853 if (qxl->mode == QXL_MODE_VGA) {
1854 qemu_spice_display_update(&qxl->ssd, x, y, w, h);
a19cbfb3
GH		 1855 }
1856}
1857
c12aeb86 1858static void display_switch(DisplayChangeListener *dcl,
c12aeb86 1859 struct DisplaySurface *surface)
a19cbfb3 1860{
c6c06853
GH		 1861 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1862
71874c17 1863 qxl->ssd.ds = surface;
c6c06853 1864 if (qxl->mode == QXL_MODE_VGA) {
c12aeb86 1865 qemu_spice_display_switch(&qxl->ssd, surface);
a19cbfb3
GH		 1866 }
1867}
1868
bc2ed970 1869static void display_refresh(DisplayChangeListener *dcl)
a19cbfb3 1870{
c6c06853
GH		 1871 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1872
1873 if (qxl->mode == QXL_MODE_VGA) {
1874 qemu_spice_display_refresh(&qxl->ssd);
a19cbfb3
GH		 1875 }
1876}
1877
7c20b4a3
GH		 1878static DisplayChangeListenerOps display_listener_ops = {
1879 .dpy_name = "spice/qxl",
a93a4a22 1880 .dpy_gfx_update = display_update,
c12aeb86 1881 .dpy_gfx_switch = display_switch,
7c20b4a3 1882 .dpy_refresh = display_refresh,
a19cbfb3
GH		 1883};
1884
13d1fd44 1885static void qxl_init_ramsize(PCIQXLDevice *qxl)
a974192c 1886{
13d1fd44
AL		 1887 /* vga mode framebuffer / primary surface (bar 0, first part) */
1888 if (qxl->vgamem_size_mb < 8) {
1889 qxl->vgamem_size_mb = 8;
1890 }
876d5163
RK		 1891 /* XXX: we round vgamem_size_mb up to a nearest power of two and it must be
1892 * less than vga_common_init()'s maximum on qxl->vga.vram_size (512 now).
1893 */
1894 if (qxl->vgamem_size_mb > 256) {
1895 qxl->vgamem_size_mb = 256;
1896 }
13d1fd44
AL		 1897 qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024;
1898
1899 /* vga ram (bar 0, total) */
017438ee
GH		 1900 if (qxl->ram_size_mb != -1) {
1901 qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024;
1902 }
13d1fd44
AL		 1903 if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
1904 qxl->vga.vram_size = qxl->vgamem_size * 2;
a974192c
GH		 1905 }
1906
6f2b175a
GH		 1907 /* vram32 (surfaces, 32bit, bar 1) */
1908 if (qxl->vram32_size_mb != -1) {
1909 qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024;
1910 }
1911 if (qxl->vram32_size < 4096) {
1912 qxl->vram32_size = 4096;
1913 }
1914
1915 /* vram (surfaces, 64bit, bar 4+5) */
017438ee
GH		 1916 if (qxl->vram_size_mb != -1) {
1917 qxl->vram_size = qxl->vram_size_mb * 1024 * 1024;
1918 }
6f2b175a
GH		 1919 if (qxl->vram_size < qxl->vram32_size) {
1920 qxl->vram_size = qxl->vram32_size;
a974192c 1921 }
6f2b175a 1922
a974192c 1923 if (qxl->revision == 1) {
6f2b175a 1924 qxl->vram32_size = 4096;
a974192c
GH		 1925 qxl->vram_size = 4096;
1926 }
bb7443f6
RK		 1927 qxl->vgamem_size = pow2ceil(qxl->vgamem_size);
1928 qxl->vga.vram_size = pow2ceil(qxl->vga.vram_size);
1929 qxl->vram32_size = pow2ceil(qxl->vram32_size);
1930 qxl->vram_size = pow2ceil(qxl->vram_size);
a974192c
GH		 1931}
1932
042a24db 1933static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp)
a19cbfb3
GH		 1934{
1935 uint8_t* config = qxl->pci.config;
a19cbfb3
GH		 1936 uint32_t pci_device_rev;
1937 uint32_t io_size;
1938
1939 qxl->mode = QXL_MODE_UNDEFINED;
1940 qxl->generation = 1;
1941 qxl->num_memslots = NUM_MEMSLOTS;
14898cf6 1942 qemu_mutex_init(&qxl->track_lock);
5ff4e36c
AL		 1943 qemu_mutex_init(&qxl->async_lock);
1944 qxl->current_async = QXL_UNDEFINED_IO;
087e6a42 1945 qxl->guest_bug = 0;
a19cbfb3
GH		 1946
1947 switch (qxl->revision) {
1948 case 1: /* spice 0.4 -- qxl-1 */
a19cbfb3 1949 pci_device_rev = QXL_REVISION_STABLE_V04;
3f6297b9 1950 io_size = 8;
a19cbfb3
GH		 1951 break;
1952 case 2: /* spice 0.6 -- qxl-2 */
a19cbfb3 1953 pci_device_rev = QXL_REVISION_STABLE_V06;
3f6297b9 1954 io_size = 16;
a19cbfb3 1955 break;
9197a7c8 1956 case 3: /* qxl-3 */
020af1c4
AL		 1957 pci_device_rev = QXL_REVISION_STABLE_V10;
1958 io_size = 32; /* PCI region size must be pow2 */
1959 break;
020af1c4
AL		 1960 case 4: /* qxl-4 */
1961 pci_device_rev = QXL_REVISION_STABLE_V12;
bb7443f6 1962 io_size = pow2ceil(QXL_IO_RANGE_SIZE);
9197a7c8 1963 break;
36839d35 1964 default:
042a24db
MA		 1965 error_setg(errp, "Invalid revision %d for qxl device (max %d)",
1966 qxl->revision, QXL_DEFAULT_REVISION);
1967 return;
a19cbfb3
GH		 1968 }
1969
a19cbfb3
GH		 1970 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1971 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1972
1973 qxl->rom_size = qxl_rom_size();
3eadad55 1974 memory_region_init_ram(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom",
f8ed85ac 1975 qxl->rom_size, &error_fatal);
c5705a77 1976 vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev);
a19cbfb3
GH		 1977 init_qxl_rom(qxl);
1978 init_qxl_ram(qxl);
1979
ddd8fdc7 1980 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
3eadad55 1981 memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram",
f8ed85ac 1982 qxl->vram_size, &error_fatal);
c5705a77 1983 vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev);
3eadad55
PB		 1984 memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32",
1985 &qxl->vram_bar, 0, qxl->vram32_size);
a19cbfb3 1986
3eadad55 1987 memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl,
b1950430
AK		 1988 "qxl-ioports", io_size);
1989 if (qxl->id == 0) {
1990 vga_dirty_log_start(&qxl->vga);
1991 }
bd8f2f5d 1992 memory_region_set_flush_coalesced(&qxl->io_bar);
b1950430
AK		 1993
1994
e824b2cc
AK		 1995 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
1996 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
a19cbfb3 1997
e824b2cc
AK		 1998 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
1999 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
a19cbfb3 2000
e824b2cc
AK		 2001 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
2002 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
a19cbfb3 2003
e824b2cc 2004 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
6f2b175a
GH		 2005 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
2006
2007 if (qxl->vram32_size < qxl->vram_size) {
2008 /*
2009 * Make the 64bit vram bar show up only in case it is
2010 * configured to be larger than the 32bit vram bar.
2011 */
2012 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
2013 PCI_BASE_ADDRESS_SPACE_MEMORY |
2014 PCI_BASE_ADDRESS_MEM_TYPE_64 |
2015 PCI_BASE_ADDRESS_MEM_PREFETCH,
2016 &qxl->vram_bar);
2017 }
2018
2019 /* print pci bar details */
2020 dprint(qxl, 1, "ram/%s: %d MB [region 0]\n",
2021 qxl->id == 0 ? "pri" : "sec",
2022 qxl->vga.vram_size / (1024*1024));
2023 dprint(qxl, 1, "vram/32: %d MB [region 1]\n",
2024 qxl->vram32_size / (1024*1024));
2025 dprint(qxl, 1, "vram/64: %d MB %s\n",
2026 qxl->vram_size / (1024*1024),
2027 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
a19cbfb3
GH		 2028
2029 qxl->ssd.qxl.base.sif = &qxl_interface.base;
9fa03286 2030 if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) {
042a24db
MA		 2031 error_setg(errp, "qxl interface %d.%d not supported by spice-server",
2032 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR);
2033 return;
e25a0651 2034 }
a19cbfb3
GH		 2035 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
2036
4a46c99c 2037 qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl);
a19cbfb3
GH		 2038 qxl_reset_state(qxl);
2039
81fb6f15 2040 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
0b2824e5 2041 qxl->ssd.cursor_bh = qemu_bh_new(qemu_spice_cursor_refresh_bh, &qxl->ssd);
a19cbfb3
GH		 2042}
2043
042a24db 2044static void qxl_realize_primary(PCIDevice *dev, Error **errp)
a19cbfb3 2045{
c69f6c7d 2046 PCIQXLDevice *qxl = PCI_QXL(dev);
a19cbfb3 2047 VGACommonState *vga = &qxl->vga;
042a24db 2048 Error *local_err = NULL;
a19cbfb3
GH		 2049
2050 qxl->id = 0;
13d1fd44 2051 qxl_init_ramsize(qxl);
54a85d46 2052 vga->vbe_size = qxl->vgamem_size;
4a1e244e 2053 vga->vram_size_mb = qxl->vga.vram_size >> 20;
e2bbfc8e 2054 vga_common_init(vga, OBJECT(dev), true);
712f0cc7
PB		 2055 vga_init(vga, OBJECT(dev),
2056 pci_address_space(dev), pci_address_space_io(dev), false);
848696bf 2057 portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list,
db10ca90 2058 vga, "vga");
848696bf
KB		 2059 portio_list_set_flush_coalesced(&qxl->vga_port_list);
2060 portio_list_add(&qxl->vga_port_list, pci_address_space_io(dev), 0x3b0);
a19cbfb3 2061
5643706a 2062 vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
c78f7137 2063 qemu_spice_display_init_common(&qxl->ssd);
a19cbfb3 2064
042a24db
MA		 2065 qxl_realize_common(qxl, &local_err);
2066 if (local_err) {
2067 error_propagate(errp, local_err);
2068 return;
bdd4df33
GH		 2069 }
2070
7c20b4a3 2071 qxl->ssd.dcl.ops = &display_listener_ops;
284d1c6b 2072 qxl->ssd.dcl.con = vga->con;
5209089f 2073 register_displaychangelistener(&qxl->ssd.dcl);
a19cbfb3
GH		 2074}
2075
042a24db 2076static void qxl_realize_secondary(PCIDevice *dev, Error **errp)
a19cbfb3
GH		 2077{
2078 static int device_id = 1;
c69f6c7d 2079 PCIQXLDevice *qxl = PCI_QXL(dev);
a19cbfb3
GH		 2080
2081 qxl->id = device_id++;
13d1fd44 2082 qxl_init_ramsize(qxl);
3eadad55 2083 memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram",
f8ed85ac 2084 qxl->vga.vram_size, &error_fatal);
c5705a77 2085 vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev);
b1950430 2086 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
5643706a 2087 qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
a19cbfb3 2088
042a24db 2089 qxl_realize_common(qxl, errp);
a19cbfb3
GH		 2090}
2091
2092static void qxl_pre_save(void *opaque)
2093{
2094 PCIQXLDevice* d = opaque;
2095 uint8_t *ram_start = d->vga.vram_ptr;
2096
c480bb7d 2097 trace_qxl_pre_save(d->id);
a19cbfb3
GH		 2098 if (d->last_release == NULL) {
2099 d->last_release_offset = 0;
2100 } else {
2101 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
2102 }
2103 assert(d->last_release_offset < d->vga.vram_size);
2104}
2105
2106static int qxl_pre_load(void *opaque)
2107{
2108 PCIQXLDevice* d = opaque;
2109
c480bb7d 2110 trace_qxl_pre_load(d->id);
a19cbfb3
GH		 2111 qxl_hard_reset(d, 1);
2112 qxl_exit_vga_mode(d);
a19cbfb3
GH		 2113 return 0;
2114}
2115
54825d2e
AL		 2116static void qxl_create_memslots(PCIQXLDevice *d)
2117{
2118 int i;
2119
2120 for (i = 0; i < NUM_MEMSLOTS; i++) {
2121 if (!d->guest_slots[i].active) {
2122 continue;
2123 }
54825d2e
AL		 2124 qxl_add_memslot(d, i, 0, QXL_SYNC);
2125 }
2126}
2127
a19cbfb3
GH		 2128static int qxl_post_load(void *opaque, int version)
2129{
2130 PCIQXLDevice* d = opaque;
2131 uint8_t *ram_start = d->vga.vram_ptr;
2132 QXLCommandExt *cmds;
54825d2e 2133 int in, out, newmode;
a19cbfb3 2134
a19cbfb3
GH		 2135 assert(d->last_release_offset < d->vga.vram_size);
2136 if (d->last_release_offset == 0) {
2137 d->last_release = NULL;
2138 } else {
2139 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
2140 }
2141
2142 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
2143
c480bb7d 2144 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
a19cbfb3
GH		 2145 newmode = d->mode;
2146 d->mode = QXL_MODE_UNDEFINED;
54825d2e 2147
a19cbfb3
GH		 2148 switch (newmode) {
2149 case QXL_MODE_UNDEFINED:
fa98efe9 2150 qxl_create_memslots(d);
a19cbfb3
GH		 2151 break;
2152 case QXL_MODE_VGA:
54825d2e 2153 qxl_create_memslots(d);
a19cbfb3
GH		 2154 qxl_enter_vga_mode(d);
2155 break;
2156 case QXL_MODE_NATIVE:
54825d2e 2157 qxl_create_memslots(d);
5ff4e36c 2158 qxl_create_guest_primary(d, 1, QXL_SYNC);
a19cbfb3
GH		 2159
2160 /* replay surface-create and cursor-set commands */
9de68637 2161 cmds = g_new0(QXLCommandExt, d->ssd.num_surfaces + 1);
ddd8fdc7 2162 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) {
a19cbfb3
GH		 2163 if (d->guest_surfaces.cmds[in] == 0) {
2164 continue;
2165 }
2166 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
2167 cmds[out].cmd.type = QXL_CMD_SURFACE;
2168 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2169 out++;
2170 }
30f6da66
YH		 2171 if (d->guest_cursor) {
2172 cmds[out].cmd.data = d->guest_cursor;
2173 cmds[out].cmd.type = QXL_CMD_CURSOR;
2174 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2175 out++;
2176 }
aee32bf3 2177 qxl_spice_loadvm_commands(d, cmds, out);
7267c094 2178 g_free(cmds);
020af1c4
AL		 2179 if (d->guest_monitors_config) {
2180 qxl_spice_monitors_config_async(d, 1);
2181 }
a19cbfb3
GH		 2182 break;
2183 case QXL_MODE_COMPAT:
54825d2e
AL		 2184 /* note: no need to call qxl_create_memslots, qxl_set_mode
2185 * creates the mem slot. */
a19cbfb3
GH		 2186 qxl_set_mode(d, d->shadow_rom.mode, 1);
2187 break;
2188 }
a19cbfb3
GH		 2189 return 0;
2190}
2191
b67737a6 2192#define QXL_SAVE_VERSION 21
a19cbfb3 2193
020af1c4
AL		 2194static bool qxl_monitors_config_needed(void *opaque)
2195{
2196 PCIQXLDevice *qxl = opaque;
2197
2198 return qxl->guest_monitors_config != 0;
2199}
2200
2201
a19cbfb3
GH		 2202static VMStateDescription qxl_memslot = {
2203 .name = "qxl-memslot",
2204 .version_id = QXL_SAVE_VERSION,
2205 .minimum_version_id = QXL_SAVE_VERSION,
2206 .fields = (VMStateField[]) {
2207 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
2208 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
2209 VMSTATE_UINT32(active, struct guest_slots),
2210 VMSTATE_END_OF_LIST()
2211 }
2212};
2213
2214static VMStateDescription qxl_surface = {
2215 .name = "qxl-surface",
2216 .version_id = QXL_SAVE_VERSION,
2217 .minimum_version_id = QXL_SAVE_VERSION,
2218 .fields = (VMStateField[]) {
2219 VMSTATE_UINT32(width, QXLSurfaceCreate),
2220 VMSTATE_UINT32(height, QXLSurfaceCreate),
2221 VMSTATE_INT32(stride, QXLSurfaceCreate),
2222 VMSTATE_UINT32(format, QXLSurfaceCreate),
2223 VMSTATE_UINT32(position, QXLSurfaceCreate),
2224 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
2225 VMSTATE_UINT32(flags, QXLSurfaceCreate),
2226 VMSTATE_UINT32(type, QXLSurfaceCreate),
2227 VMSTATE_UINT64(mem, QXLSurfaceCreate),
2228 VMSTATE_END_OF_LIST()
2229 }
2230};
2231
020af1c4
AL		 2232static VMStateDescription qxl_vmstate_monitors_config = {
2233 .name = "qxl/monitors-config",
2234 .version_id = 1,
2235 .minimum_version_id = 1,
5cd8cada 2236 .needed = qxl_monitors_config_needed,
020af1c4
AL		 2237 .fields = (VMStateField[]) {
2238 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice),
2239 VMSTATE_END_OF_LIST()
2240 },
2241};
2242
a19cbfb3
GH		 2243static VMStateDescription qxl_vmstate = {
2244 .name = "qxl",
2245 .version_id = QXL_SAVE_VERSION,
2246 .minimum_version_id = QXL_SAVE_VERSION,
2247 .pre_save = qxl_pre_save,
2248 .pre_load = qxl_pre_load,
2249 .post_load = qxl_post_load,
020af1c4 2250 .fields = (VMStateField[]) {
a19cbfb3
GH		 2251 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
2252 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
2253 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
2254 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
2255 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
2256 VMSTATE_UINT32(mode, PCIQXLDevice),
2257 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
b67737a6
GH		 2258 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
2259 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
2260 qxl_memslot, struct guest_slots),
2261 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
2262 qxl_surface, QXLSurfaceCreate),
ddd8fdc7
GH		 2263 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice),
2264 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice,
2265 ssd.num_surfaces, 0,
2266 vmstate_info_uint64, uint64_t),
b67737a6 2267 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
a19cbfb3
GH		 2268 VMSTATE_END_OF_LIST()
2269 },
5cd8cada
JQ		 2270 .subsections = (const VMStateDescription*[]) {
2271 &qxl_vmstate_monitors_config,
2272 NULL
020af1c4 2273 }
a19cbfb3
GH		 2274};
2275
78e60ba5
GH		 2276static Property qxl_properties[] = {
2277 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
2278 64 * 1024 * 1024),
6f2b175a 2279 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size,
78e60ba5
GH		 2280 64 * 1024 * 1024),
2281 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
2282 QXL_DEFAULT_REVISION),
2283 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
2284 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
2285 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
017438ee 2286 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
79ce3567
AL		 2287 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
2288 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
9e56edcf 2289 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16),
ddd8fdc7 2290 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024),
567161fd
FZ		 2291#if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
2292 DEFINE_PROP_UINT16("max_outputs", PCIQXLDevice, max_outputs, 0),
2293#endif
78e60ba5
GH		 2294 DEFINE_PROP_END_OF_LIST(),
2295};
2296
c69f6c7d 2297static void qxl_pci_class_init(ObjectClass *klass, void *data)
40021f08 2298{
39bffca2 2299 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 2300 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2301
40021f08
AL		 2302 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2303 k->device_id = QXL_DEVICE_ID_STABLE;
125ee0ed 2304 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
39bffca2
AL		 2305 dc->reset = qxl_reset_handler;
2306 dc->vmsd = &qxl_vmstate;
2307 dc->props = qxl_properties;
c69f6c7d
GA		 2308}
2309
2310static const TypeInfo qxl_pci_type_info = {
2311 .name = TYPE_PCI_QXL,
2312 .parent = TYPE_PCI_DEVICE,
2313 .instance_size = sizeof(PCIQXLDevice),
2314 .abstract = true,
2315 .class_init = qxl_pci_class_init,
2316};
2317
2318static void qxl_primary_class_init(ObjectClass *klass, void *data)
2319{
2320 DeviceClass *dc = DEVICE_CLASS(klass);
2321 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2322
2323 k->realize = qxl_realize_primary;
2324 k->romfile = "vgabios-qxl.bin";
2325 k->class_id = PCI_CLASS_DISPLAY_VGA;
2326 dc->desc = "Spice QXL GPU (primary, vga compatible)";
2897ae02 2327 dc->hotpluggable = false;
40021f08
AL		 2328}
2329
8c43a6f0 2330static const TypeInfo qxl_primary_info = {
39bffca2 2331 .name = "qxl-vga",
c69f6c7d 2332 .parent = TYPE_PCI_QXL,
39bffca2 2333 .class_init = qxl_primary_class_init,
a19cbfb3
GH		 2334};
2335
40021f08
AL		 2336static void qxl_secondary_class_init(ObjectClass *klass, void *data)
2337{
39bffca2 2338 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 2339 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2340
042a24db 2341 k->realize = qxl_realize_secondary;
40021f08 2342 k->class_id = PCI_CLASS_DISPLAY_OTHER;
39bffca2 2343 dc->desc = "Spice QXL GPU (secondary)";
40021f08
AL		 2344}
2345
8c43a6f0 2346static const TypeInfo qxl_secondary_info = {
39bffca2 2347 .name = "qxl",
c69f6c7d 2348 .parent = TYPE_PCI_QXL,
39bffca2 2349 .class_init = qxl_secondary_class_init,
a19cbfb3
GH		 2350};
2351
83f7d43a 2352static void qxl_register_types(void)
a19cbfb3 2353{
c69f6c7d 2354 type_register_static(&qxl_pci_type_info);
39bffca2
AL		 2355 type_register_static(&qxl_primary_info);
2356 type_register_static(&qxl_secondary_info);
a19cbfb3
GH		 2357}
2358
83f7d43a 2359type_init(qxl_register_types)
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