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Merge remote-tracking branch 'remotes/kraxel/tags/ipxe-pull-request' into staging
[mirror_qemu.git] / hw / display / qxl.c
CommitLineData
a19cbfb3
GH		 1/*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
47df5154 21#include "qemu/osdep.h"
a639ab04
AL		 22#include <zlib.h>
23
a19cbfb3 24#include "qemu-common.h"
1de7afc9
PB		 25#include "qemu/timer.h"
26#include "qemu/queue.h"
5444e768 27#include "qemu/atomic.h"
9c17d615 28#include "sysemu/sysemu.h"
795c40b8 29#include "migration/blocker.h"
c480bb7d 30#include "trace.h"
a19cbfb3 31
47b43a1f 32#include "qxl.h"
a19cbfb3 33
0b81c478
AL		 34/*
35 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as
36 * such can be changed by the guest, so to avoid a guest trigerrable
0a530548 37 * abort we just qxl_set_guest_bug and set the return to NULL. Still
0b81c478
AL		 38 * it may happen as a result of emulator bug as well.
39 */
a19cbfb3 40#undef SPICE_RING_PROD_ITEM
0b81c478 41#define SPICE_RING_PROD_ITEM(qxl, r, ret) { \
a19cbfb3 42 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
bc5f92e5 43 if (prod >= ARRAY_SIZE((r)->items)) { \
0a530548 44 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
bc5f92e5 45 "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \
0b81c478
AL		 46 ret = NULL; \
47 } else { \
bc5f92e5 48 ret = &(r)->items[prod].el; \
a19cbfb3 49 } \
a19cbfb3
GH		 50 }
51
52#undef SPICE_RING_CONS_ITEM
0b81c478 53#define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
a19cbfb3 54 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
bc5f92e5 55 if (cons >= ARRAY_SIZE((r)->items)) { \
0a530548 56 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
bc5f92e5 57 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \
0b81c478
AL		 58 ret = NULL; \
59 } else { \
bc5f92e5 60 ret = &(r)->items[cons].el; \
a19cbfb3 61 } \
a19cbfb3
GH		 62 }
63
64#undef ALIGN
65#define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
66
67#define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
68
69#define QXL_MODE(_x, _y, _b, _o) \
70 { .x_res = _x, \
71 .y_res = _y, \
72 .bits = _b, \
73 .stride = (_x) * (_b) / 8, \
74 .x_mili = PIXEL_SIZE * (_x), \
75 .y_mili = PIXEL_SIZE * (_y), \
76 .orientation = _o, \
77 }
78
79#define QXL_MODE_16_32(x_res, y_res, orientation) \
80 QXL_MODE(x_res, y_res, 16, orientation), \
81 QXL_MODE(x_res, y_res, 32, orientation)
82
83#define QXL_MODE_EX(x_res, y_res) \
84 QXL_MODE_16_32(x_res, y_res, 0), \
038c1879 85 QXL_MODE_16_32(x_res, y_res, 1)
a19cbfb3
GH		 86
87static QXLMode qxl_modes[] = {
88 QXL_MODE_EX(640, 480),
89 QXL_MODE_EX(800, 480),
90 QXL_MODE_EX(800, 600),
91 QXL_MODE_EX(832, 624),
92 QXL_MODE_EX(960, 640),
93 QXL_MODE_EX(1024, 600),
94 QXL_MODE_EX(1024, 768),
95 QXL_MODE_EX(1152, 864),
96 QXL_MODE_EX(1152, 870),
97 QXL_MODE_EX(1280, 720),
98 QXL_MODE_EX(1280, 760),
99 QXL_MODE_EX(1280, 768),
100 QXL_MODE_EX(1280, 800),
101 QXL_MODE_EX(1280, 960),
102 QXL_MODE_EX(1280, 1024),
103 QXL_MODE_EX(1360, 768),
104 QXL_MODE_EX(1366, 768),
105 QXL_MODE_EX(1400, 1050),
106 QXL_MODE_EX(1440, 900),
107 QXL_MODE_EX(1600, 900),
108 QXL_MODE_EX(1600, 1200),
109 QXL_MODE_EX(1680, 1050),
110 QXL_MODE_EX(1920, 1080),
a19cbfb3
GH		 111 /* these modes need more than 8 MB video memory */
112 QXL_MODE_EX(1920, 1200),
113 QXL_MODE_EX(1920, 1440),
5c74fb27 114 QXL_MODE_EX(2000, 2000),
a19cbfb3 115 QXL_MODE_EX(2048, 1536),
5c74fb27 116 QXL_MODE_EX(2048, 2048),
a19cbfb3
GH		 117 QXL_MODE_EX(2560, 1440),
118 QXL_MODE_EX(2560, 1600),
a19cbfb3
GH		 119 /* these modes need more than 16 MB video memory */
120 QXL_MODE_EX(2560, 2048),
121 QXL_MODE_EX(2800, 2100),
122 QXL_MODE_EX(3200, 2400),
03d9825d 123 /* these modes need more than 32 MB video memory */
d4bcb199
GH		 124 QXL_MODE_EX(3840, 2160), /* 4k mainstream */
125 QXL_MODE_EX(4096, 2160), /* 4k */
03d9825d 126 /* these modes need more than 64 MB video memory */
d4bcb199 127 QXL_MODE_EX(7680, 4320), /* 8k mainstream */
03d9825d 128 /* these modes need more than 128 MB video memory */
d4bcb199 129 QXL_MODE_EX(8192, 4320), /* 8k */
a19cbfb3
GH		 130};
131
a19cbfb3 132static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
5ff4e36c 133static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
a19cbfb3
GH		 134static void qxl_reset_memslots(PCIQXLDevice *d);
135static void qxl_reset_surfaces(PCIQXLDevice *d);
136static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
137
15162335
GH		 138static void qxl_hw_update(void *opaque);
139
0a530548 140void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
2bce0400 141{
917ae08c 142 trace_qxl_set_guest_bug(qxl->id);
2bce0400 143 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
087e6a42 144 qxl->guest_bug = 1;
2bce0400 145 if (qxl->guestdebug) {
7635392c
AL		 146 va_list ap;
147 va_start(ap, msg);
148 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
149 vfprintf(stderr, msg, ap);
150 fprintf(stderr, "\n");
151 va_end(ap);
2bce0400
GH		 152 }
153}
154
087e6a42
AL		 155static void qxl_clear_guest_bug(PCIQXLDevice *qxl)
156{
157 qxl->guest_bug = 0;
158}
aee32bf3
GH		 159
160void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
161 struct QXLRect *area, struct QXLRect *dirty_rects,
162 uint32_t num_dirty_rects,
5ff4e36c 163 uint32_t clear_dirty_region,
2e1a98c9 164 qxl_async_io async, struct QXLCookie *cookie)
aee32bf3 165{
c480bb7d
AL		 166 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
167 area->top, area->bottom);
168 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
169 clear_dirty_region);
5ff4e36c 170 if (async == QXL_SYNC) {
26defe81 171 spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area,
5ff4e36c
AL		 172 dirty_rects, num_dirty_rects, clear_dirty_region);
173 } else {
2e1a98c9 174 assert(cookie != NULL);
5ff4e36c 175 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
5dba0d45 176 clear_dirty_region, (uintptr_t)cookie);
5ff4e36c 177 }
aee32bf3
GH		 178}
179
5ff4e36c
AL		 180static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
181 uint32_t id)
aee32bf3 182{
c480bb7d 183 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
14898cf6 184 qemu_mutex_lock(&qxl->track_lock);
14898cf6
GH		 185 qxl->guest_surfaces.cmds[id] = 0;
186 qxl->guest_surfaces.count--;
187 qemu_mutex_unlock(&qxl->track_lock);
aee32bf3
GH		 188}
189
5ff4e36c
AL		 190static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
191 qxl_async_io async)
192{
2e1a98c9
AL		 193 QXLCookie *cookie;
194
c480bb7d 195 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
5ff4e36c 196 if (async) {
2e1a98c9
AL		 197 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
198 QXL_IO_DESTROY_SURFACE_ASYNC);
199 cookie->u.surface_id = id;
5dba0d45 200 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
5ff4e36c 201 } else {
26defe81 202 spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id);
753b8b0d 203 qxl_spice_destroy_surface_wait_complete(qxl, id);
5ff4e36c
AL		 204 }
205}
206
3e16b9c5
AL		 207static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
208{
c480bb7d
AL		 209 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
210 qxl->num_free_res);
2e1a98c9 211 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
5dba0d45
PM		 212 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
213 QXL_IO_FLUSH_SURFACES_ASYNC));
3e16b9c5 214}
3e16b9c5 215
aee32bf3
GH		 216void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
217 uint32_t count)
218{
c480bb7d 219 trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
26defe81 220 spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count);
aee32bf3
GH		 221}
222
223void qxl_spice_oom(PCIQXLDevice *qxl)
224{
c480bb7d 225 trace_qxl_spice_oom(qxl->id);
26defe81 226 spice_qxl_oom(&qxl->ssd.qxl);
aee32bf3
GH		 227}
228
229void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
230{
c480bb7d 231 trace_qxl_spice_reset_memslots(qxl->id);
26defe81 232 spice_qxl_reset_memslots(&qxl->ssd.qxl);
aee32bf3
GH		 233}
234
5ff4e36c 235static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
aee32bf3 236{
c480bb7d 237 trace_qxl_spice_destroy_surfaces_complete(qxl->id);
14898cf6 238 qemu_mutex_lock(&qxl->track_lock);
ddd8fdc7 239 memset(qxl->guest_surfaces.cmds, 0,
8bb9f51c 240 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces);
14898cf6
GH		 241 qxl->guest_surfaces.count = 0;
242 qemu_mutex_unlock(&qxl->track_lock);
aee32bf3
GH		 243}
244
5ff4e36c
AL		 245static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
246{
c480bb7d 247 trace_qxl_spice_destroy_surfaces(qxl->id, async);
5ff4e36c 248 if (async) {
2e1a98c9 249 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
5dba0d45
PM		 250 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
251 QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
5ff4e36c 252 } else {
26defe81 253 spice_qxl_destroy_surfaces(&qxl->ssd.qxl);
5ff4e36c
AL		 254 qxl_spice_destroy_surfaces_complete(qxl);
255 }
256}
257
020af1c4
AL		 258static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay)
259{
260 trace_qxl_spice_monitors_config(qxl->id);
020af1c4
AL		 261 if (replay) {
262 /*
263 * don't use QXL_COOKIE_TYPE_IO:
264 * - we are not running yet (post_load), we will assert
265 * in send_events
266 * - this is not a guest io, but a reply, so async_io isn't set.
267 */
268 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
269 qxl->guest_monitors_config,
270 MEMSLOT_GROUP_GUEST,
271 (uintptr_t)qxl_cookie_new(
272 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG,
273 0));
274 } else {
567161fd
FZ		 275#if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
276 if (qxl->max_outputs) {
a52b2cbf 277 spice_qxl_set_max_monitors(&qxl->ssd.qxl, qxl->max_outputs);
567161fd
FZ		 278 }
279#endif
020af1c4
AL		 280 qxl->guest_monitors_config = qxl->ram->monitors_config;
281 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
282 qxl->ram->monitors_config,
283 MEMSLOT_GROUP_GUEST,
284 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
285 QXL_IO_MONITORS_CONFIG_ASYNC));
286 }
020af1c4
AL		 287}
288
aee32bf3
GH		 289void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
290{
c480bb7d 291 trace_qxl_spice_reset_image_cache(qxl->id);
26defe81 292 spice_qxl_reset_image_cache(&qxl->ssd.qxl);
aee32bf3
GH		 293}
294
295void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
296{
c480bb7d 297 trace_qxl_spice_reset_cursor(qxl->id);
26defe81 298 spice_qxl_reset_cursor(&qxl->ssd.qxl);
30f6da66
YH		 299 qemu_mutex_lock(&qxl->track_lock);
300 qxl->guest_cursor = 0;
301 qemu_mutex_unlock(&qxl->track_lock);
958c2bce
GH		 302 if (qxl->ssd.cursor) {
303 cursor_put(qxl->ssd.cursor);
304 }
305 qxl->ssd.cursor = cursor_builtin_hidden();
aee32bf3
GH		 306}
307
6f663d7b
GH		 308static uint32_t qxl_crc32(const uint8_t *p, unsigned len)
309{
310 /*
311 * zlib xors the seed with 0xffffffff, and xors the result
312 * again with 0xffffffff; Both are not done with linux's crc32,
313 * which we want to be compatible with, so undo that.
314 */
315 return crc32(0xffffffff, p, len) ^ 0xffffffff;
316}
317
a19cbfb3
GH		 318static ram_addr_t qxl_rom_size(void)
319{
df45892c
MT		 320#define QXL_REQUIRED_SZ (sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes))
321#define QXL_ROM_SZ 8192
13d1fd44 322
df45892c
MT		 323 QEMU_BUILD_BUG_ON(QXL_REQUIRED_SZ > QXL_ROM_SZ);
324 return QXL_ROM_SZ;
a19cbfb3
GH		 325}
326
327static void init_qxl_rom(PCIQXLDevice *d)
328{
b1950430 329 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
a19cbfb3
GH		 330 QXLModes *modes = (QXLModes *)(rom + 1);
331 uint32_t ram_header_size;
332 uint32_t surface0_area_size;
333 uint32_t num_pages;
13d1fd44
AL		 334 uint32_t fb;
335 int i, n;
a19cbfb3
GH		 336
337 memset(rom, 0, d->rom_size);
338
339 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
340 rom->id = cpu_to_le32(d->id);
341 rom->log_level = cpu_to_le32(d->guestdebug);
342 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
343
344 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
345 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
346 rom->slots_start = 1;
347 rom->slots_end = NUM_MEMSLOTS - 1;
ddd8fdc7 348 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces);
a19cbfb3 349
13d1fd44 350 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) {
a19cbfb3 351 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
13d1fd44
AL		 352 if (fb > d->vgamem_size) {
353 continue;
a19cbfb3 354 }
13d1fd44
AL		 355 modes->modes[n].id = cpu_to_le32(i);
356 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res);
357 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res);
358 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits);
359 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride);
360 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
361 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
362 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation);
363 n++;
364 }
365 modes->n_modes = cpu_to_le32(n);
a19cbfb3
GH		 366
367 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
13d1fd44 368 surface0_area_size = ALIGN(d->vgamem_size, 4096);
a19cbfb3
GH		 369 num_pages = d->vga.vram_size;
370 num_pages -= ram_header_size;
371 num_pages -= surface0_area_size;
9efc2d8d 372 num_pages = num_pages / QXL_PAGE_SIZE;
a19cbfb3 373
876d5163
RK		 374 assert(ram_header_size + surface0_area_size <= d->vga.vram_size);
375
a19cbfb3
GH		 376 rom->draw_area_offset = cpu_to_le32(0);
377 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
378 rom->pages_offset = cpu_to_le32(surface0_area_size);
379 rom->num_pages = cpu_to_le32(num_pages);
380 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
381
6f663d7b
GH		 382 if (d->xres && d->yres) {
383 /* needs linux kernel 4.12+ to work */
384 rom->client_monitors_config.count = 1;
385 rom->client_monitors_config.heads[0].left = 0;
386 rom->client_monitors_config.heads[0].top = 0;
387 rom->client_monitors_config.heads[0].right = cpu_to_le32(d->xres);
388 rom->client_monitors_config.heads[0].bottom = cpu_to_le32(d->yres);
389 rom->client_monitors_config_crc = qxl_crc32(
390 (const uint8_t *)&rom->client_monitors_config,
391 sizeof(rom->client_monitors_config));
392 }
393
a19cbfb3
GH		 394 d->shadow_rom = *rom;
395 d->rom = rom;
396 d->modes = modes;
397}
398
399static void init_qxl_ram(PCIQXLDevice *d)
400{
401 uint8_t *buf;
402 uint64_t *item;
403
404 buf = d->vga.vram_ptr;
405 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
406 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
407 d->ram->int_pending = cpu_to_le32(0);
408 d->ram->int_mask = cpu_to_le32(0);
9f0f352d 409 d->ram->update_surface = 0;
329f97fc 410 d->ram->monitors_config = 0;
a19cbfb3
GH		 411 SPICE_RING_INIT(&d->ram->cmd_ring);
412 SPICE_RING_INIT(&d->ram->cursor_ring);
413 SPICE_RING_INIT(&d->ram->release_ring);
0b81c478
AL		 414 SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item);
415 assert(item);
a19cbfb3
GH		 416 *item = 0;
417 qxl_ring_set_dirty(d);
418}
419
420/* can be called from spice server thread context */
b1950430 421static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
a19cbfb3 422{
fd4aa979 423 memory_region_set_dirty(mr, addr, end - addr);
a19cbfb3
GH		 424}
425
426static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
427{
b1950430 428 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
a19cbfb3
GH		 429}
430
431/* called from spice server thread context only */
432static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
433{
a19cbfb3
GH		 434 void *base = qxl->vga.vram_ptr;
435 intptr_t offset;
436
437 offset = ptr - base;
a19cbfb3 438 assert(offset < qxl->vga.vram_size);
b0297b4a 439 qxl_set_dirty(&qxl->vga.vram, offset, offset + 3);
a19cbfb3
GH		 440}
441
442/* can be called from spice server thread context */
443static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
444{
b1950430
AK		 445 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
446 ram_addr_t end = qxl->vga.vram_size;
447 qxl_set_dirty(&qxl->vga.vram, addr, end);
a19cbfb3
GH		 448}
449
450/*
451 * keep track of some command state, for savevm/loadvm.
452 * called from spice server thread context only
453 */
fae2afb1 454static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
a19cbfb3
GH		 455{
456 switch (le32_to_cpu(ext->cmd.type)) {
457 case QXL_CMD_SURFACE:
458 {
459 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
fae2afb1
AL		 460
461 if (!cmd) {
462 return 1;
463 }
a19cbfb3 464 uint32_t id = le32_to_cpu(cmd->surface_id);
47eddfbf 465
ddd8fdc7 466 if (id >= qxl->ssd.num_surfaces) {
0a530548 467 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id,
ddd8fdc7 468 qxl->ssd.num_surfaces);
47eddfbf
AL		 469 return 1;
470 }
48f4ba67
AL		 471 if (cmd->type == QXL_SURFACE_CMD_CREATE &&
472 (cmd->u.surface_create.stride & 0x03) != 0) {
473 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
474 cmd->u.surface_create.stride);
475 return 1;
476 }
14898cf6 477 qemu_mutex_lock(&qxl->track_lock);
a19cbfb3
GH		 478 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
479 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
480 qxl->guest_surfaces.count++;
481 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
482 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
483 }
484 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
485 qxl->guest_surfaces.cmds[id] = 0;
486 qxl->guest_surfaces.count--;
487 }
14898cf6 488 qemu_mutex_unlock(&qxl->track_lock);
a19cbfb3
GH		 489 break;
490 }
491 case QXL_CMD_CURSOR:
492 {
493 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
fae2afb1
AL		 494
495 if (!cmd) {
496 return 1;
497 }
a19cbfb3 498 if (cmd->type == QXL_CURSOR_SET) {
30f6da66 499 qemu_mutex_lock(&qxl->track_lock);
a19cbfb3 500 qxl->guest_cursor = ext->cmd.data;
30f6da66 501 qemu_mutex_unlock(&qxl->track_lock);
a19cbfb3 502 }
dbb5fb8d
GH		 503 if (cmd->type == QXL_CURSOR_HIDE) {
504 qemu_mutex_lock(&qxl->track_lock);
505 qxl->guest_cursor = 0;
506 qemu_mutex_unlock(&qxl->track_lock);
507 }
a19cbfb3
GH		 508 break;
509 }
510 }
fae2afb1 511 return 0;
a19cbfb3
GH		 512}
513
514/* spice display interface callbacks */
515
516static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
517{
518 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
519
c480bb7d 520 trace_qxl_interface_attach_worker(qxl->id);
a19cbfb3
GH		 521 qxl->ssd.worker = qxl_worker;
522}
523
524static void interface_set_compression_level(QXLInstance *sin, int level)
525{
526 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
527
c480bb7d 528 trace_qxl_interface_set_compression_level(qxl->id, level);
a19cbfb3
GH		 529 qxl->shadow_rom.compression_level = cpu_to_le32(level);
530 qxl->rom->compression_level = cpu_to_le32(level);
531 qxl_rom_set_dirty(qxl);
532}
533
015e02f8 534#if SPICE_NEEDS_SET_MM_TIME
a19cbfb3
GH		 535static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
536{
537 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
538
641381c1
GH		 539 if (!qemu_spice_display_is_running(&qxl->ssd)) {
540 return;
541 }
542
c480bb7d 543 trace_qxl_interface_set_mm_time(qxl->id, mm_time);
a19cbfb3
GH		 544 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
545 qxl->rom->mm_clock = cpu_to_le32(mm_time);
546 qxl_rom_set_dirty(qxl);
547}
015e02f8 548#endif
a19cbfb3
GH		 549
550static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
551{
552 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
553
c480bb7d 554 trace_qxl_interface_get_init_info(qxl->id);
a19cbfb3
GH		 555 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
556 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
557 info->num_memslots = NUM_MEMSLOTS;
558 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
559 info->internal_groupslot_id = 0;
9efc2d8d
GH		 560 info->qxl_ram_size =
561 le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS;
ddd8fdc7 562 info->n_surfaces = qxl->ssd.num_surfaces;
a19cbfb3
GH		 563}
564
5b77870c
AL		 565static const char *qxl_mode_to_string(int mode)
566{
567 switch (mode) {
568 case QXL_MODE_COMPAT:
569 return "compat";
570 case QXL_MODE_NATIVE:
571 return "native";
572 case QXL_MODE_UNDEFINED:
573 return "undefined";
574 case QXL_MODE_VGA:
575 return "vga";
576 }
577 return "INVALID";
578}
579
8b92e298
AL		 580static const char *io_port_to_string(uint32_t io_port)
581{
582 if (io_port >= QXL_IO_RANGE_SIZE) {
583 return "out of range";
584 }
585 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
586 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
587 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
588 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
589 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
590 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
591 [QXL_IO_RESET] = "QXL_IO_RESET",
592 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
593 [QXL_IO_LOG] = "QXL_IO_LOG",
594 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
595 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
596 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
597 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
598 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
599 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
600 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
601 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
8b92e298
AL		 602 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
603 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
604 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
605 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
606 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
607 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
608 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
609 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
610 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
020af1c4 611 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC",
8b92e298
AL		 612 };
613 return io_port_to_string[io_port];
614}
615
a19cbfb3
GH		 616/* called from spice server thread context only */
617static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
618{
619 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
620 SimpleSpiceUpdate *update;
621 QXLCommandRing *ring;
622 QXLCommand *cmd;
e0c64d08 623 int notify, ret;
a19cbfb3 624
c480bb7d
AL		 625 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
626
a19cbfb3
GH		 627 switch (qxl->mode) {
628 case QXL_MODE_VGA:
e0c64d08
GH		 629 ret = false;
630 qemu_mutex_lock(&qxl->ssd.lock);
b1af98ba
GH		 631 update = QTAILQ_FIRST(&qxl->ssd.updates);
632 if (update != NULL) {
633 QTAILQ_REMOVE(&qxl->ssd.updates, update, next);
e0c64d08
GH		 634 *ext = update->ext;
635 ret = true;
a19cbfb3 636 }
e0c64d08 637 qemu_mutex_unlock(&qxl->ssd.lock);
212496c9 638 if (ret) {
c480bb7d 639 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
212496c9
AL		 640 qxl_log_command(qxl, "vga", ext);
641 }
e0c64d08 642 return ret;
a19cbfb3
GH		 643 case QXL_MODE_COMPAT:
644 case QXL_MODE_NATIVE:
645 case QXL_MODE_UNDEFINED:
a19cbfb3 646 ring = &qxl->ram->cmd_ring;
087e6a42 647 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) {
a19cbfb3
GH		 648 return false;
649 }
0b81c478
AL		 650 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
651 if (!cmd) {
652 return false;
653 }
a19cbfb3
GH		 654 ext->cmd = *cmd;
655 ext->group_id = MEMSLOT_GROUP_GUEST;
656 ext->flags = qxl->cmdflags;
657 SPICE_RING_POP(ring, notify);
658 qxl_ring_set_dirty(qxl);
659 if (notify) {
660 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
661 }
662 qxl->guest_primary.commands++;
663 qxl_track_command(qxl, ext);
664 qxl_log_command(qxl, "cmd", ext);
86dbcdd9
GH		 665 {
666 /*
667 * Windows 8 drivers place qxl commands in the vram
668 * (instead of the ram) bar. We can't live migrate such a
669 * guest, so add a migration blocker in case we detect
670 * this, to avoid triggering the assert in pre_save().
671 *
672 * https://cgit.freedesktop.org/spice/win32/qxl-wddm-dod/commit/?id=f6e099db39e7d0787f294d5fd0dce328b5210faa
673 */
674 void *msg = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
675 if (msg != NULL && (
676 msg < (void *)qxl->vga.vram_ptr ||
677 msg > ((void *)qxl->vga.vram_ptr + qxl->vga.vram_size))) {
678 if (!qxl->migration_blocker) {
679 Error *local_err = NULL;
680 error_setg(&qxl->migration_blocker,
681 "qxl: guest bug: command not in ram bar");
682 migrate_add_blocker(qxl->migration_blocker, &local_err);
683 if (local_err) {
684 error_report_err(local_err);
685 }
686 }
687 }
688 }
0b81c478 689 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
a19cbfb3
GH		 690 return true;
691 default:
692 return false;
693 }
694}
695
696/* called from spice server thread context only */
697static int interface_req_cmd_notification(QXLInstance *sin)
698{
699 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
700 int wait = 1;
701
c480bb7d 702 trace_qxl_ring_command_req_notification(qxl->id);
a19cbfb3
GH		 703 switch (qxl->mode) {
704 case QXL_MODE_COMPAT:
705 case QXL_MODE_NATIVE:
706 case QXL_MODE_UNDEFINED:
707 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
708 qxl_ring_set_dirty(qxl);
709 break;
710 default:
711 /* nothing */
712 break;
713 }
714 return wait;
715}
716
717/* called from spice server thread context only */
718static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
719{
720 QXLReleaseRing *ring = &d->ram->release_ring;
721 uint64_t *item;
722 int notify;
723
724#define QXL_FREE_BUNCH_SIZE 32
725
726 if (ring->prod - ring->cons + 1 == ring->num_items) {
727 /* ring full -- can't push */
728 return;
729 }
730 if (!flush && d->oom_running) {
731 /* collect everything from oom handler before pushing */
732 return;
733 }
734 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
735 /* collect a bit more before pushing */
736 return;
737 }
738
739 SPICE_RING_PUSH(ring, notify);
c480bb7d
AL		 740 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
741 d->guest_surfaces.count, d->num_free_res,
742 d->last_release, notify ? "yes" : "no");
743 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
744 ring->num_items, ring->prod, ring->cons);
a19cbfb3
GH		 745 if (notify) {
746 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
747 }
0b81c478
AL		 748 SPICE_RING_PROD_ITEM(d, ring, item);
749 if (!item) {
750 return;
751 }
a19cbfb3
GH		 752 *item = 0;
753 d->num_free_res = 0;
754 d->last_release = NULL;
755 qxl_ring_set_dirty(d);
756}
757
758/* called from spice server thread context only */
759static void interface_release_resource(QXLInstance *sin,
c9f88ce3 760 QXLReleaseInfoExt ext)
a19cbfb3
GH		 761{
762 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
763 QXLReleaseRing *ring;
764 uint64_t *item, id;
765
766 if (ext.group_id == MEMSLOT_GROUP_HOST) {
767 /* host group -> vga mode update request */
e8e23b7d 768 QXLCommandExt *cmdext = (void *)(intptr_t)(ext.info->id);
5643fc01
GH		 769 SimpleSpiceUpdate *update;
770 g_assert(cmdext->cmd.type == QXL_CMD_DRAW);
771 update = container_of(cmdext, SimpleSpiceUpdate, ext);
772 qemu_spice_destroy_update(&qxl->ssd, update);
a19cbfb3
GH		 773 return;
774 }
775
776 /*
777 * ext->info points into guest-visible memory
778 * pci bar 0, $command.release_info
779 */
780 ring = &qxl->ram->release_ring;
0b81c478
AL		 781 SPICE_RING_PROD_ITEM(qxl, ring, item);
782 if (!item) {
783 return;
784 }
a19cbfb3
GH		 785 if (*item == 0) {
786 /* stick head into the ring */
787 id = ext.info->id;
788 ext.info->next = 0;
789 qxl_ram_set_dirty(qxl, &ext.info->next);
790 *item = id;
791 qxl_ring_set_dirty(qxl);
792 } else {
793 /* append item to the list */
794 qxl->last_release->next = ext.info->id;
795 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
796 ext.info->next = 0;
797 qxl_ram_set_dirty(qxl, &ext.info->next);
798 }
799 qxl->last_release = ext.info;
800 qxl->num_free_res++;
c480bb7d 801 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
a19cbfb3
GH		 802 qxl_push_free_res(qxl, 0);
803}
804
805/* called from spice server thread context only */
806static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
807{
808 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
809 QXLCursorRing *ring;
810 QXLCommand *cmd;
811 int notify;
812
c480bb7d
AL		 813 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
814
a19cbfb3
GH		 815 switch (qxl->mode) {
816 case QXL_MODE_COMPAT:
817 case QXL_MODE_NATIVE:
818 case QXL_MODE_UNDEFINED:
819 ring = &qxl->ram->cursor_ring;
820 if (SPICE_RING_IS_EMPTY(ring)) {
821 return false;
822 }
0b81c478
AL		 823 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
824 if (!cmd) {
825 return false;
826 }
a19cbfb3
GH		 827 ext->cmd = *cmd;
828 ext->group_id = MEMSLOT_GROUP_GUEST;
829 ext->flags = qxl->cmdflags;
830 SPICE_RING_POP(ring, notify);
831 qxl_ring_set_dirty(qxl);
832 if (notify) {
833 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
834 }
835 qxl->guest_primary.commands++;
836 qxl_track_command(qxl, ext);
837 qxl_log_command(qxl, "csr", ext);
838 if (qxl->id == 0) {
839 qxl_render_cursor(qxl, ext);
840 }
c480bb7d 841 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
a19cbfb3
GH		 842 return true;
843 default:
844 return false;
845 }
846}
847
848/* called from spice server thread context only */
849static int interface_req_cursor_notification(QXLInstance *sin)
850{
851 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
852 int wait = 1;
853
c480bb7d 854 trace_qxl_ring_cursor_req_notification(qxl->id);
a19cbfb3
GH		 855 switch (qxl->mode) {
856 case QXL_MODE_COMPAT:
857 case QXL_MODE_NATIVE:
858 case QXL_MODE_UNDEFINED:
859 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
860 qxl_ring_set_dirty(qxl);
861 break;
862 default:
863 /* nothing */
864 break;
865 }
866 return wait;
867}
868
869/* called from spice server thread context */
870static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
871{
baeae407
AL		 872 /*
873 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
874 * use by xf86-video-qxl and is defined out in the qxl windows driver.
875 * Probably was at some earlier version that is prior to git start (2009),
876 * and is still guest trigerrable.
877 */
878 fprintf(stderr, "%s: deprecated\n", __func__);
a19cbfb3
GH		 879}
880
881/* called from spice server thread context only */
882static int interface_flush_resources(QXLInstance *sin)
883{
884 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
885 int ret;
886
a19cbfb3
GH		 887 ret = qxl->num_free_res;
888 if (ret) {
889 qxl_push_free_res(qxl, 1);
890 }
891 return ret;
892}
893
5ff4e36c
AL		 894static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
895
5ff4e36c 896/* called from spice server thread context only */
2e1a98c9 897static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
5ff4e36c 898{
5ff4e36c
AL		 899 uint32_t current_async;
900
901 qemu_mutex_lock(&qxl->async_lock);
902 current_async = qxl->current_async;
903 qxl->current_async = QXL_UNDEFINED_IO;
904 qemu_mutex_unlock(&qxl->async_lock);
905
c480bb7d 906 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
2e1a98c9
AL		 907 if (!cookie) {
908 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
909 return;
910 }
911 if (cookie && current_async != cookie->io) {
912 fprintf(stderr,
2fce7edf
AL		 913 "qxl: %s: error: current_async = %d != %"
914 PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
2e1a98c9 915 }
5ff4e36c 916 switch (current_async) {
81fb6f15
AL		 917 case QXL_IO_MEMSLOT_ADD_ASYNC:
918 case QXL_IO_DESTROY_PRIMARY_ASYNC:
919 case QXL_IO_UPDATE_AREA_ASYNC:
920 case QXL_IO_FLUSH_SURFACES_ASYNC:
020af1c4 921 case QXL_IO_MONITORS_CONFIG_ASYNC:
81fb6f15 922 break;
5ff4e36c
AL		 923 case QXL_IO_CREATE_PRIMARY_ASYNC:
924 qxl_create_guest_primary_complete(qxl);
925 break;
926 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
927 qxl_spice_destroy_surfaces_complete(qxl);
928 break;
929 case QXL_IO_DESTROY_SURFACE_ASYNC:
2e1a98c9 930 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
5ff4e36c 931 break;
81fb6f15
AL		 932 default:
933 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__,
934 current_async);
5ff4e36c
AL		 935 }
936 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
937}
938
81fb6f15
AL		 939/* called from spice server thread context only */
940static void interface_update_area_complete(QXLInstance *sin,
941 uint32_t surface_id,
942 QXLRect *dirty, uint32_t num_updated_rects)
943{
944 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
945 int i;
946 int qxl_i;
947
948 qemu_mutex_lock(&qxl->ssd.lock);
2f5ae772
GH		 949 if (surface_id != 0 || !num_updated_rects ||
950 !qxl->render_update_cookie_num) {
81fb6f15
AL		 951 qemu_mutex_unlock(&qxl->ssd.lock);
952 return;
953 }
c480bb7d
AL		 954 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
955 dirty->right, dirty->top, dirty->bottom);
956 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
81fb6f15
AL		 957 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
958 /*
959 * overflow - treat this as a full update. Not expected to be common.
960 */
c480bb7d
AL		 961 trace_qxl_interface_update_area_complete_overflow(qxl->id,
962 QXL_NUM_DIRTY_RECTS);
81fb6f15
AL		 963 qxl->guest_primary.resized = 1;
964 }
965 if (qxl->guest_primary.resized) {
966 /*
967 * Don't bother copying or scheduling the bh since we will flip
968 * the whole area anyway on completion of the update_area async call
969 */
970 qemu_mutex_unlock(&qxl->ssd.lock);
971 return;
972 }
973 qxl_i = qxl->num_dirty_rects;
974 for (i = 0; i < num_updated_rects; i++) {
975 qxl->dirty[qxl_i++] = dirty[i];
976 }
977 qxl->num_dirty_rects += num_updated_rects;
c480bb7d
AL		 978 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
979 qxl->num_dirty_rects);
81fb6f15
AL		 980 qemu_bh_schedule(qxl->update_area_bh);
981 qemu_mutex_unlock(&qxl->ssd.lock);
982}
983
2e1a98c9
AL		 984/* called from spice server thread context only */
985static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
986{
987 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
5dba0d45 988 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
2e1a98c9
AL		 989
990 switch (cookie->type) {
991 case QXL_COOKIE_TYPE_IO:
992 interface_async_complete_io(qxl, cookie);
81fb6f15
AL		 993 g_free(cookie);
994 break;
995 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
996 qxl_render_update_area_done(qxl, cookie);
2e1a98c9 997 break;
020af1c4
AL		 998 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG:
999 break;
2e1a98c9
AL		 1000 default:
1001 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
1002 __func__, cookie->type);
81fb6f15 1003 g_free(cookie);
2e1a98c9 1004 }
2e1a98c9
AL		 1005}
1006
c10018d6
SSP		 1007/* called from spice server thread context only */
1008static void interface_set_client_capabilities(QXLInstance *sin,
1009 uint8_t client_present,
1010 uint8_t caps[58])
1011{
1012 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1013
e0ac6097
AL		 1014 if (qxl->revision < 4) {
1015 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id,
1016 qxl->revision);
1017 return;
1018 }
1019
ab902981
HG		 1020 if (runstate_check(RUN_STATE_INMIGRATE) ||
1021 runstate_check(RUN_STATE_POSTMIGRATE)) {
1022 return;
1023 }
1024
c10018d6 1025 qxl->shadow_rom.client_present = client_present;
08688af0
MA		 1026 memcpy(qxl->shadow_rom.client_capabilities, caps,
1027 sizeof(qxl->shadow_rom.client_capabilities));
c10018d6 1028 qxl->rom->client_present = client_present;
08688af0
MA		 1029 memcpy(qxl->rom->client_capabilities, caps,
1030 sizeof(qxl->rom->client_capabilities));
c10018d6
SSP		 1031 qxl_rom_set_dirty(qxl);
1032
1033 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT);
1034}
1035
6c756502
CF		 1036static bool qxl_rom_monitors_config_changed(QXLRom *rom,
1037 VDAgentMonitorsConfig *monitors_config,
1038 unsigned int max_outputs)
1039{
1040 int i;
1041 unsigned int monitors_count;
1042
1043 monitors_count = MIN(monitors_config->num_of_monitors, max_outputs);
1044
1045 if (rom->client_monitors_config.count != monitors_count) {
1046 return true;
1047 }
1048
1049 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1050 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1051 QXLURect *rect = &rom->client_monitors_config.heads[i];
1052 /* monitor->depth ignored */
1053 if ((rect->left != monitor->x) ||
1054 (rect->top != monitor->y) ||
1055 (rect->right != monitor->x + monitor->width) ||
1056 (rect->bottom != monitor->y + monitor->height)) {
1057 return true;
1058 }
1059 }
1060
1061 return false;
1062}
1063
a639ab04
AL		 1064/* called from main context only */
1065static int interface_client_monitors_config(QXLInstance *sin,
1066 VDAgentMonitorsConfig *monitors_config)
1067{
1068 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1069 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar);
1070 int i;
567161fd 1071 unsigned max_outputs = ARRAY_SIZE(rom->client_monitors_config.heads);
6c756502 1072 bool config_changed = false;
a639ab04 1073
e0ac6097
AL		 1074 if (qxl->revision < 4) {
1075 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id,
1076 qxl->revision);
1077 return 0;
1078 }
a639ab04
AL		 1079 /*
1080 * Older windows drivers set int_mask to 0 when their ISR is called,
1081 * then later set it to ~0. So it doesn't relate to the actual interrupts
1082 * handled. However, they are old, so clearly they don't support this
1083 * interrupt
1084 */
1085 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 ||
1086 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) {
1087 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id,
1088 qxl->ram->int_mask,
1089 monitors_config);
1090 return 0;
1091 }
1092 if (!monitors_config) {
1093 return 1;
1094 }
567161fd
FZ		 1095
1096#if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
1097 /* limit number of outputs based on setting limit */
1098 if (qxl->max_outputs && qxl->max_outputs <= max_outputs) {
1099 max_outputs = qxl->max_outputs;
1100 }
1101#endif
1102
6c756502
CF		 1103 config_changed = qxl_rom_monitors_config_changed(rom,
1104 monitors_config,
1105 max_outputs);
1106
a639ab04
AL		 1107 memset(&rom->client_monitors_config, 0,
1108 sizeof(rom->client_monitors_config));
1109 rom->client_monitors_config.count = monitors_config->num_of_monitors;
1110 /* monitors_config->flags ignored */
567161fd 1111 if (rom->client_monitors_config.count >= max_outputs) {
a639ab04
AL		 1112 trace_qxl_client_monitors_config_capped(qxl->id,
1113 monitors_config->num_of_monitors,
567161fd
FZ		 1114 max_outputs);
1115 rom->client_monitors_config.count = max_outputs;
a639ab04
AL		 1116 }
1117 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1118 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1119 QXLURect *rect = &rom->client_monitors_config.heads[i];
1120 /* monitor->depth ignored */
1121 rect->left = monitor->x;
1122 rect->top = monitor->y;
1123 rect->right = monitor->x + monitor->width;
1124 rect->bottom = monitor->y + monitor->height;
1125 }
1126 rom->client_monitors_config_crc = qxl_crc32(
1127 (const uint8_t *)&rom->client_monitors_config,
1128 sizeof(rom->client_monitors_config));
1129 trace_qxl_client_monitors_config_crc(qxl->id,
1130 sizeof(rom->client_monitors_config),
1131 rom->client_monitors_config_crc);
1132
1133 trace_qxl_interrupt_client_monitors_config(qxl->id,
1134 rom->client_monitors_config.count,
1135 rom->client_monitors_config.heads);
6c756502
CF		 1136 if (config_changed) {
1137 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG);
1138 }
a639ab04
AL		 1139 return 1;
1140}
a639ab04 1141
a19cbfb3
GH		 1142static const QXLInterface qxl_interface = {
1143 .base.type = SPICE_INTERFACE_QXL,
1144 .base.description = "qxl gpu",
1145 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
1146 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
1147
1148 .attache_worker = interface_attach_worker,
1149 .set_compression_level = interface_set_compression_level,
015e02f8 1150#if SPICE_NEEDS_SET_MM_TIME
a19cbfb3 1151 .set_mm_time = interface_set_mm_time,
015e02f8 1152#endif
a19cbfb3
GH		 1153 .get_init_info = interface_get_init_info,
1154
1155 /* the callbacks below are called from spice server thread context */
1156 .get_command = interface_get_command,
1157 .req_cmd_notification = interface_req_cmd_notification,
1158 .release_resource = interface_release_resource,
1159 .get_cursor_command = interface_get_cursor_command,
1160 .req_cursor_notification = interface_req_cursor_notification,
1161 .notify_update = interface_notify_update,
1162 .flush_resources = interface_flush_resources,
5ff4e36c 1163 .async_complete = interface_async_complete,
81fb6f15 1164 .update_area_complete = interface_update_area_complete,
c10018d6 1165 .set_client_capabilities = interface_set_client_capabilities,
a639ab04 1166 .client_monitors_config = interface_client_monitors_config,
a19cbfb3
GH		 1167};
1168
15162335
GH		 1169static const GraphicHwOps qxl_ops = {
1170 .gfx_update = qxl_hw_update,
1171};
1172
a19cbfb3
GH		 1173static void qxl_enter_vga_mode(PCIQXLDevice *d)
1174{
1175 if (d->mode == QXL_MODE_VGA) {
1176 return;
1177 }
c480bb7d 1178 trace_qxl_enter_vga_mode(d->id);
0a2b5e3a
HG		 1179#if SPICE_SERVER_VERSION >= 0x000c03 /* release 0.12.3 */
1180 spice_qxl_driver_unload(&d->ssd.qxl);
1181#endif
15162335 1182 graphic_console_set_hwops(d->ssd.dcl.con, d->vga.hw_ops, &d->vga);
3dcadce5 1183 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_DEFAULT);
a19cbfb3
GH		 1184 qemu_spice_create_host_primary(&d->ssd);
1185 d->mode = QXL_MODE_VGA;
a703d3ae 1186 qemu_spice_display_switch(&d->ssd, d->ssd.ds);
0f7bfd81 1187 vga_dirty_log_start(&d->vga);
1dbfa005 1188 graphic_hw_update(d->vga.con);
a19cbfb3
GH		 1189}
1190
1191static void qxl_exit_vga_mode(PCIQXLDevice *d)
1192{
1193 if (d->mode != QXL_MODE_VGA) {
1194 return;
1195 }
c480bb7d 1196 trace_qxl_exit_vga_mode(d->id);
15162335 1197 graphic_console_set_hwops(d->ssd.dcl.con, &qxl_ops, d);
3dcadce5 1198 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_IDLE);
0f7bfd81 1199 vga_dirty_log_stop(&d->vga);
5ff4e36c 1200 qxl_destroy_primary(d, QXL_SYNC);
a19cbfb3
GH		 1201}
1202
40010aea 1203static void qxl_update_irq(PCIQXLDevice *d)
a19cbfb3
GH		 1204{
1205 uint32_t pending = le32_to_cpu(d->ram->int_pending);
1206 uint32_t mask = le32_to_cpu(d->ram->int_mask);
1207 int level = !!(pending & mask);
9e64f8a3 1208 pci_set_irq(&d->pci, level);
a19cbfb3
GH		 1209 qxl_ring_set_dirty(d);
1210}
1211
a19cbfb3
GH		 1212static void qxl_check_state(PCIQXLDevice *d)
1213{
1214 QXLRam *ram = d->ram;
71d388d4 1215 int spice_display_running = qemu_spice_display_is_running(&d->ssd);
a19cbfb3 1216
71d388d4
YH		 1217 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
1218 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
a19cbfb3
GH		 1219}
1220
1221static void qxl_reset_state(PCIQXLDevice *d)
1222{
a19cbfb3
GH		 1223 QXLRom *rom = d->rom;
1224
be48e995 1225 qxl_check_state(d);
a19cbfb3
GH		 1226 d->shadow_rom.update_id = cpu_to_le32(0);
1227 *rom = d->shadow_rom;
1228 qxl_rom_set_dirty(d);
1229 init_qxl_ram(d);
1230 d->num_free_res = 0;
1231 d->last_release = NULL;
1232 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
f06b8521 1233 qxl_update_irq(d);
a19cbfb3
GH		 1234}
1235
1236static void qxl_soft_reset(PCIQXLDevice *d)
1237{
c480bb7d 1238 trace_qxl_soft_reset(d->id);
a19cbfb3 1239 qxl_check_state(d);
087e6a42 1240 qxl_clear_guest_bug(d);
05fa1c74 1241 qemu_mutex_lock(&d->async_lock);
a5f68c22 1242 d->current_async = QXL_UNDEFINED_IO;
05fa1c74 1243 qemu_mutex_unlock(&d->async_lock);
a19cbfb3
GH		 1244
1245 if (d->id == 0) {
1246 qxl_enter_vga_mode(d);
1247 } else {
1248 d->mode = QXL_MODE_UNDEFINED;
1249 }
1250}
1251
1252static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
1253{
75c70e37
GH		 1254 bool startstop = qemu_spice_display_is_running(&d->ssd);
1255
c480bb7d 1256 trace_qxl_hard_reset(d->id, loadvm);
a19cbfb3 1257
75c70e37
GH		 1258 if (startstop) {
1259 qemu_spice_display_stop();
1260 }
1261
aee32bf3
GH		 1262 qxl_spice_reset_cursor(d);
1263 qxl_spice_reset_image_cache(d);
a19cbfb3
GH		 1264 qxl_reset_surfaces(d);
1265 qxl_reset_memslots(d);
1266
1267 /* pre loadvm reset must not touch QXLRam. This lives in
1268 * device memory, is migrated together with RAM and thus
1269 * already loaded at this point */
1270 if (!loadvm) {
1271 qxl_reset_state(d);
1272 }
1273 qemu_spice_create_host_memslot(&d->ssd);
1274 qxl_soft_reset(d);
75c70e37 1275
86dbcdd9
GH		 1276 if (d->migration_blocker) {
1277 migrate_del_blocker(d->migration_blocker);
1278 error_free(d->migration_blocker);
1279 d->migration_blocker = NULL;
1280 }
1281
75c70e37
GH		 1282 if (startstop) {
1283 qemu_spice_display_start();
1284 }
a19cbfb3
GH		 1285}
1286
1287static void qxl_reset_handler(DeviceState *dev)
1288{
c69f6c7d 1289 PCIQXLDevice *d = PCI_QXL(PCI_DEVICE(dev));
c480bb7d 1290
a19cbfb3
GH		 1291 qxl_hard_reset(d, 0);
1292}
1293
1294static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1295{
1296 VGACommonState *vga = opaque;
1297 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
1298
c480bb7d 1299 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
a19cbfb3 1300 if (qxl->mode != QXL_MODE_VGA) {
5ff4e36c 1301 qxl_destroy_primary(qxl, QXL_SYNC);
a19cbfb3
GH		 1302 qxl_soft_reset(qxl);
1303 }
1304 vga_ioport_write(opaque, addr, val);
1305}
1306
f67ab77a
GH		 1307static const MemoryRegionPortio qxl_vga_portio_list[] = {
1308 { 0x04, 2, 1, .read = vga_ioport_read,
1309 .write = qxl_vga_ioport_write }, /* 3b4 */
1310 { 0x0a, 1, 1, .read = vga_ioport_read,
1311 .write = qxl_vga_ioport_write }, /* 3ba */
1312 { 0x10, 16, 1, .read = vga_ioport_read,
1313 .write = qxl_vga_ioport_write }, /* 3c0 */
1314 { 0x24, 2, 1, .read = vga_ioport_read,
1315 .write = qxl_vga_ioport_write }, /* 3d4 */
1316 { 0x2a, 1, 1, .read = vga_ioport_read,
1317 .write = qxl_vga_ioport_write }, /* 3da */
1318 PORTIO_END_OF_LIST(),
1319};
1320
e954ea28
AL		 1321static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
1322 qxl_async_io async)
a19cbfb3
GH		 1323{
1324 static const int regions[] = {
1325 QXL_RAM_RANGE_INDEX,
1326 QXL_VRAM_RANGE_INDEX,
6f2b175a 1327 QXL_VRAM64_RANGE_INDEX,
a19cbfb3
GH		 1328 };
1329 uint64_t guest_start;
1330 uint64_t guest_end;
1331 int pci_region;
1332 pcibus_t pci_start;
1333 pcibus_t pci_end;
3cb5158f 1334 MemoryRegion *mr;
a19cbfb3
GH		 1335 intptr_t virt_start;
1336 QXLDevMemSlot memslot;
1337 int i;
1338
1339 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1340 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1341
c480bb7d 1342 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
a19cbfb3 1343
e954ea28 1344 if (slot_id >= NUM_MEMSLOTS) {
0a530548 1345 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
e954ea28
AL		 1346 slot_id, NUM_MEMSLOTS);
1347 return 1;
1348 }
1349 if (guest_start > guest_end) {
0a530548 1350 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64
e954ea28
AL		 1351 " > 0x%" PRIx64, __func__, guest_start, guest_end);
1352 return 1;
1353 }
a19cbfb3
GH		 1354
1355 for (i = 0; i < ARRAY_SIZE(regions); i++) {
1356 pci_region = regions[i];
1357 pci_start = d->pci.io_regions[pci_region].addr;
1358 pci_end = pci_start + d->pci.io_regions[pci_region].size;
1359 /* mapped? */
1360 if (pci_start == -1) {
1361 continue;
1362 }
1363 /* start address in range ? */
1364 if (guest_start < pci_start || guest_start > pci_end) {
1365 continue;
1366 }
1367 /* end address in range ? */
1368 if (guest_end > pci_end) {
1369 continue;
1370 }
1371 /* passed */
1372 break;
1373 }
e954ea28 1374 if (i == ARRAY_SIZE(regions)) {
0a530548 1375 qxl_set_guest_bug(d, "%s: finished loop without match", __func__);
e954ea28
AL		 1376 return 1;
1377 }
a19cbfb3
GH		 1378
1379 switch (pci_region) {
1380 case QXL_RAM_RANGE_INDEX:
3cb5158f 1381 mr = &d->vga.vram;
a19cbfb3
GH		 1382 break;
1383 case QXL_VRAM_RANGE_INDEX:
6f2b175a 1384 case 4 /* vram 64bit */:
3cb5158f 1385 mr = &d->vram_bar;
a19cbfb3
GH		 1386 break;
1387 default:
1388 /* should not happen */
0a530548 1389 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
e954ea28 1390 return 1;
a19cbfb3
GH		 1391 }
1392
3cb5158f 1393 virt_start = (intptr_t)memory_region_get_ram_ptr(mr);
a19cbfb3
GH		 1394 memslot.slot_id = slot_id;
1395 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
1396 memslot.virt_start = virt_start + (guest_start - pci_start);
1397 memslot.virt_end = virt_start + (guest_end - pci_start);
1398 memslot.addr_delta = memslot.virt_start - delta;
1399 memslot.generation = d->rom->slot_generation = 0;
1400 qxl_rom_set_dirty(d);
1401
5ff4e36c 1402 qemu_spice_add_memslot(&d->ssd, &memslot, async);
3cb5158f
GH		 1403 d->guest_slots[slot_id].mr = mr;
1404 d->guest_slots[slot_id].offset = memslot.virt_start - virt_start;
a19cbfb3
GH		 1405 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1406 d->guest_slots[slot_id].delta = delta;
1407 d->guest_slots[slot_id].active = 1;
e954ea28 1408 return 0;
a19cbfb3
GH		 1409}
1410
1411static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1412{
5c59d118 1413 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
a19cbfb3
GH		 1414 d->guest_slots[slot_id].active = 0;
1415}
1416
1417static void qxl_reset_memslots(PCIQXLDevice *d)
1418{
aee32bf3 1419 qxl_spice_reset_memslots(d);
a19cbfb3
GH		 1420 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1421}
1422
1423static void qxl_reset_surfaces(PCIQXLDevice *d)
1424{
c480bb7d 1425 trace_qxl_reset_surfaces(d->id);
a19cbfb3 1426 d->mode = QXL_MODE_UNDEFINED;
5ff4e36c 1427 qxl_spice_destroy_surfaces(d, QXL_SYNC);
a19cbfb3
GH		 1428}
1429
e25139b3 1430/* can be also called from spice server thread context */
726bdf65
GH		 1431static bool qxl_get_check_slot_offset(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
1432 uint32_t *s, uint64_t *o)
a19cbfb3
GH		 1433{
1434 uint64_t phys = le64_to_cpu(pqxl);
1435 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1436 uint64_t offset = phys & 0xffffffffffff;
1437
726bdf65
GH		 1438 if (slot >= NUM_MEMSLOTS) {
1439 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
1440 NUM_MEMSLOTS);
1441 return false;
1442 }
1443 if (!qxl->guest_slots[slot].active) {
1444 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
1445 return false;
1446 }
1447 if (offset < qxl->guest_slots[slot].delta) {
1448 qxl_set_guest_bug(qxl,
0a530548 1449 "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
4b635c59 1450 slot, offset, qxl->guest_slots[slot].delta);
726bdf65
GH		 1451 return false;
1452 }
1453 offset -= qxl->guest_slots[slot].delta;
1454 if (offset > qxl->guest_slots[slot].size) {
1455 qxl_set_guest_bug(qxl,
0a530548 1456 "slot %d offset %"PRIu64" > size %"PRIu64"\n",
4b635c59 1457 slot, offset, qxl->guest_slots[slot].size);
726bdf65
GH		 1458 return false;
1459 }
1460
1461 *s = slot;
1462 *o = offset;
1463 return true;
1464}
1465
1466/* can be also called from spice server thread context */
1467void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1468{
1469 uint64_t offset;
1470 uint32_t slot;
3cb5158f 1471 void *ptr;
726bdf65
GH		 1472
1473 switch (group_id) {
1474 case MEMSLOT_GROUP_HOST:
1475 offset = le64_to_cpu(pqxl) & 0xffffffffffff;
1476 return (void *)(intptr_t)offset;
1477 case MEMSLOT_GROUP_GUEST:
1478 if (!qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset)) {
4b635c59
AL		 1479 return NULL;
1480 }
3cb5158f
GH		 1481 ptr = memory_region_get_ram_ptr(qxl->guest_slots[slot].mr);
1482 ptr += qxl->guest_slots[slot].offset;
1483 ptr += offset;
1484 return ptr;
a19cbfb3 1485 }
4b635c59 1486 return NULL;
a19cbfb3
GH		 1487}
1488
5ff4e36c
AL		 1489static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1490{
1491 /* for local rendering */
1492 qxl_render_resize(qxl);
1493}
1494
1495static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1496 qxl_async_io async)
a19cbfb3
GH		 1497{
1498 QXLDevSurfaceCreate surface;
1499 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
3761abb1 1500 uint32_t requested_height = le32_to_cpu(sc->height);
13d1fd44
AL		 1501 int requested_stride = le32_to_cpu(sc->stride);
1502
3761abb1
AL		 1503 if (requested_stride == INT32_MIN ||
1504 abs(requested_stride) * (uint64_t)requested_height
1505 > qxl->vgamem_size) {
1506 qxl_set_guest_bug(qxl, "%s: requested primary larger than framebuffer"
1507 " stride %d x height %" PRIu32 " > %" PRIu32,
1508 __func__, requested_stride, requested_height,
1509 qxl->vgamem_size);
13d1fd44
AL		 1510 return;
1511 }
a19cbfb3 1512
ddf9f4b7 1513 if (qxl->mode == QXL_MODE_NATIVE) {
0a530548 1514 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
ddf9f4b7
AL		 1515 __func__);
1516 }
a19cbfb3
GH		 1517 qxl_exit_vga_mode(qxl);
1518
a19cbfb3
GH		 1519 surface.format = le32_to_cpu(sc->format);
1520 surface.height = le32_to_cpu(sc->height);
1521 surface.mem = le64_to_cpu(sc->mem);
1522 surface.position = le32_to_cpu(sc->position);
1523 surface.stride = le32_to_cpu(sc->stride);
1524 surface.width = le32_to_cpu(sc->width);
1525 surface.type = le32_to_cpu(sc->type);
1526 surface.flags = le32_to_cpu(sc->flags);
c480bb7d
AL		 1527 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1528 sc->format, sc->position);
1529 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1530 sc->flags);
a19cbfb3 1531
48f4ba67
AL		 1532 if ((surface.stride & 0x3) != 0) {
1533 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0",
1534 surface.stride);
1535 return;
1536 }
1537
a19cbfb3
GH		 1538 surface.mouse_mode = true;
1539 surface.group_id = MEMSLOT_GROUP_GUEST;
1540 if (loadvm) {
1541 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1542 }
1543
1544 qxl->mode = QXL_MODE_NATIVE;
1545 qxl->cmdflags = 0;
5ff4e36c 1546 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
a19cbfb3 1547
5ff4e36c
AL		 1548 if (async == QXL_SYNC) {
1549 qxl_create_guest_primary_complete(qxl);
1550 }
a19cbfb3
GH		 1551}
1552
5ff4e36c
AL		 1553/* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1554 * done (in QXL_SYNC case), 0 otherwise. */
1555static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
a19cbfb3
GH		 1556{
1557 if (d->mode == QXL_MODE_UNDEFINED) {
5ff4e36c 1558 return 0;
a19cbfb3 1559 }
c480bb7d 1560 trace_qxl_destroy_primary(d->id);
a19cbfb3 1561 d->mode = QXL_MODE_UNDEFINED;
5ff4e36c 1562 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
30f6da66 1563 qxl_spice_reset_cursor(d);
5ff4e36c 1564 return 1;
a19cbfb3
GH		 1565}
1566
9c70434f 1567static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm)
a19cbfb3
GH		 1568{
1569 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1570 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1571 QXLMode *mode = d->modes->modes + modenr;
1572 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1573 QXLMemSlot slot = {
1574 .mem_start = start,
1575 .mem_end = end
1576 };
9c70434f
GH		 1577
1578 if (modenr >= d->modes->n_modes) {
1579 qxl_set_guest_bug(d, "mode number out of range");
1580 return;
1581 }
1582
a19cbfb3
GH		 1583 QXLSurfaceCreate surface = {
1584 .width = mode->x_res,
1585 .height = mode->y_res,
1586 .stride = -mode->x_res * 4,
1587 .format = SPICE_SURFACE_FMT_32_xRGB,
1588 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1589 .mouse_mode = true,
1590 .mem = devmem + d->shadow_rom.draw_area_offset,
1591 };
1592
c480bb7d
AL		 1593 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1594 devmem);
a19cbfb3
GH		 1595 if (!loadvm) {
1596 qxl_hard_reset(d, 0);
1597 }
1598
1599 d->guest_slots[0].slot = slot;
e954ea28 1600 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0);
a19cbfb3
GH		 1601
1602 d->guest_primary.surface = surface;
5ff4e36c 1603 qxl_create_guest_primary(d, 0, QXL_SYNC);
a19cbfb3
GH		 1604
1605 d->mode = QXL_MODE_COMPAT;
1606 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
a19cbfb3
GH		 1607 if (mode->bits == 16) {
1608 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1609 }
a19cbfb3
GH		 1610 d->shadow_rom.mode = cpu_to_le32(modenr);
1611 d->rom->mode = cpu_to_le32(modenr);
1612 qxl_rom_set_dirty(d);
1613}
1614
a8170e5e 1615static void ioport_write(void *opaque, hwaddr addr,
b1950430 1616 uint64_t val, unsigned size)
a19cbfb3
GH		 1617{
1618 PCIQXLDevice *d = opaque;
b1950430 1619 uint32_t io_port = addr;
5ff4e36c 1620 qxl_async_io async = QXL_SYNC;
5ff4e36c 1621 uint32_t orig_io_port = io_port;
a19cbfb3 1622
d96aafca 1623 if (d->guest_bug && io_port != QXL_IO_RESET) {
087e6a42
AL		 1624 return;
1625 }
1626
020af1c4 1627 if (d->revision <= QXL_REVISION_STABLE_V10 &&
ffe01e59 1628 io_port > QXL_IO_FLUSH_RELEASE) {
020af1c4
AL		 1629 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n",
1630 io_port, d->revision);
1631 return;
1632 }
1633
a19cbfb3
GH		 1634 switch (io_port) {
1635 case QXL_IO_RESET:
1636 case QXL_IO_SET_MODE:
1637 case QXL_IO_MEMSLOT_ADD:
1638 case QXL_IO_MEMSLOT_DEL:
1639 case QXL_IO_CREATE_PRIMARY:
81144d1a 1640 case QXL_IO_UPDATE_IRQ:
a3d14054 1641 case QXL_IO_LOG:
5ff4e36c
AL		 1642 case QXL_IO_MEMSLOT_ADD_ASYNC:
1643 case QXL_IO_CREATE_PRIMARY_ASYNC:
a19cbfb3
GH		 1644 break;
1645 default:
e21a298a 1646 if (d->mode != QXL_MODE_VGA) {
a19cbfb3 1647 break;
e21a298a 1648 }
c480bb7d 1649 trace_qxl_io_unexpected_vga_mode(d->id,
917ae08c 1650 addr, val, io_port_to_string(io_port));
5ff4e36c
AL		 1651 /* be nice to buggy guest drivers */
1652 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
020af1c4 1653 io_port < QXL_IO_RANGE_SIZE) {
5ff4e36c
AL		 1654 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1655 }
a19cbfb3
GH		 1656 return;
1657 }
1658
5ff4e36c
AL		 1659 /* we change the io_port to avoid ifdeffery in the main switch */
1660 orig_io_port = io_port;
1661 switch (io_port) {
1662 case QXL_IO_UPDATE_AREA_ASYNC:
1663 io_port = QXL_IO_UPDATE_AREA;
1664 goto async_common;
1665 case QXL_IO_MEMSLOT_ADD_ASYNC:
1666 io_port = QXL_IO_MEMSLOT_ADD;
1667 goto async_common;
1668 case QXL_IO_CREATE_PRIMARY_ASYNC:
1669 io_port = QXL_IO_CREATE_PRIMARY;
1670 goto async_common;
1671 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1672 io_port = QXL_IO_DESTROY_PRIMARY;
1673 goto async_common;
1674 case QXL_IO_DESTROY_SURFACE_ASYNC:
1675 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1676 goto async_common;
1677 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1678 io_port = QXL_IO_DESTROY_ALL_SURFACES;
3e16b9c5
AL		 1679 goto async_common;
1680 case QXL_IO_FLUSH_SURFACES_ASYNC:
020af1c4 1681 case QXL_IO_MONITORS_CONFIG_ASYNC:
5ff4e36c
AL		 1682async_common:
1683 async = QXL_ASYNC;
1684 qemu_mutex_lock(&d->async_lock);
1685 if (d->current_async != QXL_UNDEFINED_IO) {
0a530548 1686 qxl_set_guest_bug(d, "%d async started before last (%d) complete",
5ff4e36c
AL		 1687 io_port, d->current_async);
1688 qemu_mutex_unlock(&d->async_lock);
1689 return;
1690 }
1691 d->current_async = orig_io_port;
1692 qemu_mutex_unlock(&d->async_lock);
5ff4e36c
AL		 1693 break;
1694 default:
1695 break;
1696 }
18b20385
GH		 1697 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode),
1698 addr, io_port_to_string(addr),
1699 val, size, async);
5ff4e36c 1700
a19cbfb3
GH		 1701 switch (io_port) {
1702 case QXL_IO_UPDATE_AREA:
1703 {
81fb6f15 1704 QXLCookie *cookie = NULL;
a19cbfb3 1705 QXLRect update = d->ram->update_area;
81fb6f15 1706
ddd8fdc7 1707 if (d->ram->update_surface > d->ssd.num_surfaces) {
511b13e2
AL		 1708 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1709 d->ram->update_surface);
36a03e0b 1710 break;
511b13e2 1711 }
36a03e0b
MT		 1712 if (update.left >= update.right || update.top >= update.bottom ||
1713 update.left < 0 || update.top < 0) {
511b13e2
AL		 1714 qxl_set_guest_bug(d,
1715 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1716 update.left, update.top, update.right, update.bottom);
9e5a25f1
MAL		 1717 if (update.left == update.right || update.top == update.bottom) {
1718 /* old drivers may provide empty area, keep going */
1719 qxl_clear_guest_bug(d);
1720 goto cancel_async;
1721 }
ccc2960d
DH		 1722 break;
1723 }
81fb6f15
AL		 1724 if (async == QXL_ASYNC) {
1725 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1726 QXL_IO_UPDATE_AREA_ASYNC);
1727 cookie->u.area = update;
1728 }
aee32bf3 1729 qxl_spice_update_area(d, d->ram->update_surface,
81fb6f15
AL		 1730 cookie ? &cookie->u.area : &update,
1731 NULL, 0, 0, async, cookie);
a19cbfb3
GH		 1732 break;
1733 }
1734 case QXL_IO_NOTIFY_CMD:
5c59d118 1735 qemu_spice_wakeup(&d->ssd);
a19cbfb3
GH		 1736 break;
1737 case QXL_IO_NOTIFY_CURSOR:
5c59d118 1738 qemu_spice_wakeup(&d->ssd);
a19cbfb3
GH		 1739 break;
1740 case QXL_IO_UPDATE_IRQ:
40010aea 1741 qxl_update_irq(d);
a19cbfb3
GH		 1742 break;
1743 case QXL_IO_NOTIFY_OOM:
a19cbfb3
GH		 1744 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1745 break;
1746 }
1747 d->oom_running = 1;
aee32bf3 1748 qxl_spice_oom(d);
a19cbfb3
GH		 1749 d->oom_running = 0;
1750 break;
1751 case QXL_IO_SET_MODE:
a19cbfb3
GH		 1752 qxl_set_mode(d, val, 0);
1753 break;
1754 case QXL_IO_LOG:
1a1bc085 1755 trace_qxl_io_log(d->id, d->ram->log_buf);
a19cbfb3 1756 if (d->guestdebug) {
a680f7e7 1757 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
bc72ad67 1758 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), d->ram->log_buf);
a19cbfb3
GH		 1759 }
1760 break;
1761 case QXL_IO_RESET:
a19cbfb3
GH		 1762 qxl_hard_reset(d, 0);
1763 break;
1764 case QXL_IO_MEMSLOT_ADD:
2bce0400 1765 if (val >= NUM_MEMSLOTS) {
0a530548 1766 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
2bce0400
GH		 1767 break;
1768 }
1769 if (d->guest_slots[val].active) {
0a530548
AL		 1770 qxl_set_guest_bug(d,
1771 "QXL_IO_MEMSLOT_ADD: memory slot already active");
2bce0400
GH		 1772 break;
1773 }
a19cbfb3 1774 d->guest_slots[val].slot = d->ram->mem_slot;
5ff4e36c 1775 qxl_add_memslot(d, val, 0, async);
a19cbfb3
GH		 1776 break;
1777 case QXL_IO_MEMSLOT_DEL:
2bce0400 1778 if (val >= NUM_MEMSLOTS) {
0a530548 1779 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
2bce0400
GH		 1780 break;
1781 }
a19cbfb3
GH		 1782 qxl_del_memslot(d, val);
1783 break;
1784 case QXL_IO_CREATE_PRIMARY:
2bce0400 1785 if (val != 0) {
0a530548 1786 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
5ff4e36c
AL		 1787 async);
1788 goto cancel_async;
2bce0400 1789 }
a19cbfb3 1790 d->guest_primary.surface = d->ram->create_surface;
5ff4e36c 1791 qxl_create_guest_primary(d, 0, async);
a19cbfb3
GH		 1792 break;
1793 case QXL_IO_DESTROY_PRIMARY:
2bce0400 1794 if (val != 0) {
0a530548 1795 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
5ff4e36c
AL		 1796 async);
1797 goto cancel_async;
1798 }
5ff4e36c 1799 if (!qxl_destroy_primary(d, async)) {
c480bb7d
AL		 1800 trace_qxl_io_destroy_primary_ignored(d->id,
1801 qxl_mode_to_string(d->mode));
5ff4e36c 1802 goto cancel_async;
2bce0400 1803 }
a19cbfb3
GH		 1804 break;
1805 case QXL_IO_DESTROY_SURFACE_WAIT:
ddd8fdc7 1806 if (val >= d->ssd.num_surfaces) {
0a530548 1807 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
5f8daf2e 1808 "%" PRIu64 " >= NUM_SURFACES", async, val);
5ff4e36c
AL		 1809 goto cancel_async;
1810 }
1811 qxl_spice_destroy_surface_wait(d, val, async);
a19cbfb3 1812 break;
3e16b9c5
AL		 1813 case QXL_IO_FLUSH_RELEASE: {
1814 QXLReleaseRing *ring = &d->ram->release_ring;
1815 if (ring->prod - ring->cons + 1 == ring->num_items) {
1816 fprintf(stderr,
1817 "ERROR: no flush, full release ring [p%d,%dc]\n",
1818 ring->prod, ring->cons);
1819 }
1820 qxl_push_free_res(d, 1 /* flush */);
3e16b9c5
AL		 1821 break;
1822 }
1823 case QXL_IO_FLUSH_SURFACES_ASYNC:
3e16b9c5
AL		 1824 qxl_spice_flush_surfaces_async(d);
1825 break;
a19cbfb3 1826 case QXL_IO_DESTROY_ALL_SURFACES:
5ff4e36c
AL		 1827 d->mode = QXL_MODE_UNDEFINED;
1828 qxl_spice_destroy_surfaces(d, async);
a19cbfb3 1829 break;
020af1c4
AL		 1830 case QXL_IO_MONITORS_CONFIG_ASYNC:
1831 qxl_spice_monitors_config_async(d, 0);
1832 break;
a19cbfb3 1833 default:
0a530548 1834 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
a19cbfb3 1835 }
5ff4e36c
AL		 1836 return;
1837cancel_async:
5ff4e36c
AL		 1838 if (async) {
1839 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1840 qemu_mutex_lock(&d->async_lock);
1841 d->current_async = QXL_UNDEFINED_IO;
1842 qemu_mutex_unlock(&d->async_lock);
1843 }
a19cbfb3
GH		 1844}
1845
a8170e5e 1846static uint64_t ioport_read(void *opaque, hwaddr addr,
b1950430 1847 unsigned size)
a19cbfb3 1848{
917ae08c 1849 PCIQXLDevice *qxl = opaque;
a19cbfb3 1850
917ae08c 1851 trace_qxl_io_read_unexpected(qxl->id);
a19cbfb3
GH		 1852 return 0xff;
1853}
1854
b1950430
AK		 1855static const MemoryRegionOps qxl_io_ops = {
1856 .read = ioport_read,
1857 .write = ioport_write,
1858 .valid = {
1859 .min_access_size = 1,
1860 .max_access_size = 1,
1861 },
1862};
a19cbfb3 1863
4a46c99c 1864static void qxl_update_irq_bh(void *opaque)
a19cbfb3
GH		 1865{
1866 PCIQXLDevice *d = opaque;
40010aea 1867 qxl_update_irq(d);
a19cbfb3
GH		 1868}
1869
a19cbfb3
GH		 1870static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1871{
1872 uint32_t old_pending;
1873 uint32_t le_events = cpu_to_le32(events);
1874
917ae08c 1875 trace_qxl_send_events(d->id, events);
511aefb0
AL		 1876 if (!qemu_spice_display_is_running(&d->ssd)) {
1877 /* spice-server tracks guest running state and should not do this */
1878 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n",
1879 __func__);
1880 trace_qxl_send_events_vm_stopped(d->id, events);
1881 return;
1882 }
5444e768 1883 old_pending = atomic_fetch_or(&d->ram->int_pending, le_events);
a19cbfb3
GH		 1884 if ((old_pending & le_events) == le_events) {
1885 return;
1886 }
4a46c99c 1887 qemu_bh_schedule(d->update_irq);
a19cbfb3
GH		 1888}
1889
1890/* graphics console */
1891
1892static void qxl_hw_update(void *opaque)
1893{
1894 PCIQXLDevice *qxl = opaque;
a19cbfb3 1895
15162335 1896 qxl_render_update(qxl);
a19cbfb3
GH		 1897}
1898
1331eab2
GH		 1899static void qxl_dirty_one_surface(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
1900 uint32_t height, int32_t stride)
1901{
e0127d2e
GH		 1902 uint64_t offset, size;
1903 uint32_t slot;
1331eab2
GH		 1904 bool rc;
1905
1906 rc = qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset);
1907 assert(rc == true);
e0127d2e
GH		 1908 size = (uint64_t)height * abs(stride);
1909 trace_qxl_surfaces_dirty(qxl->id, offset, size);
1331eab2 1910 qxl_set_dirty(qxl->guest_slots[slot].mr,
e0127d2e
GH		 1911 qxl->guest_slots[slot].offset + offset,
1912 qxl->guest_slots[slot].offset + offset + size);
1331eab2
GH		 1913}
1914
e25139b3
YH		 1915static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1916{
e25139b3
YH		 1917 int i;
1918
2aa9e85c 1919 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
e25139b3
YH		 1920 return;
1921 }
1922
1923 /* dirty the primary surface */
1331eab2
GH		 1924 qxl_dirty_one_surface(qxl, qxl->guest_primary.surface.mem,
1925 qxl->guest_primary.surface.height,
1926 qxl->guest_primary.surface.stride);
e25139b3
YH		 1927
1928 /* dirty the off-screen surfaces */
ddd8fdc7 1929 for (i = 0; i < qxl->ssd.num_surfaces; i++) {
e25139b3 1930 QXLSurfaceCmd *cmd;
e25139b3
YH		 1931
1932 if (qxl->guest_surfaces.cmds[i] == 0) {
1933 continue;
1934 }
1935
1936 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1937 MEMSLOT_GROUP_GUEST);
fae2afb1 1938 assert(cmd);
e25139b3 1939 assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1331eab2
GH		 1940 qxl_dirty_one_surface(qxl, cmd->u.surface_create.data,
1941 cmd->u.surface_create.height,
1942 cmd->u.surface_create.stride);
e25139b3
YH		 1943 }
1944}
1945
1dfb4dd9
LC		 1946static void qxl_vm_change_state_handler(void *opaque, int running,
1947 RunState state)
a19cbfb3
GH		 1948{
1949 PCIQXLDevice *qxl = opaque;
a19cbfb3 1950
efbf2950
YH		 1951 if (running) {
1952 /*
1953 * if qxl_send_events was called from spice server context before
40010aea 1954 * migration ended, qxl_update_irq for these events might not have been
efbf2950
YH		 1955 * called
1956 */
40010aea 1957 qxl_update_irq(qxl);
e25139b3
YH		 1958 } else {
1959 /* make sure surfaces are saved before migration */
1960 qxl_dirty_surfaces(qxl);
a19cbfb3
GH		 1961 }
1962}
1963
1964/* display change listener */
1965
7c20b4a3 1966static void display_update(DisplayChangeListener *dcl,
7c20b4a3 1967 int x, int y, int w, int h)
a19cbfb3 1968{
c6c06853
GH		 1969 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1970
1971 if (qxl->mode == QXL_MODE_VGA) {
1972 qemu_spice_display_update(&qxl->ssd, x, y, w, h);
a19cbfb3
GH		 1973 }
1974}
1975
c12aeb86 1976static void display_switch(DisplayChangeListener *dcl,
c12aeb86 1977 struct DisplaySurface *surface)
a19cbfb3 1978{
c6c06853
GH		 1979 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1980
71874c17 1981 qxl->ssd.ds = surface;
c6c06853 1982 if (qxl->mode == QXL_MODE_VGA) {
c12aeb86 1983 qemu_spice_display_switch(&qxl->ssd, surface);
a19cbfb3
GH		 1984 }
1985}
1986
bc2ed970 1987static void display_refresh(DisplayChangeListener *dcl)
a19cbfb3 1988{
c6c06853
GH		 1989 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1990
1991 if (qxl->mode == QXL_MODE_VGA) {
1992 qemu_spice_display_refresh(&qxl->ssd);
a19cbfb3
GH		 1993 }
1994}
1995
7c20b4a3
GH		 1996static DisplayChangeListenerOps display_listener_ops = {
1997 .dpy_name = "spice/qxl",
a93a4a22 1998 .dpy_gfx_update = display_update,
c12aeb86 1999 .dpy_gfx_switch = display_switch,
7c20b4a3 2000 .dpy_refresh = display_refresh,
a19cbfb3
GH		 2001};
2002
13d1fd44 2003static void qxl_init_ramsize(PCIQXLDevice *qxl)
a974192c 2004{
13d1fd44
AL		 2005 /* vga mode framebuffer / primary surface (bar 0, first part) */
2006 if (qxl->vgamem_size_mb < 8) {
2007 qxl->vgamem_size_mb = 8;
2008 }
876d5163
RK		 2009 /* XXX: we round vgamem_size_mb up to a nearest power of two and it must be
2010 * less than vga_common_init()'s maximum on qxl->vga.vram_size (512 now).
2011 */
2012 if (qxl->vgamem_size_mb > 256) {
2013 qxl->vgamem_size_mb = 256;
2014 }
13d1fd44
AL		 2015 qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024;
2016
2017 /* vga ram (bar 0, total) */
017438ee
GH		 2018 if (qxl->ram_size_mb != -1) {
2019 qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024;
2020 }
13d1fd44
AL		 2021 if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
2022 qxl->vga.vram_size = qxl->vgamem_size * 2;
a974192c
GH		 2023 }
2024
6f2b175a
GH		 2025 /* vram32 (surfaces, 32bit, bar 1) */
2026 if (qxl->vram32_size_mb != -1) {
2027 qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024;
2028 }
2029 if (qxl->vram32_size < 4096) {
2030 qxl->vram32_size = 4096;
2031 }
2032
2033 /* vram (surfaces, 64bit, bar 4+5) */
017438ee 2034 if (qxl->vram_size_mb != -1) {
de1b9b85 2035 qxl->vram_size = (uint64_t)qxl->vram_size_mb * 1024 * 1024;
017438ee 2036 }
6f2b175a
GH		 2037 if (qxl->vram_size < qxl->vram32_size) {
2038 qxl->vram_size = qxl->vram32_size;
a974192c 2039 }
6f2b175a 2040
a974192c 2041 if (qxl->revision == 1) {
6f2b175a 2042 qxl->vram32_size = 4096;
a974192c
GH		 2043 qxl->vram_size = 4096;
2044 }
bb7443f6
RK		 2045 qxl->vgamem_size = pow2ceil(qxl->vgamem_size);
2046 qxl->vga.vram_size = pow2ceil(qxl->vga.vram_size);
2047 qxl->vram32_size = pow2ceil(qxl->vram32_size);
2048 qxl->vram_size = pow2ceil(qxl->vram_size);
a974192c
GH		 2049}
2050
042a24db 2051static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp)
a19cbfb3
GH		 2052{
2053 uint8_t* config = qxl->pci.config;
a19cbfb3
GH		 2054 uint32_t pci_device_rev;
2055 uint32_t io_size;
2056
2057 qxl->mode = QXL_MODE_UNDEFINED;
2058 qxl->generation = 1;
2059 qxl->num_memslots = NUM_MEMSLOTS;
14898cf6 2060 qemu_mutex_init(&qxl->track_lock);
5ff4e36c
AL		 2061 qemu_mutex_init(&qxl->async_lock);
2062 qxl->current_async = QXL_UNDEFINED_IO;
087e6a42 2063 qxl->guest_bug = 0;
a19cbfb3
GH		 2064
2065 switch (qxl->revision) {
2066 case 1: /* spice 0.4 -- qxl-1 */
a19cbfb3 2067 pci_device_rev = QXL_REVISION_STABLE_V04;
3f6297b9 2068 io_size = 8;
a19cbfb3
GH		 2069 break;
2070 case 2: /* spice 0.6 -- qxl-2 */
a19cbfb3 2071 pci_device_rev = QXL_REVISION_STABLE_V06;
3f6297b9 2072 io_size = 16;
a19cbfb3 2073 break;
9197a7c8 2074 case 3: /* qxl-3 */
020af1c4
AL		 2075 pci_device_rev = QXL_REVISION_STABLE_V10;
2076 io_size = 32; /* PCI region size must be pow2 */
2077 break;
020af1c4
AL		 2078 case 4: /* qxl-4 */
2079 pci_device_rev = QXL_REVISION_STABLE_V12;
bb7443f6 2080 io_size = pow2ceil(QXL_IO_RANGE_SIZE);
9197a7c8 2081 break;
36839d35 2082 default:
042a24db
MA		 2083 error_setg(errp, "Invalid revision %d for qxl device (max %d)",
2084 qxl->revision, QXL_DEFAULT_REVISION);
2085 return;
a19cbfb3
GH		 2086 }
2087
a19cbfb3
GH		 2088 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
2089 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
2090
2091 qxl->rom_size = qxl_rom_size();
ce66d778 2092 memory_region_init_ram(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom",
f8ed85ac 2093 qxl->rom_size, &error_fatal);
a19cbfb3
GH		 2094 init_qxl_rom(qxl);
2095 init_qxl_ram(qxl);
2096
ddd8fdc7 2097 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
ce66d778 2098 memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram",
f8ed85ac 2099 qxl->vram_size, &error_fatal);
3eadad55
PB		 2100 memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32",
2101 &qxl->vram_bar, 0, qxl->vram32_size);
a19cbfb3 2102
3eadad55 2103 memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl,
b1950430
AK		 2104 "qxl-ioports", io_size);
2105 if (qxl->id == 0) {
2106 vga_dirty_log_start(&qxl->vga);
2107 }
bd8f2f5d 2108 memory_region_set_flush_coalesced(&qxl->io_bar);
b1950430
AK		 2109
2110
e824b2cc
AK		 2111 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
2112 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
a19cbfb3 2113
e824b2cc
AK		 2114 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
2115 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
a19cbfb3 2116
e824b2cc
AK		 2117 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
2118 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
a19cbfb3 2119
e824b2cc 2120 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
6f2b175a
GH		 2121 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
2122
2123 if (qxl->vram32_size < qxl->vram_size) {
2124 /*
2125 * Make the 64bit vram bar show up only in case it is
2126 * configured to be larger than the 32bit vram bar.
2127 */
2128 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
2129 PCI_BASE_ADDRESS_SPACE_MEMORY |
2130 PCI_BASE_ADDRESS_MEM_TYPE_64 |
2131 PCI_BASE_ADDRESS_MEM_PREFETCH,
2132 &qxl->vram_bar);
2133 }
2134
2135 /* print pci bar details */
2136 dprint(qxl, 1, "ram/%s: %d MB [region 0]\n",
2137 qxl->id == 0 ? "pri" : "sec",
2138 qxl->vga.vram_size / (1024*1024));
de1b9b85 2139 dprint(qxl, 1, "vram/32: %" PRIx64 "d MB [region 1]\n",
6f2b175a 2140 qxl->vram32_size / (1024*1024));
de1b9b85 2141 dprint(qxl, 1, "vram/64: %" PRIx64 "d MB %s\n",
6f2b175a
GH		 2142 qxl->vram_size / (1024*1024),
2143 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
a19cbfb3
GH		 2144
2145 qxl->ssd.qxl.base.sif = &qxl_interface.base;
9fa03286 2146 if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) {
042a24db
MA		 2147 error_setg(errp, "qxl interface %d.%d not supported by spice-server",
2148 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR);
2149 return;
e25a0651 2150 }
a19cbfb3
GH		 2151 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
2152
4a46c99c 2153 qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl);
a19cbfb3
GH		 2154 qxl_reset_state(qxl);
2155
81fb6f15 2156 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
0b2824e5 2157 qxl->ssd.cursor_bh = qemu_bh_new(qemu_spice_cursor_refresh_bh, &qxl->ssd);
a19cbfb3
GH		 2158}
2159
042a24db 2160static void qxl_realize_primary(PCIDevice *dev, Error **errp)
a19cbfb3 2161{
c69f6c7d 2162 PCIQXLDevice *qxl = PCI_QXL(dev);
a19cbfb3 2163 VGACommonState *vga = &qxl->vga;
042a24db 2164 Error *local_err = NULL;
a19cbfb3
GH		 2165
2166 qxl->id = 0;
13d1fd44 2167 qxl_init_ramsize(qxl);
54a85d46 2168 vga->vbe_size = qxl->vgamem_size;
4a1e244e 2169 vga->vram_size_mb = qxl->vga.vram_size >> 20;
e2bbfc8e 2170 vga_common_init(vga, OBJECT(dev), true);
712f0cc7
PB		 2171 vga_init(vga, OBJECT(dev),
2172 pci_address_space(dev), pci_address_space_io(dev), false);
848696bf 2173 portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list,
db10ca90 2174 vga, "vga");
848696bf
KB		 2175 portio_list_set_flush_coalesced(&qxl->vga_port_list);
2176 portio_list_add(&qxl->vga_port_list, pci_address_space_io(dev), 0x3b0);
a19cbfb3 2177
5643706a 2178 vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
c78f7137 2179 qemu_spice_display_init_common(&qxl->ssd);
a19cbfb3 2180
042a24db
MA		 2181 qxl_realize_common(qxl, &local_err);
2182 if (local_err) {
2183 error_propagate(errp, local_err);
2184 return;
bdd4df33
GH		 2185 }
2186
7c20b4a3 2187 qxl->ssd.dcl.ops = &display_listener_ops;
284d1c6b 2188 qxl->ssd.dcl.con = vga->con;
5209089f 2189 register_displaychangelistener(&qxl->ssd.dcl);
a19cbfb3
GH		 2190}
2191
042a24db 2192static void qxl_realize_secondary(PCIDevice *dev, Error **errp)
a19cbfb3
GH		 2193{
2194 static int device_id = 1;
c69f6c7d 2195 PCIQXLDevice *qxl = PCI_QXL(dev);
a19cbfb3
GH		 2196
2197 qxl->id = device_id++;
13d1fd44 2198 qxl_init_ramsize(qxl);
ce66d778 2199 memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram",
f8ed85ac 2200 qxl->vga.vram_size, &error_fatal);
b1950430 2201 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
5643706a 2202 qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
a19cbfb3 2203
042a24db 2204 qxl_realize_common(qxl, errp);
a19cbfb3
GH		 2205}
2206
2207static void qxl_pre_save(void *opaque)
2208{
2209 PCIQXLDevice* d = opaque;
2210 uint8_t *ram_start = d->vga.vram_ptr;
2211
c480bb7d 2212 trace_qxl_pre_save(d->id);
a19cbfb3
GH		 2213 if (d->last_release == NULL) {
2214 d->last_release_offset = 0;
2215 } else {
2216 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
2217 }
2218 assert(d->last_release_offset < d->vga.vram_size);
2219}
2220
2221static int qxl_pre_load(void *opaque)
2222{
2223 PCIQXLDevice* d = opaque;
2224
c480bb7d 2225 trace_qxl_pre_load(d->id);
a19cbfb3
GH		 2226 qxl_hard_reset(d, 1);
2227 qxl_exit_vga_mode(d);
a19cbfb3
GH		 2228 return 0;
2229}
2230
54825d2e
AL		 2231static void qxl_create_memslots(PCIQXLDevice *d)
2232{
2233 int i;
2234
2235 for (i = 0; i < NUM_MEMSLOTS; i++) {
2236 if (!d->guest_slots[i].active) {
2237 continue;
2238 }
54825d2e
AL		 2239 qxl_add_memslot(d, i, 0, QXL_SYNC);
2240 }
2241}
2242
a19cbfb3
GH		 2243static int qxl_post_load(void *opaque, int version)
2244{
2245 PCIQXLDevice* d = opaque;
2246 uint8_t *ram_start = d->vga.vram_ptr;
2247 QXLCommandExt *cmds;
54825d2e 2248 int in, out, newmode;
a19cbfb3 2249
a19cbfb3
GH		 2250 assert(d->last_release_offset < d->vga.vram_size);
2251 if (d->last_release_offset == 0) {
2252 d->last_release = NULL;
2253 } else {
2254 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
2255 }
2256
2257 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
2258
c480bb7d 2259 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
a19cbfb3
GH		 2260 newmode = d->mode;
2261 d->mode = QXL_MODE_UNDEFINED;
54825d2e 2262
a19cbfb3
GH		 2263 switch (newmode) {
2264 case QXL_MODE_UNDEFINED:
fa98efe9 2265 qxl_create_memslots(d);
a19cbfb3
GH		 2266 break;
2267 case QXL_MODE_VGA:
54825d2e 2268 qxl_create_memslots(d);
a19cbfb3
GH		 2269 qxl_enter_vga_mode(d);
2270 break;
2271 case QXL_MODE_NATIVE:
54825d2e 2272 qxl_create_memslots(d);
5ff4e36c 2273 qxl_create_guest_primary(d, 1, QXL_SYNC);
a19cbfb3
GH		 2274
2275 /* replay surface-create and cursor-set commands */
9de68637 2276 cmds = g_new0(QXLCommandExt, d->ssd.num_surfaces + 1);
ddd8fdc7 2277 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) {
a19cbfb3
GH		 2278 if (d->guest_surfaces.cmds[in] == 0) {
2279 continue;
2280 }
2281 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
2282 cmds[out].cmd.type = QXL_CMD_SURFACE;
2283 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2284 out++;
2285 }
30f6da66
YH		 2286 if (d->guest_cursor) {
2287 cmds[out].cmd.data = d->guest_cursor;
2288 cmds[out].cmd.type = QXL_CMD_CURSOR;
2289 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2290 out++;
2291 }
aee32bf3 2292 qxl_spice_loadvm_commands(d, cmds, out);
7267c094 2293 g_free(cmds);
020af1c4
AL		 2294 if (d->guest_monitors_config) {
2295 qxl_spice_monitors_config_async(d, 1);
2296 }
a19cbfb3
GH		 2297 break;
2298 case QXL_MODE_COMPAT:
54825d2e
AL		 2299 /* note: no need to call qxl_create_memslots, qxl_set_mode
2300 * creates the mem slot. */
a19cbfb3
GH		 2301 qxl_set_mode(d, d->shadow_rom.mode, 1);
2302 break;
2303 }
a19cbfb3
GH		 2304 return 0;
2305}
2306
b67737a6 2307#define QXL_SAVE_VERSION 21
a19cbfb3 2308
020af1c4
AL		 2309static bool qxl_monitors_config_needed(void *opaque)
2310{
2311 PCIQXLDevice *qxl = opaque;
2312
2313 return qxl->guest_monitors_config != 0;
2314}
2315
2316
a19cbfb3
GH		 2317static VMStateDescription qxl_memslot = {
2318 .name = "qxl-memslot",
2319 .version_id = QXL_SAVE_VERSION,
2320 .minimum_version_id = QXL_SAVE_VERSION,
2321 .fields = (VMStateField[]) {
2322 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
2323 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
2324 VMSTATE_UINT32(active, struct guest_slots),
2325 VMSTATE_END_OF_LIST()
2326 }
2327};
2328
2329static VMStateDescription qxl_surface = {
2330 .name = "qxl-surface",
2331 .version_id = QXL_SAVE_VERSION,
2332 .minimum_version_id = QXL_SAVE_VERSION,
2333 .fields = (VMStateField[]) {
2334 VMSTATE_UINT32(width, QXLSurfaceCreate),
2335 VMSTATE_UINT32(height, QXLSurfaceCreate),
2336 VMSTATE_INT32(stride, QXLSurfaceCreate),
2337 VMSTATE_UINT32(format, QXLSurfaceCreate),
2338 VMSTATE_UINT32(position, QXLSurfaceCreate),
2339 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
2340 VMSTATE_UINT32(flags, QXLSurfaceCreate),
2341 VMSTATE_UINT32(type, QXLSurfaceCreate),
2342 VMSTATE_UINT64(mem, QXLSurfaceCreate),
2343 VMSTATE_END_OF_LIST()
2344 }
2345};
2346
020af1c4
AL		 2347static VMStateDescription qxl_vmstate_monitors_config = {
2348 .name = "qxl/monitors-config",
2349 .version_id = 1,
2350 .minimum_version_id = 1,
5cd8cada 2351 .needed = qxl_monitors_config_needed,
020af1c4
AL		 2352 .fields = (VMStateField[]) {
2353 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice),
2354 VMSTATE_END_OF_LIST()
2355 },
2356};
2357
a19cbfb3
GH		 2358static VMStateDescription qxl_vmstate = {
2359 .name = "qxl",
2360 .version_id = QXL_SAVE_VERSION,
2361 .minimum_version_id = QXL_SAVE_VERSION,
2362 .pre_save = qxl_pre_save,
2363 .pre_load = qxl_pre_load,
2364 .post_load = qxl_post_load,
020af1c4 2365 .fields = (VMStateField[]) {
a19cbfb3
GH		 2366 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
2367 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
2368 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
2369 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
2370 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
2371 VMSTATE_UINT32(mode, PCIQXLDevice),
2372 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
d2164ad3 2373 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice, NULL),
b67737a6
GH		 2374 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
2375 qxl_memslot, struct guest_slots),
2376 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
2377 qxl_surface, QXLSurfaceCreate),
d2164ad3 2378 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice, NULL),
ddd8fdc7
GH		 2379 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice,
2380 ssd.num_surfaces, 0,
2381 vmstate_info_uint64, uint64_t),
b67737a6 2382 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
a19cbfb3
GH		 2383 VMSTATE_END_OF_LIST()
2384 },
5cd8cada
JQ		 2385 .subsections = (const VMStateDescription*[]) {
2386 &qxl_vmstate_monitors_config,
2387 NULL
020af1c4 2388 }
a19cbfb3
GH		 2389};
2390
78e60ba5
GH		 2391static Property qxl_properties[] = {
2392 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
2393 64 * 1024 * 1024),
de1b9b85 2394 DEFINE_PROP_UINT64("vram_size", PCIQXLDevice, vram32_size,
78e60ba5
GH		 2395 64 * 1024 * 1024),
2396 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
2397 QXL_DEFAULT_REVISION),
2398 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
2399 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
2400 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
017438ee 2401 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
79ce3567
AL		 2402 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
2403 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
9e56edcf 2404 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16),
ddd8fdc7 2405 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024),
567161fd
FZ		 2406#if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
2407 DEFINE_PROP_UINT16("max_outputs", PCIQXLDevice, max_outputs, 0),
2408#endif
6f663d7b
GH		 2409 DEFINE_PROP_UINT32("xres", PCIQXLDevice, xres, 0),
2410 DEFINE_PROP_UINT32("yres", PCIQXLDevice, yres, 0),
78e60ba5
GH		 2411 DEFINE_PROP_END_OF_LIST(),
2412};
2413
c69f6c7d 2414static void qxl_pci_class_init(ObjectClass *klass, void *data)
40021f08 2415{
39bffca2 2416 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 2417 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2418
40021f08
AL		 2419 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2420 k->device_id = QXL_DEVICE_ID_STABLE;
125ee0ed 2421 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
39bffca2
AL		 2422 dc->reset = qxl_reset_handler;
2423 dc->vmsd = &qxl_vmstate;
2424 dc->props = qxl_properties;
c69f6c7d
GA		 2425}
2426
2427static const TypeInfo qxl_pci_type_info = {
2428 .name = TYPE_PCI_QXL,
2429 .parent = TYPE_PCI_DEVICE,
2430 .instance_size = sizeof(PCIQXLDevice),
2431 .abstract = true,
2432 .class_init = qxl_pci_class_init,
2433};
2434
2435static void qxl_primary_class_init(ObjectClass *klass, void *data)
2436{
2437 DeviceClass *dc = DEVICE_CLASS(klass);
2438 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2439
2440 k->realize = qxl_realize_primary;
2441 k->romfile = "vgabios-qxl.bin";
2442 k->class_id = PCI_CLASS_DISPLAY_VGA;
2443 dc->desc = "Spice QXL GPU (primary, vga compatible)";
2897ae02 2444 dc->hotpluggable = false;
40021f08
AL		 2445}
2446
8c43a6f0 2447static const TypeInfo qxl_primary_info = {
39bffca2 2448 .name = "qxl-vga",
c69f6c7d 2449 .parent = TYPE_PCI_QXL,
39bffca2 2450 .class_init = qxl_primary_class_init,
a19cbfb3
GH		 2451};
2452
40021f08
AL		 2453static void qxl_secondary_class_init(ObjectClass *klass, void *data)
2454{
39bffca2 2455 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 2456 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2457
042a24db 2458 k->realize = qxl_realize_secondary;
40021f08 2459 k->class_id = PCI_CLASS_DISPLAY_OTHER;
39bffca2 2460 dc->desc = "Spice QXL GPU (secondary)";
40021f08
AL		 2461}
2462
8c43a6f0 2463static const TypeInfo qxl_secondary_info = {
39bffca2 2464 .name = "qxl",
c69f6c7d 2465 .parent = TYPE_PCI_QXL,
39bffca2 2466 .class_init = qxl_secondary_class_init,
a19cbfb3
GH		 2467};
2468
83f7d43a 2469static void qxl_register_types(void)
a19cbfb3 2470{
c69f6c7d 2471 type_register_static(&qxl_pci_type_info);
39bffca2
AL		 2472 type_register_static(&qxl_primary_info);
2473 type_register_static(&qxl_secondary_info);
a19cbfb3
GH		 2474}
2475
83f7d43a 2476type_init(qxl_register_types)
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