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Fix bad error handling after memory_region_init_ram()
[mirror_qemu.git] / hw / display / qxl.c
CommitLineData
a19cbfb3
GH		 1/*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
a639ab04 21#include <zlib.h>
3761abb1 22#include <stdint.h>
a639ab04 23
a19cbfb3 24#include "qemu-common.h"
1de7afc9
PB		 25#include "qemu/timer.h"
26#include "qemu/queue.h"
5444e768 27#include "qemu/atomic.h"
9c17d615 28#include "sysemu/sysemu.h"
c480bb7d 29#include "trace.h"
a19cbfb3 30
47b43a1f 31#include "qxl.h"
a19cbfb3 32
0b81c478
AL		 33/*
34 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as
35 * such can be changed by the guest, so to avoid a guest trigerrable
0a530548 36 * abort we just qxl_set_guest_bug and set the return to NULL. Still
0b81c478
AL		 37 * it may happen as a result of emulator bug as well.
38 */
a19cbfb3 39#undef SPICE_RING_PROD_ITEM
0b81c478 40#define SPICE_RING_PROD_ITEM(qxl, r, ret) { \
a19cbfb3 41 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
bc5f92e5 42 if (prod >= ARRAY_SIZE((r)->items)) { \
0a530548 43 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
bc5f92e5 44 "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \
0b81c478
AL		 45 ret = NULL; \
46 } else { \
bc5f92e5 47 ret = &(r)->items[prod].el; \
a19cbfb3 48 } \
a19cbfb3
GH		 49 }
50
51#undef SPICE_RING_CONS_ITEM
0b81c478 52#define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
a19cbfb3 53 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
bc5f92e5 54 if (cons >= ARRAY_SIZE((r)->items)) { \
0a530548 55 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
bc5f92e5 56 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \
0b81c478
AL		 57 ret = NULL; \
58 } else { \
bc5f92e5 59 ret = &(r)->items[cons].el; \
a19cbfb3 60 } \
a19cbfb3
GH		 61 }
62
63#undef ALIGN
64#define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
65
66#define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
67
68#define QXL_MODE(_x, _y, _b, _o) \
69 { .x_res = _x, \
70 .y_res = _y, \
71 .bits = _b, \
72 .stride = (_x) * (_b) / 8, \
73 .x_mili = PIXEL_SIZE * (_x), \
74 .y_mili = PIXEL_SIZE * (_y), \
75 .orientation = _o, \
76 }
77
78#define QXL_MODE_16_32(x_res, y_res, orientation) \
79 QXL_MODE(x_res, y_res, 16, orientation), \
80 QXL_MODE(x_res, y_res, 32, orientation)
81
82#define QXL_MODE_EX(x_res, y_res) \
83 QXL_MODE_16_32(x_res, y_res, 0), \
038c1879 84 QXL_MODE_16_32(x_res, y_res, 1)
a19cbfb3
GH		 85
86static QXLMode qxl_modes[] = {
87 QXL_MODE_EX(640, 480),
88 QXL_MODE_EX(800, 480),
89 QXL_MODE_EX(800, 600),
90 QXL_MODE_EX(832, 624),
91 QXL_MODE_EX(960, 640),
92 QXL_MODE_EX(1024, 600),
93 QXL_MODE_EX(1024, 768),
94 QXL_MODE_EX(1152, 864),
95 QXL_MODE_EX(1152, 870),
96 QXL_MODE_EX(1280, 720),
97 QXL_MODE_EX(1280, 760),
98 QXL_MODE_EX(1280, 768),
99 QXL_MODE_EX(1280, 800),
100 QXL_MODE_EX(1280, 960),
101 QXL_MODE_EX(1280, 1024),
102 QXL_MODE_EX(1360, 768),
103 QXL_MODE_EX(1366, 768),
104 QXL_MODE_EX(1400, 1050),
105 QXL_MODE_EX(1440, 900),
106 QXL_MODE_EX(1600, 900),
107 QXL_MODE_EX(1600, 1200),
108 QXL_MODE_EX(1680, 1050),
109 QXL_MODE_EX(1920, 1080),
a19cbfb3
GH		 110 /* these modes need more than 8 MB video memory */
111 QXL_MODE_EX(1920, 1200),
112 QXL_MODE_EX(1920, 1440),
5c74fb27 113 QXL_MODE_EX(2000, 2000),
a19cbfb3 114 QXL_MODE_EX(2048, 1536),
5c74fb27 115 QXL_MODE_EX(2048, 2048),
a19cbfb3
GH		 116 QXL_MODE_EX(2560, 1440),
117 QXL_MODE_EX(2560, 1600),
a19cbfb3
GH		 118 /* these modes need more than 16 MB video memory */
119 QXL_MODE_EX(2560, 2048),
120 QXL_MODE_EX(2800, 2100),
121 QXL_MODE_EX(3200, 2400),
03d9825d 122 /* these modes need more than 32 MB video memory */
d4bcb199
GH		 123 QXL_MODE_EX(3840, 2160), /* 4k mainstream */
124 QXL_MODE_EX(4096, 2160), /* 4k */
03d9825d 125 /* these modes need more than 64 MB video memory */
d4bcb199 126 QXL_MODE_EX(7680, 4320), /* 8k mainstream */
03d9825d 127 /* these modes need more than 128 MB video memory */
d4bcb199 128 QXL_MODE_EX(8192, 4320), /* 8k */
a19cbfb3
GH		 129};
130
a19cbfb3 131static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
5ff4e36c 132static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
a19cbfb3
GH		 133static void qxl_reset_memslots(PCIQXLDevice *d);
134static void qxl_reset_surfaces(PCIQXLDevice *d);
135static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
136
15162335
GH		 137static void qxl_hw_update(void *opaque);
138
0a530548 139void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
2bce0400 140{
917ae08c 141 trace_qxl_set_guest_bug(qxl->id);
2bce0400 142 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
087e6a42 143 qxl->guest_bug = 1;
2bce0400 144 if (qxl->guestdebug) {
7635392c
AL		 145 va_list ap;
146 va_start(ap, msg);
147 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
148 vfprintf(stderr, msg, ap);
149 fprintf(stderr, "\n");
150 va_end(ap);
2bce0400
GH		 151 }
152}
153
087e6a42
AL		 154static void qxl_clear_guest_bug(PCIQXLDevice *qxl)
155{
156 qxl->guest_bug = 0;
157}
aee32bf3
GH		 158
159void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
160 struct QXLRect *area, struct QXLRect *dirty_rects,
161 uint32_t num_dirty_rects,
5ff4e36c 162 uint32_t clear_dirty_region,
2e1a98c9 163 qxl_async_io async, struct QXLCookie *cookie)
aee32bf3 164{
c480bb7d
AL		 165 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
166 area->top, area->bottom);
167 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
168 clear_dirty_region);
5ff4e36c 169 if (async == QXL_SYNC) {
26defe81 170 spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area,
5ff4e36c
AL		 171 dirty_rects, num_dirty_rects, clear_dirty_region);
172 } else {
2e1a98c9 173 assert(cookie != NULL);
5ff4e36c 174 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
5dba0d45 175 clear_dirty_region, (uintptr_t)cookie);
5ff4e36c 176 }
aee32bf3
GH		 177}
178
5ff4e36c
AL		 179static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
180 uint32_t id)
aee32bf3 181{
c480bb7d 182 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
14898cf6 183 qemu_mutex_lock(&qxl->track_lock);
14898cf6
GH		 184 qxl->guest_surfaces.cmds[id] = 0;
185 qxl->guest_surfaces.count--;
186 qemu_mutex_unlock(&qxl->track_lock);
aee32bf3
GH		 187}
188
5ff4e36c
AL		 189static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
190 qxl_async_io async)
191{
2e1a98c9
AL		 192 QXLCookie *cookie;
193
c480bb7d 194 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
5ff4e36c 195 if (async) {
2e1a98c9
AL		 196 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
197 QXL_IO_DESTROY_SURFACE_ASYNC);
198 cookie->u.surface_id = id;
5dba0d45 199 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
5ff4e36c 200 } else {
26defe81 201 spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id);
753b8b0d 202 qxl_spice_destroy_surface_wait_complete(qxl, id);
5ff4e36c
AL		 203 }
204}
205
3e16b9c5
AL		 206static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
207{
c480bb7d
AL		 208 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
209 qxl->num_free_res);
2e1a98c9 210 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
5dba0d45
PM		 211 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
212 QXL_IO_FLUSH_SURFACES_ASYNC));
3e16b9c5 213}
3e16b9c5 214
aee32bf3
GH		 215void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
216 uint32_t count)
217{
c480bb7d 218 trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
26defe81 219 spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count);
aee32bf3
GH		 220}
221
222void qxl_spice_oom(PCIQXLDevice *qxl)
223{
c480bb7d 224 trace_qxl_spice_oom(qxl->id);
26defe81 225 spice_qxl_oom(&qxl->ssd.qxl);
aee32bf3
GH		 226}
227
228void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
229{
c480bb7d 230 trace_qxl_spice_reset_memslots(qxl->id);
26defe81 231 spice_qxl_reset_memslots(&qxl->ssd.qxl);
aee32bf3
GH		 232}
233
5ff4e36c 234static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
aee32bf3 235{
c480bb7d 236 trace_qxl_spice_destroy_surfaces_complete(qxl->id);
14898cf6 237 qemu_mutex_lock(&qxl->track_lock);
ddd8fdc7 238 memset(qxl->guest_surfaces.cmds, 0,
8bb9f51c 239 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces);
14898cf6
GH		 240 qxl->guest_surfaces.count = 0;
241 qemu_mutex_unlock(&qxl->track_lock);
aee32bf3
GH		 242}
243
5ff4e36c
AL		 244static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
245{
c480bb7d 246 trace_qxl_spice_destroy_surfaces(qxl->id, async);
5ff4e36c 247 if (async) {
2e1a98c9 248 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
5dba0d45
PM		 249 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
250 QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
5ff4e36c 251 } else {
26defe81 252 spice_qxl_destroy_surfaces(&qxl->ssd.qxl);
5ff4e36c
AL		 253 qxl_spice_destroy_surfaces_complete(qxl);
254 }
255}
256
020af1c4
AL		 257static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay)
258{
259 trace_qxl_spice_monitors_config(qxl->id);
020af1c4
AL		 260 if (replay) {
261 /*
262 * don't use QXL_COOKIE_TYPE_IO:
263 * - we are not running yet (post_load), we will assert
264 * in send_events
265 * - this is not a guest io, but a reply, so async_io isn't set.
266 */
267 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
268 qxl->guest_monitors_config,
269 MEMSLOT_GROUP_GUEST,
270 (uintptr_t)qxl_cookie_new(
271 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG,
272 0));
273 } else {
567161fd
FZ		 274#if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
275 if (qxl->max_outputs) {
a52b2cbf 276 spice_qxl_set_max_monitors(&qxl->ssd.qxl, qxl->max_outputs);
567161fd
FZ		 277 }
278#endif
020af1c4
AL		 279 qxl->guest_monitors_config = qxl->ram->monitors_config;
280 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
281 qxl->ram->monitors_config,
282 MEMSLOT_GROUP_GUEST,
283 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
284 QXL_IO_MONITORS_CONFIG_ASYNC));
285 }
020af1c4
AL		 286}
287
aee32bf3
GH		 288void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
289{
c480bb7d 290 trace_qxl_spice_reset_image_cache(qxl->id);
26defe81 291 spice_qxl_reset_image_cache(&qxl->ssd.qxl);
aee32bf3
GH		 292}
293
294void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
295{
c480bb7d 296 trace_qxl_spice_reset_cursor(qxl->id);
26defe81 297 spice_qxl_reset_cursor(&qxl->ssd.qxl);
30f6da66
YH		 298 qemu_mutex_lock(&qxl->track_lock);
299 qxl->guest_cursor = 0;
300 qemu_mutex_unlock(&qxl->track_lock);
958c2bce
GH		 301 if (qxl->ssd.cursor) {
302 cursor_put(qxl->ssd.cursor);
303 }
304 qxl->ssd.cursor = cursor_builtin_hidden();
aee32bf3
GH		 305}
306
a19cbfb3
GH		 307static ram_addr_t qxl_rom_size(void)
308{
038c1879
AL		 309 uint32_t required_rom_size = sizeof(QXLRom) + sizeof(QXLModes) +
310 sizeof(qxl_modes);
311 uint32_t rom_size = 8192; /* two pages */
13d1fd44 312
60b3b2a5 313 QEMU_BUILD_BUG_ON(required_rom_size > rom_size);
a19cbfb3
GH		 314 return rom_size;
315}
316
317static void init_qxl_rom(PCIQXLDevice *d)
318{
b1950430 319 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
a19cbfb3
GH		 320 QXLModes *modes = (QXLModes *)(rom + 1);
321 uint32_t ram_header_size;
322 uint32_t surface0_area_size;
323 uint32_t num_pages;
13d1fd44
AL		 324 uint32_t fb;
325 int i, n;
a19cbfb3
GH		 326
327 memset(rom, 0, d->rom_size);
328
329 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
330 rom->id = cpu_to_le32(d->id);
331 rom->log_level = cpu_to_le32(d->guestdebug);
332 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
333
334 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
335 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
336 rom->slots_start = 1;
337 rom->slots_end = NUM_MEMSLOTS - 1;
ddd8fdc7 338 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces);
a19cbfb3 339
13d1fd44 340 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) {
a19cbfb3 341 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
13d1fd44
AL		 342 if (fb > d->vgamem_size) {
343 continue;
a19cbfb3 344 }
13d1fd44
AL		 345 modes->modes[n].id = cpu_to_le32(i);
346 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res);
347 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res);
348 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits);
349 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride);
350 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
351 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
352 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation);
353 n++;
354 }
355 modes->n_modes = cpu_to_le32(n);
a19cbfb3
GH		 356
357 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
13d1fd44 358 surface0_area_size = ALIGN(d->vgamem_size, 4096);
a19cbfb3
GH		 359 num_pages = d->vga.vram_size;
360 num_pages -= ram_header_size;
361 num_pages -= surface0_area_size;
9efc2d8d 362 num_pages = num_pages / QXL_PAGE_SIZE;
a19cbfb3 363
876d5163
RK		 364 assert(ram_header_size + surface0_area_size <= d->vga.vram_size);
365
a19cbfb3
GH		 366 rom->draw_area_offset = cpu_to_le32(0);
367 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
368 rom->pages_offset = cpu_to_le32(surface0_area_size);
369 rom->num_pages = cpu_to_le32(num_pages);
370 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
371
372 d->shadow_rom = *rom;
373 d->rom = rom;
374 d->modes = modes;
375}
376
377static void init_qxl_ram(PCIQXLDevice *d)
378{
379 uint8_t *buf;
380 uint64_t *item;
381
382 buf = d->vga.vram_ptr;
383 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
384 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
385 d->ram->int_pending = cpu_to_le32(0);
386 d->ram->int_mask = cpu_to_le32(0);
9f0f352d 387 d->ram->update_surface = 0;
329f97fc 388 d->ram->monitors_config = 0;
a19cbfb3
GH		 389 SPICE_RING_INIT(&d->ram->cmd_ring);
390 SPICE_RING_INIT(&d->ram->cursor_ring);
391 SPICE_RING_INIT(&d->ram->release_ring);
0b81c478
AL		 392 SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item);
393 assert(item);
a19cbfb3
GH		 394 *item = 0;
395 qxl_ring_set_dirty(d);
396}
397
398/* can be called from spice server thread context */
b1950430 399static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
a19cbfb3 400{
fd4aa979 401 memory_region_set_dirty(mr, addr, end - addr);
a19cbfb3
GH		 402}
403
404static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
405{
b1950430 406 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
a19cbfb3
GH		 407}
408
409/* called from spice server thread context only */
410static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
411{
a19cbfb3
GH		 412 void *base = qxl->vga.vram_ptr;
413 intptr_t offset;
414
415 offset = ptr - base;
a19cbfb3 416 assert(offset < qxl->vga.vram_size);
b0297b4a 417 qxl_set_dirty(&qxl->vga.vram, offset, offset + 3);
a19cbfb3
GH		 418}
419
420/* can be called from spice server thread context */
421static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
422{
b1950430
AK		 423 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
424 ram_addr_t end = qxl->vga.vram_size;
425 qxl_set_dirty(&qxl->vga.vram, addr, end);
a19cbfb3
GH		 426}
427
428/*
429 * keep track of some command state, for savevm/loadvm.
430 * called from spice server thread context only
431 */
fae2afb1 432static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
a19cbfb3
GH		 433{
434 switch (le32_to_cpu(ext->cmd.type)) {
435 case QXL_CMD_SURFACE:
436 {
437 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
fae2afb1
AL		 438
439 if (!cmd) {
440 return 1;
441 }
a19cbfb3 442 uint32_t id = le32_to_cpu(cmd->surface_id);
47eddfbf 443
ddd8fdc7 444 if (id >= qxl->ssd.num_surfaces) {
0a530548 445 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id,
ddd8fdc7 446 qxl->ssd.num_surfaces);
47eddfbf
AL		 447 return 1;
448 }
48f4ba67
AL		 449 if (cmd->type == QXL_SURFACE_CMD_CREATE &&
450 (cmd->u.surface_create.stride & 0x03) != 0) {
451 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
452 cmd->u.surface_create.stride);
453 return 1;
454 }
14898cf6 455 qemu_mutex_lock(&qxl->track_lock);
a19cbfb3
GH		 456 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
457 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
458 qxl->guest_surfaces.count++;
459 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
460 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
461 }
462 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
463 qxl->guest_surfaces.cmds[id] = 0;
464 qxl->guest_surfaces.count--;
465 }
14898cf6 466 qemu_mutex_unlock(&qxl->track_lock);
a19cbfb3
GH		 467 break;
468 }
469 case QXL_CMD_CURSOR:
470 {
471 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
fae2afb1
AL		 472
473 if (!cmd) {
474 return 1;
475 }
a19cbfb3 476 if (cmd->type == QXL_CURSOR_SET) {
30f6da66 477 qemu_mutex_lock(&qxl->track_lock);
a19cbfb3 478 qxl->guest_cursor = ext->cmd.data;
30f6da66 479 qemu_mutex_unlock(&qxl->track_lock);
a19cbfb3
GH		 480 }
481 break;
482 }
483 }
fae2afb1 484 return 0;
a19cbfb3
GH		 485}
486
487/* spice display interface callbacks */
488
489static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
490{
491 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
492
c480bb7d 493 trace_qxl_interface_attach_worker(qxl->id);
a19cbfb3
GH		 494 qxl->ssd.worker = qxl_worker;
495}
496
497static void interface_set_compression_level(QXLInstance *sin, int level)
498{
499 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
500
c480bb7d 501 trace_qxl_interface_set_compression_level(qxl->id, level);
a19cbfb3
GH		 502 qxl->shadow_rom.compression_level = cpu_to_le32(level);
503 qxl->rom->compression_level = cpu_to_le32(level);
504 qxl_rom_set_dirty(qxl);
505}
506
507static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
508{
509 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
510
641381c1
GH		 511 if (!qemu_spice_display_is_running(&qxl->ssd)) {
512 return;
513 }
514
c480bb7d 515 trace_qxl_interface_set_mm_time(qxl->id, mm_time);
a19cbfb3
GH		 516 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
517 qxl->rom->mm_clock = cpu_to_le32(mm_time);
518 qxl_rom_set_dirty(qxl);
519}
520
521static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
522{
523 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
524
c480bb7d 525 trace_qxl_interface_get_init_info(qxl->id);
a19cbfb3
GH		 526 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
527 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
528 info->num_memslots = NUM_MEMSLOTS;
529 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
530 info->internal_groupslot_id = 0;
9efc2d8d
GH		 531 info->qxl_ram_size =
532 le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS;
ddd8fdc7 533 info->n_surfaces = qxl->ssd.num_surfaces;
a19cbfb3
GH		 534}
535
5b77870c
AL		 536static const char *qxl_mode_to_string(int mode)
537{
538 switch (mode) {
539 case QXL_MODE_COMPAT:
540 return "compat";
541 case QXL_MODE_NATIVE:
542 return "native";
543 case QXL_MODE_UNDEFINED:
544 return "undefined";
545 case QXL_MODE_VGA:
546 return "vga";
547 }
548 return "INVALID";
549}
550
8b92e298
AL		 551static const char *io_port_to_string(uint32_t io_port)
552{
553 if (io_port >= QXL_IO_RANGE_SIZE) {
554 return "out of range";
555 }
556 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
557 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
558 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
559 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
560 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
561 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
562 [QXL_IO_RESET] = "QXL_IO_RESET",
563 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
564 [QXL_IO_LOG] = "QXL_IO_LOG",
565 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
566 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
567 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
568 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
569 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
570 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
571 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
572 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
8b92e298
AL		 573 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
574 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
575 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
576 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
577 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
578 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
579 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
580 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
581 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
020af1c4 582 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC",
8b92e298
AL		 583 };
584 return io_port_to_string[io_port];
585}
586
a19cbfb3
GH		 587/* called from spice server thread context only */
588static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
589{
590 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
591 SimpleSpiceUpdate *update;
592 QXLCommandRing *ring;
593 QXLCommand *cmd;
e0c64d08 594 int notify, ret;
a19cbfb3 595
c480bb7d
AL		 596 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
597
a19cbfb3
GH		 598 switch (qxl->mode) {
599 case QXL_MODE_VGA:
e0c64d08
GH		 600 ret = false;
601 qemu_mutex_lock(&qxl->ssd.lock);
b1af98ba
GH		 602 update = QTAILQ_FIRST(&qxl->ssd.updates);
603 if (update != NULL) {
604 QTAILQ_REMOVE(&qxl->ssd.updates, update, next);
e0c64d08
GH		 605 *ext = update->ext;
606 ret = true;
a19cbfb3 607 }
e0c64d08 608 qemu_mutex_unlock(&qxl->ssd.lock);
212496c9 609 if (ret) {
c480bb7d 610 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
212496c9
AL		 611 qxl_log_command(qxl, "vga", ext);
612 }
e0c64d08 613 return ret;
a19cbfb3
GH		 614 case QXL_MODE_COMPAT:
615 case QXL_MODE_NATIVE:
616 case QXL_MODE_UNDEFINED:
a19cbfb3 617 ring = &qxl->ram->cmd_ring;
087e6a42 618 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) {
a19cbfb3
GH		 619 return false;
620 }
0b81c478
AL		 621 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
622 if (!cmd) {
623 return false;
624 }
a19cbfb3
GH		 625 ext->cmd = *cmd;
626 ext->group_id = MEMSLOT_GROUP_GUEST;
627 ext->flags = qxl->cmdflags;
628 SPICE_RING_POP(ring, notify);
629 qxl_ring_set_dirty(qxl);
630 if (notify) {
631 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
632 }
633 qxl->guest_primary.commands++;
634 qxl_track_command(qxl, ext);
635 qxl_log_command(qxl, "cmd", ext);
0b81c478 636 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
a19cbfb3
GH		 637 return true;
638 default:
639 return false;
640 }
641}
642
643/* called from spice server thread context only */
644static int interface_req_cmd_notification(QXLInstance *sin)
645{
646 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
647 int wait = 1;
648
c480bb7d 649 trace_qxl_ring_command_req_notification(qxl->id);
a19cbfb3
GH		 650 switch (qxl->mode) {
651 case QXL_MODE_COMPAT:
652 case QXL_MODE_NATIVE:
653 case QXL_MODE_UNDEFINED:
654 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
655 qxl_ring_set_dirty(qxl);
656 break;
657 default:
658 /* nothing */
659 break;
660 }
661 return wait;
662}
663
664/* called from spice server thread context only */
665static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
666{
667 QXLReleaseRing *ring = &d->ram->release_ring;
668 uint64_t *item;
669 int notify;
670
671#define QXL_FREE_BUNCH_SIZE 32
672
673 if (ring->prod - ring->cons + 1 == ring->num_items) {
674 /* ring full -- can't push */
675 return;
676 }
677 if (!flush && d->oom_running) {
678 /* collect everything from oom handler before pushing */
679 return;
680 }
681 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
682 /* collect a bit more before pushing */
683 return;
684 }
685
686 SPICE_RING_PUSH(ring, notify);
c480bb7d
AL		 687 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
688 d->guest_surfaces.count, d->num_free_res,
689 d->last_release, notify ? "yes" : "no");
690 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
691 ring->num_items, ring->prod, ring->cons);
a19cbfb3
GH		 692 if (notify) {
693 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
694 }
0b81c478
AL		 695 SPICE_RING_PROD_ITEM(d, ring, item);
696 if (!item) {
697 return;
698 }
a19cbfb3
GH		 699 *item = 0;
700 d->num_free_res = 0;
701 d->last_release = NULL;
702 qxl_ring_set_dirty(d);
703}
704
705/* called from spice server thread context only */
706static void interface_release_resource(QXLInstance *sin,
c9f88ce3 707 QXLReleaseInfoExt ext)
a19cbfb3
GH		 708{
709 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
710 QXLReleaseRing *ring;
711 uint64_t *item, id;
712
713 if (ext.group_id == MEMSLOT_GROUP_HOST) {
714 /* host group -> vga mode update request */
e8e23b7d 715 QXLCommandExt *cmdext = (void *)(intptr_t)(ext.info->id);
5643fc01
GH		 716 SimpleSpiceUpdate *update;
717 g_assert(cmdext->cmd.type == QXL_CMD_DRAW);
718 update = container_of(cmdext, SimpleSpiceUpdate, ext);
719 qemu_spice_destroy_update(&qxl->ssd, update);
a19cbfb3
GH		 720 return;
721 }
722
723 /*
724 * ext->info points into guest-visible memory
725 * pci bar 0, $command.release_info
726 */
727 ring = &qxl->ram->release_ring;
0b81c478
AL		 728 SPICE_RING_PROD_ITEM(qxl, ring, item);
729 if (!item) {
730 return;
731 }
a19cbfb3
GH		 732 if (*item == 0) {
733 /* stick head into the ring */
734 id = ext.info->id;
735 ext.info->next = 0;
736 qxl_ram_set_dirty(qxl, &ext.info->next);
737 *item = id;
738 qxl_ring_set_dirty(qxl);
739 } else {
740 /* append item to the list */
741 qxl->last_release->next = ext.info->id;
742 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
743 ext.info->next = 0;
744 qxl_ram_set_dirty(qxl, &ext.info->next);
745 }
746 qxl->last_release = ext.info;
747 qxl->num_free_res++;
c480bb7d 748 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
a19cbfb3
GH		 749 qxl_push_free_res(qxl, 0);
750}
751
752/* called from spice server thread context only */
753static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
754{
755 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
756 QXLCursorRing *ring;
757 QXLCommand *cmd;
758 int notify;
759
c480bb7d
AL		 760 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
761
a19cbfb3
GH		 762 switch (qxl->mode) {
763 case QXL_MODE_COMPAT:
764 case QXL_MODE_NATIVE:
765 case QXL_MODE_UNDEFINED:
766 ring = &qxl->ram->cursor_ring;
767 if (SPICE_RING_IS_EMPTY(ring)) {
768 return false;
769 }
0b81c478
AL		 770 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
771 if (!cmd) {
772 return false;
773 }
a19cbfb3
GH		 774 ext->cmd = *cmd;
775 ext->group_id = MEMSLOT_GROUP_GUEST;
776 ext->flags = qxl->cmdflags;
777 SPICE_RING_POP(ring, notify);
778 qxl_ring_set_dirty(qxl);
779 if (notify) {
780 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
781 }
782 qxl->guest_primary.commands++;
783 qxl_track_command(qxl, ext);
784 qxl_log_command(qxl, "csr", ext);
785 if (qxl->id == 0) {
786 qxl_render_cursor(qxl, ext);
787 }
c480bb7d 788 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
a19cbfb3
GH		 789 return true;
790 default:
791 return false;
792 }
793}
794
795/* called from spice server thread context only */
796static int interface_req_cursor_notification(QXLInstance *sin)
797{
798 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
799 int wait = 1;
800
c480bb7d 801 trace_qxl_ring_cursor_req_notification(qxl->id);
a19cbfb3
GH		 802 switch (qxl->mode) {
803 case QXL_MODE_COMPAT:
804 case QXL_MODE_NATIVE:
805 case QXL_MODE_UNDEFINED:
806 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
807 qxl_ring_set_dirty(qxl);
808 break;
809 default:
810 /* nothing */
811 break;
812 }
813 return wait;
814}
815
816/* called from spice server thread context */
817static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
818{
baeae407
AL		 819 /*
820 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
821 * use by xf86-video-qxl and is defined out in the qxl windows driver.
822 * Probably was at some earlier version that is prior to git start (2009),
823 * and is still guest trigerrable.
824 */
825 fprintf(stderr, "%s: deprecated\n", __func__);
a19cbfb3
GH		 826}
827
828/* called from spice server thread context only */
829static int interface_flush_resources(QXLInstance *sin)
830{
831 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
832 int ret;
833
a19cbfb3
GH		 834 ret = qxl->num_free_res;
835 if (ret) {
836 qxl_push_free_res(qxl, 1);
837 }
838 return ret;
839}
840
5ff4e36c
AL		 841static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
842
5ff4e36c 843/* called from spice server thread context only */
2e1a98c9 844static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
5ff4e36c 845{
5ff4e36c
AL		 846 uint32_t current_async;
847
848 qemu_mutex_lock(&qxl->async_lock);
849 current_async = qxl->current_async;
850 qxl->current_async = QXL_UNDEFINED_IO;
851 qemu_mutex_unlock(&qxl->async_lock);
852
c480bb7d 853 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
2e1a98c9
AL		 854 if (!cookie) {
855 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
856 return;
857 }
858 if (cookie && current_async != cookie->io) {
859 fprintf(stderr,
2fce7edf
AL		 860 "qxl: %s: error: current_async = %d != %"
861 PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
2e1a98c9 862 }
5ff4e36c 863 switch (current_async) {
81fb6f15
AL		 864 case QXL_IO_MEMSLOT_ADD_ASYNC:
865 case QXL_IO_DESTROY_PRIMARY_ASYNC:
866 case QXL_IO_UPDATE_AREA_ASYNC:
867 case QXL_IO_FLUSH_SURFACES_ASYNC:
020af1c4 868 case QXL_IO_MONITORS_CONFIG_ASYNC:
81fb6f15 869 break;
5ff4e36c
AL		 870 case QXL_IO_CREATE_PRIMARY_ASYNC:
871 qxl_create_guest_primary_complete(qxl);
872 break;
873 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
874 qxl_spice_destroy_surfaces_complete(qxl);
875 break;
876 case QXL_IO_DESTROY_SURFACE_ASYNC:
2e1a98c9 877 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
5ff4e36c 878 break;
81fb6f15
AL		 879 default:
880 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__,
881 current_async);
5ff4e36c
AL		 882 }
883 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
884}
885
81fb6f15
AL		 886/* called from spice server thread context only */
887static void interface_update_area_complete(QXLInstance *sin,
888 uint32_t surface_id,
889 QXLRect *dirty, uint32_t num_updated_rects)
890{
891 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
892 int i;
893 int qxl_i;
894
895 qemu_mutex_lock(&qxl->ssd.lock);
896 if (surface_id != 0 || !qxl->render_update_cookie_num) {
897 qemu_mutex_unlock(&qxl->ssd.lock);
898 return;
899 }
c480bb7d
AL		 900 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
901 dirty->right, dirty->top, dirty->bottom);
902 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
81fb6f15
AL		 903 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
904 /*
905 * overflow - treat this as a full update. Not expected to be common.
906 */
c480bb7d
AL		 907 trace_qxl_interface_update_area_complete_overflow(qxl->id,
908 QXL_NUM_DIRTY_RECTS);
81fb6f15
AL		 909 qxl->guest_primary.resized = 1;
910 }
911 if (qxl->guest_primary.resized) {
912 /*
913 * Don't bother copying or scheduling the bh since we will flip
914 * the whole area anyway on completion of the update_area async call
915 */
916 qemu_mutex_unlock(&qxl->ssd.lock);
917 return;
918 }
919 qxl_i = qxl->num_dirty_rects;
920 for (i = 0; i < num_updated_rects; i++) {
921 qxl->dirty[qxl_i++] = dirty[i];
922 }
923 qxl->num_dirty_rects += num_updated_rects;
c480bb7d
AL		 924 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
925 qxl->num_dirty_rects);
81fb6f15
AL		 926 qemu_bh_schedule(qxl->update_area_bh);
927 qemu_mutex_unlock(&qxl->ssd.lock);
928}
929
2e1a98c9
AL		 930/* called from spice server thread context only */
931static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
932{
933 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
5dba0d45 934 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
2e1a98c9
AL		 935
936 switch (cookie->type) {
937 case QXL_COOKIE_TYPE_IO:
938 interface_async_complete_io(qxl, cookie);
81fb6f15
AL		 939 g_free(cookie);
940 break;
941 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
942 qxl_render_update_area_done(qxl, cookie);
2e1a98c9 943 break;
020af1c4
AL		 944 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG:
945 break;
2e1a98c9
AL		 946 default:
947 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
948 __func__, cookie->type);
81fb6f15 949 g_free(cookie);
2e1a98c9 950 }
2e1a98c9
AL		 951}
952
c10018d6
SSP		 953/* called from spice server thread context only */
954static void interface_set_client_capabilities(QXLInstance *sin,
955 uint8_t client_present,
956 uint8_t caps[58])
957{
958 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
959
e0ac6097
AL		 960 if (qxl->revision < 4) {
961 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id,
962 qxl->revision);
963 return;
964 }
965
ab902981
HG		 966 if (runstate_check(RUN_STATE_INMIGRATE) ||
967 runstate_check(RUN_STATE_POSTMIGRATE)) {
968 return;
969 }
970
c10018d6 971 qxl->shadow_rom.client_present = client_present;
08688af0
MA		 972 memcpy(qxl->shadow_rom.client_capabilities, caps,
973 sizeof(qxl->shadow_rom.client_capabilities));
c10018d6 974 qxl->rom->client_present = client_present;
08688af0
MA		 975 memcpy(qxl->rom->client_capabilities, caps,
976 sizeof(qxl->rom->client_capabilities));
c10018d6
SSP		 977 qxl_rom_set_dirty(qxl);
978
979 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT);
980}
981
a639ab04
AL		 982static uint32_t qxl_crc32(const uint8_t *p, unsigned len)
983{
984 /*
985 * zlib xors the seed with 0xffffffff, and xors the result
986 * again with 0xffffffff; Both are not done with linux's crc32,
987 * which we want to be compatible with, so undo that.
988 */
989 return crc32(0xffffffff, p, len) ^ 0xffffffff;
990}
991
992/* called from main context only */
993static int interface_client_monitors_config(QXLInstance *sin,
994 VDAgentMonitorsConfig *monitors_config)
995{
996 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
997 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar);
998 int i;
567161fd 999 unsigned max_outputs = ARRAY_SIZE(rom->client_monitors_config.heads);
a639ab04 1000
e0ac6097
AL		 1001 if (qxl->revision < 4) {
1002 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id,
1003 qxl->revision);
1004 return 0;
1005 }
a639ab04
AL		 1006 /*
1007 * Older windows drivers set int_mask to 0 when their ISR is called,
1008 * then later set it to ~0. So it doesn't relate to the actual interrupts
1009 * handled. However, they are old, so clearly they don't support this
1010 * interrupt
1011 */
1012 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 ||
1013 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) {
1014 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id,
1015 qxl->ram->int_mask,
1016 monitors_config);
1017 return 0;
1018 }
1019 if (!monitors_config) {
1020 return 1;
1021 }
567161fd
FZ		 1022
1023#if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
1024 /* limit number of outputs based on setting limit */
1025 if (qxl->max_outputs && qxl->max_outputs <= max_outputs) {
1026 max_outputs = qxl->max_outputs;
1027 }
1028#endif
1029
a639ab04
AL		 1030 memset(&rom->client_monitors_config, 0,
1031 sizeof(rom->client_monitors_config));
1032 rom->client_monitors_config.count = monitors_config->num_of_monitors;
1033 /* monitors_config->flags ignored */
567161fd 1034 if (rom->client_monitors_config.count >= max_outputs) {
a639ab04
AL		 1035 trace_qxl_client_monitors_config_capped(qxl->id,
1036 monitors_config->num_of_monitors,
567161fd
FZ		 1037 max_outputs);
1038 rom->client_monitors_config.count = max_outputs;
a639ab04
AL		 1039 }
1040 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1041 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1042 QXLURect *rect = &rom->client_monitors_config.heads[i];
1043 /* monitor->depth ignored */
1044 rect->left = monitor->x;
1045 rect->top = monitor->y;
1046 rect->right = monitor->x + monitor->width;
1047 rect->bottom = monitor->y + monitor->height;
1048 }
1049 rom->client_monitors_config_crc = qxl_crc32(
1050 (const uint8_t *)&rom->client_monitors_config,
1051 sizeof(rom->client_monitors_config));
1052 trace_qxl_client_monitors_config_crc(qxl->id,
1053 sizeof(rom->client_monitors_config),
1054 rom->client_monitors_config_crc);
1055
1056 trace_qxl_interrupt_client_monitors_config(qxl->id,
1057 rom->client_monitors_config.count,
1058 rom->client_monitors_config.heads);
1059 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG);
1060 return 1;
1061}
a639ab04 1062
a19cbfb3
GH		 1063static const QXLInterface qxl_interface = {
1064 .base.type = SPICE_INTERFACE_QXL,
1065 .base.description = "qxl gpu",
1066 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
1067 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
1068
1069 .attache_worker = interface_attach_worker,
1070 .set_compression_level = interface_set_compression_level,
1071 .set_mm_time = interface_set_mm_time,
1072 .get_init_info = interface_get_init_info,
1073
1074 /* the callbacks below are called from spice server thread context */
1075 .get_command = interface_get_command,
1076 .req_cmd_notification = interface_req_cmd_notification,
1077 .release_resource = interface_release_resource,
1078 .get_cursor_command = interface_get_cursor_command,
1079 .req_cursor_notification = interface_req_cursor_notification,
1080 .notify_update = interface_notify_update,
1081 .flush_resources = interface_flush_resources,
5ff4e36c 1082 .async_complete = interface_async_complete,
81fb6f15 1083 .update_area_complete = interface_update_area_complete,
c10018d6 1084 .set_client_capabilities = interface_set_client_capabilities,
a639ab04 1085 .client_monitors_config = interface_client_monitors_config,
a19cbfb3
GH		 1086};
1087
15162335
GH		 1088static const GraphicHwOps qxl_ops = {
1089 .gfx_update = qxl_hw_update,
1090};
1091
a19cbfb3
GH		 1092static void qxl_enter_vga_mode(PCIQXLDevice *d)
1093{
1094 if (d->mode == QXL_MODE_VGA) {
1095 return;
1096 }
c480bb7d 1097 trace_qxl_enter_vga_mode(d->id);
0a2b5e3a
HG		 1098#if SPICE_SERVER_VERSION >= 0x000c03 /* release 0.12.3 */
1099 spice_qxl_driver_unload(&d->ssd.qxl);
1100#endif
15162335 1101 graphic_console_set_hwops(d->ssd.dcl.con, d->vga.hw_ops, &d->vga);
3dcadce5 1102 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_DEFAULT);
a19cbfb3
GH		 1103 qemu_spice_create_host_primary(&d->ssd);
1104 d->mode = QXL_MODE_VGA;
0f7bfd81 1105 vga_dirty_log_start(&d->vga);
1dbfa005 1106 graphic_hw_update(d->vga.con);
a19cbfb3
GH		 1107}
1108
1109static void qxl_exit_vga_mode(PCIQXLDevice *d)
1110{
1111 if (d->mode != QXL_MODE_VGA) {
1112 return;
1113 }
c480bb7d 1114 trace_qxl_exit_vga_mode(d->id);
15162335 1115 graphic_console_set_hwops(d->ssd.dcl.con, &qxl_ops, d);
3dcadce5 1116 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_IDLE);
0f7bfd81 1117 vga_dirty_log_stop(&d->vga);
5ff4e36c 1118 qxl_destroy_primary(d, QXL_SYNC);
a19cbfb3
GH		 1119}
1120
40010aea 1121static void qxl_update_irq(PCIQXLDevice *d)
a19cbfb3
GH		 1122{
1123 uint32_t pending = le32_to_cpu(d->ram->int_pending);
1124 uint32_t mask = le32_to_cpu(d->ram->int_mask);
1125 int level = !!(pending & mask);
9e64f8a3 1126 pci_set_irq(&d->pci, level);
a19cbfb3
GH		 1127 qxl_ring_set_dirty(d);
1128}
1129
a19cbfb3
GH		 1130static void qxl_check_state(PCIQXLDevice *d)
1131{
1132 QXLRam *ram = d->ram;
71d388d4 1133 int spice_display_running = qemu_spice_display_is_running(&d->ssd);
a19cbfb3 1134
71d388d4
YH		 1135 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
1136 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
a19cbfb3
GH		 1137}
1138
1139static void qxl_reset_state(PCIQXLDevice *d)
1140{
a19cbfb3
GH		 1141 QXLRom *rom = d->rom;
1142
be48e995 1143 qxl_check_state(d);
a19cbfb3
GH		 1144 d->shadow_rom.update_id = cpu_to_le32(0);
1145 *rom = d->shadow_rom;
1146 qxl_rom_set_dirty(d);
1147 init_qxl_ram(d);
1148 d->num_free_res = 0;
1149 d->last_release = NULL;
1150 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
f06b8521 1151 qxl_update_irq(d);
a19cbfb3
GH		 1152}
1153
1154static void qxl_soft_reset(PCIQXLDevice *d)
1155{
c480bb7d 1156 trace_qxl_soft_reset(d->id);
a19cbfb3 1157 qxl_check_state(d);
087e6a42 1158 qxl_clear_guest_bug(d);
a5f68c22 1159 d->current_async = QXL_UNDEFINED_IO;
a19cbfb3
GH		 1160
1161 if (d->id == 0) {
1162 qxl_enter_vga_mode(d);
1163 } else {
1164 d->mode = QXL_MODE_UNDEFINED;
1165 }
1166}
1167
1168static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
1169{
75c70e37
GH		 1170 bool startstop = qemu_spice_display_is_running(&d->ssd);
1171
c480bb7d 1172 trace_qxl_hard_reset(d->id, loadvm);
a19cbfb3 1173
75c70e37
GH		 1174 if (startstop) {
1175 qemu_spice_display_stop();
1176 }
1177
aee32bf3
GH		 1178 qxl_spice_reset_cursor(d);
1179 qxl_spice_reset_image_cache(d);
a19cbfb3
GH		 1180 qxl_reset_surfaces(d);
1181 qxl_reset_memslots(d);
1182
1183 /* pre loadvm reset must not touch QXLRam. This lives in
1184 * device memory, is migrated together with RAM and thus
1185 * already loaded at this point */
1186 if (!loadvm) {
1187 qxl_reset_state(d);
1188 }
1189 qemu_spice_create_host_memslot(&d->ssd);
1190 qxl_soft_reset(d);
75c70e37
GH		 1191
1192 if (startstop) {
1193 qemu_spice_display_start();
1194 }
a19cbfb3
GH		 1195}
1196
1197static void qxl_reset_handler(DeviceState *dev)
1198{
c69f6c7d 1199 PCIQXLDevice *d = PCI_QXL(PCI_DEVICE(dev));
c480bb7d 1200
a19cbfb3
GH		 1201 qxl_hard_reset(d, 0);
1202}
1203
1204static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1205{
1206 VGACommonState *vga = opaque;
1207 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
1208
c480bb7d 1209 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
a19cbfb3 1210 if (qxl->mode != QXL_MODE_VGA) {
5ff4e36c 1211 qxl_destroy_primary(qxl, QXL_SYNC);
a19cbfb3
GH		 1212 qxl_soft_reset(qxl);
1213 }
1214 vga_ioport_write(opaque, addr, val);
1215}
1216
f67ab77a
GH		 1217static const MemoryRegionPortio qxl_vga_portio_list[] = {
1218 { 0x04, 2, 1, .read = vga_ioport_read,
1219 .write = qxl_vga_ioport_write }, /* 3b4 */
1220 { 0x0a, 1, 1, .read = vga_ioport_read,
1221 .write = qxl_vga_ioport_write }, /* 3ba */
1222 { 0x10, 16, 1, .read = vga_ioport_read,
1223 .write = qxl_vga_ioport_write }, /* 3c0 */
1224 { 0x24, 2, 1, .read = vga_ioport_read,
1225 .write = qxl_vga_ioport_write }, /* 3d4 */
1226 { 0x2a, 1, 1, .read = vga_ioport_read,
1227 .write = qxl_vga_ioport_write }, /* 3da */
1228 PORTIO_END_OF_LIST(),
1229};
1230
e954ea28
AL		 1231static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
1232 qxl_async_io async)
a19cbfb3
GH		 1233{
1234 static const int regions[] = {
1235 QXL_RAM_RANGE_INDEX,
1236 QXL_VRAM_RANGE_INDEX,
6f2b175a 1237 QXL_VRAM64_RANGE_INDEX,
a19cbfb3
GH		 1238 };
1239 uint64_t guest_start;
1240 uint64_t guest_end;
1241 int pci_region;
1242 pcibus_t pci_start;
1243 pcibus_t pci_end;
1244 intptr_t virt_start;
1245 QXLDevMemSlot memslot;
1246 int i;
1247
1248 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1249 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1250
c480bb7d 1251 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
a19cbfb3 1252
e954ea28 1253 if (slot_id >= NUM_MEMSLOTS) {
0a530548 1254 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
e954ea28
AL		 1255 slot_id, NUM_MEMSLOTS);
1256 return 1;
1257 }
1258 if (guest_start > guest_end) {
0a530548 1259 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64
e954ea28
AL		 1260 " > 0x%" PRIx64, __func__, guest_start, guest_end);
1261 return 1;
1262 }
a19cbfb3
GH		 1263
1264 for (i = 0; i < ARRAY_SIZE(regions); i++) {
1265 pci_region = regions[i];
1266 pci_start = d->pci.io_regions[pci_region].addr;
1267 pci_end = pci_start + d->pci.io_regions[pci_region].size;
1268 /* mapped? */
1269 if (pci_start == -1) {
1270 continue;
1271 }
1272 /* start address in range ? */
1273 if (guest_start < pci_start || guest_start > pci_end) {
1274 continue;
1275 }
1276 /* end address in range ? */
1277 if (guest_end > pci_end) {
1278 continue;
1279 }
1280 /* passed */
1281 break;
1282 }
e954ea28 1283 if (i == ARRAY_SIZE(regions)) {
0a530548 1284 qxl_set_guest_bug(d, "%s: finished loop without match", __func__);
e954ea28
AL		 1285 return 1;
1286 }
a19cbfb3
GH		 1287
1288 switch (pci_region) {
1289 case QXL_RAM_RANGE_INDEX:
b1950430 1290 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram);
a19cbfb3
GH		 1291 break;
1292 case QXL_VRAM_RANGE_INDEX:
6f2b175a 1293 case 4 /* vram 64bit */:
b1950430 1294 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar);
a19cbfb3
GH		 1295 break;
1296 default:
1297 /* should not happen */
0a530548 1298 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
e954ea28 1299 return 1;
a19cbfb3
GH		 1300 }
1301
1302 memslot.slot_id = slot_id;
1303 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
1304 memslot.virt_start = virt_start + (guest_start - pci_start);
1305 memslot.virt_end = virt_start + (guest_end - pci_start);
1306 memslot.addr_delta = memslot.virt_start - delta;
1307 memslot.generation = d->rom->slot_generation = 0;
1308 qxl_rom_set_dirty(d);
1309
5ff4e36c 1310 qemu_spice_add_memslot(&d->ssd, &memslot, async);
a19cbfb3
GH		 1311 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
1312 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1313 d->guest_slots[slot_id].delta = delta;
1314 d->guest_slots[slot_id].active = 1;
e954ea28 1315 return 0;
a19cbfb3
GH		 1316}
1317
1318static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1319{
5c59d118 1320 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
a19cbfb3
GH		 1321 d->guest_slots[slot_id].active = 0;
1322}
1323
1324static void qxl_reset_memslots(PCIQXLDevice *d)
1325{
aee32bf3 1326 qxl_spice_reset_memslots(d);
a19cbfb3
GH		 1327 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1328}
1329
1330static void qxl_reset_surfaces(PCIQXLDevice *d)
1331{
c480bb7d 1332 trace_qxl_reset_surfaces(d->id);
a19cbfb3 1333 d->mode = QXL_MODE_UNDEFINED;
5ff4e36c 1334 qxl_spice_destroy_surfaces(d, QXL_SYNC);
a19cbfb3
GH		 1335}
1336
e25139b3 1337/* can be also called from spice server thread context */
a19cbfb3
GH		 1338void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1339{
1340 uint64_t phys = le64_to_cpu(pqxl);
1341 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1342 uint64_t offset = phys & 0xffffffffffff;
1343
1344 switch (group_id) {
1345 case MEMSLOT_GROUP_HOST:
f4a8a424 1346 return (void *)(intptr_t)offset;
a19cbfb3 1347 case MEMSLOT_GROUP_GUEST:
4b635c59 1348 if (slot >= NUM_MEMSLOTS) {
0a530548
AL		 1349 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
1350 NUM_MEMSLOTS);
4b635c59
AL		 1351 return NULL;
1352 }
1353 if (!qxl->guest_slots[slot].active) {
0a530548 1354 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
4b635c59
AL		 1355 return NULL;
1356 }
1357 if (offset < qxl->guest_slots[slot].delta) {
0a530548
AL		 1358 qxl_set_guest_bug(qxl,
1359 "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
4b635c59
AL		 1360 slot, offset, qxl->guest_slots[slot].delta);
1361 return NULL;
1362 }
a19cbfb3 1363 offset -= qxl->guest_slots[slot].delta;
4b635c59 1364 if (offset > qxl->guest_slots[slot].size) {
0a530548
AL		 1365 qxl_set_guest_bug(qxl,
1366 "slot %d offset %"PRIu64" > size %"PRIu64"\n",
4b635c59
AL		 1367 slot, offset, qxl->guest_slots[slot].size);
1368 return NULL;
1369 }
a19cbfb3 1370 return qxl->guest_slots[slot].ptr + offset;
a19cbfb3 1371 }
4b635c59 1372 return NULL;
a19cbfb3
GH		 1373}
1374
5ff4e36c
AL		 1375static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1376{
1377 /* for local rendering */
1378 qxl_render_resize(qxl);
1379}
1380
1381static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1382 qxl_async_io async)
a19cbfb3
GH		 1383{
1384 QXLDevSurfaceCreate surface;
1385 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
3761abb1 1386 uint32_t requested_height = le32_to_cpu(sc->height);
13d1fd44
AL		 1387 int requested_stride = le32_to_cpu(sc->stride);
1388
3761abb1
AL		 1389 if (requested_stride == INT32_MIN ||
1390 abs(requested_stride) * (uint64_t)requested_height
1391 > qxl->vgamem_size) {
1392 qxl_set_guest_bug(qxl, "%s: requested primary larger than framebuffer"
1393 " stride %d x height %" PRIu32 " > %" PRIu32,
1394 __func__, requested_stride, requested_height,
1395 qxl->vgamem_size);
13d1fd44
AL		 1396 return;
1397 }
a19cbfb3 1398
ddf9f4b7 1399 if (qxl->mode == QXL_MODE_NATIVE) {
0a530548 1400 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
ddf9f4b7
AL		 1401 __func__);
1402 }
a19cbfb3
GH		 1403 qxl_exit_vga_mode(qxl);
1404
a19cbfb3
GH		 1405 surface.format = le32_to_cpu(sc->format);
1406 surface.height = le32_to_cpu(sc->height);
1407 surface.mem = le64_to_cpu(sc->mem);
1408 surface.position = le32_to_cpu(sc->position);
1409 surface.stride = le32_to_cpu(sc->stride);
1410 surface.width = le32_to_cpu(sc->width);
1411 surface.type = le32_to_cpu(sc->type);
1412 surface.flags = le32_to_cpu(sc->flags);
c480bb7d
AL		 1413 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1414 sc->format, sc->position);
1415 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1416 sc->flags);
a19cbfb3 1417
48f4ba67
AL		 1418 if ((surface.stride & 0x3) != 0) {
1419 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0",
1420 surface.stride);
1421 return;
1422 }
1423
a19cbfb3
GH		 1424 surface.mouse_mode = true;
1425 surface.group_id = MEMSLOT_GROUP_GUEST;
1426 if (loadvm) {
1427 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1428 }
1429
1430 qxl->mode = QXL_MODE_NATIVE;
1431 qxl->cmdflags = 0;
5ff4e36c 1432 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
a19cbfb3 1433
5ff4e36c
AL		 1434 if (async == QXL_SYNC) {
1435 qxl_create_guest_primary_complete(qxl);
1436 }
a19cbfb3
GH		 1437}
1438
5ff4e36c
AL		 1439/* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1440 * done (in QXL_SYNC case), 0 otherwise. */
1441static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
a19cbfb3
GH		 1442{
1443 if (d->mode == QXL_MODE_UNDEFINED) {
5ff4e36c 1444 return 0;
a19cbfb3 1445 }
c480bb7d 1446 trace_qxl_destroy_primary(d->id);
a19cbfb3 1447 d->mode = QXL_MODE_UNDEFINED;
5ff4e36c 1448 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
30f6da66 1449 qxl_spice_reset_cursor(d);
5ff4e36c 1450 return 1;
a19cbfb3
GH		 1451}
1452
9c70434f 1453static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm)
a19cbfb3
GH		 1454{
1455 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1456 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1457 QXLMode *mode = d->modes->modes + modenr;
1458 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1459 QXLMemSlot slot = {
1460 .mem_start = start,
1461 .mem_end = end
1462 };
9c70434f
GH		 1463
1464 if (modenr >= d->modes->n_modes) {
1465 qxl_set_guest_bug(d, "mode number out of range");
1466 return;
1467 }
1468
a19cbfb3
GH		 1469 QXLSurfaceCreate surface = {
1470 .width = mode->x_res,
1471 .height = mode->y_res,
1472 .stride = -mode->x_res * 4,
1473 .format = SPICE_SURFACE_FMT_32_xRGB,
1474 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1475 .mouse_mode = true,
1476 .mem = devmem + d->shadow_rom.draw_area_offset,
1477 };
1478
c480bb7d
AL		 1479 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1480 devmem);
a19cbfb3
GH		 1481 if (!loadvm) {
1482 qxl_hard_reset(d, 0);
1483 }
1484
1485 d->guest_slots[0].slot = slot;
e954ea28 1486 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0);
a19cbfb3
GH		 1487
1488 d->guest_primary.surface = surface;
5ff4e36c 1489 qxl_create_guest_primary(d, 0, QXL_SYNC);
a19cbfb3
GH		 1490
1491 d->mode = QXL_MODE_COMPAT;
1492 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
a19cbfb3
GH		 1493 if (mode->bits == 16) {
1494 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1495 }
a19cbfb3
GH		 1496 d->shadow_rom.mode = cpu_to_le32(modenr);
1497 d->rom->mode = cpu_to_le32(modenr);
1498 qxl_rom_set_dirty(d);
1499}
1500
a8170e5e 1501static void ioport_write(void *opaque, hwaddr addr,
b1950430 1502 uint64_t val, unsigned size)
a19cbfb3
GH		 1503{
1504 PCIQXLDevice *d = opaque;
b1950430 1505 uint32_t io_port = addr;
5ff4e36c 1506 qxl_async_io async = QXL_SYNC;
5ff4e36c 1507 uint32_t orig_io_port = io_port;
a19cbfb3 1508
d96aafca 1509 if (d->guest_bug && io_port != QXL_IO_RESET) {
087e6a42
AL		 1510 return;
1511 }
1512
020af1c4 1513 if (d->revision <= QXL_REVISION_STABLE_V10 &&
ffe01e59 1514 io_port > QXL_IO_FLUSH_RELEASE) {
020af1c4
AL		 1515 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n",
1516 io_port, d->revision);
1517 return;
1518 }
1519
a19cbfb3
GH		 1520 switch (io_port) {
1521 case QXL_IO_RESET:
1522 case QXL_IO_SET_MODE:
1523 case QXL_IO_MEMSLOT_ADD:
1524 case QXL_IO_MEMSLOT_DEL:
1525 case QXL_IO_CREATE_PRIMARY:
81144d1a 1526 case QXL_IO_UPDATE_IRQ:
a3d14054 1527 case QXL_IO_LOG:
5ff4e36c
AL		 1528 case QXL_IO_MEMSLOT_ADD_ASYNC:
1529 case QXL_IO_CREATE_PRIMARY_ASYNC:
a19cbfb3
GH		 1530 break;
1531 default:
e21a298a 1532 if (d->mode != QXL_MODE_VGA) {
a19cbfb3 1533 break;
e21a298a 1534 }
c480bb7d 1535 trace_qxl_io_unexpected_vga_mode(d->id,
917ae08c 1536 addr, val, io_port_to_string(io_port));
5ff4e36c
AL		 1537 /* be nice to buggy guest drivers */
1538 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
020af1c4 1539 io_port < QXL_IO_RANGE_SIZE) {
5ff4e36c
AL		 1540 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1541 }
a19cbfb3
GH		 1542 return;
1543 }
1544
5ff4e36c
AL		 1545 /* we change the io_port to avoid ifdeffery in the main switch */
1546 orig_io_port = io_port;
1547 switch (io_port) {
1548 case QXL_IO_UPDATE_AREA_ASYNC:
1549 io_port = QXL_IO_UPDATE_AREA;
1550 goto async_common;
1551 case QXL_IO_MEMSLOT_ADD_ASYNC:
1552 io_port = QXL_IO_MEMSLOT_ADD;
1553 goto async_common;
1554 case QXL_IO_CREATE_PRIMARY_ASYNC:
1555 io_port = QXL_IO_CREATE_PRIMARY;
1556 goto async_common;
1557 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1558 io_port = QXL_IO_DESTROY_PRIMARY;
1559 goto async_common;
1560 case QXL_IO_DESTROY_SURFACE_ASYNC:
1561 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1562 goto async_common;
1563 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1564 io_port = QXL_IO_DESTROY_ALL_SURFACES;
3e16b9c5
AL		 1565 goto async_common;
1566 case QXL_IO_FLUSH_SURFACES_ASYNC:
020af1c4 1567 case QXL_IO_MONITORS_CONFIG_ASYNC:
5ff4e36c
AL		 1568async_common:
1569 async = QXL_ASYNC;
1570 qemu_mutex_lock(&d->async_lock);
1571 if (d->current_async != QXL_UNDEFINED_IO) {
0a530548 1572 qxl_set_guest_bug(d, "%d async started before last (%d) complete",
5ff4e36c
AL		 1573 io_port, d->current_async);
1574 qemu_mutex_unlock(&d->async_lock);
1575 return;
1576 }
1577 d->current_async = orig_io_port;
1578 qemu_mutex_unlock(&d->async_lock);
5ff4e36c
AL		 1579 break;
1580 default:
1581 break;
1582 }
18b20385
GH		 1583 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode),
1584 addr, io_port_to_string(addr),
1585 val, size, async);
5ff4e36c 1586
a19cbfb3
GH		 1587 switch (io_port) {
1588 case QXL_IO_UPDATE_AREA:
1589 {
81fb6f15 1590 QXLCookie *cookie = NULL;
a19cbfb3 1591 QXLRect update = d->ram->update_area;
81fb6f15 1592
ddd8fdc7 1593 if (d->ram->update_surface > d->ssd.num_surfaces) {
511b13e2
AL		 1594 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1595 d->ram->update_surface);
36a03e0b 1596 break;
511b13e2 1597 }
36a03e0b
MT		 1598 if (update.left >= update.right || update.top >= update.bottom ||
1599 update.left < 0 || update.top < 0) {
511b13e2
AL		 1600 qxl_set_guest_bug(d,
1601 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1602 update.left, update.top, update.right, update.bottom);
9e5a25f1
MAL		 1603 if (update.left == update.right || update.top == update.bottom) {
1604 /* old drivers may provide empty area, keep going */
1605 qxl_clear_guest_bug(d);
1606 goto cancel_async;
1607 }
ccc2960d
DH		 1608 break;
1609 }
81fb6f15
AL		 1610 if (async == QXL_ASYNC) {
1611 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1612 QXL_IO_UPDATE_AREA_ASYNC);
1613 cookie->u.area = update;
1614 }
aee32bf3 1615 qxl_spice_update_area(d, d->ram->update_surface,
81fb6f15
AL		 1616 cookie ? &cookie->u.area : &update,
1617 NULL, 0, 0, async, cookie);
a19cbfb3
GH		 1618 break;
1619 }
1620 case QXL_IO_NOTIFY_CMD:
5c59d118 1621 qemu_spice_wakeup(&d->ssd);
a19cbfb3
GH		 1622 break;
1623 case QXL_IO_NOTIFY_CURSOR:
5c59d118 1624 qemu_spice_wakeup(&d->ssd);
a19cbfb3
GH		 1625 break;
1626 case QXL_IO_UPDATE_IRQ:
40010aea 1627 qxl_update_irq(d);
a19cbfb3
GH		 1628 break;
1629 case QXL_IO_NOTIFY_OOM:
a19cbfb3
GH		 1630 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1631 break;
1632 }
1633 d->oom_running = 1;
aee32bf3 1634 qxl_spice_oom(d);
a19cbfb3
GH		 1635 d->oom_running = 0;
1636 break;
1637 case QXL_IO_SET_MODE:
a19cbfb3
GH		 1638 qxl_set_mode(d, val, 0);
1639 break;
1640 case QXL_IO_LOG:
1a1bc085 1641 trace_qxl_io_log(d->id, d->ram->log_buf);
a19cbfb3 1642 if (d->guestdebug) {
a680f7e7 1643 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
bc72ad67 1644 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), d->ram->log_buf);
a19cbfb3
GH		 1645 }
1646 break;
1647 case QXL_IO_RESET:
a19cbfb3
GH		 1648 qxl_hard_reset(d, 0);
1649 break;
1650 case QXL_IO_MEMSLOT_ADD:
2bce0400 1651 if (val >= NUM_MEMSLOTS) {
0a530548 1652 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
2bce0400
GH		 1653 break;
1654 }
1655 if (d->guest_slots[val].active) {
0a530548
AL		 1656 qxl_set_guest_bug(d,
1657 "QXL_IO_MEMSLOT_ADD: memory slot already active");
2bce0400
GH		 1658 break;
1659 }
a19cbfb3 1660 d->guest_slots[val].slot = d->ram->mem_slot;
5ff4e36c 1661 qxl_add_memslot(d, val, 0, async);
a19cbfb3
GH		 1662 break;
1663 case QXL_IO_MEMSLOT_DEL:
2bce0400 1664 if (val >= NUM_MEMSLOTS) {
0a530548 1665 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
2bce0400
GH		 1666 break;
1667 }
a19cbfb3
GH		 1668 qxl_del_memslot(d, val);
1669 break;
1670 case QXL_IO_CREATE_PRIMARY:
2bce0400 1671 if (val != 0) {
0a530548 1672 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
5ff4e36c
AL		 1673 async);
1674 goto cancel_async;
2bce0400 1675 }
a19cbfb3 1676 d->guest_primary.surface = d->ram->create_surface;
5ff4e36c 1677 qxl_create_guest_primary(d, 0, async);
a19cbfb3
GH		 1678 break;
1679 case QXL_IO_DESTROY_PRIMARY:
2bce0400 1680 if (val != 0) {
0a530548 1681 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
5ff4e36c
AL		 1682 async);
1683 goto cancel_async;
1684 }
5ff4e36c 1685 if (!qxl_destroy_primary(d, async)) {
c480bb7d
AL		 1686 trace_qxl_io_destroy_primary_ignored(d->id,
1687 qxl_mode_to_string(d->mode));
5ff4e36c 1688 goto cancel_async;
2bce0400 1689 }
a19cbfb3
GH		 1690 break;
1691 case QXL_IO_DESTROY_SURFACE_WAIT:
ddd8fdc7 1692 if (val >= d->ssd.num_surfaces) {
0a530548 1693 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
5f8daf2e 1694 "%" PRIu64 " >= NUM_SURFACES", async, val);
5ff4e36c
AL		 1695 goto cancel_async;
1696 }
1697 qxl_spice_destroy_surface_wait(d, val, async);
a19cbfb3 1698 break;
3e16b9c5
AL		 1699 case QXL_IO_FLUSH_RELEASE: {
1700 QXLReleaseRing *ring = &d->ram->release_ring;
1701 if (ring->prod - ring->cons + 1 == ring->num_items) {
1702 fprintf(stderr,
1703 "ERROR: no flush, full release ring [p%d,%dc]\n",
1704 ring->prod, ring->cons);
1705 }
1706 qxl_push_free_res(d, 1 /* flush */);
3e16b9c5
AL		 1707 break;
1708 }
1709 case QXL_IO_FLUSH_SURFACES_ASYNC:
3e16b9c5
AL		 1710 qxl_spice_flush_surfaces_async(d);
1711 break;
a19cbfb3 1712 case QXL_IO_DESTROY_ALL_SURFACES:
5ff4e36c
AL		 1713 d->mode = QXL_MODE_UNDEFINED;
1714 qxl_spice_destroy_surfaces(d, async);
a19cbfb3 1715 break;
020af1c4
AL		 1716 case QXL_IO_MONITORS_CONFIG_ASYNC:
1717 qxl_spice_monitors_config_async(d, 0);
1718 break;
a19cbfb3 1719 default:
0a530548 1720 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
a19cbfb3 1721 }
5ff4e36c
AL		 1722 return;
1723cancel_async:
5ff4e36c
AL		 1724 if (async) {
1725 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1726 qemu_mutex_lock(&d->async_lock);
1727 d->current_async = QXL_UNDEFINED_IO;
1728 qemu_mutex_unlock(&d->async_lock);
1729 }
a19cbfb3
GH		 1730}
1731
a8170e5e 1732static uint64_t ioport_read(void *opaque, hwaddr addr,
b1950430 1733 unsigned size)
a19cbfb3 1734{
917ae08c 1735 PCIQXLDevice *qxl = opaque;
a19cbfb3 1736
917ae08c 1737 trace_qxl_io_read_unexpected(qxl->id);
a19cbfb3
GH		 1738 return 0xff;
1739}
1740
b1950430
AK		 1741static const MemoryRegionOps qxl_io_ops = {
1742 .read = ioport_read,
1743 .write = ioport_write,
1744 .valid = {
1745 .min_access_size = 1,
1746 .max_access_size = 1,
1747 },
1748};
a19cbfb3 1749
4a46c99c 1750static void qxl_update_irq_bh(void *opaque)
a19cbfb3
GH		 1751{
1752 PCIQXLDevice *d = opaque;
40010aea 1753 qxl_update_irq(d);
a19cbfb3
GH		 1754}
1755
a19cbfb3
GH		 1756static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1757{
1758 uint32_t old_pending;
1759 uint32_t le_events = cpu_to_le32(events);
1760
917ae08c 1761 trace_qxl_send_events(d->id, events);
511aefb0
AL		 1762 if (!qemu_spice_display_is_running(&d->ssd)) {
1763 /* spice-server tracks guest running state and should not do this */
1764 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n",
1765 __func__);
1766 trace_qxl_send_events_vm_stopped(d->id, events);
1767 return;
1768 }
5444e768 1769 old_pending = atomic_fetch_or(&d->ram->int_pending, le_events);
a19cbfb3
GH		 1770 if ((old_pending & le_events) == le_events) {
1771 return;
1772 }
4a46c99c 1773 qemu_bh_schedule(d->update_irq);
a19cbfb3
GH		 1774}
1775
1776/* graphics console */
1777
1778static void qxl_hw_update(void *opaque)
1779{
1780 PCIQXLDevice *qxl = opaque;
a19cbfb3 1781
15162335 1782 qxl_render_update(qxl);
a19cbfb3
GH		 1783}
1784
e25139b3
YH		 1785static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1786{
c5825ac6 1787 uintptr_t vram_start;
e25139b3
YH		 1788 int i;
1789
2aa9e85c 1790 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
e25139b3
YH		 1791 return;
1792 }
1793
1794 /* dirty the primary surface */
1795 qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset,
1796 qxl->shadow_rom.surface0_area_size);
1797
c5825ac6 1798 vram_start = (uintptr_t)memory_region_get_ram_ptr(&qxl->vram_bar);
e25139b3
YH		 1799
1800 /* dirty the off-screen surfaces */
ddd8fdc7 1801 for (i = 0; i < qxl->ssd.num_surfaces; i++) {
e25139b3
YH		 1802 QXLSurfaceCmd *cmd;
1803 intptr_t surface_offset;
1804 int surface_size;
1805
1806 if (qxl->guest_surfaces.cmds[i] == 0) {
1807 continue;
1808 }
1809
1810 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1811 MEMSLOT_GROUP_GUEST);
fae2afb1 1812 assert(cmd);
e25139b3
YH		 1813 assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1814 surface_offset = (intptr_t)qxl_phys2virt(qxl,
1815 cmd->u.surface_create.data,
1816 MEMSLOT_GROUP_GUEST);
fae2afb1 1817 assert(surface_offset);
e25139b3
YH		 1818 surface_offset -= vram_start;
1819 surface_size = cmd->u.surface_create.height *
1820 abs(cmd->u.surface_create.stride);
c480bb7d 1821 trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size);
e25139b3
YH		 1822 qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size);
1823 }
1824}
1825
1dfb4dd9
LC		 1826static void qxl_vm_change_state_handler(void *opaque, int running,
1827 RunState state)
a19cbfb3
GH		 1828{
1829 PCIQXLDevice *qxl = opaque;
a19cbfb3 1830
efbf2950
YH		 1831 if (running) {
1832 /*
1833 * if qxl_send_events was called from spice server context before
40010aea 1834 * migration ended, qxl_update_irq for these events might not have been
efbf2950
YH		 1835 * called
1836 */
40010aea 1837 qxl_update_irq(qxl);
e25139b3
YH		 1838 } else {
1839 /* make sure surfaces are saved before migration */
1840 qxl_dirty_surfaces(qxl);
a19cbfb3
GH		 1841 }
1842}
1843
1844/* display change listener */
1845
7c20b4a3 1846static void display_update(DisplayChangeListener *dcl,
7c20b4a3 1847 int x, int y, int w, int h)
a19cbfb3 1848{
c6c06853
GH		 1849 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1850
1851 if (qxl->mode == QXL_MODE_VGA) {
1852 qemu_spice_display_update(&qxl->ssd, x, y, w, h);
a19cbfb3
GH		 1853 }
1854}
1855
c12aeb86 1856static void display_switch(DisplayChangeListener *dcl,
c12aeb86 1857 struct DisplaySurface *surface)
a19cbfb3 1858{
c6c06853
GH		 1859 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1860
71874c17 1861 qxl->ssd.ds = surface;
c6c06853 1862 if (qxl->mode == QXL_MODE_VGA) {
c12aeb86 1863 qemu_spice_display_switch(&qxl->ssd, surface);
a19cbfb3
GH		 1864 }
1865}
1866
bc2ed970 1867static void display_refresh(DisplayChangeListener *dcl)
a19cbfb3 1868{
c6c06853
GH		 1869 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1870
1871 if (qxl->mode == QXL_MODE_VGA) {
1872 qemu_spice_display_refresh(&qxl->ssd);
a19cbfb3
GH		 1873 }
1874}
1875
7c20b4a3
GH		 1876static DisplayChangeListenerOps display_listener_ops = {
1877 .dpy_name = "spice/qxl",
a93a4a22 1878 .dpy_gfx_update = display_update,
c12aeb86 1879 .dpy_gfx_switch = display_switch,
7c20b4a3 1880 .dpy_refresh = display_refresh,
a19cbfb3
GH		 1881};
1882
13d1fd44 1883static void qxl_init_ramsize(PCIQXLDevice *qxl)
a974192c 1884{
13d1fd44
AL		 1885 /* vga mode framebuffer / primary surface (bar 0, first part) */
1886 if (qxl->vgamem_size_mb < 8) {
1887 qxl->vgamem_size_mb = 8;
1888 }
876d5163
RK		 1889 /* XXX: we round vgamem_size_mb up to a nearest power of two and it must be
1890 * less than vga_common_init()'s maximum on qxl->vga.vram_size (512 now).
1891 */
1892 if (qxl->vgamem_size_mb > 256) {
1893 qxl->vgamem_size_mb = 256;
1894 }
13d1fd44
AL		 1895 qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024;
1896
1897 /* vga ram (bar 0, total) */
017438ee
GH		 1898 if (qxl->ram_size_mb != -1) {
1899 qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024;
1900 }
13d1fd44
AL		 1901 if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
1902 qxl->vga.vram_size = qxl->vgamem_size * 2;
a974192c
GH		 1903 }
1904
6f2b175a
GH		 1905 /* vram32 (surfaces, 32bit, bar 1) */
1906 if (qxl->vram32_size_mb != -1) {
1907 qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024;
1908 }
1909 if (qxl->vram32_size < 4096) {
1910 qxl->vram32_size = 4096;
1911 }
1912
1913 /* vram (surfaces, 64bit, bar 4+5) */
017438ee
GH		 1914 if (qxl->vram_size_mb != -1) {
1915 qxl->vram_size = qxl->vram_size_mb * 1024 * 1024;
1916 }
6f2b175a
GH		 1917 if (qxl->vram_size < qxl->vram32_size) {
1918 qxl->vram_size = qxl->vram32_size;
a974192c 1919 }
6f2b175a 1920
a974192c 1921 if (qxl->revision == 1) {
6f2b175a 1922 qxl->vram32_size = 4096;
a974192c
GH		 1923 qxl->vram_size = 4096;
1924 }
bb7443f6
RK		 1925 qxl->vgamem_size = pow2ceil(qxl->vgamem_size);
1926 qxl->vga.vram_size = pow2ceil(qxl->vga.vram_size);
1927 qxl->vram32_size = pow2ceil(qxl->vram32_size);
1928 qxl->vram_size = pow2ceil(qxl->vram_size);
a974192c
GH		 1929}
1930
042a24db 1931static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp)
a19cbfb3
GH		 1932{
1933 uint8_t* config = qxl->pci.config;
a19cbfb3
GH		 1934 uint32_t pci_device_rev;
1935 uint32_t io_size;
1936
1937 qxl->mode = QXL_MODE_UNDEFINED;
1938 qxl->generation = 1;
1939 qxl->num_memslots = NUM_MEMSLOTS;
14898cf6 1940 qemu_mutex_init(&qxl->track_lock);
5ff4e36c
AL		 1941 qemu_mutex_init(&qxl->async_lock);
1942 qxl->current_async = QXL_UNDEFINED_IO;
087e6a42 1943 qxl->guest_bug = 0;
a19cbfb3
GH		 1944
1945 switch (qxl->revision) {
1946 case 1: /* spice 0.4 -- qxl-1 */
a19cbfb3 1947 pci_device_rev = QXL_REVISION_STABLE_V04;
3f6297b9 1948 io_size = 8;
a19cbfb3
GH		 1949 break;
1950 case 2: /* spice 0.6 -- qxl-2 */
a19cbfb3 1951 pci_device_rev = QXL_REVISION_STABLE_V06;
3f6297b9 1952 io_size = 16;
a19cbfb3 1953 break;
9197a7c8 1954 case 3: /* qxl-3 */
020af1c4
AL		 1955 pci_device_rev = QXL_REVISION_STABLE_V10;
1956 io_size = 32; /* PCI region size must be pow2 */
1957 break;
020af1c4
AL		 1958 case 4: /* qxl-4 */
1959 pci_device_rev = QXL_REVISION_STABLE_V12;
bb7443f6 1960 io_size = pow2ceil(QXL_IO_RANGE_SIZE);
9197a7c8 1961 break;
36839d35 1962 default:
042a24db
MA		 1963 error_setg(errp, "Invalid revision %d for qxl device (max %d)",
1964 qxl->revision, QXL_DEFAULT_REVISION);
1965 return;
a19cbfb3
GH		 1966 }
1967
a19cbfb3
GH		 1968 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1969 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1970
1971 qxl->rom_size = qxl_rom_size();
3eadad55 1972 memory_region_init_ram(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom",
f8ed85ac 1973 qxl->rom_size, &error_fatal);
c5705a77 1974 vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev);
a19cbfb3
GH		 1975 init_qxl_rom(qxl);
1976 init_qxl_ram(qxl);
1977
ddd8fdc7 1978 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
3eadad55 1979 memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram",
f8ed85ac 1980 qxl->vram_size, &error_fatal);
c5705a77 1981 vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev);
3eadad55
PB		 1982 memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32",
1983 &qxl->vram_bar, 0, qxl->vram32_size);
a19cbfb3 1984
3eadad55 1985 memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl,
b1950430
AK		 1986 "qxl-ioports", io_size);
1987 if (qxl->id == 0) {
1988 vga_dirty_log_start(&qxl->vga);
1989 }
bd8f2f5d 1990 memory_region_set_flush_coalesced(&qxl->io_bar);
b1950430
AK		 1991
1992
e824b2cc
AK		 1993 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
1994 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
a19cbfb3 1995
e824b2cc
AK		 1996 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
1997 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
a19cbfb3 1998
e824b2cc
AK		 1999 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
2000 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
a19cbfb3 2001
e824b2cc 2002 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
6f2b175a
GH		 2003 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
2004
2005 if (qxl->vram32_size < qxl->vram_size) {
2006 /*
2007 * Make the 64bit vram bar show up only in case it is
2008 * configured to be larger than the 32bit vram bar.
2009 */
2010 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
2011 PCI_BASE_ADDRESS_SPACE_MEMORY |
2012 PCI_BASE_ADDRESS_MEM_TYPE_64 |
2013 PCI_BASE_ADDRESS_MEM_PREFETCH,
2014 &qxl->vram_bar);
2015 }
2016
2017 /* print pci bar details */
2018 dprint(qxl, 1, "ram/%s: %d MB [region 0]\n",
2019 qxl->id == 0 ? "pri" : "sec",
2020 qxl->vga.vram_size / (1024*1024));
2021 dprint(qxl, 1, "vram/32: %d MB [region 1]\n",
2022 qxl->vram32_size / (1024*1024));
2023 dprint(qxl, 1, "vram/64: %d MB %s\n",
2024 qxl->vram_size / (1024*1024),
2025 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
a19cbfb3
GH		 2026
2027 qxl->ssd.qxl.base.sif = &qxl_interface.base;
9fa03286 2028 if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) {
042a24db
MA		 2029 error_setg(errp, "qxl interface %d.%d not supported by spice-server",
2030 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR);
2031 return;
e25a0651 2032 }
a19cbfb3
GH		 2033 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
2034
4a46c99c 2035 qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl);
a19cbfb3
GH		 2036 qxl_reset_state(qxl);
2037
81fb6f15 2038 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
0b2824e5 2039 qxl->ssd.cursor_bh = qemu_bh_new(qemu_spice_cursor_refresh_bh, &qxl->ssd);
a19cbfb3
GH		 2040}
2041
042a24db 2042static void qxl_realize_primary(PCIDevice *dev, Error **errp)
a19cbfb3 2043{
c69f6c7d 2044 PCIQXLDevice *qxl = PCI_QXL(dev);
a19cbfb3 2045 VGACommonState *vga = &qxl->vga;
042a24db 2046 Error *local_err = NULL;
a19cbfb3
GH		 2047
2048 qxl->id = 0;
13d1fd44 2049 qxl_init_ramsize(qxl);
54a85d46 2050 vga->vbe_size = qxl->vgamem_size;
4a1e244e 2051 vga->vram_size_mb = qxl->vga.vram_size >> 20;
e2bbfc8e 2052 vga_common_init(vga, OBJECT(dev), true);
712f0cc7
PB		 2053 vga_init(vga, OBJECT(dev),
2054 pci_address_space(dev), pci_address_space_io(dev), false);
848696bf 2055 portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list,
db10ca90 2056 vga, "vga");
848696bf
KB		 2057 portio_list_set_flush_coalesced(&qxl->vga_port_list);
2058 portio_list_add(&qxl->vga_port_list, pci_address_space_io(dev), 0x3b0);
a19cbfb3 2059
5643706a 2060 vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
c78f7137 2061 qemu_spice_display_init_common(&qxl->ssd);
a19cbfb3 2062
042a24db
MA		 2063 qxl_realize_common(qxl, &local_err);
2064 if (local_err) {
2065 error_propagate(errp, local_err);
2066 return;
bdd4df33
GH		 2067 }
2068
7c20b4a3 2069 qxl->ssd.dcl.ops = &display_listener_ops;
284d1c6b 2070 qxl->ssd.dcl.con = vga->con;
5209089f 2071 register_displaychangelistener(&qxl->ssd.dcl);
a19cbfb3
GH		 2072}
2073
042a24db 2074static void qxl_realize_secondary(PCIDevice *dev, Error **errp)
a19cbfb3
GH		 2075{
2076 static int device_id = 1;
c69f6c7d 2077 PCIQXLDevice *qxl = PCI_QXL(dev);
a19cbfb3
GH		 2078
2079 qxl->id = device_id++;
13d1fd44 2080 qxl_init_ramsize(qxl);
3eadad55 2081 memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram",
f8ed85ac 2082 qxl->vga.vram_size, &error_fatal);
c5705a77 2083 vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev);
b1950430 2084 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
5643706a 2085 qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
a19cbfb3 2086
042a24db 2087 qxl_realize_common(qxl, errp);
a19cbfb3
GH		 2088}
2089
2090static void qxl_pre_save(void *opaque)
2091{
2092 PCIQXLDevice* d = opaque;
2093 uint8_t *ram_start = d->vga.vram_ptr;
2094
c480bb7d 2095 trace_qxl_pre_save(d->id);
a19cbfb3
GH		 2096 if (d->last_release == NULL) {
2097 d->last_release_offset = 0;
2098 } else {
2099 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
2100 }
2101 assert(d->last_release_offset < d->vga.vram_size);
2102}
2103
2104static int qxl_pre_load(void *opaque)
2105{
2106 PCIQXLDevice* d = opaque;
2107
c480bb7d 2108 trace_qxl_pre_load(d->id);
a19cbfb3
GH		 2109 qxl_hard_reset(d, 1);
2110 qxl_exit_vga_mode(d);
a19cbfb3
GH		 2111 return 0;
2112}
2113
54825d2e
AL		 2114static void qxl_create_memslots(PCIQXLDevice *d)
2115{
2116 int i;
2117
2118 for (i = 0; i < NUM_MEMSLOTS; i++) {
2119 if (!d->guest_slots[i].active) {
2120 continue;
2121 }
54825d2e
AL		 2122 qxl_add_memslot(d, i, 0, QXL_SYNC);
2123 }
2124}
2125
a19cbfb3
GH		 2126static int qxl_post_load(void *opaque, int version)
2127{
2128 PCIQXLDevice* d = opaque;
2129 uint8_t *ram_start = d->vga.vram_ptr;
2130 QXLCommandExt *cmds;
54825d2e 2131 int in, out, newmode;
a19cbfb3 2132
a19cbfb3
GH		 2133 assert(d->last_release_offset < d->vga.vram_size);
2134 if (d->last_release_offset == 0) {
2135 d->last_release = NULL;
2136 } else {
2137 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
2138 }
2139
2140 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
2141
c480bb7d 2142 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
a19cbfb3
GH		 2143 newmode = d->mode;
2144 d->mode = QXL_MODE_UNDEFINED;
54825d2e 2145
a19cbfb3
GH		 2146 switch (newmode) {
2147 case QXL_MODE_UNDEFINED:
fa98efe9 2148 qxl_create_memslots(d);
a19cbfb3
GH		 2149 break;
2150 case QXL_MODE_VGA:
54825d2e 2151 qxl_create_memslots(d);
a19cbfb3
GH		 2152 qxl_enter_vga_mode(d);
2153 break;
2154 case QXL_MODE_NATIVE:
54825d2e 2155 qxl_create_memslots(d);
5ff4e36c 2156 qxl_create_guest_primary(d, 1, QXL_SYNC);
a19cbfb3
GH		 2157
2158 /* replay surface-create and cursor-set commands */
ddd8fdc7
GH		 2159 cmds = g_malloc0(sizeof(QXLCommandExt) * (d->ssd.num_surfaces + 1));
2160 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) {
a19cbfb3
GH		 2161 if (d->guest_surfaces.cmds[in] == 0) {
2162 continue;
2163 }
2164 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
2165 cmds[out].cmd.type = QXL_CMD_SURFACE;
2166 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2167 out++;
2168 }
30f6da66
YH		 2169 if (d->guest_cursor) {
2170 cmds[out].cmd.data = d->guest_cursor;
2171 cmds[out].cmd.type = QXL_CMD_CURSOR;
2172 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2173 out++;
2174 }
aee32bf3 2175 qxl_spice_loadvm_commands(d, cmds, out);
7267c094 2176 g_free(cmds);
020af1c4
AL		 2177 if (d->guest_monitors_config) {
2178 qxl_spice_monitors_config_async(d, 1);
2179 }
a19cbfb3
GH		 2180 break;
2181 case QXL_MODE_COMPAT:
54825d2e
AL		 2182 /* note: no need to call qxl_create_memslots, qxl_set_mode
2183 * creates the mem slot. */
a19cbfb3
GH		 2184 qxl_set_mode(d, d->shadow_rom.mode, 1);
2185 break;
2186 }
a19cbfb3
GH		 2187 return 0;
2188}
2189
b67737a6 2190#define QXL_SAVE_VERSION 21
a19cbfb3 2191
020af1c4
AL		 2192static bool qxl_monitors_config_needed(void *opaque)
2193{
2194 PCIQXLDevice *qxl = opaque;
2195
2196 return qxl->guest_monitors_config != 0;
2197}
2198
2199
a19cbfb3
GH		 2200static VMStateDescription qxl_memslot = {
2201 .name = "qxl-memslot",
2202 .version_id = QXL_SAVE_VERSION,
2203 .minimum_version_id = QXL_SAVE_VERSION,
2204 .fields = (VMStateField[]) {
2205 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
2206 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
2207 VMSTATE_UINT32(active, struct guest_slots),
2208 VMSTATE_END_OF_LIST()
2209 }
2210};
2211
2212static VMStateDescription qxl_surface = {
2213 .name = "qxl-surface",
2214 .version_id = QXL_SAVE_VERSION,
2215 .minimum_version_id = QXL_SAVE_VERSION,
2216 .fields = (VMStateField[]) {
2217 VMSTATE_UINT32(width, QXLSurfaceCreate),
2218 VMSTATE_UINT32(height, QXLSurfaceCreate),
2219 VMSTATE_INT32(stride, QXLSurfaceCreate),
2220 VMSTATE_UINT32(format, QXLSurfaceCreate),
2221 VMSTATE_UINT32(position, QXLSurfaceCreate),
2222 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
2223 VMSTATE_UINT32(flags, QXLSurfaceCreate),
2224 VMSTATE_UINT32(type, QXLSurfaceCreate),
2225 VMSTATE_UINT64(mem, QXLSurfaceCreate),
2226 VMSTATE_END_OF_LIST()
2227 }
2228};
2229
020af1c4
AL		 2230static VMStateDescription qxl_vmstate_monitors_config = {
2231 .name = "qxl/monitors-config",
2232 .version_id = 1,
2233 .minimum_version_id = 1,
5cd8cada 2234 .needed = qxl_monitors_config_needed,
020af1c4
AL		 2235 .fields = (VMStateField[]) {
2236 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice),
2237 VMSTATE_END_OF_LIST()
2238 },
2239};
2240
a19cbfb3
GH		 2241static VMStateDescription qxl_vmstate = {
2242 .name = "qxl",
2243 .version_id = QXL_SAVE_VERSION,
2244 .minimum_version_id = QXL_SAVE_VERSION,
2245 .pre_save = qxl_pre_save,
2246 .pre_load = qxl_pre_load,
2247 .post_load = qxl_post_load,
020af1c4 2248 .fields = (VMStateField[]) {
a19cbfb3
GH		 2249 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
2250 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
2251 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
2252 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
2253 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
2254 VMSTATE_UINT32(mode, PCIQXLDevice),
2255 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
b67737a6
GH		 2256 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
2257 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
2258 qxl_memslot, struct guest_slots),
2259 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
2260 qxl_surface, QXLSurfaceCreate),
ddd8fdc7
GH		 2261 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice),
2262 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice,
2263 ssd.num_surfaces, 0,
2264 vmstate_info_uint64, uint64_t),
b67737a6 2265 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
a19cbfb3
GH		 2266 VMSTATE_END_OF_LIST()
2267 },
5cd8cada
JQ		 2268 .subsections = (const VMStateDescription*[]) {
2269 &qxl_vmstate_monitors_config,
2270 NULL
020af1c4 2271 }
a19cbfb3
GH		 2272};
2273
78e60ba5
GH		 2274static Property qxl_properties[] = {
2275 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
2276 64 * 1024 * 1024),
6f2b175a 2277 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size,
78e60ba5
GH		 2278 64 * 1024 * 1024),
2279 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
2280 QXL_DEFAULT_REVISION),
2281 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
2282 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
2283 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
017438ee 2284 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
79ce3567
AL		 2285 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
2286 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
9e56edcf 2287 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16),
ddd8fdc7 2288 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024),
567161fd
FZ		 2289#if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
2290 DEFINE_PROP_UINT16("max_outputs", PCIQXLDevice, max_outputs, 0),
2291#endif
78e60ba5
GH		 2292 DEFINE_PROP_END_OF_LIST(),
2293};
2294
c69f6c7d 2295static void qxl_pci_class_init(ObjectClass *klass, void *data)
40021f08 2296{
39bffca2 2297 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 2298 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2299
40021f08
AL		 2300 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2301 k->device_id = QXL_DEVICE_ID_STABLE;
125ee0ed 2302 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
39bffca2
AL		 2303 dc->reset = qxl_reset_handler;
2304 dc->vmsd = &qxl_vmstate;
2305 dc->props = qxl_properties;
c69f6c7d
GA		 2306}
2307
2308static const TypeInfo qxl_pci_type_info = {
2309 .name = TYPE_PCI_QXL,
2310 .parent = TYPE_PCI_DEVICE,
2311 .instance_size = sizeof(PCIQXLDevice),
2312 .abstract = true,
2313 .class_init = qxl_pci_class_init,
2314};
2315
2316static void qxl_primary_class_init(ObjectClass *klass, void *data)
2317{
2318 DeviceClass *dc = DEVICE_CLASS(klass);
2319 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2320
2321 k->realize = qxl_realize_primary;
2322 k->romfile = "vgabios-qxl.bin";
2323 k->class_id = PCI_CLASS_DISPLAY_VGA;
2324 dc->desc = "Spice QXL GPU (primary, vga compatible)";
2897ae02 2325 dc->hotpluggable = false;
40021f08
AL		 2326}
2327
8c43a6f0 2328static const TypeInfo qxl_primary_info = {
39bffca2 2329 .name = "qxl-vga",
c69f6c7d 2330 .parent = TYPE_PCI_QXL,
39bffca2 2331 .class_init = qxl_primary_class_init,
a19cbfb3
GH		 2332};
2333
40021f08
AL		 2334static void qxl_secondary_class_init(ObjectClass *klass, void *data)
2335{
39bffca2 2336 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 2337 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2338
042a24db 2339 k->realize = qxl_realize_secondary;
40021f08 2340 k->class_id = PCI_CLASS_DISPLAY_OTHER;
39bffca2 2341 dc->desc = "Spice QXL GPU (secondary)";
40021f08
AL		 2342}
2343
8c43a6f0 2344static const TypeInfo qxl_secondary_info = {
39bffca2 2345 .name = "qxl",
c69f6c7d 2346 .parent = TYPE_PCI_QXL,
39bffca2 2347 .class_init = qxl_secondary_class_init,
a19cbfb3
GH		 2348};
2349
83f7d43a 2350static void qxl_register_types(void)
a19cbfb3 2351{
c69f6c7d 2352 type_register_static(&qxl_pci_type_info);
39bffca2
AL		 2353 type_register_static(&qxl_primary_info);
2354 type_register_static(&qxl_secondary_info);
a19cbfb3
GH		 2355}
2356
83f7d43a 2357type_init(qxl_register_types)
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