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1 | /* |
2 | * QEMU SM501 Device | |
3 | * | |
4 | * Copyright (c) 2008 Shin-ichiro KAWASAKI | |
fa0013a1 | 5 | * Copyright (c) 2016-2020 BALATON Zoltan |
ffd39257 BS |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | ||
47df5154 | 26 | #include "qemu/osdep.h" |
fc6b3cf9 | 27 | #include "qemu/units.h" |
da34e65c | 28 | #include "qapi/error.h" |
4a1f253a | 29 | #include "qemu/log.h" |
0b8fa32f | 30 | #include "qemu/module.h" |
01c400ae | 31 | #include "hw/usb/hcd-ohci.h" |
0d09e41a | 32 | #include "hw/char/serial.h" |
28ecbaee | 33 | #include "ui/console.h" |
83c9f4ca | 34 | #include "hw/sysbus.h" |
d6454270 | 35 | #include "migration/vmstate.h" |
edf5ca5d | 36 | #include "hw/pci/pci_device.h" |
a27bd6c7 | 37 | #include "hw/qdev-properties.h" |
4a1f253a | 38 | #include "hw/i2c/i2c.h" |
6306cae2 | 39 | #include "hw/display/i2c-ddc.h" |
1de7afc9 | 40 | #include "qemu/range.h" |
28ecbaee | 41 | #include "ui/pixel_ops.h" |
f3a60058 | 42 | #include "qemu/bswap.h" |
d8327a68 | 43 | #include "trace.h" |
db1015e9 | 44 | #include "qom/object.h" |
ffd39257 | 45 | |
ffd39257 | 46 | #define MMIO_BASE_OFFSET 0x3e00000 |
ca8a1104 | 47 | #define MMIO_SIZE 0x200000 |
2edd6e4a | 48 | #define DC_PALETTE_ENTRIES (0x400 * 3) |
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49 | |
50 | /* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */ | |
51 | ||
52 | /* System Configuration area */ | |
53 | /* System config base */ | |
7be3fbbd | 54 | #define SM501_SYS_CONFIG 0x000000 |
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55 | |
56 | /* config 1 */ | |
7be3fbbd | 57 | #define SM501_SYSTEM_CONTROL 0x000000 |
ffd39257 | 58 | |
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59 | #define SM501_SYSCTRL_PANEL_TRISTATE (1 << 0) |
60 | #define SM501_SYSCTRL_MEM_TRISTATE (1 << 1) | |
61 | #define SM501_SYSCTRL_CRT_TRISTATE (1 << 2) | |
ffd39257 | 62 | |
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63 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3 << 4) |
64 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0 << 4) | |
65 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1 << 4) | |
66 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2 << 4) | |
67 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3 << 4) | |
ffd39257 | 68 | |
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69 | #define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1 << 6) |
70 | #define SM501_SYSCTRL_PCI_RETRY_DISABLE (1 << 7) | |
71 | #define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1 << 11) | |
72 | #define SM501_SYSCTRL_PCI_BURST_READ_EN (1 << 15) | |
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73 | |
74 | /* miscellaneous control */ | |
75 | ||
7be3fbbd | 76 | #define SM501_MISC_CONTROL 0x000004 |
ffd39257 | 77 | |
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78 | #define SM501_MISC_BUS_SH 0x0 |
79 | #define SM501_MISC_BUS_PCI 0x1 | |
80 | #define SM501_MISC_BUS_XSCALE 0x2 | |
81 | #define SM501_MISC_BUS_NEC 0x6 | |
82 | #define SM501_MISC_BUS_MASK 0x7 | |
ffd39257 | 83 | |
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84 | #define SM501_MISC_VR_62MB (1 << 3) |
85 | #define SM501_MISC_CDR_RESET (1 << 7) | |
86 | #define SM501_MISC_USB_LB (1 << 8) | |
87 | #define SM501_MISC_USB_SLAVE (1 << 9) | |
88 | #define SM501_MISC_BL_1 (1 << 10) | |
89 | #define SM501_MISC_MC (1 << 11) | |
90 | #define SM501_MISC_DAC_POWER (1 << 12) | |
91 | #define SM501_MISC_IRQ_INVERT (1 << 16) | |
92 | #define SM501_MISC_SH (1 << 17) | |
ffd39257 | 93 | |
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94 | #define SM501_MISC_HOLD_EMPTY (0 << 18) |
95 | #define SM501_MISC_HOLD_8 (1 << 18) | |
96 | #define SM501_MISC_HOLD_16 (2 << 18) | |
97 | #define SM501_MISC_HOLD_24 (3 << 18) | |
98 | #define SM501_MISC_HOLD_32 (4 << 18) | |
99 | #define SM501_MISC_HOLD_MASK (7 << 18) | |
ffd39257 | 100 | |
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101 | #define SM501_MISC_FREQ_12 (1 << 24) |
102 | #define SM501_MISC_PNL_24BIT (1 << 25) | |
103 | #define SM501_MISC_8051_LE (1 << 26) | |
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104 | |
105 | ||
106 | ||
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107 | #define SM501_GPIO31_0_CONTROL 0x000008 |
108 | #define SM501_GPIO63_32_CONTROL 0x00000C | |
109 | #define SM501_DRAM_CONTROL 0x000010 | |
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110 | |
111 | /* command list */ | |
7be3fbbd | 112 | #define SM501_ARBTRTN_CONTROL 0x000014 |
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113 | |
114 | /* command list */ | |
7be3fbbd | 115 | #define SM501_COMMAND_LIST_STATUS 0x000024 |
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116 | |
117 | /* interrupt debug */ | |
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118 | #define SM501_RAW_IRQ_STATUS 0x000028 |
119 | #define SM501_RAW_IRQ_CLEAR 0x000028 | |
120 | #define SM501_IRQ_STATUS 0x00002C | |
121 | #define SM501_IRQ_MASK 0x000030 | |
122 | #define SM501_DEBUG_CONTROL 0x000034 | |
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123 | |
124 | /* power management */ | |
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125 | #define SM501_POWERMODE_P2X_SRC (1 << 29) |
126 | #define SM501_POWERMODE_V2X_SRC (1 << 20) | |
127 | #define SM501_POWERMODE_M_SRC (1 << 12) | |
128 | #define SM501_POWERMODE_M1_SRC (1 << 4) | |
129 | ||
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130 | #define SM501_CURRENT_GATE 0x000038 |
131 | #define SM501_CURRENT_CLOCK 0x00003C | |
132 | #define SM501_POWER_MODE_0_GATE 0x000040 | |
133 | #define SM501_POWER_MODE_0_CLOCK 0x000044 | |
134 | #define SM501_POWER_MODE_1_GATE 0x000048 | |
135 | #define SM501_POWER_MODE_1_CLOCK 0x00004C | |
136 | #define SM501_SLEEP_MODE_GATE 0x000050 | |
137 | #define SM501_POWER_MODE_CONTROL 0x000054 | |
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138 | |
139 | /* power gates for units within the 501 */ | |
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140 | #define SM501_GATE_HOST 0 |
141 | #define SM501_GATE_MEMORY 1 | |
142 | #define SM501_GATE_DISPLAY 2 | |
143 | #define SM501_GATE_2D_ENGINE 3 | |
144 | #define SM501_GATE_CSC 4 | |
145 | #define SM501_GATE_ZVPORT 5 | |
146 | #define SM501_GATE_GPIO 6 | |
147 | #define SM501_GATE_UART0 7 | |
148 | #define SM501_GATE_UART1 8 | |
149 | #define SM501_GATE_SSP 10 | |
150 | #define SM501_GATE_USB_HOST 11 | |
151 | #define SM501_GATE_USB_GADGET 12 | |
152 | #define SM501_GATE_UCONTROLLER 17 | |
153 | #define SM501_GATE_AC97 18 | |
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154 | |
155 | /* panel clock */ | |
7be3fbbd | 156 | #define SM501_CLOCK_P2XCLK 24 |
ffd39257 | 157 | /* crt clock */ |
7be3fbbd | 158 | #define SM501_CLOCK_V2XCLK 16 |
ffd39257 | 159 | /* main clock */ |
7be3fbbd | 160 | #define SM501_CLOCK_MCLK 8 |
ffd39257 | 161 | /* SDRAM controller clock */ |
7be3fbbd | 162 | #define SM501_CLOCK_M1XCLK 0 |
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163 | |
164 | /* config 2 */ | |
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165 | #define SM501_PCI_MASTER_BASE 0x000058 |
166 | #define SM501_ENDIAN_CONTROL 0x00005C | |
167 | #define SM501_DEVICEID 0x000060 | |
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168 | /* 0x050100A0 */ |
169 | ||
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170 | #define SM501_DEVICEID_SM501 0x05010000 |
171 | #define SM501_DEVICEID_IDMASK 0xffff0000 | |
172 | #define SM501_DEVICEID_REVMASK 0x000000ff | |
ffd39257 | 173 | |
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174 | #define SM501_PLLCLOCK_COUNT 0x000064 |
175 | #define SM501_MISC_TIMING 0x000068 | |
176 | #define SM501_CURRENT_SDRAM_CLOCK 0x00006C | |
ffd39257 | 177 | |
7be3fbbd | 178 | #define SM501_PROGRAMMABLE_PLL_CONTROL 0x000074 |
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179 | |
180 | /* GPIO base */ | |
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181 | #define SM501_GPIO 0x010000 |
182 | #define SM501_GPIO_DATA_LOW 0x00 | |
183 | #define SM501_GPIO_DATA_HIGH 0x04 | |
184 | #define SM501_GPIO_DDR_LOW 0x08 | |
185 | #define SM501_GPIO_DDR_HIGH 0x0C | |
186 | #define SM501_GPIO_IRQ_SETUP 0x10 | |
187 | #define SM501_GPIO_IRQ_STATUS 0x14 | |
188 | #define SM501_GPIO_IRQ_RESET 0x14 | |
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189 | |
190 | /* I2C controller base */ | |
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191 | #define SM501_I2C 0x010040 |
192 | #define SM501_I2C_BYTE_COUNT 0x00 | |
193 | #define SM501_I2C_CONTROL 0x01 | |
194 | #define SM501_I2C_STATUS 0x02 | |
195 | #define SM501_I2C_RESET 0x02 | |
196 | #define SM501_I2C_SLAVE_ADDRESS 0x03 | |
197 | #define SM501_I2C_DATA 0x04 | |
ffd39257 | 198 | |
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199 | #define SM501_I2C_CONTROL_START (1 << 2) |
200 | #define SM501_I2C_CONTROL_ENABLE (1 << 0) | |
201 | ||
202 | #define SM501_I2C_STATUS_COMPLETE (1 << 3) | |
203 | #define SM501_I2C_STATUS_ERROR (1 << 2) | |
204 | ||
205 | #define SM501_I2C_RESET_ERROR (1 << 2) | |
206 | ||
ffd39257 | 207 | /* SSP base */ |
7be3fbbd | 208 | #define SM501_SSP 0x020000 |
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209 | |
210 | /* Uart 0 base */ | |
7be3fbbd | 211 | #define SM501_UART0 0x030000 |
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212 | |
213 | /* Uart 1 base */ | |
7be3fbbd | 214 | #define SM501_UART1 0x030020 |
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215 | |
216 | /* USB host port base */ | |
7be3fbbd | 217 | #define SM501_USB_HOST 0x040000 |
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218 | |
219 | /* USB slave/gadget base */ | |
7be3fbbd | 220 | #define SM501_USB_GADGET 0x060000 |
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221 | |
222 | /* USB slave/gadget data port base */ | |
7be3fbbd | 223 | #define SM501_USB_GADGET_DATA 0x070000 |
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224 | |
225 | /* Display controller/video engine base */ | |
7be3fbbd | 226 | #define SM501_DC 0x080000 |
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227 | |
228 | /* common defines for the SM501 address registers */ | |
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229 | #define SM501_ADDR_FLIP (1 << 31) |
230 | #define SM501_ADDR_EXT (1 << 27) | |
231 | #define SM501_ADDR_CS1 (1 << 26) | |
232 | #define SM501_ADDR_MASK (0x3f << 26) | |
ffd39257 | 233 | |
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234 | #define SM501_FIFO_MASK (0x3 << 16) |
235 | #define SM501_FIFO_1 (0x0 << 16) | |
236 | #define SM501_FIFO_3 (0x1 << 16) | |
237 | #define SM501_FIFO_7 (0x2 << 16) | |
238 | #define SM501_FIFO_11 (0x3 << 16) | |
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239 | |
240 | /* common registers for panel and the crt */ | |
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241 | #define SM501_OFF_DC_H_TOT 0x000 |
242 | #define SM501_OFF_DC_V_TOT 0x008 | |
243 | #define SM501_OFF_DC_H_SYNC 0x004 | |
244 | #define SM501_OFF_DC_V_SYNC 0x00C | |
64f1603b | 245 | |
7be3fbbd | 246 | #define SM501_DC_PANEL_CONTROL 0x000 |
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247 | |
248 | #define SM501_DC_PANEL_CONTROL_FPEN (1 << 27) | |
249 | #define SM501_DC_PANEL_CONTROL_BIAS (1 << 26) | |
250 | #define SM501_DC_PANEL_CONTROL_DATA (1 << 25) | |
251 | #define SM501_DC_PANEL_CONTROL_VDD (1 << 24) | |
252 | #define SM501_DC_PANEL_CONTROL_DP (1 << 23) | |
253 | ||
254 | #define SM501_DC_PANEL_CONTROL_TFT_888 (0 << 21) | |
255 | #define SM501_DC_PANEL_CONTROL_TFT_333 (1 << 21) | |
256 | #define SM501_DC_PANEL_CONTROL_TFT_444 (2 << 21) | |
257 | ||
258 | #define SM501_DC_PANEL_CONTROL_DE (1 << 20) | |
259 | ||
260 | #define SM501_DC_PANEL_CONTROL_LCD_TFT (0 << 18) | |
261 | #define SM501_DC_PANEL_CONTROL_LCD_STN8 (1 << 18) | |
262 | #define SM501_DC_PANEL_CONTROL_LCD_STN12 (2 << 18) | |
263 | ||
264 | #define SM501_DC_PANEL_CONTROL_CP (1 << 14) | |
265 | #define SM501_DC_PANEL_CONTROL_VSP (1 << 13) | |
266 | #define SM501_DC_PANEL_CONTROL_HSP (1 << 12) | |
267 | #define SM501_DC_PANEL_CONTROL_CK (1 << 9) | |
268 | #define SM501_DC_PANEL_CONTROL_TE (1 << 8) | |
269 | #define SM501_DC_PANEL_CONTROL_VPD (1 << 7) | |
270 | #define SM501_DC_PANEL_CONTROL_VP (1 << 6) | |
271 | #define SM501_DC_PANEL_CONTROL_HPD (1 << 5) | |
272 | #define SM501_DC_PANEL_CONTROL_HP (1 << 4) | |
273 | #define SM501_DC_PANEL_CONTROL_GAMMA (1 << 3) | |
274 | #define SM501_DC_PANEL_CONTROL_EN (1 << 2) | |
275 | ||
276 | #define SM501_DC_PANEL_CONTROL_8BPP (0 << 0) | |
277 | #define SM501_DC_PANEL_CONTROL_16BPP (1 << 0) | |
278 | #define SM501_DC_PANEL_CONTROL_32BPP (2 << 0) | |
279 | ||
280 | ||
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281 | #define SM501_DC_PANEL_PANNING_CONTROL 0x004 |
282 | #define SM501_DC_PANEL_COLOR_KEY 0x008 | |
283 | #define SM501_DC_PANEL_FB_ADDR 0x00C | |
284 | #define SM501_DC_PANEL_FB_OFFSET 0x010 | |
285 | #define SM501_DC_PANEL_FB_WIDTH 0x014 | |
286 | #define SM501_DC_PANEL_FB_HEIGHT 0x018 | |
287 | #define SM501_DC_PANEL_TL_LOC 0x01C | |
288 | #define SM501_DC_PANEL_BR_LOC 0x020 | |
289 | #define SM501_DC_PANEL_H_TOT 0x024 | |
290 | #define SM501_DC_PANEL_H_SYNC 0x028 | |
291 | #define SM501_DC_PANEL_V_TOT 0x02C | |
292 | #define SM501_DC_PANEL_V_SYNC 0x030 | |
293 | #define SM501_DC_PANEL_CUR_LINE 0x034 | |
294 | ||
295 | #define SM501_DC_VIDEO_CONTROL 0x040 | |
296 | #define SM501_DC_VIDEO_FB0_ADDR 0x044 | |
297 | #define SM501_DC_VIDEO_FB_WIDTH 0x048 | |
298 | #define SM501_DC_VIDEO_FB0_LAST_ADDR 0x04C | |
299 | #define SM501_DC_VIDEO_TL_LOC 0x050 | |
300 | #define SM501_DC_VIDEO_BR_LOC 0x054 | |
301 | #define SM501_DC_VIDEO_SCALE 0x058 | |
302 | #define SM501_DC_VIDEO_INIT_SCALE 0x05C | |
303 | #define SM501_DC_VIDEO_YUV_CONSTANTS 0x060 | |
304 | #define SM501_DC_VIDEO_FB1_ADDR 0x064 | |
305 | #define SM501_DC_VIDEO_FB1_LAST_ADDR 0x068 | |
306 | ||
307 | #define SM501_DC_VIDEO_ALPHA_CONTROL 0x080 | |
308 | #define SM501_DC_VIDEO_ALPHA_FB_ADDR 0x084 | |
309 | #define SM501_DC_VIDEO_ALPHA_FB_OFFSET 0x088 | |
310 | #define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR 0x08C | |
311 | #define SM501_DC_VIDEO_ALPHA_TL_LOC 0x090 | |
312 | #define SM501_DC_VIDEO_ALPHA_BR_LOC 0x094 | |
313 | #define SM501_DC_VIDEO_ALPHA_SCALE 0x098 | |
314 | #define SM501_DC_VIDEO_ALPHA_INIT_SCALE 0x09C | |
315 | #define SM501_DC_VIDEO_ALPHA_CHROMA_KEY 0x0A0 | |
316 | #define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP 0x0A4 | |
317 | ||
318 | #define SM501_DC_PANEL_HWC_BASE 0x0F0 | |
319 | #define SM501_DC_PANEL_HWC_ADDR 0x0F0 | |
320 | #define SM501_DC_PANEL_HWC_LOC 0x0F4 | |
321 | #define SM501_DC_PANEL_HWC_COLOR_1_2 0x0F8 | |
322 | #define SM501_DC_PANEL_HWC_COLOR_3 0x0FC | |
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323 | |
324 | #define SM501_HWC_EN (1 << 31) | |
325 | ||
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326 | #define SM501_OFF_HWC_ADDR 0x00 |
327 | #define SM501_OFF_HWC_LOC 0x04 | |
328 | #define SM501_OFF_HWC_COLOR_1_2 0x08 | |
329 | #define SM501_OFF_HWC_COLOR_3 0x0C | |
64f1603b | 330 | |
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331 | #define SM501_DC_ALPHA_CONTROL 0x100 |
332 | #define SM501_DC_ALPHA_FB_ADDR 0x104 | |
333 | #define SM501_DC_ALPHA_FB_OFFSET 0x108 | |
334 | #define SM501_DC_ALPHA_TL_LOC 0x10C | |
335 | #define SM501_DC_ALPHA_BR_LOC 0x110 | |
336 | #define SM501_DC_ALPHA_CHROMA_KEY 0x114 | |
337 | #define SM501_DC_ALPHA_COLOR_LOOKUP 0x118 | |
64f1603b | 338 | |
7be3fbbd | 339 | #define SM501_DC_CRT_CONTROL 0x200 |
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340 | |
341 | #define SM501_DC_CRT_CONTROL_TVP (1 << 15) | |
342 | #define SM501_DC_CRT_CONTROL_CP (1 << 14) | |
343 | #define SM501_DC_CRT_CONTROL_VSP (1 << 13) | |
344 | #define SM501_DC_CRT_CONTROL_HSP (1 << 12) | |
345 | #define SM501_DC_CRT_CONTROL_VS (1 << 11) | |
346 | #define SM501_DC_CRT_CONTROL_BLANK (1 << 10) | |
347 | #define SM501_DC_CRT_CONTROL_SEL (1 << 9) | |
348 | #define SM501_DC_CRT_CONTROL_TE (1 << 8) | |
ffd39257 | 349 | #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4) |
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350 | #define SM501_DC_CRT_CONTROL_GAMMA (1 << 3) |
351 | #define SM501_DC_CRT_CONTROL_ENABLE (1 << 2) | |
ffd39257 | 352 | |
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353 | #define SM501_DC_CRT_CONTROL_8BPP (0 << 0) |
354 | #define SM501_DC_CRT_CONTROL_16BPP (1 << 0) | |
355 | #define SM501_DC_CRT_CONTROL_32BPP (2 << 0) | |
ffd39257 | 356 | |
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357 | #define SM501_DC_CRT_FB_ADDR 0x204 |
358 | #define SM501_DC_CRT_FB_OFFSET 0x208 | |
359 | #define SM501_DC_CRT_H_TOT 0x20C | |
360 | #define SM501_DC_CRT_H_SYNC 0x210 | |
361 | #define SM501_DC_CRT_V_TOT 0x214 | |
362 | #define SM501_DC_CRT_V_SYNC 0x218 | |
363 | #define SM501_DC_CRT_SIGNATURE_ANALYZER 0x21C | |
364 | #define SM501_DC_CRT_CUR_LINE 0x220 | |
365 | #define SM501_DC_CRT_MONITOR_DETECT 0x224 | |
ffd39257 | 366 | |
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367 | #define SM501_DC_CRT_HWC_BASE 0x230 |
368 | #define SM501_DC_CRT_HWC_ADDR 0x230 | |
369 | #define SM501_DC_CRT_HWC_LOC 0x234 | |
370 | #define SM501_DC_CRT_HWC_COLOR_1_2 0x238 | |
371 | #define SM501_DC_CRT_HWC_COLOR_3 0x23C | |
ffd39257 | 372 | |
7be3fbbd | 373 | #define SM501_DC_PANEL_PALETTE 0x400 |
ffd39257 | 374 | |
7be3fbbd | 375 | #define SM501_DC_VIDEO_PALETTE 0x800 |
ffd39257 | 376 | |
7be3fbbd | 377 | #define SM501_DC_CRT_PALETTE 0xC00 |
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378 | |
379 | /* Zoom Video port base */ | |
7be3fbbd | 380 | #define SM501_ZVPORT 0x090000 |
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381 | |
382 | /* AC97/I2S base */ | |
7be3fbbd | 383 | #define SM501_AC97 0x0A0000 |
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384 | |
385 | /* 8051 micro controller base */ | |
7be3fbbd | 386 | #define SM501_UCONTROLLER 0x0B0000 |
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387 | |
388 | /* 8051 micro controller SRAM base */ | |
7be3fbbd | 389 | #define SM501_UCONTROLLER_SRAM 0x0C0000 |
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390 | |
391 | /* DMA base */ | |
7be3fbbd | 392 | #define SM501_DMA 0x0D0000 |
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393 | |
394 | /* 2d engine base */ | |
7be3fbbd BZ |
395 | #define SM501_2D_ENGINE 0x100000 |
396 | #define SM501_2D_SOURCE 0x00 | |
397 | #define SM501_2D_DESTINATION 0x04 | |
398 | #define SM501_2D_DIMENSION 0x08 | |
399 | #define SM501_2D_CONTROL 0x0C | |
400 | #define SM501_2D_PITCH 0x10 | |
401 | #define SM501_2D_FOREGROUND 0x14 | |
402 | #define SM501_2D_BACKGROUND 0x18 | |
403 | #define SM501_2D_STRETCH 0x1C | |
404 | #define SM501_2D_COLOR_COMPARE 0x20 | |
405 | #define SM501_2D_COLOR_COMPARE_MASK 0x24 | |
406 | #define SM501_2D_MASK 0x28 | |
407 | #define SM501_2D_CLIP_TL 0x2C | |
408 | #define SM501_2D_CLIP_BR 0x30 | |
409 | #define SM501_2D_MONO_PATTERN_LOW 0x34 | |
410 | #define SM501_2D_MONO_PATTERN_HIGH 0x38 | |
411 | #define SM501_2D_WINDOW_WIDTH 0x3C | |
412 | #define SM501_2D_SOURCE_BASE 0x40 | |
413 | #define SM501_2D_DESTINATION_BASE 0x44 | |
414 | #define SM501_2D_ALPHA 0x48 | |
415 | #define SM501_2D_WRAP 0x4C | |
416 | #define SM501_2D_STATUS 0x50 | |
417 | ||
418 | #define SM501_CSC_Y_SOURCE_BASE 0xC8 | |
419 | #define SM501_CSC_CONSTANTS 0xCC | |
420 | #define SM501_CSC_Y_SOURCE_X 0xD0 | |
421 | #define SM501_CSC_Y_SOURCE_Y 0xD4 | |
422 | #define SM501_CSC_U_SOURCE_BASE 0xD8 | |
423 | #define SM501_CSC_V_SOURCE_BASE 0xDC | |
424 | #define SM501_CSC_SOURCE_DIMENSION 0xE0 | |
425 | #define SM501_CSC_SOURCE_PITCH 0xE4 | |
426 | #define SM501_CSC_DESTINATION 0xE8 | |
427 | #define SM501_CSC_DESTINATION_DIMENSION 0xEC | |
428 | #define SM501_CSC_DESTINATION_PITCH 0xF0 | |
429 | #define SM501_CSC_SCALE_FACTOR 0xF4 | |
430 | #define SM501_CSC_DESTINATION_BASE 0xF8 | |
431 | #define SM501_CSC_CONTROL 0xFC | |
ffd39257 BS |
432 | |
433 | /* 2d engine data port base */ | |
7be3fbbd | 434 | #define SM501_2D_ENGINE_DATA 0x110000 |
ffd39257 BS |
435 | |
436 | /* end of register definitions */ | |
437 | ||
7be3fbbd BZ |
438 | #define SM501_HWC_WIDTH 64 |
439 | #define SM501_HWC_HEIGHT 64 | |
ffd39257 BS |
440 | |
441 | /* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */ | |
442 | static const uint32_t sm501_mem_local_size[] = { | |
d23b6caa PMD |
443 | [0] = 4 * MiB, |
444 | [1] = 8 * MiB, | |
445 | [2] = 16 * MiB, | |
446 | [3] = 32 * MiB, | |
447 | [4] = 64 * MiB, | |
448 | [5] = 2 * MiB, | |
ffd39257 BS |
449 | }; |
450 | #define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index] | |
451 | ||
452 | typedef struct SM501State { | |
453 | /* graphic console status */ | |
c78f7137 | 454 | QemuConsole *con; |
ffd39257 BS |
455 | |
456 | /* status & internal resources */ | |
ffd39257 | 457 | uint32_t local_mem_size_index; |
64f1603b | 458 | uint8_t *local_mem; |
25793bfa | 459 | MemoryRegion local_mem_region; |
ca8a1104 BZ |
460 | MemoryRegion mmio_region; |
461 | MemoryRegion system_config_region; | |
4a1f253a | 462 | MemoryRegion i2c_region; |
ca8a1104 BZ |
463 | MemoryRegion disp_ctrl_region; |
464 | MemoryRegion twoD_engine_region; | |
ffd39257 BS |
465 | uint32_t last_width; |
466 | uint32_t last_height; | |
d2733559 | 467 | bool do_full_update; /* perform a full update next time */ |
4e021052 | 468 | uint8_t use_pixman; |
4a1f253a | 469 | I2CBus *i2c_bus; |
ffd39257 BS |
470 | |
471 | /* mmio registers */ | |
472 | uint32_t system_control; | |
473 | uint32_t misc_control; | |
474 | uint32_t gpio_31_0_control; | |
475 | uint32_t gpio_63_32_control; | |
476 | uint32_t dram_control; | |
70e46ca8 | 477 | uint32_t arbitration_control; |
ffd39257 BS |
478 | uint32_t irq_mask; |
479 | uint32_t misc_timing; | |
480 | uint32_t power_mode_control; | |
481 | ||
4a1f253a BZ |
482 | uint8_t i2c_byte_count; |
483 | uint8_t i2c_status; | |
484 | uint8_t i2c_addr; | |
485 | uint8_t i2c_data[16]; | |
486 | ||
ffd39257 BS |
487 | uint32_t uart0_ier; |
488 | uint32_t uart0_lcr; | |
489 | uint32_t uart0_mcr; | |
490 | uint32_t uart0_scr; | |
491 | ||
2edd6e4a | 492 | uint8_t dc_palette[DC_PALETTE_ENTRIES]; |
ffd39257 BS |
493 | |
494 | uint32_t dc_panel_control; | |
495 | uint32_t dc_panel_panning_control; | |
496 | uint32_t dc_panel_fb_addr; | |
497 | uint32_t dc_panel_fb_offset; | |
498 | uint32_t dc_panel_fb_width; | |
499 | uint32_t dc_panel_fb_height; | |
500 | uint32_t dc_panel_tl_location; | |
501 | uint32_t dc_panel_br_location; | |
502 | uint32_t dc_panel_h_total; | |
503 | uint32_t dc_panel_h_sync; | |
504 | uint32_t dc_panel_v_total; | |
505 | uint32_t dc_panel_v_sync; | |
506 | ||
507 | uint32_t dc_panel_hwc_addr; | |
508 | uint32_t dc_panel_hwc_location; | |
509 | uint32_t dc_panel_hwc_color_1_2; | |
510 | uint32_t dc_panel_hwc_color_3; | |
511 | ||
b612a49d BZ |
512 | uint32_t dc_video_control; |
513 | ||
ffd39257 BS |
514 | uint32_t dc_crt_control; |
515 | uint32_t dc_crt_fb_addr; | |
516 | uint32_t dc_crt_fb_offset; | |
517 | uint32_t dc_crt_h_total; | |
518 | uint32_t dc_crt_h_sync; | |
519 | uint32_t dc_crt_v_total; | |
520 | uint32_t dc_crt_v_sync; | |
521 | ||
522 | uint32_t dc_crt_hwc_addr; | |
523 | uint32_t dc_crt_hwc_location; | |
524 | uint32_t dc_crt_hwc_color_1_2; | |
525 | uint32_t dc_crt_hwc_color_3; | |
526 | ||
07d8a50c | 527 | uint32_t twoD_source; |
604be200 SK |
528 | uint32_t twoD_destination; |
529 | uint32_t twoD_dimension; | |
530 | uint32_t twoD_control; | |
531 | uint32_t twoD_pitch; | |
532 | uint32_t twoD_foreground; | |
b612a49d | 533 | uint32_t twoD_background; |
604be200 | 534 | uint32_t twoD_stretch; |
b612a49d | 535 | uint32_t twoD_color_compare; |
604be200 SK |
536 | uint32_t twoD_color_compare_mask; |
537 | uint32_t twoD_mask; | |
b612a49d BZ |
538 | uint32_t twoD_clip_tl; |
539 | uint32_t twoD_clip_br; | |
540 | uint32_t twoD_mono_pattern_low; | |
541 | uint32_t twoD_mono_pattern_high; | |
604be200 SK |
542 | uint32_t twoD_window_width; |
543 | uint32_t twoD_source_base; | |
544 | uint32_t twoD_destination_base; | |
b612a49d BZ |
545 | uint32_t twoD_alpha; |
546 | uint32_t twoD_wrap; | |
ffd39257 BS |
547 | } SM501State; |
548 | ||
549 | static uint32_t get_local_mem_size_index(uint32_t size) | |
550 | { | |
551 | uint32_t norm_size = 0; | |
552 | int i, index = 0; | |
553 | ||
b1503cda | 554 | for (i = 0; i < ARRAY_SIZE(sm501_mem_local_size); i++) { |
64f1603b BZ |
555 | uint32_t new_size = sm501_mem_local_size[i]; |
556 | if (new_size >= size) { | |
557 | if (norm_size == 0 || norm_size > new_size) { | |
558 | norm_size = new_size; | |
559 | index = i; | |
560 | } | |
561 | } | |
ffd39257 BS |
562 | } |
563 | ||
564 | return index; | |
565 | } | |
566 | ||
33159dd7 BZ |
567 | static ram_addr_t get_fb_addr(SM501State *s, int crt) |
568 | { | |
569 | return (crt ? s->dc_crt_fb_addr : s->dc_panel_fb_addr) & 0x3FFFFF0; | |
570 | } | |
571 | ||
6a2a5aae BZ |
572 | static inline int get_width(SM501State *s, int crt) |
573 | { | |
574 | int width = crt ? s->dc_crt_h_total : s->dc_panel_h_total; | |
575 | return (width & 0x00000FFF) + 1; | |
576 | } | |
577 | ||
578 | static inline int get_height(SM501State *s, int crt) | |
579 | { | |
580 | int height = crt ? s->dc_crt_v_total : s->dc_panel_v_total; | |
581 | return (height & 0x00000FFF) + 1; | |
582 | } | |
583 | ||
584 | static inline int get_bpp(SM501State *s, int crt) | |
585 | { | |
586 | int bpp = crt ? s->dc_crt_control : s->dc_panel_control; | |
587 | return 1 << (bpp & 3); | |
588 | } | |
589 | ||
0a4e7cd2 SK |
590 | /** |
591 | * Check the availability of hardware cursor. | |
592 | * @param crt 0 for PANEL, 1 for CRT. | |
593 | */ | |
594 | static inline int is_hwc_enabled(SM501State *state, int crt) | |
595 | { | |
596 | uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr; | |
e2ee8476 | 597 | return addr & SM501_HWC_EN; |
0a4e7cd2 SK |
598 | } |
599 | ||
600 | /** | |
601 | * Get the address which holds cursor pattern data. | |
602 | * @param crt 0 for PANEL, 1 for CRT. | |
603 | */ | |
6a2a5aae | 604 | static inline uint8_t *get_hwc_address(SM501State *state, int crt) |
0a4e7cd2 SK |
605 | { |
606 | uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr; | |
6a2a5aae | 607 | return state->local_mem + (addr & 0x03FFFFF0); |
0a4e7cd2 SK |
608 | } |
609 | ||
610 | /** | |
611 | * Get the cursor position in y coordinate. | |
612 | * @param crt 0 for PANEL, 1 for CRT. | |
613 | */ | |
614 | static inline uint32_t get_hwc_y(SM501State *state, int crt) | |
615 | { | |
616 | uint32_t location = crt ? state->dc_crt_hwc_location | |
617 | : state->dc_panel_hwc_location; | |
618 | return (location & 0x07FF0000) >> 16; | |
619 | } | |
620 | ||
621 | /** | |
622 | * Get the cursor position in x coordinate. | |
623 | * @param crt 0 for PANEL, 1 for CRT. | |
624 | */ | |
625 | static inline uint32_t get_hwc_x(SM501State *state, int crt) | |
626 | { | |
627 | uint32_t location = crt ? state->dc_crt_hwc_location | |
628 | : state->dc_panel_hwc_location; | |
629 | return location & 0x000007FF; | |
630 | } | |
631 | ||
632 | /** | |
6a2a5aae | 633 | * Get the hardware cursor palette. |
0a4e7cd2 | 634 | * @param crt 0 for PANEL, 1 for CRT. |
6a2a5aae | 635 | * @param palette pointer to a [3 * 3] array to store color values in |
0a4e7cd2 | 636 | */ |
6a2a5aae | 637 | static inline void get_hwc_palette(SM501State *state, int crt, uint8_t *palette) |
0a4e7cd2 | 638 | { |
6a2a5aae BZ |
639 | int i; |
640 | uint32_t color_reg; | |
641 | uint16_t rgb565; | |
642 | ||
643 | for (i = 0; i < 3; i++) { | |
644 | if (i + 1 == 3) { | |
645 | color_reg = crt ? state->dc_crt_hwc_color_3 | |
646 | : state->dc_panel_hwc_color_3; | |
647 | } else { | |
648 | color_reg = crt ? state->dc_crt_hwc_color_1_2 | |
649 | : state->dc_panel_hwc_color_1_2; | |
650 | } | |
0a4e7cd2 | 651 | |
6a2a5aae BZ |
652 | if (i + 1 == 2) { |
653 | rgb565 = (color_reg >> 16) & 0xFFFF; | |
654 | } else { | |
655 | rgb565 = color_reg & 0xFFFF; | |
656 | } | |
a69232e2 SB |
657 | palette[i * 3 + 0] = ((rgb565 >> 11) * 527 + 23) >> 6; /* r */ |
658 | palette[i * 3 + 1] = (((rgb565 >> 5) & 0x3f) * 259 + 33) >> 6; /* g */ | |
659 | palette[i * 3 + 2] = ((rgb565 & 0x1f) * 527 + 23) >> 6; /* b */ | |
0a4e7cd2 | 660 | } |
0a4e7cd2 SK |
661 | } |
662 | ||
6a2a5aae | 663 | static inline void hwc_invalidate(SM501State *s, int crt) |
0a4e7cd2 | 664 | { |
6a2a5aae BZ |
665 | int w = get_width(s, crt); |
666 | int h = get_height(s, crt); | |
667 | int bpp = get_bpp(s, crt); | |
668 | int start = get_hwc_y(s, crt); | |
669 | int end = MIN(h, start + SM501_HWC_HEIGHT) + 1; | |
670 | ||
671 | start *= w * bpp; | |
672 | end *= w * bpp; | |
673 | ||
33159dd7 BZ |
674 | memory_region_set_dirty(&s->local_mem_region, |
675 | get_fb_addr(s, crt) + start, end - start); | |
0a4e7cd2 SK |
676 | } |
677 | ||
64f1603b | 678 | static void sm501_2d_operation(SM501State *s) |
604be200 | 679 | { |
6f8183b5 | 680 | int cmd = (s->twoD_control >> 16) & 0x1F; |
2824809b | 681 | int rtl = s->twoD_control & BIT(27); |
299778d5 BZ |
682 | int format = (s->twoD_stretch >> 20) & 3; |
683 | int bypp = 1 << format; /* bytes per pixel */ | |
684 | int rop_mode = (s->twoD_control >> 15) & 1; /* 1 for rop2, else rop3 */ | |
06cb926a | 685 | /* 1 if rop2 source is the pattern, otherwise the source is the bitmap */ |
299778d5 | 686 | int rop2_source_is_pattern = (s->twoD_control >> 14) & 1; |
debc7e7d | 687 | int rop = s->twoD_control & 0xFF; |
b15a22bb BZ |
688 | unsigned int dst_x = (s->twoD_destination >> 16) & 0x01FFF; |
689 | unsigned int dst_y = s->twoD_destination & 0xFFFF; | |
690 | unsigned int width = (s->twoD_dimension >> 16) & 0x1FFF; | |
691 | unsigned int height = s->twoD_dimension & 0xFFFF; | |
eb76243c | 692 | uint32_t dst_base = s->twoD_destination_base & 0x03FFFFFF; |
b15a22bb | 693 | unsigned int dst_pitch = (s->twoD_pitch >> 16) & 0x1FFF; |
eb76243c BZ |
694 | int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0; |
695 | int fb_len = get_width(s, crt) * get_height(s, crt) * get_bpp(s, crt); | |
c09b5158 | 696 | bool overlap = false, fallback = false; |
604be200 | 697 | |
6f8183b5 | 698 | if ((s->twoD_stretch >> 16) & 0xF) { |
e29da77e BZ |
699 | qemu_log_mask(LOG_UNIMP, "sm501: only XY addressing is supported.\n"); |
700 | return; | |
604be200 SK |
701 | } |
702 | ||
2824809b | 703 | if (s->twoD_source_base & BIT(27) || s->twoD_destination_base & BIT(27)) { |
e29da77e BZ |
704 | qemu_log_mask(LOG_UNIMP, "sm501: only local memory is supported.\n"); |
705 | return; | |
604be200 SK |
706 | } |
707 | ||
b15a22bb BZ |
708 | if (!dst_pitch) { |
709 | qemu_log_mask(LOG_GUEST_ERROR, "sm501: Zero dest pitch.\n"); | |
710 | return; | |
711 | } | |
712 | ||
713 | if (!width || !height) { | |
714 | qemu_log_mask(LOG_GUEST_ERROR, "sm501: Zero size 2D op.\n"); | |
715 | return; | |
716 | } | |
717 | ||
718 | if (rtl) { | |
719 | dst_x -= width - 1; | |
720 | dst_y -= height - 1; | |
721 | } | |
722 | ||
84ec3f94 | 723 | if (dst_base >= get_local_mem_size(s) || |
299778d5 BZ |
724 | dst_base + (dst_x + width + (dst_y + height) * dst_pitch) * bypp >= |
725 | get_local_mem_size(s)) { | |
b15a22bb BZ |
726 | qemu_log_mask(LOG_GUEST_ERROR, "sm501: 2D op dest is outside vram.\n"); |
727 | return; | |
728 | } | |
729 | ||
6f8183b5 | 730 | switch (cmd) { |
b15a22bb | 731 | case 0: /* BitBlt */ |
3d0b0962 | 732 | { |
fa70c287 | 733 | static uint32_t tmp_buf[16384]; |
b15a22bb BZ |
734 | unsigned int src_x = (s->twoD_source >> 16) & 0x01FFF; |
735 | unsigned int src_y = s->twoD_source & 0xFFFF; | |
3d0b0962 | 736 | uint32_t src_base = s->twoD_source_base & 0x03FFFFFF; |
b15a22bb BZ |
737 | unsigned int src_pitch = s->twoD_pitch & 0x1FFF; |
738 | ||
739 | if (!src_pitch) { | |
740 | qemu_log_mask(LOG_GUEST_ERROR, "sm501: Zero src pitch.\n"); | |
741 | return; | |
742 | } | |
743 | ||
744 | if (rtl) { | |
745 | src_x -= width - 1; | |
746 | src_y -= height - 1; | |
747 | } | |
748 | ||
84ec3f94 | 749 | if (src_base >= get_local_mem_size(s) || |
299778d5 BZ |
750 | src_base + (src_x + width + (src_y + height) * src_pitch) * bypp >= |
751 | get_local_mem_size(s)) { | |
b15a22bb BZ |
752 | qemu_log_mask(LOG_GUEST_ERROR, |
753 | "sm501: 2D op src is outside vram.\n"); | |
754 | return; | |
755 | } | |
756 | ||
757 | if ((rop_mode && rop == 0x5) || (!rop_mode && rop == 0x55)) { | |
8b0ce7f7 | 758 | /* DSTINVERT, is there a way to do this with pixman? */ |
b15a22bb BZ |
759 | unsigned int x, y, i; |
760 | uint8_t *d = s->local_mem + dst_base; | |
761 | ||
762 | for (y = 0; y < height; y++) { | |
299778d5 BZ |
763 | i = (dst_x + (dst_y + y) * dst_pitch) * bypp; |
764 | for (x = 0; x < width; x++, i += bypp) { | |
ba27110f | 765 | stn_he_p(&d[i], bypp, ~ldn_he_p(&d[i], bypp)); |
b15a22bb BZ |
766 | } |
767 | } | |
8b0ce7f7 BZ |
768 | } else if (!rop_mode && rop == 0x99) { |
769 | /* DSxn, is there a way to do this with pixman? */ | |
770 | unsigned int x, y, i, j; | |
771 | uint8_t *sp = s->local_mem + src_base; | |
772 | uint8_t *d = s->local_mem + dst_base; | |
773 | ||
774 | for (y = 0; y < height; y++) { | |
775 | i = (dst_x + (dst_y + y) * dst_pitch) * bypp; | |
776 | j = (src_x + (src_y + y) * src_pitch) * bypp; | |
777 | for (x = 0; x < width; x++, i += bypp, j += bypp) { | |
778 | stn_he_p(&d[i], bypp, | |
779 | ~(ldn_he_p(&sp[j], bypp) ^ ldn_he_p(&d[i], bypp))); | |
780 | } | |
781 | } | |
782 | } else if (!rop_mode && rop == 0xee) { | |
783 | /* SRCPAINT, is there a way to do this with pixman? */ | |
784 | unsigned int x, y, i, j; | |
785 | uint8_t *sp = s->local_mem + src_base; | |
786 | uint8_t *d = s->local_mem + dst_base; | |
787 | ||
788 | for (y = 0; y < height; y++) { | |
789 | i = (dst_x + (dst_y + y) * dst_pitch) * bypp; | |
790 | j = (src_x + (src_y + y) * src_pitch) * bypp; | |
791 | for (x = 0; x < width; x++, i += bypp, j += bypp) { | |
792 | stn_he_p(&d[i], bypp, | |
793 | ldn_he_p(&sp[j], bypp) | ldn_he_p(&d[i], bypp)); | |
794 | } | |
795 | } | |
b15a22bb BZ |
796 | } else { |
797 | /* Do copy src for unimplemented ops, better than unpainted area */ | |
798 | if ((rop_mode && (rop != 0xc || rop2_source_is_pattern)) || | |
799 | (!rop_mode && rop != 0xcc)) { | |
800 | qemu_log_mask(LOG_UNIMP, | |
801 | "sm501: rop%d op %x%s not implemented\n", | |
802 | (rop_mode ? 2 : 3), rop, | |
803 | (rop2_source_is_pattern ? | |
804 | " with pattern source" : "")); | |
805 | } | |
1cb62e36 BZ |
806 | /* Ignore no-op blits, some guests seem to do this */ |
807 | if (src_base == dst_base && src_pitch == dst_pitch && | |
808 | src_x == dst_x && src_y == dst_y) { | |
809 | break; | |
810 | } | |
c208085a BZ |
811 | /* Some clients also do 1 pixel blits, avoid overhead for these */ |
812 | if (width == 1 && height == 1) { | |
813 | unsigned int si = (src_x + src_y * src_pitch) * bypp; | |
814 | unsigned int di = (dst_x + dst_y * dst_pitch) * bypp; | |
815 | stn_he_p(&s->local_mem[dst_base + di], bypp, | |
816 | ldn_he_p(&s->local_mem[src_base + si], bypp)); | |
817 | break; | |
818 | } | |
9982c605 BZ |
819 | /* If reverse blit do simple check for overlaps */ |
820 | if (rtl && src_base == dst_base && src_pitch == dst_pitch) { | |
821 | overlap = (src_x < dst_x + width && src_x + width > dst_x && | |
822 | src_y < dst_y + height && src_y + height > dst_y); | |
823 | } else if (rtl) { | |
824 | unsigned int sb, se, db, de; | |
825 | sb = src_base + (src_x + src_y * src_pitch) * bypp; | |
826 | se = sb + (width + (height - 1) * src_pitch) * bypp; | |
827 | db = dst_base + (dst_x + dst_y * dst_pitch) * bypp; | |
828 | de = db + (width + (height - 1) * dst_pitch) * bypp; | |
829 | overlap = (db < se && sb < de); | |
830 | } | |
4e021052 | 831 | if (overlap && (s->use_pixman & BIT(2))) { |
9982c605 BZ |
832 | /* pixman can't do reverse blit: copy via temporary */ |
833 | int tmp_stride = DIV_ROUND_UP(width * bypp, sizeof(uint32_t)); | |
fa70c287 BZ |
834 | uint32_t *tmp = tmp_buf; |
835 | ||
836 | if (tmp_stride * sizeof(uint32_t) * height > sizeof(tmp_buf)) { | |
837 | tmp = g_malloc(tmp_stride * sizeof(uint32_t) * height); | |
fa70c287 | 838 | } |
c09b5158 BZ |
839 | fallback = !pixman_blt((uint32_t *)&s->local_mem[src_base], |
840 | tmp, | |
841 | src_pitch * bypp / sizeof(uint32_t), | |
842 | tmp_stride, | |
843 | 8 * bypp, 8 * bypp, | |
844 | src_x, src_y, 0, 0, width, height); | |
845 | if (!fallback) { | |
846 | fallback = !pixman_blt(tmp, | |
847 | (uint32_t *)&s->local_mem[dst_base], | |
848 | tmp_stride, | |
849 | dst_pitch * bypp / sizeof(uint32_t), | |
850 | 8 * bypp, 8 * bypp, | |
851 | 0, 0, dst_x, dst_y, width, height); | |
852 | } | |
4decaad9 | 853 | if (tmp != tmp_buf) { |
fa70c287 BZ |
854 | g_free(tmp); |
855 | } | |
4e021052 | 856 | } else if (!overlap && (s->use_pixman & BIT(1))) { |
c09b5158 BZ |
857 | fallback = !pixman_blt((uint32_t *)&s->local_mem[src_base], |
858 | (uint32_t *)&s->local_mem[dst_base], | |
859 | src_pitch * bypp / sizeof(uint32_t), | |
860 | dst_pitch * bypp / sizeof(uint32_t), | |
861 | 8 * bypp, 8 * bypp, src_x, src_y, | |
862 | dst_x, dst_y, width, height); | |
4e021052 BZ |
863 | } else { |
864 | fallback = true; | |
c09b5158 BZ |
865 | } |
866 | if (fallback) { | |
867 | uint8_t *sp = s->local_mem + src_base; | |
868 | uint8_t *d = s->local_mem + dst_base; | |
869 | unsigned int y, i, j; | |
870 | for (y = 0; y < height; y++) { | |
871 | if (overlap) { /* overlap also means rtl */ | |
872 | i = (dst_y + height - 1 - y) * dst_pitch; | |
873 | i = (dst_x + i) * bypp; | |
874 | j = (src_y + height - 1 - y) * src_pitch; | |
875 | j = (src_x + j) * bypp; | |
876 | memmove(&d[i], &sp[j], width * bypp); | |
877 | } else { | |
878 | i = (dst_x + (dst_y + y) * dst_pitch) * bypp; | |
879 | j = (src_x + (src_y + y) * src_pitch) * bypp; | |
880 | memcpy(&d[i], &sp[j], width * bypp); | |
881 | } | |
882 | } | |
b15a22bb | 883 | } |
07d8a50c AJ |
884 | } |
885 | break; | |
3d0b0962 | 886 | } |
b15a22bb | 887 | case 1: /* Rectangle Fill */ |
3d0b0962 BZ |
888 | { |
889 | uint32_t color = s->twoD_foreground; | |
890 | ||
b15a22bb | 891 | if (format == 2) { |
f3a60058 | 892 | color = cpu_to_le32(color); |
b15a22bb BZ |
893 | } else if (format == 1) { |
894 | color = cpu_to_le16(color); | |
604be200 | 895 | } |
b15a22bb | 896 | |
4e021052 | 897 | if (!(s->use_pixman & BIT(0)) || (width == 1 && height == 1) || |
c09b5158 BZ |
898 | !pixman_fill((uint32_t *)&s->local_mem[dst_base], |
899 | dst_pitch * bypp / sizeof(uint32_t), 8 * bypp, | |
900 | dst_x, dst_y, width, height, color)) { | |
901 | /* fallback when pixman failed or we don't want to call it */ | |
902 | uint8_t *d = s->local_mem + dst_base; | |
903 | unsigned int x, y, i; | |
1b336bb6 | 904 | for (y = 0; y < height; y++) { |
c09b5158 BZ |
905 | i = (dst_x + (dst_y + y) * dst_pitch) * bypp; |
906 | for (x = 0; x < width; x++, i += bypp) { | |
907 | stn_he_p(&d[i], bypp, color); | |
908 | } | |
909 | } | |
c208085a | 910 | } |
604be200 | 911 | break; |
3d0b0962 | 912 | } |
604be200 | 913 | default: |
e29da77e | 914 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented 2D operation: %d\n", |
6f8183b5 | 915 | cmd); |
e29da77e | 916 | return; |
604be200 | 917 | } |
eb76243c BZ |
918 | |
919 | if (dst_base >= get_fb_addr(s, crt) && | |
920 | dst_base <= get_fb_addr(s, crt) + fb_len) { | |
6f8183b5 | 921 | int dst_len = MIN(fb_len, ((dst_y + height - 1) * dst_pitch + |
299778d5 | 922 | dst_x + width) * bypp); |
eb76243c BZ |
923 | if (dst_len) { |
924 | memory_region_set_dirty(&s->local_mem_region, dst_base, dst_len); | |
925 | } | |
926 | } | |
604be200 SK |
927 | } |
928 | ||
a8170e5e | 929 | static uint64_t sm501_system_config_read(void *opaque, hwaddr addr, |
25793bfa | 930 | unsigned size) |
ffd39257 | 931 | { |
57ad5b5a | 932 | SM501State *s = opaque; |
ffd39257 | 933 | uint32_t ret = 0; |
ffd39257 | 934 | |
64f1603b | 935 | switch (addr) { |
ffd39257 | 936 | case SM501_SYSTEM_CONTROL: |
64f1603b BZ |
937 | ret = s->system_control; |
938 | break; | |
ffd39257 | 939 | case SM501_MISC_CONTROL: |
64f1603b BZ |
940 | ret = s->misc_control; |
941 | break; | |
ffd39257 | 942 | case SM501_GPIO31_0_CONTROL: |
64f1603b BZ |
943 | ret = s->gpio_31_0_control; |
944 | break; | |
ffd39257 | 945 | case SM501_GPIO63_32_CONTROL: |
64f1603b BZ |
946 | ret = s->gpio_63_32_control; |
947 | break; | |
ffd39257 | 948 | case SM501_DEVICEID: |
64f1603b BZ |
949 | ret = 0x050100A0; |
950 | break; | |
ffd39257 | 951 | case SM501_DRAM_CONTROL: |
64f1603b BZ |
952 | ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13; |
953 | break; | |
70e46ca8 BZ |
954 | case SM501_ARBTRTN_CONTROL: |
955 | ret = s->arbitration_control; | |
956 | break; | |
5690d9ec BZ |
957 | case SM501_COMMAND_LIST_STATUS: |
958 | ret = 0x00180002; /* FIFOs are empty, everything idle */ | |
cf4969ec | 959 | break; |
ffd39257 | 960 | case SM501_IRQ_MASK: |
64f1603b BZ |
961 | ret = s->irq_mask; |
962 | break; | |
ffd39257 | 963 | case SM501_MISC_TIMING: |
64f1603b BZ |
964 | /* TODO : simulate gate control */ |
965 | ret = s->misc_timing; | |
966 | break; | |
ffd39257 | 967 | case SM501_CURRENT_GATE: |
64f1603b BZ |
968 | /* TODO : simulate gate control */ |
969 | ret = 0x00021807; | |
970 | break; | |
ffd39257 | 971 | case SM501_CURRENT_CLOCK: |
64f1603b BZ |
972 | ret = 0x2A1A0A09; |
973 | break; | |
ffd39257 | 974 | case SM501_POWER_MODE_CONTROL: |
64f1603b BZ |
975 | ret = s->power_mode_control; |
976 | break; | |
5690d9ec BZ |
977 | case SM501_ENDIAN_CONTROL: |
978 | ret = 0; /* Only default little endian mode is supported */ | |
979 | break; | |
ffd39257 BS |
980 | |
981 | default: | |
e29da77e BZ |
982 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented system config" |
983 | "register read. addr=%" HWADDR_PRIx "\n", addr); | |
ffd39257 | 984 | } |
d8327a68 | 985 | trace_sm501_system_config_read(addr, ret); |
ffd39257 BS |
986 | return ret; |
987 | } | |
988 | ||
a8170e5e | 989 | static void sm501_system_config_write(void *opaque, hwaddr addr, |
25793bfa | 990 | uint64_t value, unsigned size) |
ffd39257 | 991 | { |
57ad5b5a | 992 | SM501State *s = opaque; |
ffd39257 | 993 | |
d8327a68 | 994 | trace_sm501_system_config_write((uint32_t)addr, (uint32_t)value); |
64f1603b | 995 | switch (addr) { |
ffd39257 | 996 | case SM501_SYSTEM_CONTROL: |
2100b6b2 BZ |
997 | s->system_control &= 0x10DB0000; |
998 | s->system_control |= value & 0xEF00B8F7; | |
64f1603b | 999 | break; |
ffd39257 | 1000 | case SM501_MISC_CONTROL: |
2100b6b2 BZ |
1001 | s->misc_control &= 0xEF; |
1002 | s->misc_control |= value & 0xFF7FFF10; | |
64f1603b | 1003 | break; |
ffd39257 | 1004 | case SM501_GPIO31_0_CONTROL: |
64f1603b BZ |
1005 | s->gpio_31_0_control = value; |
1006 | break; | |
ffd39257 | 1007 | case SM501_GPIO63_32_CONTROL: |
2100b6b2 | 1008 | s->gpio_63_32_control = value & 0xFF80FFFF; |
64f1603b | 1009 | break; |
ffd39257 | 1010 | case SM501_DRAM_CONTROL: |
64f1603b BZ |
1011 | s->local_mem_size_index = (value >> 13) & 0x7; |
1012 | /* TODO : check validity of size change */ | |
2100b6b2 BZ |
1013 | s->dram_control &= 0x80000000; |
1014 | s->dram_control |= value & 0x7FFFFFC3; | |
64f1603b | 1015 | break; |
70e46ca8 | 1016 | case SM501_ARBTRTN_CONTROL: |
2100b6b2 | 1017 | s->arbitration_control = value & 0x37777777; |
70e46ca8 | 1018 | break; |
ffd39257 | 1019 | case SM501_IRQ_MASK: |
2100b6b2 | 1020 | s->irq_mask = value & 0xFFDF3F5F; |
64f1603b | 1021 | break; |
ffd39257 | 1022 | case SM501_MISC_TIMING: |
64f1603b BZ |
1023 | s->misc_timing = value & 0xF31F1FFF; |
1024 | break; | |
ffd39257 BS |
1025 | case SM501_POWER_MODE_0_GATE: |
1026 | case SM501_POWER_MODE_1_GATE: | |
1027 | case SM501_POWER_MODE_0_CLOCK: | |
1028 | case SM501_POWER_MODE_1_CLOCK: | |
64f1603b BZ |
1029 | /* TODO : simulate gate & clock control */ |
1030 | break; | |
ffd39257 | 1031 | case SM501_POWER_MODE_CONTROL: |
64f1603b BZ |
1032 | s->power_mode_control = value & 0x00000003; |
1033 | break; | |
5690d9ec BZ |
1034 | case SM501_ENDIAN_CONTROL: |
1035 | if (value & 0x00000001) { | |
e29da77e BZ |
1036 | qemu_log_mask(LOG_UNIMP, "sm501: system config big endian mode not" |
1037 | " implemented.\n"); | |
5690d9ec BZ |
1038 | } |
1039 | break; | |
ffd39257 BS |
1040 | |
1041 | default: | |
e29da77e BZ |
1042 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented system config" |
1043 | "register write. addr=%" HWADDR_PRIx | |
1044 | ", val=%" PRIx64 "\n", addr, value); | |
ffd39257 BS |
1045 | } |
1046 | } | |
1047 | ||
25793bfa AK |
1048 | static const MemoryRegionOps sm501_system_config_ops = { |
1049 | .read = sm501_system_config_read, | |
1050 | .write = sm501_system_config_write, | |
1051 | .valid = { | |
1052 | .min_access_size = 4, | |
1053 | .max_access_size = 4, | |
1054 | }, | |
afef2e1d | 1055 | .endianness = DEVICE_LITTLE_ENDIAN, |
ffd39257 BS |
1056 | }; |
1057 | ||
4a1f253a BZ |
1058 | static uint64_t sm501_i2c_read(void *opaque, hwaddr addr, unsigned size) |
1059 | { | |
57ad5b5a | 1060 | SM501State *s = opaque; |
4a1f253a BZ |
1061 | uint8_t ret = 0; |
1062 | ||
1063 | switch (addr) { | |
1064 | case SM501_I2C_BYTE_COUNT: | |
1065 | ret = s->i2c_byte_count; | |
1066 | break; | |
1067 | case SM501_I2C_STATUS: | |
1068 | ret = s->i2c_status; | |
1069 | break; | |
1070 | case SM501_I2C_SLAVE_ADDRESS: | |
1071 | ret = s->i2c_addr; | |
1072 | break; | |
1073 | case SM501_I2C_DATA ... SM501_I2C_DATA + 15: | |
1074 | ret = s->i2c_data[addr - SM501_I2C_DATA]; | |
1075 | break; | |
1076 | default: | |
1077 | qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register read." | |
1078 | " addr=0x%" HWADDR_PRIx "\n", addr); | |
1079 | } | |
d8327a68 | 1080 | trace_sm501_i2c_read((uint32_t)addr, ret); |
4a1f253a BZ |
1081 | return ret; |
1082 | } | |
1083 | ||
1084 | static void sm501_i2c_write(void *opaque, hwaddr addr, uint64_t value, | |
1085 | unsigned size) | |
1086 | { | |
57ad5b5a | 1087 | SM501State *s = opaque; |
4a1f253a | 1088 | |
d8327a68 | 1089 | trace_sm501_i2c_write((uint32_t)addr, (uint32_t)value); |
4a1f253a BZ |
1090 | switch (addr) { |
1091 | case SM501_I2C_BYTE_COUNT: | |
1092 | s->i2c_byte_count = value & 0xf; | |
1093 | break; | |
1094 | case SM501_I2C_CONTROL: | |
1095 | if (value & SM501_I2C_CONTROL_ENABLE) { | |
1096 | if (value & SM501_I2C_CONTROL_START) { | |
4e7019bd | 1097 | bool is_recv = s->i2c_addr & 1; |
4a1f253a BZ |
1098 | int res = i2c_start_transfer(s->i2c_bus, |
1099 | s->i2c_addr >> 1, | |
4e7019bd | 1100 | is_recv); |
e91113d0 PMD |
1101 | if (res) { |
1102 | s->i2c_status |= SM501_I2C_STATUS_ERROR; | |
1103 | } else { | |
4a1f253a | 1104 | int i; |
4a1f253a | 1105 | for (i = 0; i <= s->i2c_byte_count; i++) { |
4e7019bd PMD |
1106 | if (is_recv) { |
1107 | s->i2c_data[i] = i2c_recv(s->i2c_bus); | |
1108 | } else if (i2c_send(s->i2c_bus, s->i2c_data[i]) < 0) { | |
6730df05 | 1109 | s->i2c_status |= SM501_I2C_STATUS_ERROR; |
4a1f253a BZ |
1110 | return; |
1111 | } | |
1112 | } | |
1113 | if (i) { | |
4a1f253a BZ |
1114 | s->i2c_status = SM501_I2C_STATUS_COMPLETE; |
1115 | } | |
1116 | } | |
1117 | } else { | |
4a1f253a BZ |
1118 | i2c_end_transfer(s->i2c_bus); |
1119 | s->i2c_status &= ~SM501_I2C_STATUS_ERROR; | |
1120 | } | |
1121 | } | |
1122 | break; | |
1123 | case SM501_I2C_RESET: | |
1124 | if ((value & SM501_I2C_RESET_ERROR) == 0) { | |
1125 | s->i2c_status &= ~SM501_I2C_STATUS_ERROR; | |
1126 | } | |
1127 | break; | |
1128 | case SM501_I2C_SLAVE_ADDRESS: | |
1129 | s->i2c_addr = value & 0xff; | |
1130 | break; | |
1131 | case SM501_I2C_DATA ... SM501_I2C_DATA + 15: | |
1132 | s->i2c_data[addr - SM501_I2C_DATA] = value & 0xff; | |
1133 | break; | |
1134 | default: | |
1135 | qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register write. " | |
1136 | "addr=0x%" HWADDR_PRIx " val=%" PRIx64 "\n", addr, value); | |
1137 | } | |
1138 | } | |
1139 | ||
1140 | static const MemoryRegionOps sm501_i2c_ops = { | |
1141 | .read = sm501_i2c_read, | |
1142 | .write = sm501_i2c_write, | |
1143 | .valid = { | |
1144 | .min_access_size = 1, | |
1145 | .max_access_size = 1, | |
1146 | }, | |
1147 | .impl = { | |
1148 | .min_access_size = 1, | |
1149 | .max_access_size = 1, | |
1150 | }, | |
1151 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1152 | }; | |
1153 | ||
a8170e5e | 1154 | static uint32_t sm501_palette_read(void *opaque, hwaddr addr) |
486579de | 1155 | { |
57ad5b5a | 1156 | SM501State *s = opaque; |
d8327a68 BZ |
1157 | |
1158 | trace_sm501_palette_read((uint32_t)addr); | |
486579de AZ |
1159 | |
1160 | /* TODO : consider BYTE/WORD access */ | |
1161 | /* TODO : consider endian */ | |
1162 | ||
45416789 | 1163 | assert(range_covers_byte(0, 0x400 * 3, addr)); |
64f1603b | 1164 | return *(uint32_t *)&s->dc_palette[addr]; |
486579de AZ |
1165 | } |
1166 | ||
64f1603b BZ |
1167 | static void sm501_palette_write(void *opaque, hwaddr addr, |
1168 | uint32_t value) | |
486579de | 1169 | { |
57ad5b5a | 1170 | SM501State *s = opaque; |
d8327a68 BZ |
1171 | |
1172 | trace_sm501_palette_write((uint32_t)addr, value); | |
486579de AZ |
1173 | |
1174 | /* TODO : consider BYTE/WORD access */ | |
1175 | /* TODO : consider endian */ | |
1176 | ||
45416789 | 1177 | assert(range_covers_byte(0, 0x400 * 3, addr)); |
64f1603b | 1178 | *(uint32_t *)&s->dc_palette[addr] = value; |
d2733559 | 1179 | s->do_full_update = true; |
486579de AZ |
1180 | } |
1181 | ||
a8170e5e | 1182 | static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr, |
25793bfa | 1183 | unsigned size) |
ffd39257 | 1184 | { |
57ad5b5a | 1185 | SM501State *s = opaque; |
ffd39257 | 1186 | uint32_t ret = 0; |
ffd39257 | 1187 | |
64f1603b | 1188 | switch (addr) { |
ffd39257 BS |
1189 | |
1190 | case SM501_DC_PANEL_CONTROL: | |
64f1603b BZ |
1191 | ret = s->dc_panel_control; |
1192 | break; | |
ffd39257 | 1193 | case SM501_DC_PANEL_PANNING_CONTROL: |
64f1603b BZ |
1194 | ret = s->dc_panel_panning_control; |
1195 | break; | |
5690d9ec BZ |
1196 | case SM501_DC_PANEL_COLOR_KEY: |
1197 | /* Not implemented yet */ | |
1198 | break; | |
ffd39257 | 1199 | case SM501_DC_PANEL_FB_ADDR: |
64f1603b BZ |
1200 | ret = s->dc_panel_fb_addr; |
1201 | break; | |
ffd39257 | 1202 | case SM501_DC_PANEL_FB_OFFSET: |
64f1603b BZ |
1203 | ret = s->dc_panel_fb_offset; |
1204 | break; | |
ffd39257 | 1205 | case SM501_DC_PANEL_FB_WIDTH: |
64f1603b BZ |
1206 | ret = s->dc_panel_fb_width; |
1207 | break; | |
ffd39257 | 1208 | case SM501_DC_PANEL_FB_HEIGHT: |
64f1603b BZ |
1209 | ret = s->dc_panel_fb_height; |
1210 | break; | |
ffd39257 | 1211 | case SM501_DC_PANEL_TL_LOC: |
64f1603b BZ |
1212 | ret = s->dc_panel_tl_location; |
1213 | break; | |
ffd39257 | 1214 | case SM501_DC_PANEL_BR_LOC: |
64f1603b BZ |
1215 | ret = s->dc_panel_br_location; |
1216 | break; | |
ffd39257 BS |
1217 | |
1218 | case SM501_DC_PANEL_H_TOT: | |
64f1603b BZ |
1219 | ret = s->dc_panel_h_total; |
1220 | break; | |
ffd39257 | 1221 | case SM501_DC_PANEL_H_SYNC: |
64f1603b BZ |
1222 | ret = s->dc_panel_h_sync; |
1223 | break; | |
ffd39257 | 1224 | case SM501_DC_PANEL_V_TOT: |
64f1603b BZ |
1225 | ret = s->dc_panel_v_total; |
1226 | break; | |
ffd39257 | 1227 | case SM501_DC_PANEL_V_SYNC: |
64f1603b BZ |
1228 | ret = s->dc_panel_v_sync; |
1229 | break; | |
ffd39257 | 1230 | |
a45de179 BZ |
1231 | case SM501_DC_PANEL_HWC_ADDR: |
1232 | ret = s->dc_panel_hwc_addr; | |
1233 | break; | |
1234 | case SM501_DC_PANEL_HWC_LOC: | |
1235 | ret = s->dc_panel_hwc_location; | |
1236 | break; | |
1237 | case SM501_DC_PANEL_HWC_COLOR_1_2: | |
1238 | ret = s->dc_panel_hwc_color_1_2; | |
1239 | break; | |
1240 | case SM501_DC_PANEL_HWC_COLOR_3: | |
1241 | ret = s->dc_panel_hwc_color_3; | |
1242 | break; | |
1243 | ||
b612a49d BZ |
1244 | case SM501_DC_VIDEO_CONTROL: |
1245 | ret = s->dc_video_control; | |
1246 | break; | |
1247 | ||
ffd39257 | 1248 | case SM501_DC_CRT_CONTROL: |
64f1603b BZ |
1249 | ret = s->dc_crt_control; |
1250 | break; | |
ffd39257 | 1251 | case SM501_DC_CRT_FB_ADDR: |
64f1603b BZ |
1252 | ret = s->dc_crt_fb_addr; |
1253 | break; | |
ffd39257 | 1254 | case SM501_DC_CRT_FB_OFFSET: |
64f1603b BZ |
1255 | ret = s->dc_crt_fb_offset; |
1256 | break; | |
ffd39257 | 1257 | case SM501_DC_CRT_H_TOT: |
64f1603b BZ |
1258 | ret = s->dc_crt_h_total; |
1259 | break; | |
ffd39257 | 1260 | case SM501_DC_CRT_H_SYNC: |
64f1603b BZ |
1261 | ret = s->dc_crt_h_sync; |
1262 | break; | |
ffd39257 | 1263 | case SM501_DC_CRT_V_TOT: |
64f1603b BZ |
1264 | ret = s->dc_crt_v_total; |
1265 | break; | |
ffd39257 | 1266 | case SM501_DC_CRT_V_SYNC: |
64f1603b BZ |
1267 | ret = s->dc_crt_v_sync; |
1268 | break; | |
ffd39257 BS |
1269 | |
1270 | case SM501_DC_CRT_HWC_ADDR: | |
64f1603b BZ |
1271 | ret = s->dc_crt_hwc_addr; |
1272 | break; | |
ffd39257 | 1273 | case SM501_DC_CRT_HWC_LOC: |
64f1603b BZ |
1274 | ret = s->dc_crt_hwc_location; |
1275 | break; | |
ffd39257 | 1276 | case SM501_DC_CRT_HWC_COLOR_1_2: |
64f1603b BZ |
1277 | ret = s->dc_crt_hwc_color_1_2; |
1278 | break; | |
ffd39257 | 1279 | case SM501_DC_CRT_HWC_COLOR_3: |
64f1603b BZ |
1280 | ret = s->dc_crt_hwc_color_3; |
1281 | break; | |
ffd39257 | 1282 | |
64f1603b | 1283 | case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4: |
486579de AZ |
1284 | ret = sm501_palette_read(opaque, addr - SM501_DC_PANEL_PALETTE); |
1285 | break; | |
1286 | ||
ffd39257 | 1287 | default: |
e29da77e BZ |
1288 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register " |
1289 | "read. addr=%" HWADDR_PRIx "\n", addr); | |
ffd39257 | 1290 | } |
d8327a68 | 1291 | trace_sm501_disp_ctrl_read((uint32_t)addr, ret); |
ffd39257 BS |
1292 | return ret; |
1293 | } | |
1294 | ||
a8170e5e | 1295 | static void sm501_disp_ctrl_write(void *opaque, hwaddr addr, |
25793bfa | 1296 | uint64_t value, unsigned size) |
ffd39257 | 1297 | { |
57ad5b5a | 1298 | SM501State *s = opaque; |
ffd39257 | 1299 | |
d8327a68 | 1300 | trace_sm501_disp_ctrl_write((uint32_t)addr, (uint32_t)value); |
64f1603b | 1301 | switch (addr) { |
ffd39257 | 1302 | case SM501_DC_PANEL_CONTROL: |
64f1603b BZ |
1303 | s->dc_panel_control = value & 0x0FFF73FF; |
1304 | break; | |
ffd39257 | 1305 | case SM501_DC_PANEL_PANNING_CONTROL: |
64f1603b BZ |
1306 | s->dc_panel_panning_control = value & 0xFF3FFF3F; |
1307 | break; | |
5690d9ec BZ |
1308 | case SM501_DC_PANEL_COLOR_KEY: |
1309 | /* Not implemented yet */ | |
1310 | break; | |
ffd39257 | 1311 | case SM501_DC_PANEL_FB_ADDR: |
64f1603b | 1312 | s->dc_panel_fb_addr = value & 0x8FFFFFF0; |
33159dd7 BZ |
1313 | if (value & 0x8000000) { |
1314 | qemu_log_mask(LOG_UNIMP, "Panel external memory not supported\n"); | |
1315 | } | |
593a1cdd | 1316 | s->do_full_update = true; |
64f1603b | 1317 | break; |
ffd39257 | 1318 | case SM501_DC_PANEL_FB_OFFSET: |
64f1603b BZ |
1319 | s->dc_panel_fb_offset = value & 0x3FF03FF0; |
1320 | break; | |
ffd39257 | 1321 | case SM501_DC_PANEL_FB_WIDTH: |
64f1603b BZ |
1322 | s->dc_panel_fb_width = value & 0x0FFF0FFF; |
1323 | break; | |
ffd39257 | 1324 | case SM501_DC_PANEL_FB_HEIGHT: |
64f1603b BZ |
1325 | s->dc_panel_fb_height = value & 0x0FFF0FFF; |
1326 | break; | |
ffd39257 | 1327 | case SM501_DC_PANEL_TL_LOC: |
64f1603b BZ |
1328 | s->dc_panel_tl_location = value & 0x07FF07FF; |
1329 | break; | |
ffd39257 | 1330 | case SM501_DC_PANEL_BR_LOC: |
64f1603b BZ |
1331 | s->dc_panel_br_location = value & 0x07FF07FF; |
1332 | break; | |
ffd39257 BS |
1333 | |
1334 | case SM501_DC_PANEL_H_TOT: | |
64f1603b BZ |
1335 | s->dc_panel_h_total = value & 0x0FFF0FFF; |
1336 | break; | |
ffd39257 | 1337 | case SM501_DC_PANEL_H_SYNC: |
64f1603b BZ |
1338 | s->dc_panel_h_sync = value & 0x00FF0FFF; |
1339 | break; | |
ffd39257 | 1340 | case SM501_DC_PANEL_V_TOT: |
64f1603b BZ |
1341 | s->dc_panel_v_total = value & 0x0FFF0FFF; |
1342 | break; | |
ffd39257 | 1343 | case SM501_DC_PANEL_V_SYNC: |
64f1603b BZ |
1344 | s->dc_panel_v_sync = value & 0x003F0FFF; |
1345 | break; | |
ffd39257 BS |
1346 | |
1347 | case SM501_DC_PANEL_HWC_ADDR: | |
6a2a5aae BZ |
1348 | value &= 0x8FFFFFF0; |
1349 | if (value != s->dc_panel_hwc_addr) { | |
1350 | hwc_invalidate(s, 0); | |
1351 | s->dc_panel_hwc_addr = value; | |
1352 | } | |
64f1603b | 1353 | break; |
ffd39257 | 1354 | case SM501_DC_PANEL_HWC_LOC: |
6a2a5aae BZ |
1355 | value &= 0x0FFF0FFF; |
1356 | if (value != s->dc_panel_hwc_location) { | |
1357 | hwc_invalidate(s, 0); | |
1358 | s->dc_panel_hwc_location = value; | |
1359 | } | |
64f1603b | 1360 | break; |
ffd39257 | 1361 | case SM501_DC_PANEL_HWC_COLOR_1_2: |
64f1603b BZ |
1362 | s->dc_panel_hwc_color_1_2 = value; |
1363 | break; | |
ffd39257 | 1364 | case SM501_DC_PANEL_HWC_COLOR_3: |
64f1603b BZ |
1365 | s->dc_panel_hwc_color_3 = value & 0x0000FFFF; |
1366 | break; | |
ffd39257 | 1367 | |
b612a49d BZ |
1368 | case SM501_DC_VIDEO_CONTROL: |
1369 | s->dc_video_control = value & 0x00037FFF; | |
1370 | break; | |
1371 | ||
ffd39257 | 1372 | case SM501_DC_CRT_CONTROL: |
64f1603b BZ |
1373 | s->dc_crt_control = value & 0x0003FFFF; |
1374 | break; | |
ffd39257 | 1375 | case SM501_DC_CRT_FB_ADDR: |
64f1603b | 1376 | s->dc_crt_fb_addr = value & 0x8FFFFFF0; |
33159dd7 BZ |
1377 | if (value & 0x8000000) { |
1378 | qemu_log_mask(LOG_UNIMP, "CRT external memory not supported\n"); | |
1379 | } | |
593a1cdd | 1380 | s->do_full_update = true; |
64f1603b | 1381 | break; |
ffd39257 | 1382 | case SM501_DC_CRT_FB_OFFSET: |
64f1603b BZ |
1383 | s->dc_crt_fb_offset = value & 0x3FF03FF0; |
1384 | break; | |
ffd39257 | 1385 | case SM501_DC_CRT_H_TOT: |
64f1603b BZ |
1386 | s->dc_crt_h_total = value & 0x0FFF0FFF; |
1387 | break; | |
ffd39257 | 1388 | case SM501_DC_CRT_H_SYNC: |
64f1603b BZ |
1389 | s->dc_crt_h_sync = value & 0x00FF0FFF; |
1390 | break; | |
ffd39257 | 1391 | case SM501_DC_CRT_V_TOT: |
64f1603b BZ |
1392 | s->dc_crt_v_total = value & 0x0FFF0FFF; |
1393 | break; | |
ffd39257 | 1394 | case SM501_DC_CRT_V_SYNC: |
64f1603b BZ |
1395 | s->dc_crt_v_sync = value & 0x003F0FFF; |
1396 | break; | |
ffd39257 BS |
1397 | |
1398 | case SM501_DC_CRT_HWC_ADDR: | |
6a2a5aae BZ |
1399 | value &= 0x8FFFFFF0; |
1400 | if (value != s->dc_crt_hwc_addr) { | |
1401 | hwc_invalidate(s, 1); | |
1402 | s->dc_crt_hwc_addr = value; | |
1403 | } | |
64f1603b | 1404 | break; |
ffd39257 | 1405 | case SM501_DC_CRT_HWC_LOC: |
6a2a5aae BZ |
1406 | value &= 0x0FFF0FFF; |
1407 | if (value != s->dc_crt_hwc_location) { | |
1408 | hwc_invalidate(s, 1); | |
1409 | s->dc_crt_hwc_location = value; | |
1410 | } | |
64f1603b | 1411 | break; |
ffd39257 | 1412 | case SM501_DC_CRT_HWC_COLOR_1_2: |
64f1603b BZ |
1413 | s->dc_crt_hwc_color_1_2 = value; |
1414 | break; | |
ffd39257 | 1415 | case SM501_DC_CRT_HWC_COLOR_3: |
64f1603b BZ |
1416 | s->dc_crt_hwc_color_3 = value & 0x0000FFFF; |
1417 | break; | |
ffd39257 | 1418 | |
64f1603b | 1419 | case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4: |
486579de AZ |
1420 | sm501_palette_write(opaque, addr - SM501_DC_PANEL_PALETTE, value); |
1421 | break; | |
1422 | ||
ffd39257 | 1423 | default: |
e29da77e BZ |
1424 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register " |
1425 | "write. addr=%" HWADDR_PRIx | |
1426 | ", val=%" PRIx64 "\n", addr, value); | |
ffd39257 BS |
1427 | } |
1428 | } | |
1429 | ||
25793bfa AK |
1430 | static const MemoryRegionOps sm501_disp_ctrl_ops = { |
1431 | .read = sm501_disp_ctrl_read, | |
1432 | .write = sm501_disp_ctrl_write, | |
1433 | .valid = { | |
1434 | .min_access_size = 4, | |
1435 | .max_access_size = 4, | |
1436 | }, | |
afef2e1d | 1437 | .endianness = DEVICE_LITTLE_ENDIAN, |
ffd39257 BS |
1438 | }; |
1439 | ||
a8170e5e | 1440 | static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr, |
25793bfa | 1441 | unsigned size) |
604be200 | 1442 | { |
57ad5b5a | 1443 | SM501State *s = opaque; |
604be200 | 1444 | uint32_t ret = 0; |
604be200 | 1445 | |
64f1603b | 1446 | switch (addr) { |
b612a49d BZ |
1447 | case SM501_2D_SOURCE: |
1448 | ret = s->twoD_source; | |
1449 | break; | |
1450 | case SM501_2D_DESTINATION: | |
1451 | ret = s->twoD_destination; | |
1452 | break; | |
1453 | case SM501_2D_DIMENSION: | |
1454 | ret = s->twoD_dimension; | |
1455 | break; | |
1456 | case SM501_2D_CONTROL: | |
1457 | ret = s->twoD_control; | |
1458 | break; | |
1459 | case SM501_2D_PITCH: | |
1460 | ret = s->twoD_pitch; | |
1461 | break; | |
1462 | case SM501_2D_FOREGROUND: | |
1463 | ret = s->twoD_foreground; | |
1464 | break; | |
1465 | case SM501_2D_BACKGROUND: | |
1466 | ret = s->twoD_background; | |
1467 | break; | |
1468 | case SM501_2D_STRETCH: | |
1469 | ret = s->twoD_stretch; | |
1470 | break; | |
1471 | case SM501_2D_COLOR_COMPARE: | |
1472 | ret = s->twoD_color_compare; | |
1473 | break; | |
1474 | case SM501_2D_COLOR_COMPARE_MASK: | |
1475 | ret = s->twoD_color_compare_mask; | |
1476 | break; | |
1477 | case SM501_2D_MASK: | |
1478 | ret = s->twoD_mask; | |
1479 | break; | |
1480 | case SM501_2D_CLIP_TL: | |
1481 | ret = s->twoD_clip_tl; | |
1482 | break; | |
1483 | case SM501_2D_CLIP_BR: | |
1484 | ret = s->twoD_clip_br; | |
1485 | break; | |
1486 | case SM501_2D_MONO_PATTERN_LOW: | |
1487 | ret = s->twoD_mono_pattern_low; | |
1488 | break; | |
1489 | case SM501_2D_MONO_PATTERN_HIGH: | |
1490 | ret = s->twoD_mono_pattern_high; | |
1491 | break; | |
1492 | case SM501_2D_WINDOW_WIDTH: | |
1493 | ret = s->twoD_window_width; | |
1494 | break; | |
604be200 SK |
1495 | case SM501_2D_SOURCE_BASE: |
1496 | ret = s->twoD_source_base; | |
1497 | break; | |
b612a49d BZ |
1498 | case SM501_2D_DESTINATION_BASE: |
1499 | ret = s->twoD_destination_base; | |
1500 | break; | |
1501 | case SM501_2D_ALPHA: | |
1502 | ret = s->twoD_alpha; | |
1503 | break; | |
1504 | case SM501_2D_WRAP: | |
1505 | ret = s->twoD_wrap; | |
1506 | break; | |
1507 | case SM501_2D_STATUS: | |
1508 | ret = 0; /* Should return interrupt status */ | |
1509 | break; | |
604be200 | 1510 | default: |
e29da77e BZ |
1511 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register " |
1512 | "read. addr=%" HWADDR_PRIx "\n", addr); | |
604be200 | 1513 | } |
d8327a68 | 1514 | trace_sm501_2d_engine_read((uint32_t)addr, ret); |
604be200 SK |
1515 | return ret; |
1516 | } | |
1517 | ||
a8170e5e | 1518 | static void sm501_2d_engine_write(void *opaque, hwaddr addr, |
25793bfa | 1519 | uint64_t value, unsigned size) |
604be200 | 1520 | { |
57ad5b5a | 1521 | SM501State *s = opaque; |
604be200 | 1522 | |
d8327a68 | 1523 | trace_sm501_2d_engine_write((uint32_t)addr, (uint32_t)value); |
64f1603b | 1524 | switch (addr) { |
07d8a50c AJ |
1525 | case SM501_2D_SOURCE: |
1526 | s->twoD_source = value; | |
1527 | break; | |
604be200 SK |
1528 | case SM501_2D_DESTINATION: |
1529 | s->twoD_destination = value; | |
1530 | break; | |
1531 | case SM501_2D_DIMENSION: | |
1532 | s->twoD_dimension = value; | |
1533 | break; | |
1534 | case SM501_2D_CONTROL: | |
1535 | s->twoD_control = value; | |
1536 | ||
1537 | /* do 2d operation if start flag is set. */ | |
1538 | if (value & 0x80000000) { | |
1539 | sm501_2d_operation(s); | |
1540 | s->twoD_control &= ~0x80000000; /* start flag down */ | |
1541 | } | |
1542 | ||
1543 | break; | |
1544 | case SM501_2D_PITCH: | |
1545 | s->twoD_pitch = value; | |
1546 | break; | |
1547 | case SM501_2D_FOREGROUND: | |
1548 | s->twoD_foreground = value; | |
1549 | break; | |
b612a49d BZ |
1550 | case SM501_2D_BACKGROUND: |
1551 | s->twoD_background = value; | |
1552 | break; | |
604be200 | 1553 | case SM501_2D_STRETCH: |
f018edc3 BZ |
1554 | if (((value >> 20) & 3) == 3) { |
1555 | value &= ~BIT(20); | |
1556 | } | |
604be200 SK |
1557 | s->twoD_stretch = value; |
1558 | break; | |
b612a49d BZ |
1559 | case SM501_2D_COLOR_COMPARE: |
1560 | s->twoD_color_compare = value; | |
1561 | break; | |
604be200 SK |
1562 | case SM501_2D_COLOR_COMPARE_MASK: |
1563 | s->twoD_color_compare_mask = value; | |
1564 | break; | |
1565 | case SM501_2D_MASK: | |
1566 | s->twoD_mask = value; | |
1567 | break; | |
b612a49d BZ |
1568 | case SM501_2D_CLIP_TL: |
1569 | s->twoD_clip_tl = value; | |
1570 | break; | |
1571 | case SM501_2D_CLIP_BR: | |
1572 | s->twoD_clip_br = value; | |
1573 | break; | |
1574 | case SM501_2D_MONO_PATTERN_LOW: | |
1575 | s->twoD_mono_pattern_low = value; | |
1576 | break; | |
1577 | case SM501_2D_MONO_PATTERN_HIGH: | |
1578 | s->twoD_mono_pattern_high = value; | |
1579 | break; | |
604be200 SK |
1580 | case SM501_2D_WINDOW_WIDTH: |
1581 | s->twoD_window_width = value; | |
1582 | break; | |
1583 | case SM501_2D_SOURCE_BASE: | |
1584 | s->twoD_source_base = value; | |
1585 | break; | |
1586 | case SM501_2D_DESTINATION_BASE: | |
1587 | s->twoD_destination_base = value; | |
1588 | break; | |
b612a49d BZ |
1589 | case SM501_2D_ALPHA: |
1590 | s->twoD_alpha = value; | |
1591 | break; | |
1592 | case SM501_2D_WRAP: | |
1593 | s->twoD_wrap = value; | |
1594 | break; | |
1595 | case SM501_2D_STATUS: | |
1596 | /* ignored, writing 0 should clear interrupt status */ | |
1597 | break; | |
604be200 | 1598 | default: |
e29da77e BZ |
1599 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented 2d engine register " |
1600 | "write. addr=%" HWADDR_PRIx | |
1601 | ", val=%" PRIx64 "\n", addr, value); | |
604be200 SK |
1602 | } |
1603 | } | |
1604 | ||
25793bfa AK |
1605 | static const MemoryRegionOps sm501_2d_engine_ops = { |
1606 | .read = sm501_2d_engine_read, | |
1607 | .write = sm501_2d_engine_write, | |
1608 | .valid = { | |
1609 | .min_access_size = 4, | |
1610 | .max_access_size = 4, | |
1611 | }, | |
afef2e1d | 1612 | .endianness = DEVICE_LITTLE_ENDIAN, |
604be200 SK |
1613 | }; |
1614 | ||
ffd39257 BS |
1615 | /* draw line functions for all console modes */ |
1616 | ||
ffd39257 | 1617 | typedef void draw_line_func(uint8_t *d, const uint8_t *s, |
64f1603b | 1618 | int width, const uint32_t *pal); |
ffd39257 | 1619 | |
6a2a5aae BZ |
1620 | typedef void draw_hwc_line_func(uint8_t *d, const uint8_t *s, |
1621 | int width, const uint8_t *palette, | |
1622 | int c_x, int c_y); | |
0a4e7cd2 | 1623 | |
f7b5c161 PM |
1624 | static void draw_line8_32(uint8_t *d, const uint8_t *s, int width, |
1625 | const uint32_t *pal) | |
1626 | { | |
1627 | uint8_t v, r, g, b; | |
1628 | do { | |
1629 | v = ldub_p(s); | |
1630 | r = (pal[v] >> 16) & 0xff; | |
1631 | g = (pal[v] >> 8) & 0xff; | |
1632 | b = (pal[v] >> 0) & 0xff; | |
1633 | *(uint32_t *)d = rgb_to_pixel32(r, g, b); | |
1634 | s++; | |
1635 | d += 4; | |
1636 | } while (--width != 0); | |
1637 | } | |
1638 | ||
1639 | static void draw_line16_32(uint8_t *d, const uint8_t *s, int width, | |
1640 | const uint32_t *pal) | |
1641 | { | |
1642 | uint16_t rgb565; | |
1643 | uint8_t r, g, b; | |
1644 | ||
1645 | do { | |
1646 | rgb565 = lduw_le_p(s); | |
1647 | r = (rgb565 >> 8) & 0xf8; | |
1648 | g = (rgb565 >> 3) & 0xfc; | |
1649 | b = (rgb565 << 3) & 0xf8; | |
1650 | *(uint32_t *)d = rgb_to_pixel32(r, g, b); | |
1651 | s += 2; | |
1652 | d += 4; | |
1653 | } while (--width != 0); | |
1654 | } | |
1655 | ||
1656 | static void draw_line32_32(uint8_t *d, const uint8_t *s, int width, | |
1657 | const uint32_t *pal) | |
1658 | { | |
1659 | uint8_t r, g, b; | |
1660 | ||
1661 | do { | |
1662 | r = s[2]; | |
1663 | g = s[1]; | |
1664 | b = s[0]; | |
1665 | *(uint32_t *)d = rgb_to_pixel32(r, g, b); | |
1666 | s += 4; | |
1667 | d += 4; | |
1668 | } while (--width != 0); | |
1669 | } | |
1670 | ||
1671 | /** | |
1672 | * Draw hardware cursor image on the given line. | |
1673 | */ | |
1674 | static void draw_hwc_line_32(uint8_t *d, const uint8_t *s, int width, | |
1675 | const uint8_t *palette, int c_x, int c_y) | |
1676 | { | |
1677 | int i; | |
1678 | uint8_t r, g, b, v, bitset = 0; | |
1679 | ||
1680 | /* get cursor position */ | |
1681 | assert(0 <= c_y && c_y < SM501_HWC_HEIGHT); | |
1682 | s += SM501_HWC_WIDTH * c_y / 4; /* 4 pixels per byte */ | |
1683 | d += c_x * 4; | |
1684 | ||
1685 | for (i = 0; i < SM501_HWC_WIDTH && c_x + i < width; i++) { | |
1686 | /* get pixel value */ | |
1687 | if (i % 4 == 0) { | |
1688 | bitset = ldub_p(s); | |
1689 | s++; | |
1690 | } | |
1691 | v = bitset & 3; | |
1692 | bitset >>= 2; | |
1693 | ||
1694 | /* write pixel */ | |
1695 | if (v) { | |
1696 | v--; | |
1697 | r = palette[v * 3 + 0]; | |
1698 | g = palette[v * 3 + 1]; | |
1699 | b = palette[v * 3 + 2]; | |
1700 | *(uint32_t *)d = rgb_to_pixel32(r, g, b); | |
1701 | } | |
1702 | d += 4; | |
1703 | } | |
1704 | } | |
ffd39257 | 1705 | |
1ae5e6eb | 1706 | static void sm501_update_display(void *opaque) |
ffd39257 | 1707 | { |
57ad5b5a | 1708 | SM501State *s = opaque; |
c78f7137 | 1709 | DisplaySurface *surface = qemu_console_surface(s->con); |
ca7f5441 | 1710 | DirtyBitmapSnapshot *snap; |
6a2a5aae | 1711 | int y, c_x = 0, c_y = 0; |
1ae5e6eb BZ |
1712 | int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0; |
1713 | int width = get_width(s, crt); | |
1714 | int height = get_height(s, crt); | |
1715 | int src_bpp = get_bpp(s, crt); | |
c78f7137 | 1716 | int dst_bpp = surface_bytes_per_pixel(surface); |
64f1603b BZ |
1717 | draw_line_func *draw_line = NULL; |
1718 | draw_hwc_line_func *draw_hwc_line = NULL; | |
ffd39257 BS |
1719 | int full_update = 0; |
1720 | int y_start = -1; | |
33159dd7 | 1721 | ram_addr_t offset; |
1ae5e6eb BZ |
1722 | uint32_t *palette; |
1723 | uint8_t hwc_palette[3 * 3]; | |
1724 | uint8_t *hwc_src = NULL; | |
1725 | ||
ec79c563 PM |
1726 | assert(dst_bpp == 4); /* Output is always 32-bit RGB */ |
1727 | ||
1ae5e6eb BZ |
1728 | if (!((crt ? s->dc_crt_control : s->dc_panel_control) |
1729 | & SM501_DC_CRT_CONTROL_ENABLE)) { | |
1730 | return; | |
1731 | } | |
1732 | ||
1733 | palette = (uint32_t *)(crt ? &s->dc_palette[SM501_DC_CRT_PALETTE - | |
1734 | SM501_DC_PANEL_PALETTE] | |
1735 | : &s->dc_palette[0]); | |
ffd39257 BS |
1736 | |
1737 | /* choose draw_line function */ | |
6a2a5aae BZ |
1738 | switch (src_bpp) { |
1739 | case 1: | |
ec79c563 | 1740 | draw_line = draw_line8_32; |
64f1603b | 1741 | break; |
6a2a5aae | 1742 | case 2: |
ec79c563 | 1743 | draw_line = draw_line16_32; |
64f1603b | 1744 | break; |
6a2a5aae | 1745 | case 4: |
ec79c563 | 1746 | draw_line = draw_line32_32; |
64f1603b | 1747 | break; |
ffd39257 | 1748 | default: |
e29da77e BZ |
1749 | qemu_log_mask(LOG_GUEST_ERROR, "sm501: update display" |
1750 | "invalid control register value.\n"); | |
1751 | return; | |
ffd39257 BS |
1752 | } |
1753 | ||
0a4e7cd2 | 1754 | /* set up to draw hardware cursor */ |
1ae5e6eb | 1755 | if (is_hwc_enabled(s, crt)) { |
0a4e7cd2 | 1756 | /* choose cursor draw line function */ |
ec79c563 | 1757 | draw_hwc_line = draw_hwc_line_32; |
1ae5e6eb BZ |
1758 | hwc_src = get_hwc_address(s, crt); |
1759 | c_x = get_hwc_x(s, crt); | |
1760 | c_y = get_hwc_y(s, crt); | |
1761 | get_hwc_palette(s, crt, hwc_palette); | |
0a4e7cd2 SK |
1762 | } |
1763 | ||
ffd39257 BS |
1764 | /* adjust console size */ |
1765 | if (s->last_width != width || s->last_height != height) { | |
c78f7137 GH |
1766 | qemu_console_resize(s->con, width, height); |
1767 | surface = qemu_console_surface(s->con); | |
64f1603b BZ |
1768 | s->last_width = width; |
1769 | s->last_height = height; | |
1770 | full_update = 1; | |
ffd39257 BS |
1771 | } |
1772 | ||
d2733559 SB |
1773 | /* someone else requested a full update */ |
1774 | if (s->do_full_update) { | |
1775 | s->do_full_update = false; | |
1776 | full_update = 1; | |
1777 | } | |
1778 | ||
ffd39257 | 1779 | /* draw each line according to conditions */ |
33159dd7 | 1780 | offset = get_fb_addr(s, crt); |
ca7f5441 GH |
1781 | snap = memory_region_snapshot_and_clear_dirty(&s->local_mem_region, |
1782 | offset, width * height * src_bpp, DIRTY_MEMORY_VGA); | |
33159dd7 | 1783 | for (y = 0; y < height; y++, offset += width * src_bpp) { |
6a2a5aae | 1784 | int update, update_hwc; |
ffd39257 | 1785 | |
6a2a5aae BZ |
1786 | /* check if hardware cursor is enabled and we're within its range */ |
1787 | update_hwc = draw_hwc_line && c_y <= y && y < c_y + SM501_HWC_HEIGHT; | |
1788 | update = full_update || update_hwc; | |
64f1603b | 1789 | /* check dirty flags for each line */ |
ca7f5441 GH |
1790 | update |= memory_region_snapshot_get_dirty(&s->local_mem_region, snap, |
1791 | offset, width * src_bpp); | |
ffd39257 | 1792 | |
64f1603b BZ |
1793 | /* draw line and change status */ |
1794 | if (update) { | |
c78f7137 GH |
1795 | uint8_t *d = surface_data(surface); |
1796 | d += y * width * dst_bpp; | |
0a4e7cd2 SK |
1797 | |
1798 | /* draw graphics layer */ | |
1ae5e6eb | 1799 | draw_line(d, s->local_mem + offset, width, palette); |
0a4e7cd2 | 1800 | |
64f1603b | 1801 | /* draw hardware cursor */ |
0a4e7cd2 | 1802 | if (update_hwc) { |
6a2a5aae | 1803 | draw_hwc_line(d, hwc_src, width, hwc_palette, c_x, y - c_y); |
0a4e7cd2 SK |
1804 | } |
1805 | ||
64f1603b BZ |
1806 | if (y_start < 0) { |
1807 | y_start = y; | |
1808 | } | |
64f1603b BZ |
1809 | } else { |
1810 | if (y_start >= 0) { | |
1811 | /* flush to display */ | |
c78f7137 | 1812 | dpy_gfx_update(s->con, 0, y_start, width, y - y_start); |
64f1603b BZ |
1813 | y_start = -1; |
1814 | } | |
1815 | } | |
ffd39257 | 1816 | } |
ca7f5441 | 1817 | g_free(snap); |
ffd39257 BS |
1818 | |
1819 | /* complete flush to display */ | |
64f1603b | 1820 | if (y_start >= 0) { |
c78f7137 | 1821 | dpy_gfx_update(s->con, 0, y_start, width, y - y_start); |
64f1603b | 1822 | } |
ffd39257 BS |
1823 | } |
1824 | ||
380cd056 GH |
1825 | static const GraphicHwOps sm501_ops = { |
1826 | .gfx_update = sm501_update_display, | |
1827 | }; | |
1828 | ||
ca8a1104 | 1829 | static void sm501_reset(SM501State *s) |
ffd39257 | 1830 | { |
e2ee8476 | 1831 | s->system_control = 0x00100000; /* 2D engine FIFO empty */ |
bd591dc1 BZ |
1832 | /* |
1833 | * Bits 17 (SH), 7 (CDR), 6:5 (Test), 2:0 (Bus) are all supposed | |
e2ee8476 BZ |
1834 | * to be determined at reset by GPIO lines which set config bits. |
1835 | * We hardwire them: | |
1836 | * SH = 0 : Hitachi Ready Polarity == Active Low | |
1837 | * CDR = 0 : do not reset clock divider | |
1838 | * TEST = 0 : Normal mode (not testing the silicon) | |
1839 | * BUS = 0 : Hitachi SH3/SH4 | |
1840 | */ | |
1841 | s->misc_control = SM501_MISC_DAC_POWER; | |
ca8a1104 BZ |
1842 | s->gpio_31_0_control = 0; |
1843 | s->gpio_63_32_control = 0; | |
1844 | s->dram_control = 0; | |
70e46ca8 | 1845 | s->arbitration_control = 0x05146732; |
ca8a1104 BZ |
1846 | s->irq_mask = 0; |
1847 | s->misc_timing = 0; | |
1848 | s->power_mode_control = 0; | |
4a1f253a BZ |
1849 | s->i2c_byte_count = 0; |
1850 | s->i2c_status = 0; | |
1851 | s->i2c_addr = 0; | |
1852 | memset(s->i2c_data, 0, 16); | |
e2ee8476 | 1853 | s->dc_panel_control = 0x00010000; /* FIFO level 3 */ |
b612a49d | 1854 | s->dc_video_control = 0; |
ffd39257 | 1855 | s->dc_crt_control = 0x00010000; |
b612a49d BZ |
1856 | s->twoD_source = 0; |
1857 | s->twoD_destination = 0; | |
1858 | s->twoD_dimension = 0; | |
ca8a1104 | 1859 | s->twoD_control = 0; |
b612a49d BZ |
1860 | s->twoD_pitch = 0; |
1861 | s->twoD_foreground = 0; | |
1862 | s->twoD_background = 0; | |
1863 | s->twoD_stretch = 0; | |
1864 | s->twoD_color_compare = 0; | |
1865 | s->twoD_color_compare_mask = 0; | |
1866 | s->twoD_mask = 0; | |
1867 | s->twoD_clip_tl = 0; | |
1868 | s->twoD_clip_br = 0; | |
1869 | s->twoD_mono_pattern_low = 0; | |
1870 | s->twoD_mono_pattern_high = 0; | |
1871 | s->twoD_window_width = 0; | |
1872 | s->twoD_source_base = 0; | |
1873 | s->twoD_destination_base = 0; | |
1874 | s->twoD_alpha = 0; | |
1875 | s->twoD_wrap = 0; | |
ca8a1104 | 1876 | } |
ffd39257 | 1877 | |
c795fa84 | 1878 | static void sm501_init(SM501State *s, DeviceState *dev, |
ca8a1104 BZ |
1879 | uint32_t local_mem_bytes) |
1880 | { | |
ca8a1104 | 1881 | s->local_mem_size_index = get_local_mem_size_index(local_mem_bytes); |
ca8a1104 BZ |
1882 | |
1883 | /* local memory */ | |
4c4414a4 | 1884 | memory_region_init_ram(&s->local_mem_region, OBJECT(dev), "sm501.local", |
ca8a1104 | 1885 | get_local_mem_size(s), &error_fatal); |
74259ae5 | 1886 | memory_region_set_log(&s->local_mem_region, true, DIRTY_MEMORY_VGA); |
25793bfa | 1887 | s->local_mem = memory_region_get_ram_ptr(&s->local_mem_region); |
ca8a1104 | 1888 | |
4a1f253a BZ |
1889 | /* i2c */ |
1890 | s->i2c_bus = i2c_init_bus(dev, "sm501.i2c"); | |
1891 | /* ddc */ | |
df707969 | 1892 | I2CDDCState *ddc = I2CDDC(qdev_new(TYPE_I2CDDC)); |
c8665a59 | 1893 | i2c_slave_set_address(I2C_SLAVE(ddc), 0x50); |
df707969 | 1894 | qdev_realize_and_unref(DEVICE(ddc), BUS(s->i2c_bus), &error_abort); |
4a1f253a | 1895 | |
ca8a1104 BZ |
1896 | /* mmio */ |
1897 | memory_region_init(&s->mmio_region, OBJECT(dev), "sm501.mmio", MMIO_SIZE); | |
1898 | memory_region_init_io(&s->system_config_region, OBJECT(dev), | |
1899 | &sm501_system_config_ops, s, | |
1900 | "sm501-system-config", 0x6c); | |
1901 | memory_region_add_subregion(&s->mmio_region, SM501_SYS_CONFIG, | |
1902 | &s->system_config_region); | |
4a1f253a BZ |
1903 | memory_region_init_io(&s->i2c_region, OBJECT(dev), &sm501_i2c_ops, s, |
1904 | "sm501-i2c", 0x14); | |
1905 | memory_region_add_subregion(&s->mmio_region, SM501_I2C, &s->i2c_region); | |
ca8a1104 BZ |
1906 | memory_region_init_io(&s->disp_ctrl_region, OBJECT(dev), |
1907 | &sm501_disp_ctrl_ops, s, | |
25793bfa | 1908 | "sm501-disp-ctrl", 0x1000); |
ca8a1104 BZ |
1909 | memory_region_add_subregion(&s->mmio_region, SM501_DC, |
1910 | &s->disp_ctrl_region); | |
1911 | memory_region_init_io(&s->twoD_engine_region, OBJECT(dev), | |
1912 | &sm501_2d_engine_ops, s, | |
25793bfa | 1913 | "sm501-2d-engine", 0x54); |
ca8a1104 BZ |
1914 | memory_region_add_subregion(&s->mmio_region, SM501_2D_ENGINE, |
1915 | &s->twoD_engine_region); | |
1916 | ||
1917 | /* create qemu graphic console */ | |
8e5c952b | 1918 | s->con = graphic_console_init(dev, 0, &sm501_ops, s); |
ca8a1104 BZ |
1919 | } |
1920 | ||
2edd6e4a BZ |
1921 | static const VMStateDescription vmstate_sm501_state = { |
1922 | .name = "sm501-state", | |
1923 | .version_id = 1, | |
1924 | .minimum_version_id = 1, | |
1925 | .fields = (VMStateField[]) { | |
1926 | VMSTATE_UINT32(local_mem_size_index, SM501State), | |
1927 | VMSTATE_UINT32(system_control, SM501State), | |
1928 | VMSTATE_UINT32(misc_control, SM501State), | |
1929 | VMSTATE_UINT32(gpio_31_0_control, SM501State), | |
1930 | VMSTATE_UINT32(gpio_63_32_control, SM501State), | |
1931 | VMSTATE_UINT32(dram_control, SM501State), | |
1932 | VMSTATE_UINT32(arbitration_control, SM501State), | |
1933 | VMSTATE_UINT32(irq_mask, SM501State), | |
1934 | VMSTATE_UINT32(misc_timing, SM501State), | |
1935 | VMSTATE_UINT32(power_mode_control, SM501State), | |
1936 | VMSTATE_UINT32(uart0_ier, SM501State), | |
1937 | VMSTATE_UINT32(uart0_lcr, SM501State), | |
1938 | VMSTATE_UINT32(uart0_mcr, SM501State), | |
1939 | VMSTATE_UINT32(uart0_scr, SM501State), | |
1940 | VMSTATE_UINT8_ARRAY(dc_palette, SM501State, DC_PALETTE_ENTRIES), | |
1941 | VMSTATE_UINT32(dc_panel_control, SM501State), | |
1942 | VMSTATE_UINT32(dc_panel_panning_control, SM501State), | |
1943 | VMSTATE_UINT32(dc_panel_fb_addr, SM501State), | |
1944 | VMSTATE_UINT32(dc_panel_fb_offset, SM501State), | |
1945 | VMSTATE_UINT32(dc_panel_fb_width, SM501State), | |
1946 | VMSTATE_UINT32(dc_panel_fb_height, SM501State), | |
1947 | VMSTATE_UINT32(dc_panel_tl_location, SM501State), | |
1948 | VMSTATE_UINT32(dc_panel_br_location, SM501State), | |
1949 | VMSTATE_UINT32(dc_panel_h_total, SM501State), | |
1950 | VMSTATE_UINT32(dc_panel_h_sync, SM501State), | |
1951 | VMSTATE_UINT32(dc_panel_v_total, SM501State), | |
1952 | VMSTATE_UINT32(dc_panel_v_sync, SM501State), | |
1953 | VMSTATE_UINT32(dc_panel_hwc_addr, SM501State), | |
1954 | VMSTATE_UINT32(dc_panel_hwc_location, SM501State), | |
1955 | VMSTATE_UINT32(dc_panel_hwc_color_1_2, SM501State), | |
1956 | VMSTATE_UINT32(dc_panel_hwc_color_3, SM501State), | |
1957 | VMSTATE_UINT32(dc_video_control, SM501State), | |
1958 | VMSTATE_UINT32(dc_crt_control, SM501State), | |
1959 | VMSTATE_UINT32(dc_crt_fb_addr, SM501State), | |
1960 | VMSTATE_UINT32(dc_crt_fb_offset, SM501State), | |
1961 | VMSTATE_UINT32(dc_crt_h_total, SM501State), | |
1962 | VMSTATE_UINT32(dc_crt_h_sync, SM501State), | |
1963 | VMSTATE_UINT32(dc_crt_v_total, SM501State), | |
1964 | VMSTATE_UINT32(dc_crt_v_sync, SM501State), | |
1965 | VMSTATE_UINT32(dc_crt_hwc_addr, SM501State), | |
1966 | VMSTATE_UINT32(dc_crt_hwc_location, SM501State), | |
1967 | VMSTATE_UINT32(dc_crt_hwc_color_1_2, SM501State), | |
1968 | VMSTATE_UINT32(dc_crt_hwc_color_3, SM501State), | |
1969 | VMSTATE_UINT32(twoD_source, SM501State), | |
1970 | VMSTATE_UINT32(twoD_destination, SM501State), | |
1971 | VMSTATE_UINT32(twoD_dimension, SM501State), | |
1972 | VMSTATE_UINT32(twoD_control, SM501State), | |
1973 | VMSTATE_UINT32(twoD_pitch, SM501State), | |
1974 | VMSTATE_UINT32(twoD_foreground, SM501State), | |
1975 | VMSTATE_UINT32(twoD_background, SM501State), | |
1976 | VMSTATE_UINT32(twoD_stretch, SM501State), | |
1977 | VMSTATE_UINT32(twoD_color_compare, SM501State), | |
1978 | VMSTATE_UINT32(twoD_color_compare_mask, SM501State), | |
1979 | VMSTATE_UINT32(twoD_mask, SM501State), | |
1980 | VMSTATE_UINT32(twoD_clip_tl, SM501State), | |
1981 | VMSTATE_UINT32(twoD_clip_br, SM501State), | |
1982 | VMSTATE_UINT32(twoD_mono_pattern_low, SM501State), | |
1983 | VMSTATE_UINT32(twoD_mono_pattern_high, SM501State), | |
1984 | VMSTATE_UINT32(twoD_window_width, SM501State), | |
1985 | VMSTATE_UINT32(twoD_source_base, SM501State), | |
1986 | VMSTATE_UINT32(twoD_destination_base, SM501State), | |
1987 | VMSTATE_UINT32(twoD_alpha, SM501State), | |
1988 | VMSTATE_UINT32(twoD_wrap, SM501State), | |
4a1f253a BZ |
1989 | /* Added in version 2 */ |
1990 | VMSTATE_UINT8(i2c_byte_count, SM501State), | |
1991 | VMSTATE_UINT8(i2c_status, SM501State), | |
1992 | VMSTATE_UINT8(i2c_addr, SM501State), | |
1993 | VMSTATE_UINT8_ARRAY(i2c_data, SM501State, 16), | |
2edd6e4a BZ |
1994 | VMSTATE_END_OF_LIST() |
1995 | } | |
1996 | }; | |
1997 | ||
ca8a1104 | 1998 | #define TYPE_SYSBUS_SM501 "sysbus-sm501" |
8063396b | 1999 | OBJECT_DECLARE_SIMPLE_TYPE(SM501SysBusState, SYSBUS_SM501) |
ca8a1104 | 2000 | |
db1015e9 | 2001 | struct SM501SysBusState { |
ca8a1104 BZ |
2002 | /*< private >*/ |
2003 | SysBusDevice parent_obj; | |
2004 | /*< public >*/ | |
2005 | SM501State state; | |
2006 | uint32_t vram_size; | |
0ed40f16 | 2007 | SerialMM serial; |
01c400ae | 2008 | OHCISysBusState ohci; |
db1015e9 | 2009 | }; |
ca8a1104 BZ |
2010 | |
2011 | static void sm501_realize_sysbus(DeviceState *dev, Error **errp) | |
2012 | { | |
2013 | SM501SysBusState *s = SYSBUS_SM501(dev); | |
2014 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
0ed40f16 | 2015 | MemoryRegion *mr; |
ca8a1104 | 2016 | |
c795fa84 | 2017 | sm501_init(&s->state, dev, s->vram_size); |
ca8a1104 BZ |
2018 | if (get_local_mem_size(&s->state) != s->vram_size) { |
2019 | error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32, | |
2020 | get_local_mem_size(&s->state)); | |
2021 | return; | |
2022 | } | |
2023 | sysbus_init_mmio(sbd, &s->state.local_mem_region); | |
2024 | sysbus_init_mmio(sbd, &s->state.mmio_region); | |
ffd39257 | 2025 | |
ac611340 | 2026 | /* bridge to usb host emulation module */ |
01c400ae | 2027 | sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->ohci), &error_fatal); |
ca8a1104 | 2028 | memory_region_add_subregion(&s->state.mmio_region, SM501_USB_HOST, |
01c400ae PMD |
2029 | sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ohci), 0)); |
2030 | sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->ohci)); | |
ac611340 | 2031 | |
ffd39257 | 2032 | /* bridge to serial emulation module */ |
5a147c8c | 2033 | sysbus_realize(SYS_BUS_DEVICE(&s->serial), &error_fatal); |
0ed40f16 MAL |
2034 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->serial), 0); |
2035 | memory_region_add_subregion(&s->state.mmio_region, SM501_UART0, mr); | |
2036 | /* TODO : chain irq to IRL */ | |
ca8a1104 | 2037 | } |
ffd39257 | 2038 | |
ca8a1104 BZ |
2039 | static Property sm501_sysbus_properties[] = { |
2040 | DEFINE_PROP_UINT32("vram-size", SM501SysBusState, vram_size, 0), | |
4e021052 | 2041 | DEFINE_PROP_UINT8("x-pixman", SM501SysBusState, state.use_pixman, 7), |
ca8a1104 BZ |
2042 | DEFINE_PROP_END_OF_LIST(), |
2043 | }; | |
2044 | ||
2045 | static void sm501_reset_sysbus(DeviceState *dev) | |
2046 | { | |
2047 | SM501SysBusState *s = SYSBUS_SM501(dev); | |
2048 | sm501_reset(&s->state); | |
ffd39257 | 2049 | } |
ca8a1104 | 2050 | |
2edd6e4a BZ |
2051 | static const VMStateDescription vmstate_sm501_sysbus = { |
2052 | .name = TYPE_SYSBUS_SM501, | |
4a1f253a BZ |
2053 | .version_id = 2, |
2054 | .minimum_version_id = 2, | |
2edd6e4a BZ |
2055 | .fields = (VMStateField[]) { |
2056 | VMSTATE_STRUCT(state, SM501SysBusState, 1, | |
2057 | vmstate_sm501_state, SM501State), | |
2058 | VMSTATE_END_OF_LIST() | |
2059 | } | |
2060 | }; | |
2061 | ||
ca8a1104 BZ |
2062 | static void sm501_sysbus_class_init(ObjectClass *klass, void *data) |
2063 | { | |
2064 | DeviceClass *dc = DEVICE_CLASS(klass); | |
2065 | ||
2066 | dc->realize = sm501_realize_sysbus; | |
2067 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); | |
2068 | dc->desc = "SM501 Multimedia Companion"; | |
4f67d30b | 2069 | device_class_set_props(dc, sm501_sysbus_properties); |
ca8a1104 | 2070 | dc->reset = sm501_reset_sysbus; |
2edd6e4a | 2071 | dc->vmsd = &vmstate_sm501_sysbus; |
0ed40f16 MAL |
2072 | } |
2073 | ||
2074 | static void sm501_sysbus_init(Object *o) | |
2075 | { | |
2076 | SM501SysBusState *sm501 = SYSBUS_SM501(o); | |
01c400ae | 2077 | OHCISysBusState *ohci = &sm501->ohci; |
0ed40f16 MAL |
2078 | SerialMM *smm = &sm501->serial; |
2079 | ||
01c400ae | 2080 | object_initialize_child(o, "ohci", ohci, TYPE_SYSBUS_OHCI); |
6a015046 | 2081 | object_property_add_alias(o, "dma-offset", OBJECT(ohci), "dma-offset"); |
01c400ae PMD |
2082 | qdev_prop_set_uint32(DEVICE(ohci), "num-ports", 2); |
2083 | ||
5a147c8c | 2084 | object_initialize_child(o, "serial", smm, TYPE_SERIAL_MM); |
0ed40f16 MAL |
2085 | qdev_set_legacy_instance_id(DEVICE(smm), SM501_UART0, 2); |
2086 | qdev_prop_set_uint8(DEVICE(smm), "regshift", 2); | |
2087 | qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN); | |
2088 | ||
6a015046 | 2089 | object_property_add_alias(o, "chardev", OBJECT(smm), "chardev"); |
ca8a1104 BZ |
2090 | } |
2091 | ||
2092 | static const TypeInfo sm501_sysbus_info = { | |
2093 | .name = TYPE_SYSBUS_SM501, | |
2094 | .parent = TYPE_SYS_BUS_DEVICE, | |
2095 | .instance_size = sizeof(SM501SysBusState), | |
2096 | .class_init = sm501_sysbus_class_init, | |
0ed40f16 | 2097 | .instance_init = sm501_sysbus_init, |
ca8a1104 BZ |
2098 | }; |
2099 | ||
efae2784 | 2100 | #define TYPE_PCI_SM501 "sm501" |
8063396b | 2101 | OBJECT_DECLARE_SIMPLE_TYPE(SM501PCIState, PCI_SM501) |
efae2784 | 2102 | |
db1015e9 | 2103 | struct SM501PCIState { |
efae2784 BZ |
2104 | /*< private >*/ |
2105 | PCIDevice parent_obj; | |
2106 | /*< public >*/ | |
2107 | SM501State state; | |
2108 | uint32_t vram_size; | |
db1015e9 | 2109 | }; |
efae2784 BZ |
2110 | |
2111 | static void sm501_realize_pci(PCIDevice *dev, Error **errp) | |
2112 | { | |
2113 | SM501PCIState *s = PCI_SM501(dev); | |
2114 | ||
2115 | sm501_init(&s->state, DEVICE(dev), s->vram_size); | |
2116 | if (get_local_mem_size(&s->state) != s->vram_size) { | |
2117 | error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32, | |
2118 | get_local_mem_size(&s->state)); | |
2119 | return; | |
2120 | } | |
2121 | pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, | |
2122 | &s->state.local_mem_region); | |
2123 | pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, | |
2124 | &s->state.mmio_region); | |
2125 | } | |
2126 | ||
2127 | static Property sm501_pci_properties[] = { | |
d23b6caa | 2128 | DEFINE_PROP_UINT32("vram-size", SM501PCIState, vram_size, 64 * MiB), |
4e021052 | 2129 | DEFINE_PROP_UINT8("x-pixman", SM501PCIState, state.use_pixman, 7), |
efae2784 BZ |
2130 | DEFINE_PROP_END_OF_LIST(), |
2131 | }; | |
2132 | ||
2133 | static void sm501_reset_pci(DeviceState *dev) | |
2134 | { | |
2135 | SM501PCIState *s = PCI_SM501(dev); | |
2136 | sm501_reset(&s->state); | |
2137 | /* Bits 2:0 of misc_control register is 001 for PCI */ | |
2138 | s->state.misc_control |= 1; | |
2139 | } | |
2140 | ||
2edd6e4a BZ |
2141 | static const VMStateDescription vmstate_sm501_pci = { |
2142 | .name = TYPE_PCI_SM501, | |
4a1f253a BZ |
2143 | .version_id = 2, |
2144 | .minimum_version_id = 2, | |
2edd6e4a BZ |
2145 | .fields = (VMStateField[]) { |
2146 | VMSTATE_PCI_DEVICE(parent_obj, SM501PCIState), | |
2147 | VMSTATE_STRUCT(state, SM501PCIState, 1, | |
2148 | vmstate_sm501_state, SM501State), | |
2149 | VMSTATE_END_OF_LIST() | |
2150 | } | |
2151 | }; | |
2152 | ||
efae2784 BZ |
2153 | static void sm501_pci_class_init(ObjectClass *klass, void *data) |
2154 | { | |
2155 | DeviceClass *dc = DEVICE_CLASS(klass); | |
2156 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
2157 | ||
2158 | k->realize = sm501_realize_pci; | |
2159 | k->vendor_id = PCI_VENDOR_ID_SILICON_MOTION; | |
2160 | k->device_id = PCI_DEVICE_ID_SM501; | |
2161 | k->class_id = PCI_CLASS_DISPLAY_OTHER; | |
2162 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); | |
2163 | dc->desc = "SM501 Display Controller"; | |
4f67d30b | 2164 | device_class_set_props(dc, sm501_pci_properties); |
efae2784 BZ |
2165 | dc->reset = sm501_reset_pci; |
2166 | dc->hotpluggable = false; | |
2edd6e4a | 2167 | dc->vmsd = &vmstate_sm501_pci; |
efae2784 BZ |
2168 | } |
2169 | ||
4e021052 BZ |
2170 | static void sm501_pci_init(Object *o) |
2171 | { | |
2172 | object_property_set_description(o, "x-pixman", "Use pixman for: " | |
2173 | "1: fill, 2: blit, 4: overlap blit"); | |
2174 | } | |
2175 | ||
efae2784 BZ |
2176 | static const TypeInfo sm501_pci_info = { |
2177 | .name = TYPE_PCI_SM501, | |
2178 | .parent = TYPE_PCI_DEVICE, | |
2179 | .instance_size = sizeof(SM501PCIState), | |
2180 | .class_init = sm501_pci_class_init, | |
4e021052 | 2181 | .instance_init = sm501_pci_init, |
fd3b02c8 EH |
2182 | .interfaces = (InterfaceInfo[]) { |
2183 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
2184 | { }, | |
2185 | }, | |
efae2784 BZ |
2186 | }; |
2187 | ||
ca8a1104 BZ |
2188 | static void sm501_register_types(void) |
2189 | { | |
2190 | type_register_static(&sm501_sysbus_info); | |
efae2784 | 2191 | type_register_static(&sm501_pci_info); |
ca8a1104 BZ |
2192 | } |
2193 | ||
2194 | type_init(sm501_register_types) |