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ffd39257 BS |
1 | /* |
2 | * QEMU SM501 Device | |
3 | * | |
4 | * Copyright (c) 2008 Shin-ichiro KAWASAKI | |
1ae5e6eb | 5 | * Copyright (c) 2016 BALATON Zoltan |
ffd39257 BS |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | ||
47df5154 | 26 | #include "qemu/osdep.h" |
fc6b3cf9 | 27 | #include "qemu/units.h" |
da34e65c | 28 | #include "qapi/error.h" |
4a1f253a | 29 | #include "qemu/log.h" |
0b8fa32f | 30 | #include "qemu/module.h" |
0d09e41a | 31 | #include "hw/char/serial.h" |
28ecbaee | 32 | #include "ui/console.h" |
83c9f4ca | 33 | #include "hw/sysbus.h" |
d6454270 | 34 | #include "migration/vmstate.h" |
efae2784 | 35 | #include "hw/pci/pci.h" |
a27bd6c7 | 36 | #include "hw/qdev-properties.h" |
4a1f253a | 37 | #include "hw/i2c/i2c.h" |
6306cae2 | 38 | #include "hw/display/i2c-ddc.h" |
1de7afc9 | 39 | #include "qemu/range.h" |
28ecbaee | 40 | #include "ui/pixel_ops.h" |
f3a60058 | 41 | #include "qemu/bswap.h" |
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42 | |
43 | /* | |
604be200 | 44 | * Status: 2010/05/07 |
ffd39257 | 45 | * - Minimum implementation for Linux console : mmio regs and CRT layer. |
64f1603b | 46 | * - 2D graphics acceleration partially supported : only fill rectangle. |
ffd39257 | 47 | * |
1ae5e6eb BZ |
48 | * Status: 2016/12/04 |
49 | * - Misc fixes: endianness, hardware cursor | |
ffd39257 | 50 | * - Panel support |
1ae5e6eb BZ |
51 | * |
52 | * TODO: | |
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53 | * - Touch panel support |
54 | * - USB support | |
55 | * - UART support | |
604be200 | 56 | * - More 2D graphics engine support |
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57 | * - Performance tuning |
58 | */ | |
59 | ||
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60 | /*#define DEBUG_SM501*/ |
61 | /*#define DEBUG_BITBLT*/ | |
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62 | |
63 | #ifdef DEBUG_SM501 | |
001faf32 | 64 | #define SM501_DPRINTF(fmt, ...) printf(fmt, ## __VA_ARGS__) |
ffd39257 | 65 | #else |
64f1603b | 66 | #define SM501_DPRINTF(fmt, ...) do {} while (0) |
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67 | #endif |
68 | ||
ffd39257 | 69 | #define MMIO_BASE_OFFSET 0x3e00000 |
ca8a1104 | 70 | #define MMIO_SIZE 0x200000 |
2edd6e4a | 71 | #define DC_PALETTE_ENTRIES (0x400 * 3) |
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72 | |
73 | /* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */ | |
74 | ||
75 | /* System Configuration area */ | |
76 | /* System config base */ | |
64f1603b | 77 | #define SM501_SYS_CONFIG (0x000000) |
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78 | |
79 | /* config 1 */ | |
64f1603b | 80 | #define SM501_SYSTEM_CONTROL (0x000000) |
ffd39257 | 81 | |
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82 | #define SM501_SYSCTRL_PANEL_TRISTATE (1 << 0) |
83 | #define SM501_SYSCTRL_MEM_TRISTATE (1 << 1) | |
84 | #define SM501_SYSCTRL_CRT_TRISTATE (1 << 2) | |
ffd39257 | 85 | |
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86 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3 << 4) |
87 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0 << 4) | |
88 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1 << 4) | |
89 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2 << 4) | |
90 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3 << 4) | |
ffd39257 | 91 | |
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92 | #define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1 << 6) |
93 | #define SM501_SYSCTRL_PCI_RETRY_DISABLE (1 << 7) | |
94 | #define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1 << 11) | |
95 | #define SM501_SYSCTRL_PCI_BURST_READ_EN (1 << 15) | |
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96 | |
97 | /* miscellaneous control */ | |
98 | ||
64f1603b | 99 | #define SM501_MISC_CONTROL (0x000004) |
ffd39257 | 100 | |
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101 | #define SM501_MISC_BUS_SH (0x0) |
102 | #define SM501_MISC_BUS_PCI (0x1) | |
103 | #define SM501_MISC_BUS_XSCALE (0x2) | |
104 | #define SM501_MISC_BUS_NEC (0x6) | |
105 | #define SM501_MISC_BUS_MASK (0x7) | |
ffd39257 | 106 | |
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107 | #define SM501_MISC_VR_62MB (1 << 3) |
108 | #define SM501_MISC_CDR_RESET (1 << 7) | |
109 | #define SM501_MISC_USB_LB (1 << 8) | |
110 | #define SM501_MISC_USB_SLAVE (1 << 9) | |
111 | #define SM501_MISC_BL_1 (1 << 10) | |
112 | #define SM501_MISC_MC (1 << 11) | |
113 | #define SM501_MISC_DAC_POWER (1 << 12) | |
114 | #define SM501_MISC_IRQ_INVERT (1 << 16) | |
115 | #define SM501_MISC_SH (1 << 17) | |
ffd39257 | 116 | |
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117 | #define SM501_MISC_HOLD_EMPTY (0 << 18) |
118 | #define SM501_MISC_HOLD_8 (1 << 18) | |
119 | #define SM501_MISC_HOLD_16 (2 << 18) | |
120 | #define SM501_MISC_HOLD_24 (3 << 18) | |
121 | #define SM501_MISC_HOLD_32 (4 << 18) | |
122 | #define SM501_MISC_HOLD_MASK (7 << 18) | |
ffd39257 | 123 | |
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124 | #define SM501_MISC_FREQ_12 (1 << 24) |
125 | #define SM501_MISC_PNL_24BIT (1 << 25) | |
126 | #define SM501_MISC_8051_LE (1 << 26) | |
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127 | |
128 | ||
129 | ||
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130 | #define SM501_GPIO31_0_CONTROL (0x000008) |
131 | #define SM501_GPIO63_32_CONTROL (0x00000C) | |
132 | #define SM501_DRAM_CONTROL (0x000010) | |
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133 | |
134 | /* command list */ | |
64f1603b | 135 | #define SM501_ARBTRTN_CONTROL (0x000014) |
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136 | |
137 | /* command list */ | |
64f1603b | 138 | #define SM501_COMMAND_LIST_STATUS (0x000024) |
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139 | |
140 | /* interrupt debug */ | |
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141 | #define SM501_RAW_IRQ_STATUS (0x000028) |
142 | #define SM501_RAW_IRQ_CLEAR (0x000028) | |
143 | #define SM501_IRQ_STATUS (0x00002C) | |
144 | #define SM501_IRQ_MASK (0x000030) | |
145 | #define SM501_DEBUG_CONTROL (0x000034) | |
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146 | |
147 | /* power management */ | |
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148 | #define SM501_POWERMODE_P2X_SRC (1 << 29) |
149 | #define SM501_POWERMODE_V2X_SRC (1 << 20) | |
150 | #define SM501_POWERMODE_M_SRC (1 << 12) | |
151 | #define SM501_POWERMODE_M1_SRC (1 << 4) | |
152 | ||
153 | #define SM501_CURRENT_GATE (0x000038) | |
154 | #define SM501_CURRENT_CLOCK (0x00003C) | |
155 | #define SM501_POWER_MODE_0_GATE (0x000040) | |
156 | #define SM501_POWER_MODE_0_CLOCK (0x000044) | |
157 | #define SM501_POWER_MODE_1_GATE (0x000048) | |
158 | #define SM501_POWER_MODE_1_CLOCK (0x00004C) | |
159 | #define SM501_SLEEP_MODE_GATE (0x000050) | |
160 | #define SM501_POWER_MODE_CONTROL (0x000054) | |
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161 | |
162 | /* power gates for units within the 501 */ | |
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163 | #define SM501_GATE_HOST (0) |
164 | #define SM501_GATE_MEMORY (1) | |
165 | #define SM501_GATE_DISPLAY (2) | |
166 | #define SM501_GATE_2D_ENGINE (3) | |
167 | #define SM501_GATE_CSC (4) | |
168 | #define SM501_GATE_ZVPORT (5) | |
169 | #define SM501_GATE_GPIO (6) | |
170 | #define SM501_GATE_UART0 (7) | |
171 | #define SM501_GATE_UART1 (8) | |
172 | #define SM501_GATE_SSP (10) | |
173 | #define SM501_GATE_USB_HOST (11) | |
174 | #define SM501_GATE_USB_GADGET (12) | |
175 | #define SM501_GATE_UCONTROLLER (17) | |
176 | #define SM501_GATE_AC97 (18) | |
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177 | |
178 | /* panel clock */ | |
64f1603b | 179 | #define SM501_CLOCK_P2XCLK (24) |
ffd39257 | 180 | /* crt clock */ |
64f1603b | 181 | #define SM501_CLOCK_V2XCLK (16) |
ffd39257 | 182 | /* main clock */ |
64f1603b | 183 | #define SM501_CLOCK_MCLK (8) |
ffd39257 | 184 | /* SDRAM controller clock */ |
64f1603b | 185 | #define SM501_CLOCK_M1XCLK (0) |
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186 | |
187 | /* config 2 */ | |
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188 | #define SM501_PCI_MASTER_BASE (0x000058) |
189 | #define SM501_ENDIAN_CONTROL (0x00005C) | |
190 | #define SM501_DEVICEID (0x000060) | |
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191 | /* 0x050100A0 */ |
192 | ||
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193 | #define SM501_DEVICEID_SM501 (0x05010000) |
194 | #define SM501_DEVICEID_IDMASK (0xffff0000) | |
195 | #define SM501_DEVICEID_REVMASK (0x000000ff) | |
ffd39257 | 196 | |
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197 | #define SM501_PLLCLOCK_COUNT (0x000064) |
198 | #define SM501_MISC_TIMING (0x000068) | |
199 | #define SM501_CURRENT_SDRAM_CLOCK (0x00006C) | |
ffd39257 | 200 | |
64f1603b | 201 | #define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074) |
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202 | |
203 | /* GPIO base */ | |
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204 | #define SM501_GPIO (0x010000) |
205 | #define SM501_GPIO_DATA_LOW (0x00) | |
206 | #define SM501_GPIO_DATA_HIGH (0x04) | |
207 | #define SM501_GPIO_DDR_LOW (0x08) | |
208 | #define SM501_GPIO_DDR_HIGH (0x0C) | |
209 | #define SM501_GPIO_IRQ_SETUP (0x10) | |
210 | #define SM501_GPIO_IRQ_STATUS (0x14) | |
211 | #define SM501_GPIO_IRQ_RESET (0x14) | |
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212 | |
213 | /* I2C controller base */ | |
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214 | #define SM501_I2C (0x010040) |
215 | #define SM501_I2C_BYTE_COUNT (0x00) | |
216 | #define SM501_I2C_CONTROL (0x01) | |
217 | #define SM501_I2C_STATUS (0x02) | |
218 | #define SM501_I2C_RESET (0x02) | |
219 | #define SM501_I2C_SLAVE_ADDRESS (0x03) | |
220 | #define SM501_I2C_DATA (0x04) | |
ffd39257 | 221 | |
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222 | #define SM501_I2C_CONTROL_START (1 << 2) |
223 | #define SM501_I2C_CONTROL_ENABLE (1 << 0) | |
224 | ||
225 | #define SM501_I2C_STATUS_COMPLETE (1 << 3) | |
226 | #define SM501_I2C_STATUS_ERROR (1 << 2) | |
227 | ||
228 | #define SM501_I2C_RESET_ERROR (1 << 2) | |
229 | ||
ffd39257 | 230 | /* SSP base */ |
64f1603b | 231 | #define SM501_SSP (0x020000) |
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232 | |
233 | /* Uart 0 base */ | |
64f1603b | 234 | #define SM501_UART0 (0x030000) |
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235 | |
236 | /* Uart 1 base */ | |
64f1603b | 237 | #define SM501_UART1 (0x030020) |
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238 | |
239 | /* USB host port base */ | |
64f1603b | 240 | #define SM501_USB_HOST (0x040000) |
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241 | |
242 | /* USB slave/gadget base */ | |
64f1603b | 243 | #define SM501_USB_GADGET (0x060000) |
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244 | |
245 | /* USB slave/gadget data port base */ | |
64f1603b | 246 | #define SM501_USB_GADGET_DATA (0x070000) |
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247 | |
248 | /* Display controller/video engine base */ | |
64f1603b | 249 | #define SM501_DC (0x080000) |
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250 | |
251 | /* common defines for the SM501 address registers */ | |
64f1603b BZ |
252 | #define SM501_ADDR_FLIP (1 << 31) |
253 | #define SM501_ADDR_EXT (1 << 27) | |
254 | #define SM501_ADDR_CS1 (1 << 26) | |
255 | #define SM501_ADDR_MASK (0x3f << 26) | |
ffd39257 | 256 | |
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257 | #define SM501_FIFO_MASK (0x3 << 16) |
258 | #define SM501_FIFO_1 (0x0 << 16) | |
259 | #define SM501_FIFO_3 (0x1 << 16) | |
260 | #define SM501_FIFO_7 (0x2 << 16) | |
261 | #define SM501_FIFO_11 (0x3 << 16) | |
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262 | |
263 | /* common registers for panel and the crt */ | |
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264 | #define SM501_OFF_DC_H_TOT (0x000) |
265 | #define SM501_OFF_DC_V_TOT (0x008) | |
266 | #define SM501_OFF_DC_H_SYNC (0x004) | |
267 | #define SM501_OFF_DC_V_SYNC (0x00C) | |
268 | ||
269 | #define SM501_DC_PANEL_CONTROL (0x000) | |
270 | ||
271 | #define SM501_DC_PANEL_CONTROL_FPEN (1 << 27) | |
272 | #define SM501_DC_PANEL_CONTROL_BIAS (1 << 26) | |
273 | #define SM501_DC_PANEL_CONTROL_DATA (1 << 25) | |
274 | #define SM501_DC_PANEL_CONTROL_VDD (1 << 24) | |
275 | #define SM501_DC_PANEL_CONTROL_DP (1 << 23) | |
276 | ||
277 | #define SM501_DC_PANEL_CONTROL_TFT_888 (0 << 21) | |
278 | #define SM501_DC_PANEL_CONTROL_TFT_333 (1 << 21) | |
279 | #define SM501_DC_PANEL_CONTROL_TFT_444 (2 << 21) | |
280 | ||
281 | #define SM501_DC_PANEL_CONTROL_DE (1 << 20) | |
282 | ||
283 | #define SM501_DC_PANEL_CONTROL_LCD_TFT (0 << 18) | |
284 | #define SM501_DC_PANEL_CONTROL_LCD_STN8 (1 << 18) | |
285 | #define SM501_DC_PANEL_CONTROL_LCD_STN12 (2 << 18) | |
286 | ||
287 | #define SM501_DC_PANEL_CONTROL_CP (1 << 14) | |
288 | #define SM501_DC_PANEL_CONTROL_VSP (1 << 13) | |
289 | #define SM501_DC_PANEL_CONTROL_HSP (1 << 12) | |
290 | #define SM501_DC_PANEL_CONTROL_CK (1 << 9) | |
291 | #define SM501_DC_PANEL_CONTROL_TE (1 << 8) | |
292 | #define SM501_DC_PANEL_CONTROL_VPD (1 << 7) | |
293 | #define SM501_DC_PANEL_CONTROL_VP (1 << 6) | |
294 | #define SM501_DC_PANEL_CONTROL_HPD (1 << 5) | |
295 | #define SM501_DC_PANEL_CONTROL_HP (1 << 4) | |
296 | #define SM501_DC_PANEL_CONTROL_GAMMA (1 << 3) | |
297 | #define SM501_DC_PANEL_CONTROL_EN (1 << 2) | |
298 | ||
299 | #define SM501_DC_PANEL_CONTROL_8BPP (0 << 0) | |
300 | #define SM501_DC_PANEL_CONTROL_16BPP (1 << 0) | |
301 | #define SM501_DC_PANEL_CONTROL_32BPP (2 << 0) | |
302 | ||
303 | ||
304 | #define SM501_DC_PANEL_PANNING_CONTROL (0x004) | |
305 | #define SM501_DC_PANEL_COLOR_KEY (0x008) | |
306 | #define SM501_DC_PANEL_FB_ADDR (0x00C) | |
307 | #define SM501_DC_PANEL_FB_OFFSET (0x010) | |
308 | #define SM501_DC_PANEL_FB_WIDTH (0x014) | |
309 | #define SM501_DC_PANEL_FB_HEIGHT (0x018) | |
310 | #define SM501_DC_PANEL_TL_LOC (0x01C) | |
311 | #define SM501_DC_PANEL_BR_LOC (0x020) | |
312 | #define SM501_DC_PANEL_H_TOT (0x024) | |
313 | #define SM501_DC_PANEL_H_SYNC (0x028) | |
314 | #define SM501_DC_PANEL_V_TOT (0x02C) | |
315 | #define SM501_DC_PANEL_V_SYNC (0x030) | |
316 | #define SM501_DC_PANEL_CUR_LINE (0x034) | |
317 | ||
318 | #define SM501_DC_VIDEO_CONTROL (0x040) | |
319 | #define SM501_DC_VIDEO_FB0_ADDR (0x044) | |
320 | #define SM501_DC_VIDEO_FB_WIDTH (0x048) | |
321 | #define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C) | |
322 | #define SM501_DC_VIDEO_TL_LOC (0x050) | |
323 | #define SM501_DC_VIDEO_BR_LOC (0x054) | |
324 | #define SM501_DC_VIDEO_SCALE (0x058) | |
325 | #define SM501_DC_VIDEO_INIT_SCALE (0x05C) | |
326 | #define SM501_DC_VIDEO_YUV_CONSTANTS (0x060) | |
327 | #define SM501_DC_VIDEO_FB1_ADDR (0x064) | |
328 | #define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068) | |
329 | ||
330 | #define SM501_DC_VIDEO_ALPHA_CONTROL (0x080) | |
331 | #define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084) | |
332 | #define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088) | |
333 | #define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C) | |
334 | #define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090) | |
335 | #define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094) | |
336 | #define SM501_DC_VIDEO_ALPHA_SCALE (0x098) | |
337 | #define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C) | |
338 | #define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0) | |
339 | #define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4) | |
340 | ||
341 | #define SM501_DC_PANEL_HWC_BASE (0x0F0) | |
342 | #define SM501_DC_PANEL_HWC_ADDR (0x0F0) | |
343 | #define SM501_DC_PANEL_HWC_LOC (0x0F4) | |
344 | #define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8) | |
345 | #define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC) | |
346 | ||
347 | #define SM501_HWC_EN (1 << 31) | |
348 | ||
349 | #define SM501_OFF_HWC_ADDR (0x00) | |
350 | #define SM501_OFF_HWC_LOC (0x04) | |
351 | #define SM501_OFF_HWC_COLOR_1_2 (0x08) | |
352 | #define SM501_OFF_HWC_COLOR_3 (0x0C) | |
353 | ||
354 | #define SM501_DC_ALPHA_CONTROL (0x100) | |
355 | #define SM501_DC_ALPHA_FB_ADDR (0x104) | |
356 | #define SM501_DC_ALPHA_FB_OFFSET (0x108) | |
357 | #define SM501_DC_ALPHA_TL_LOC (0x10C) | |
358 | #define SM501_DC_ALPHA_BR_LOC (0x110) | |
359 | #define SM501_DC_ALPHA_CHROMA_KEY (0x114) | |
360 | #define SM501_DC_ALPHA_COLOR_LOOKUP (0x118) | |
361 | ||
362 | #define SM501_DC_CRT_CONTROL (0x200) | |
363 | ||
364 | #define SM501_DC_CRT_CONTROL_TVP (1 << 15) | |
365 | #define SM501_DC_CRT_CONTROL_CP (1 << 14) | |
366 | #define SM501_DC_CRT_CONTROL_VSP (1 << 13) | |
367 | #define SM501_DC_CRT_CONTROL_HSP (1 << 12) | |
368 | #define SM501_DC_CRT_CONTROL_VS (1 << 11) | |
369 | #define SM501_DC_CRT_CONTROL_BLANK (1 << 10) | |
370 | #define SM501_DC_CRT_CONTROL_SEL (1 << 9) | |
371 | #define SM501_DC_CRT_CONTROL_TE (1 << 8) | |
ffd39257 | 372 | #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4) |
64f1603b BZ |
373 | #define SM501_DC_CRT_CONTROL_GAMMA (1 << 3) |
374 | #define SM501_DC_CRT_CONTROL_ENABLE (1 << 2) | |
ffd39257 | 375 | |
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376 | #define SM501_DC_CRT_CONTROL_8BPP (0 << 0) |
377 | #define SM501_DC_CRT_CONTROL_16BPP (1 << 0) | |
378 | #define SM501_DC_CRT_CONTROL_32BPP (2 << 0) | |
ffd39257 | 379 | |
64f1603b BZ |
380 | #define SM501_DC_CRT_FB_ADDR (0x204) |
381 | #define SM501_DC_CRT_FB_OFFSET (0x208) | |
382 | #define SM501_DC_CRT_H_TOT (0x20C) | |
383 | #define SM501_DC_CRT_H_SYNC (0x210) | |
384 | #define SM501_DC_CRT_V_TOT (0x214) | |
385 | #define SM501_DC_CRT_V_SYNC (0x218) | |
386 | #define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C) | |
387 | #define SM501_DC_CRT_CUR_LINE (0x220) | |
388 | #define SM501_DC_CRT_MONITOR_DETECT (0x224) | |
ffd39257 | 389 | |
64f1603b BZ |
390 | #define SM501_DC_CRT_HWC_BASE (0x230) |
391 | #define SM501_DC_CRT_HWC_ADDR (0x230) | |
392 | #define SM501_DC_CRT_HWC_LOC (0x234) | |
393 | #define SM501_DC_CRT_HWC_COLOR_1_2 (0x238) | |
394 | #define SM501_DC_CRT_HWC_COLOR_3 (0x23C) | |
ffd39257 | 395 | |
64f1603b | 396 | #define SM501_DC_PANEL_PALETTE (0x400) |
ffd39257 | 397 | |
64f1603b | 398 | #define SM501_DC_VIDEO_PALETTE (0x800) |
ffd39257 | 399 | |
64f1603b | 400 | #define SM501_DC_CRT_PALETTE (0xC00) |
ffd39257 BS |
401 | |
402 | /* Zoom Video port base */ | |
64f1603b | 403 | #define SM501_ZVPORT (0x090000) |
ffd39257 BS |
404 | |
405 | /* AC97/I2S base */ | |
64f1603b | 406 | #define SM501_AC97 (0x0A0000) |
ffd39257 BS |
407 | |
408 | /* 8051 micro controller base */ | |
64f1603b | 409 | #define SM501_UCONTROLLER (0x0B0000) |
ffd39257 BS |
410 | |
411 | /* 8051 micro controller SRAM base */ | |
64f1603b | 412 | #define SM501_UCONTROLLER_SRAM (0x0C0000) |
ffd39257 BS |
413 | |
414 | /* DMA base */ | |
64f1603b | 415 | #define SM501_DMA (0x0D0000) |
ffd39257 BS |
416 | |
417 | /* 2d engine base */ | |
64f1603b BZ |
418 | #define SM501_2D_ENGINE (0x100000) |
419 | #define SM501_2D_SOURCE (0x00) | |
420 | #define SM501_2D_DESTINATION (0x04) | |
421 | #define SM501_2D_DIMENSION (0x08) | |
422 | #define SM501_2D_CONTROL (0x0C) | |
423 | #define SM501_2D_PITCH (0x10) | |
424 | #define SM501_2D_FOREGROUND (0x14) | |
425 | #define SM501_2D_BACKGROUND (0x18) | |
426 | #define SM501_2D_STRETCH (0x1C) | |
427 | #define SM501_2D_COLOR_COMPARE (0x20) | |
428 | #define SM501_2D_COLOR_COMPARE_MASK (0x24) | |
429 | #define SM501_2D_MASK (0x28) | |
430 | #define SM501_2D_CLIP_TL (0x2C) | |
431 | #define SM501_2D_CLIP_BR (0x30) | |
432 | #define SM501_2D_MONO_PATTERN_LOW (0x34) | |
433 | #define SM501_2D_MONO_PATTERN_HIGH (0x38) | |
434 | #define SM501_2D_WINDOW_WIDTH (0x3C) | |
435 | #define SM501_2D_SOURCE_BASE (0x40) | |
436 | #define SM501_2D_DESTINATION_BASE (0x44) | |
437 | #define SM501_2D_ALPHA (0x48) | |
438 | #define SM501_2D_WRAP (0x4C) | |
439 | #define SM501_2D_STATUS (0x50) | |
440 | ||
441 | #define SM501_CSC_Y_SOURCE_BASE (0xC8) | |
442 | #define SM501_CSC_CONSTANTS (0xCC) | |
443 | #define SM501_CSC_Y_SOURCE_X (0xD0) | |
444 | #define SM501_CSC_Y_SOURCE_Y (0xD4) | |
445 | #define SM501_CSC_U_SOURCE_BASE (0xD8) | |
446 | #define SM501_CSC_V_SOURCE_BASE (0xDC) | |
447 | #define SM501_CSC_SOURCE_DIMENSION (0xE0) | |
448 | #define SM501_CSC_SOURCE_PITCH (0xE4) | |
449 | #define SM501_CSC_DESTINATION (0xE8) | |
450 | #define SM501_CSC_DESTINATION_DIMENSION (0xEC) | |
451 | #define SM501_CSC_DESTINATION_PITCH (0xF0) | |
452 | #define SM501_CSC_SCALE_FACTOR (0xF4) | |
453 | #define SM501_CSC_DESTINATION_BASE (0xF8) | |
454 | #define SM501_CSC_CONTROL (0xFC) | |
ffd39257 BS |
455 | |
456 | /* 2d engine data port base */ | |
64f1603b | 457 | #define SM501_2D_ENGINE_DATA (0x110000) |
ffd39257 BS |
458 | |
459 | /* end of register definitions */ | |
460 | ||
0a4e7cd2 SK |
461 | #define SM501_HWC_WIDTH (64) |
462 | #define SM501_HWC_HEIGHT (64) | |
ffd39257 BS |
463 | |
464 | /* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */ | |
465 | static const uint32_t sm501_mem_local_size[] = { | |
d23b6caa PMD |
466 | [0] = 4 * MiB, |
467 | [1] = 8 * MiB, | |
468 | [2] = 16 * MiB, | |
469 | [3] = 32 * MiB, | |
470 | [4] = 64 * MiB, | |
471 | [5] = 2 * MiB, | |
ffd39257 BS |
472 | }; |
473 | #define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index] | |
474 | ||
475 | typedef struct SM501State { | |
476 | /* graphic console status */ | |
c78f7137 | 477 | QemuConsole *con; |
ffd39257 BS |
478 | |
479 | /* status & internal resources */ | |
ffd39257 | 480 | uint32_t local_mem_size_index; |
64f1603b | 481 | uint8_t *local_mem; |
25793bfa | 482 | MemoryRegion local_mem_region; |
ca8a1104 BZ |
483 | MemoryRegion mmio_region; |
484 | MemoryRegion system_config_region; | |
4a1f253a | 485 | MemoryRegion i2c_region; |
ca8a1104 BZ |
486 | MemoryRegion disp_ctrl_region; |
487 | MemoryRegion twoD_engine_region; | |
ffd39257 BS |
488 | uint32_t last_width; |
489 | uint32_t last_height; | |
d2733559 | 490 | bool do_full_update; /* perform a full update next time */ |
4a1f253a | 491 | I2CBus *i2c_bus; |
ffd39257 BS |
492 | |
493 | /* mmio registers */ | |
494 | uint32_t system_control; | |
495 | uint32_t misc_control; | |
496 | uint32_t gpio_31_0_control; | |
497 | uint32_t gpio_63_32_control; | |
498 | uint32_t dram_control; | |
70e46ca8 | 499 | uint32_t arbitration_control; |
ffd39257 BS |
500 | uint32_t irq_mask; |
501 | uint32_t misc_timing; | |
502 | uint32_t power_mode_control; | |
503 | ||
4a1f253a BZ |
504 | uint8_t i2c_byte_count; |
505 | uint8_t i2c_status; | |
506 | uint8_t i2c_addr; | |
507 | uint8_t i2c_data[16]; | |
508 | ||
ffd39257 BS |
509 | uint32_t uart0_ier; |
510 | uint32_t uart0_lcr; | |
511 | uint32_t uart0_mcr; | |
512 | uint32_t uart0_scr; | |
513 | ||
2edd6e4a | 514 | uint8_t dc_palette[DC_PALETTE_ENTRIES]; |
ffd39257 BS |
515 | |
516 | uint32_t dc_panel_control; | |
517 | uint32_t dc_panel_panning_control; | |
518 | uint32_t dc_panel_fb_addr; | |
519 | uint32_t dc_panel_fb_offset; | |
520 | uint32_t dc_panel_fb_width; | |
521 | uint32_t dc_panel_fb_height; | |
522 | uint32_t dc_panel_tl_location; | |
523 | uint32_t dc_panel_br_location; | |
524 | uint32_t dc_panel_h_total; | |
525 | uint32_t dc_panel_h_sync; | |
526 | uint32_t dc_panel_v_total; | |
527 | uint32_t dc_panel_v_sync; | |
528 | ||
529 | uint32_t dc_panel_hwc_addr; | |
530 | uint32_t dc_panel_hwc_location; | |
531 | uint32_t dc_panel_hwc_color_1_2; | |
532 | uint32_t dc_panel_hwc_color_3; | |
533 | ||
b612a49d BZ |
534 | uint32_t dc_video_control; |
535 | ||
ffd39257 BS |
536 | uint32_t dc_crt_control; |
537 | uint32_t dc_crt_fb_addr; | |
538 | uint32_t dc_crt_fb_offset; | |
539 | uint32_t dc_crt_h_total; | |
540 | uint32_t dc_crt_h_sync; | |
541 | uint32_t dc_crt_v_total; | |
542 | uint32_t dc_crt_v_sync; | |
543 | ||
544 | uint32_t dc_crt_hwc_addr; | |
545 | uint32_t dc_crt_hwc_location; | |
546 | uint32_t dc_crt_hwc_color_1_2; | |
547 | uint32_t dc_crt_hwc_color_3; | |
548 | ||
07d8a50c | 549 | uint32_t twoD_source; |
604be200 SK |
550 | uint32_t twoD_destination; |
551 | uint32_t twoD_dimension; | |
552 | uint32_t twoD_control; | |
553 | uint32_t twoD_pitch; | |
554 | uint32_t twoD_foreground; | |
b612a49d | 555 | uint32_t twoD_background; |
604be200 | 556 | uint32_t twoD_stretch; |
b612a49d | 557 | uint32_t twoD_color_compare; |
604be200 SK |
558 | uint32_t twoD_color_compare_mask; |
559 | uint32_t twoD_mask; | |
b612a49d BZ |
560 | uint32_t twoD_clip_tl; |
561 | uint32_t twoD_clip_br; | |
562 | uint32_t twoD_mono_pattern_low; | |
563 | uint32_t twoD_mono_pattern_high; | |
604be200 SK |
564 | uint32_t twoD_window_width; |
565 | uint32_t twoD_source_base; | |
566 | uint32_t twoD_destination_base; | |
b612a49d BZ |
567 | uint32_t twoD_alpha; |
568 | uint32_t twoD_wrap; | |
ffd39257 BS |
569 | } SM501State; |
570 | ||
571 | static uint32_t get_local_mem_size_index(uint32_t size) | |
572 | { | |
573 | uint32_t norm_size = 0; | |
574 | int i, index = 0; | |
575 | ||
b1503cda | 576 | for (i = 0; i < ARRAY_SIZE(sm501_mem_local_size); i++) { |
64f1603b BZ |
577 | uint32_t new_size = sm501_mem_local_size[i]; |
578 | if (new_size >= size) { | |
579 | if (norm_size == 0 || norm_size > new_size) { | |
580 | norm_size = new_size; | |
581 | index = i; | |
582 | } | |
583 | } | |
ffd39257 BS |
584 | } |
585 | ||
586 | return index; | |
587 | } | |
588 | ||
33159dd7 BZ |
589 | static ram_addr_t get_fb_addr(SM501State *s, int crt) |
590 | { | |
591 | return (crt ? s->dc_crt_fb_addr : s->dc_panel_fb_addr) & 0x3FFFFF0; | |
592 | } | |
593 | ||
6a2a5aae BZ |
594 | static inline int get_width(SM501State *s, int crt) |
595 | { | |
596 | int width = crt ? s->dc_crt_h_total : s->dc_panel_h_total; | |
597 | return (width & 0x00000FFF) + 1; | |
598 | } | |
599 | ||
600 | static inline int get_height(SM501State *s, int crt) | |
601 | { | |
602 | int height = crt ? s->dc_crt_v_total : s->dc_panel_v_total; | |
603 | return (height & 0x00000FFF) + 1; | |
604 | } | |
605 | ||
606 | static inline int get_bpp(SM501State *s, int crt) | |
607 | { | |
608 | int bpp = crt ? s->dc_crt_control : s->dc_panel_control; | |
609 | return 1 << (bpp & 3); | |
610 | } | |
611 | ||
0a4e7cd2 SK |
612 | /** |
613 | * Check the availability of hardware cursor. | |
614 | * @param crt 0 for PANEL, 1 for CRT. | |
615 | */ | |
616 | static inline int is_hwc_enabled(SM501State *state, int crt) | |
617 | { | |
618 | uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr; | |
e2ee8476 | 619 | return addr & SM501_HWC_EN; |
0a4e7cd2 SK |
620 | } |
621 | ||
622 | /** | |
623 | * Get the address which holds cursor pattern data. | |
624 | * @param crt 0 for PANEL, 1 for CRT. | |
625 | */ | |
6a2a5aae | 626 | static inline uint8_t *get_hwc_address(SM501State *state, int crt) |
0a4e7cd2 SK |
627 | { |
628 | uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr; | |
6a2a5aae | 629 | return state->local_mem + (addr & 0x03FFFFF0); |
0a4e7cd2 SK |
630 | } |
631 | ||
632 | /** | |
633 | * Get the cursor position in y coordinate. | |
634 | * @param crt 0 for PANEL, 1 for CRT. | |
635 | */ | |
636 | static inline uint32_t get_hwc_y(SM501State *state, int crt) | |
637 | { | |
638 | uint32_t location = crt ? state->dc_crt_hwc_location | |
639 | : state->dc_panel_hwc_location; | |
640 | return (location & 0x07FF0000) >> 16; | |
641 | } | |
642 | ||
643 | /** | |
644 | * Get the cursor position in x coordinate. | |
645 | * @param crt 0 for PANEL, 1 for CRT. | |
646 | */ | |
647 | static inline uint32_t get_hwc_x(SM501State *state, int crt) | |
648 | { | |
649 | uint32_t location = crt ? state->dc_crt_hwc_location | |
650 | : state->dc_panel_hwc_location; | |
651 | return location & 0x000007FF; | |
652 | } | |
653 | ||
654 | /** | |
6a2a5aae | 655 | * Get the hardware cursor palette. |
0a4e7cd2 | 656 | * @param crt 0 for PANEL, 1 for CRT. |
6a2a5aae | 657 | * @param palette pointer to a [3 * 3] array to store color values in |
0a4e7cd2 | 658 | */ |
6a2a5aae | 659 | static inline void get_hwc_palette(SM501State *state, int crt, uint8_t *palette) |
0a4e7cd2 | 660 | { |
6a2a5aae BZ |
661 | int i; |
662 | uint32_t color_reg; | |
663 | uint16_t rgb565; | |
664 | ||
665 | for (i = 0; i < 3; i++) { | |
666 | if (i + 1 == 3) { | |
667 | color_reg = crt ? state->dc_crt_hwc_color_3 | |
668 | : state->dc_panel_hwc_color_3; | |
669 | } else { | |
670 | color_reg = crt ? state->dc_crt_hwc_color_1_2 | |
671 | : state->dc_panel_hwc_color_1_2; | |
672 | } | |
0a4e7cd2 | 673 | |
6a2a5aae BZ |
674 | if (i + 1 == 2) { |
675 | rgb565 = (color_reg >> 16) & 0xFFFF; | |
676 | } else { | |
677 | rgb565 = color_reg & 0xFFFF; | |
678 | } | |
a69232e2 SB |
679 | palette[i * 3 + 0] = ((rgb565 >> 11) * 527 + 23) >> 6; /* r */ |
680 | palette[i * 3 + 1] = (((rgb565 >> 5) & 0x3f) * 259 + 33) >> 6; /* g */ | |
681 | palette[i * 3 + 2] = ((rgb565 & 0x1f) * 527 + 23) >> 6; /* b */ | |
0a4e7cd2 | 682 | } |
0a4e7cd2 SK |
683 | } |
684 | ||
6a2a5aae | 685 | static inline void hwc_invalidate(SM501State *s, int crt) |
0a4e7cd2 | 686 | { |
6a2a5aae BZ |
687 | int w = get_width(s, crt); |
688 | int h = get_height(s, crt); | |
689 | int bpp = get_bpp(s, crt); | |
690 | int start = get_hwc_y(s, crt); | |
691 | int end = MIN(h, start + SM501_HWC_HEIGHT) + 1; | |
692 | ||
693 | start *= w * bpp; | |
694 | end *= w * bpp; | |
695 | ||
33159dd7 BZ |
696 | memory_region_set_dirty(&s->local_mem_region, |
697 | get_fb_addr(s, crt) + start, end - start); | |
0a4e7cd2 SK |
698 | } |
699 | ||
64f1603b | 700 | static void sm501_2d_operation(SM501State *s) |
604be200 | 701 | { |
6f8183b5 | 702 | int cmd = (s->twoD_control >> 16) & 0x1F; |
2824809b | 703 | int rtl = s->twoD_control & BIT(27); |
6f8183b5 | 704 | int format = (s->twoD_stretch >> 20) & 0x3; |
debc7e7d | 705 | int rop_mode = (s->twoD_control >> 15) & 0x1; /* 1 for rop2, else rop3 */ |
06cb926a SB |
706 | /* 1 if rop2 source is the pattern, otherwise the source is the bitmap */ |
707 | int rop2_source_is_pattern = (s->twoD_control >> 14) & 0x1; | |
debc7e7d | 708 | int rop = s->twoD_control & 0xFF; |
3d0b0962 BZ |
709 | int dst_x = (s->twoD_destination >> 16) & 0x01FFF; |
710 | int dst_y = s->twoD_destination & 0xFFFF; | |
711 | int width = (s->twoD_dimension >> 16) & 0x1FFF; | |
712 | int height = s->twoD_dimension & 0xFFFF; | |
eb76243c | 713 | uint32_t dst_base = s->twoD_destination_base & 0x03FFFFFF; |
eb76243c | 714 | uint8_t *dst = s->local_mem + dst_base; |
6f8183b5 | 715 | int dst_pitch = (s->twoD_pitch >> 16) & 0x1FFF; |
eb76243c BZ |
716 | int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0; |
717 | int fb_len = get_width(s, crt) * get_height(s, crt) * get_bpp(s, crt); | |
604be200 | 718 | |
6f8183b5 | 719 | if ((s->twoD_stretch >> 16) & 0xF) { |
e29da77e BZ |
720 | qemu_log_mask(LOG_UNIMP, "sm501: only XY addressing is supported.\n"); |
721 | return; | |
604be200 SK |
722 | } |
723 | ||
06cb926a SB |
724 | if (rop_mode == 0) { |
725 | if (rop != 0xcc) { | |
726 | /* Anything other than plain copies are not supported */ | |
727 | qemu_log_mask(LOG_UNIMP, "sm501: rop3 mode with rop %x is not " | |
728 | "supported.\n", rop); | |
729 | } | |
730 | } else { | |
731 | if (rop2_source_is_pattern && rop != 0x5) { | |
732 | /* For pattern source, we support only inverse dest */ | |
733 | qemu_log_mask(LOG_UNIMP, "sm501: rop2 source being the pattern and " | |
734 | "rop %x is not supported.\n", rop); | |
735 | } else { | |
736 | if (rop != 0x5 && rop != 0xc) { | |
737 | /* Anything other than plain copies or inverse dest is not | |
738 | * supported */ | |
739 | qemu_log_mask(LOG_UNIMP, "sm501: rop mode %x is not " | |
740 | "supported.\n", rop); | |
741 | } | |
742 | } | |
743 | } | |
744 | ||
2824809b | 745 | if (s->twoD_source_base & BIT(27) || s->twoD_destination_base & BIT(27)) { |
e29da77e BZ |
746 | qemu_log_mask(LOG_UNIMP, "sm501: only local memory is supported.\n"); |
747 | return; | |
604be200 SK |
748 | } |
749 | ||
6f8183b5 | 750 | switch (cmd) { |
07d8a50c | 751 | case 0x00: /* copy area */ |
3d0b0962 BZ |
752 | { |
753 | int src_x = (s->twoD_source >> 16) & 0x01FFF; | |
754 | int src_y = s->twoD_source & 0xFFFF; | |
755 | uint32_t src_base = s->twoD_source_base & 0x03FFFFFF; | |
756 | uint8_t *src = s->local_mem + src_base; | |
757 | int src_pitch = s->twoD_pitch & 0x1FFF; | |
758 | ||
64f1603b BZ |
759 | #define COPY_AREA(_bpp, _pixel_type, rtl) { \ |
760 | int y, x, index_d, index_s; \ | |
6f8183b5 BZ |
761 | for (y = 0; y < height; y++) { \ |
762 | for (x = 0; x < width; x++) { \ | |
debc7e7d SB |
763 | _pixel_type val; \ |
764 | \ | |
64f1603b | 765 | if (rtl) { \ |
6f8183b5 BZ |
766 | index_s = ((src_y - y) * src_pitch + src_x - x) * _bpp; \ |
767 | index_d = ((dst_y - y) * dst_pitch + dst_x - x) * _bpp; \ | |
64f1603b | 768 | } else { \ |
6f8183b5 BZ |
769 | index_s = ((src_y + y) * src_pitch + src_x + x) * _bpp; \ |
770 | index_d = ((dst_y + y) * dst_pitch + dst_x + x) * _bpp; \ | |
64f1603b | 771 | } \ |
debc7e7d SB |
772 | if (rop_mode == 1 && rop == 5) { \ |
773 | /* Invert dest */ \ | |
774 | val = ~*(_pixel_type *)&dst[index_d]; \ | |
775 | } else { \ | |
776 | val = *(_pixel_type *)&src[index_s]; \ | |
777 | } \ | |
778 | *(_pixel_type *)&dst[index_d] = val; \ | |
64f1603b BZ |
779 | } \ |
780 | } \ | |
07d8a50c | 781 | } |
6f8183b5 | 782 | switch (format) { |
07d8a50c AJ |
783 | case 0: |
784 | COPY_AREA(1, uint8_t, rtl); | |
785 | break; | |
786 | case 1: | |
787 | COPY_AREA(2, uint16_t, rtl); | |
788 | break; | |
789 | case 2: | |
790 | COPY_AREA(4, uint32_t, rtl); | |
791 | break; | |
792 | } | |
793 | break; | |
3d0b0962 | 794 | } |
07d8a50c | 795 | case 0x01: /* fill rectangle */ |
3d0b0962 BZ |
796 | { |
797 | uint32_t color = s->twoD_foreground; | |
798 | ||
604be200 SK |
799 | #define FILL_RECT(_bpp, _pixel_type) { \ |
800 | int y, x; \ | |
6f8183b5 BZ |
801 | for (y = 0; y < height; y++) { \ |
802 | for (x = 0; x < width; x++) { \ | |
803 | int index = ((dst_y + y) * dst_pitch + dst_x + x) * _bpp; \ | |
64f1603b | 804 | *(_pixel_type *)&dst[index] = (_pixel_type)color; \ |
604be200 SK |
805 | } \ |
806 | } \ | |
807 | } | |
808 | ||
6f8183b5 | 809 | switch (format) { |
604be200 SK |
810 | case 0: |
811 | FILL_RECT(1, uint8_t); | |
812 | break; | |
813 | case 1: | |
f3a60058 | 814 | color = cpu_to_le16(color); |
604be200 SK |
815 | FILL_RECT(2, uint16_t); |
816 | break; | |
817 | case 2: | |
f3a60058 | 818 | color = cpu_to_le32(color); |
604be200 SK |
819 | FILL_RECT(4, uint32_t); |
820 | break; | |
821 | } | |
822 | break; | |
3d0b0962 | 823 | } |
604be200 | 824 | default: |
e29da77e | 825 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented 2D operation: %d\n", |
6f8183b5 | 826 | cmd); |
e29da77e | 827 | return; |
604be200 | 828 | } |
eb76243c BZ |
829 | |
830 | if (dst_base >= get_fb_addr(s, crt) && | |
831 | dst_base <= get_fb_addr(s, crt) + fb_len) { | |
6f8183b5 BZ |
832 | int dst_len = MIN(fb_len, ((dst_y + height - 1) * dst_pitch + |
833 | dst_x + width) * (1 << format)); | |
eb76243c BZ |
834 | if (dst_len) { |
835 | memory_region_set_dirty(&s->local_mem_region, dst_base, dst_len); | |
836 | } | |
837 | } | |
604be200 SK |
838 | } |
839 | ||
a8170e5e | 840 | static uint64_t sm501_system_config_read(void *opaque, hwaddr addr, |
25793bfa | 841 | unsigned size) |
ffd39257 | 842 | { |
64f1603b | 843 | SM501State *s = (SM501State *)opaque; |
ffd39257 | 844 | uint32_t ret = 0; |
8da3ff18 | 845 | SM501_DPRINTF("sm501 system config regs : read addr=%x\n", (int)addr); |
ffd39257 | 846 | |
64f1603b | 847 | switch (addr) { |
ffd39257 | 848 | case SM501_SYSTEM_CONTROL: |
64f1603b BZ |
849 | ret = s->system_control; |
850 | break; | |
ffd39257 | 851 | case SM501_MISC_CONTROL: |
64f1603b BZ |
852 | ret = s->misc_control; |
853 | break; | |
ffd39257 | 854 | case SM501_GPIO31_0_CONTROL: |
64f1603b BZ |
855 | ret = s->gpio_31_0_control; |
856 | break; | |
ffd39257 | 857 | case SM501_GPIO63_32_CONTROL: |
64f1603b BZ |
858 | ret = s->gpio_63_32_control; |
859 | break; | |
ffd39257 | 860 | case SM501_DEVICEID: |
64f1603b BZ |
861 | ret = 0x050100A0; |
862 | break; | |
ffd39257 | 863 | case SM501_DRAM_CONTROL: |
64f1603b BZ |
864 | ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13; |
865 | break; | |
70e46ca8 BZ |
866 | case SM501_ARBTRTN_CONTROL: |
867 | ret = s->arbitration_control; | |
868 | break; | |
5690d9ec BZ |
869 | case SM501_COMMAND_LIST_STATUS: |
870 | ret = 0x00180002; /* FIFOs are empty, everything idle */ | |
cf4969ec | 871 | break; |
ffd39257 | 872 | case SM501_IRQ_MASK: |
64f1603b BZ |
873 | ret = s->irq_mask; |
874 | break; | |
ffd39257 | 875 | case SM501_MISC_TIMING: |
64f1603b BZ |
876 | /* TODO : simulate gate control */ |
877 | ret = s->misc_timing; | |
878 | break; | |
ffd39257 | 879 | case SM501_CURRENT_GATE: |
64f1603b BZ |
880 | /* TODO : simulate gate control */ |
881 | ret = 0x00021807; | |
882 | break; | |
ffd39257 | 883 | case SM501_CURRENT_CLOCK: |
64f1603b BZ |
884 | ret = 0x2A1A0A09; |
885 | break; | |
ffd39257 | 886 | case SM501_POWER_MODE_CONTROL: |
64f1603b BZ |
887 | ret = s->power_mode_control; |
888 | break; | |
5690d9ec BZ |
889 | case SM501_ENDIAN_CONTROL: |
890 | ret = 0; /* Only default little endian mode is supported */ | |
891 | break; | |
ffd39257 BS |
892 | |
893 | default: | |
e29da77e BZ |
894 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented system config" |
895 | "register read. addr=%" HWADDR_PRIx "\n", addr); | |
ffd39257 BS |
896 | } |
897 | ||
898 | return ret; | |
899 | } | |
900 | ||
a8170e5e | 901 | static void sm501_system_config_write(void *opaque, hwaddr addr, |
25793bfa | 902 | uint64_t value, unsigned size) |
ffd39257 | 903 | { |
64f1603b | 904 | SM501State *s = (SM501State *)opaque; |
8da3ff18 | 905 | SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n", |
64f1603b | 906 | (uint32_t)addr, (uint32_t)value); |
ffd39257 | 907 | |
64f1603b | 908 | switch (addr) { |
ffd39257 | 909 | case SM501_SYSTEM_CONTROL: |
2100b6b2 BZ |
910 | s->system_control &= 0x10DB0000; |
911 | s->system_control |= value & 0xEF00B8F7; | |
64f1603b | 912 | break; |
ffd39257 | 913 | case SM501_MISC_CONTROL: |
2100b6b2 BZ |
914 | s->misc_control &= 0xEF; |
915 | s->misc_control |= value & 0xFF7FFF10; | |
64f1603b | 916 | break; |
ffd39257 | 917 | case SM501_GPIO31_0_CONTROL: |
64f1603b BZ |
918 | s->gpio_31_0_control = value; |
919 | break; | |
ffd39257 | 920 | case SM501_GPIO63_32_CONTROL: |
2100b6b2 | 921 | s->gpio_63_32_control = value & 0xFF80FFFF; |
64f1603b | 922 | break; |
ffd39257 | 923 | case SM501_DRAM_CONTROL: |
64f1603b BZ |
924 | s->local_mem_size_index = (value >> 13) & 0x7; |
925 | /* TODO : check validity of size change */ | |
2100b6b2 BZ |
926 | s->dram_control &= 0x80000000; |
927 | s->dram_control |= value & 0x7FFFFFC3; | |
64f1603b | 928 | break; |
70e46ca8 | 929 | case SM501_ARBTRTN_CONTROL: |
2100b6b2 | 930 | s->arbitration_control = value & 0x37777777; |
70e46ca8 | 931 | break; |
ffd39257 | 932 | case SM501_IRQ_MASK: |
2100b6b2 | 933 | s->irq_mask = value & 0xFFDF3F5F; |
64f1603b | 934 | break; |
ffd39257 | 935 | case SM501_MISC_TIMING: |
64f1603b BZ |
936 | s->misc_timing = value & 0xF31F1FFF; |
937 | break; | |
ffd39257 BS |
938 | case SM501_POWER_MODE_0_GATE: |
939 | case SM501_POWER_MODE_1_GATE: | |
940 | case SM501_POWER_MODE_0_CLOCK: | |
941 | case SM501_POWER_MODE_1_CLOCK: | |
64f1603b BZ |
942 | /* TODO : simulate gate & clock control */ |
943 | break; | |
ffd39257 | 944 | case SM501_POWER_MODE_CONTROL: |
64f1603b BZ |
945 | s->power_mode_control = value & 0x00000003; |
946 | break; | |
5690d9ec BZ |
947 | case SM501_ENDIAN_CONTROL: |
948 | if (value & 0x00000001) { | |
e29da77e BZ |
949 | qemu_log_mask(LOG_UNIMP, "sm501: system config big endian mode not" |
950 | " implemented.\n"); | |
5690d9ec BZ |
951 | } |
952 | break; | |
ffd39257 BS |
953 | |
954 | default: | |
e29da77e BZ |
955 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented system config" |
956 | "register write. addr=%" HWADDR_PRIx | |
957 | ", val=%" PRIx64 "\n", addr, value); | |
ffd39257 BS |
958 | } |
959 | } | |
960 | ||
25793bfa AK |
961 | static const MemoryRegionOps sm501_system_config_ops = { |
962 | .read = sm501_system_config_read, | |
963 | .write = sm501_system_config_write, | |
964 | .valid = { | |
965 | .min_access_size = 4, | |
966 | .max_access_size = 4, | |
967 | }, | |
afef2e1d | 968 | .endianness = DEVICE_LITTLE_ENDIAN, |
ffd39257 BS |
969 | }; |
970 | ||
4a1f253a BZ |
971 | static uint64_t sm501_i2c_read(void *opaque, hwaddr addr, unsigned size) |
972 | { | |
973 | SM501State *s = (SM501State *)opaque; | |
974 | uint8_t ret = 0; | |
975 | ||
976 | switch (addr) { | |
977 | case SM501_I2C_BYTE_COUNT: | |
978 | ret = s->i2c_byte_count; | |
979 | break; | |
980 | case SM501_I2C_STATUS: | |
981 | ret = s->i2c_status; | |
982 | break; | |
983 | case SM501_I2C_SLAVE_ADDRESS: | |
984 | ret = s->i2c_addr; | |
985 | break; | |
986 | case SM501_I2C_DATA ... SM501_I2C_DATA + 15: | |
987 | ret = s->i2c_data[addr - SM501_I2C_DATA]; | |
988 | break; | |
989 | default: | |
990 | qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register read." | |
991 | " addr=0x%" HWADDR_PRIx "\n", addr); | |
992 | } | |
993 | ||
994 | SM501_DPRINTF("sm501 i2c regs : read addr=%" HWADDR_PRIx " val=%x\n", | |
995 | addr, ret); | |
996 | return ret; | |
997 | } | |
998 | ||
999 | static void sm501_i2c_write(void *opaque, hwaddr addr, uint64_t value, | |
1000 | unsigned size) | |
1001 | { | |
1002 | SM501State *s = (SM501State *)opaque; | |
1003 | SM501_DPRINTF("sm501 i2c regs : write addr=%" HWADDR_PRIx | |
1004 | " val=%" PRIx64 "\n", addr, value); | |
1005 | ||
1006 | switch (addr) { | |
1007 | case SM501_I2C_BYTE_COUNT: | |
1008 | s->i2c_byte_count = value & 0xf; | |
1009 | break; | |
1010 | case SM501_I2C_CONTROL: | |
1011 | if (value & SM501_I2C_CONTROL_ENABLE) { | |
1012 | if (value & SM501_I2C_CONTROL_START) { | |
1013 | int res = i2c_start_transfer(s->i2c_bus, | |
1014 | s->i2c_addr >> 1, | |
1015 | s->i2c_addr & 1); | |
1016 | s->i2c_status |= (res ? SM501_I2C_STATUS_ERROR : 0); | |
1017 | if (!res) { | |
1018 | int i; | |
1019 | SM501_DPRINTF("sm501 i2c : transferring %d bytes to 0x%x\n", | |
1020 | s->i2c_byte_count + 1, s->i2c_addr >> 1); | |
1021 | for (i = 0; i <= s->i2c_byte_count; i++) { | |
1022 | res = i2c_send_recv(s->i2c_bus, &s->i2c_data[i], | |
1023 | !(s->i2c_addr & 1)); | |
1024 | if (res) { | |
1025 | SM501_DPRINTF("sm501 i2c : transfer failed" | |
1026 | " i=%d, res=%d\n", i, res); | |
6730df05 | 1027 | s->i2c_status |= SM501_I2C_STATUS_ERROR; |
4a1f253a BZ |
1028 | return; |
1029 | } | |
1030 | } | |
1031 | if (i) { | |
1032 | SM501_DPRINTF("sm501 i2c : transferred %d bytes\n", i); | |
1033 | s->i2c_status = SM501_I2C_STATUS_COMPLETE; | |
1034 | } | |
1035 | } | |
1036 | } else { | |
1037 | SM501_DPRINTF("sm501 i2c : end transfer\n"); | |
1038 | i2c_end_transfer(s->i2c_bus); | |
1039 | s->i2c_status &= ~SM501_I2C_STATUS_ERROR; | |
1040 | } | |
1041 | } | |
1042 | break; | |
1043 | case SM501_I2C_RESET: | |
1044 | if ((value & SM501_I2C_RESET_ERROR) == 0) { | |
1045 | s->i2c_status &= ~SM501_I2C_STATUS_ERROR; | |
1046 | } | |
1047 | break; | |
1048 | case SM501_I2C_SLAVE_ADDRESS: | |
1049 | s->i2c_addr = value & 0xff; | |
1050 | break; | |
1051 | case SM501_I2C_DATA ... SM501_I2C_DATA + 15: | |
1052 | s->i2c_data[addr - SM501_I2C_DATA] = value & 0xff; | |
1053 | break; | |
1054 | default: | |
1055 | qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register write. " | |
1056 | "addr=0x%" HWADDR_PRIx " val=%" PRIx64 "\n", addr, value); | |
1057 | } | |
1058 | } | |
1059 | ||
1060 | static const MemoryRegionOps sm501_i2c_ops = { | |
1061 | .read = sm501_i2c_read, | |
1062 | .write = sm501_i2c_write, | |
1063 | .valid = { | |
1064 | .min_access_size = 1, | |
1065 | .max_access_size = 1, | |
1066 | }, | |
1067 | .impl = { | |
1068 | .min_access_size = 1, | |
1069 | .max_access_size = 1, | |
1070 | }, | |
1071 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1072 | }; | |
1073 | ||
a8170e5e | 1074 | static uint32_t sm501_palette_read(void *opaque, hwaddr addr) |
486579de | 1075 | { |
64f1603b | 1076 | SM501State *s = (SM501State *)opaque; |
486579de AZ |
1077 | SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr); |
1078 | ||
1079 | /* TODO : consider BYTE/WORD access */ | |
1080 | /* TODO : consider endian */ | |
1081 | ||
45416789 | 1082 | assert(range_covers_byte(0, 0x400 * 3, addr)); |
64f1603b | 1083 | return *(uint32_t *)&s->dc_palette[addr]; |
486579de AZ |
1084 | } |
1085 | ||
64f1603b BZ |
1086 | static void sm501_palette_write(void *opaque, hwaddr addr, |
1087 | uint32_t value) | |
486579de | 1088 | { |
64f1603b | 1089 | SM501State *s = (SM501State *)opaque; |
486579de | 1090 | SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n", |
64f1603b | 1091 | (int)addr, value); |
486579de AZ |
1092 | |
1093 | /* TODO : consider BYTE/WORD access */ | |
1094 | /* TODO : consider endian */ | |
1095 | ||
45416789 | 1096 | assert(range_covers_byte(0, 0x400 * 3, addr)); |
64f1603b | 1097 | *(uint32_t *)&s->dc_palette[addr] = value; |
d2733559 | 1098 | s->do_full_update = true; |
486579de AZ |
1099 | } |
1100 | ||
a8170e5e | 1101 | static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr, |
25793bfa | 1102 | unsigned size) |
ffd39257 | 1103 | { |
64f1603b | 1104 | SM501State *s = (SM501State *)opaque; |
ffd39257 | 1105 | uint32_t ret = 0; |
8da3ff18 | 1106 | SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x\n", (int)addr); |
ffd39257 | 1107 | |
64f1603b | 1108 | switch (addr) { |
ffd39257 BS |
1109 | |
1110 | case SM501_DC_PANEL_CONTROL: | |
64f1603b BZ |
1111 | ret = s->dc_panel_control; |
1112 | break; | |
ffd39257 | 1113 | case SM501_DC_PANEL_PANNING_CONTROL: |
64f1603b BZ |
1114 | ret = s->dc_panel_panning_control; |
1115 | break; | |
5690d9ec BZ |
1116 | case SM501_DC_PANEL_COLOR_KEY: |
1117 | /* Not implemented yet */ | |
1118 | break; | |
ffd39257 | 1119 | case SM501_DC_PANEL_FB_ADDR: |
64f1603b BZ |
1120 | ret = s->dc_panel_fb_addr; |
1121 | break; | |
ffd39257 | 1122 | case SM501_DC_PANEL_FB_OFFSET: |
64f1603b BZ |
1123 | ret = s->dc_panel_fb_offset; |
1124 | break; | |
ffd39257 | 1125 | case SM501_DC_PANEL_FB_WIDTH: |
64f1603b BZ |
1126 | ret = s->dc_panel_fb_width; |
1127 | break; | |
ffd39257 | 1128 | case SM501_DC_PANEL_FB_HEIGHT: |
64f1603b BZ |
1129 | ret = s->dc_panel_fb_height; |
1130 | break; | |
ffd39257 | 1131 | case SM501_DC_PANEL_TL_LOC: |
64f1603b BZ |
1132 | ret = s->dc_panel_tl_location; |
1133 | break; | |
ffd39257 | 1134 | case SM501_DC_PANEL_BR_LOC: |
64f1603b BZ |
1135 | ret = s->dc_panel_br_location; |
1136 | break; | |
ffd39257 BS |
1137 | |
1138 | case SM501_DC_PANEL_H_TOT: | |
64f1603b BZ |
1139 | ret = s->dc_panel_h_total; |
1140 | break; | |
ffd39257 | 1141 | case SM501_DC_PANEL_H_SYNC: |
64f1603b BZ |
1142 | ret = s->dc_panel_h_sync; |
1143 | break; | |
ffd39257 | 1144 | case SM501_DC_PANEL_V_TOT: |
64f1603b BZ |
1145 | ret = s->dc_panel_v_total; |
1146 | break; | |
ffd39257 | 1147 | case SM501_DC_PANEL_V_SYNC: |
64f1603b BZ |
1148 | ret = s->dc_panel_v_sync; |
1149 | break; | |
ffd39257 | 1150 | |
a45de179 BZ |
1151 | case SM501_DC_PANEL_HWC_ADDR: |
1152 | ret = s->dc_panel_hwc_addr; | |
1153 | break; | |
1154 | case SM501_DC_PANEL_HWC_LOC: | |
1155 | ret = s->dc_panel_hwc_location; | |
1156 | break; | |
1157 | case SM501_DC_PANEL_HWC_COLOR_1_2: | |
1158 | ret = s->dc_panel_hwc_color_1_2; | |
1159 | break; | |
1160 | case SM501_DC_PANEL_HWC_COLOR_3: | |
1161 | ret = s->dc_panel_hwc_color_3; | |
1162 | break; | |
1163 | ||
b612a49d BZ |
1164 | case SM501_DC_VIDEO_CONTROL: |
1165 | ret = s->dc_video_control; | |
1166 | break; | |
1167 | ||
ffd39257 | 1168 | case SM501_DC_CRT_CONTROL: |
64f1603b BZ |
1169 | ret = s->dc_crt_control; |
1170 | break; | |
ffd39257 | 1171 | case SM501_DC_CRT_FB_ADDR: |
64f1603b BZ |
1172 | ret = s->dc_crt_fb_addr; |
1173 | break; | |
ffd39257 | 1174 | case SM501_DC_CRT_FB_OFFSET: |
64f1603b BZ |
1175 | ret = s->dc_crt_fb_offset; |
1176 | break; | |
ffd39257 | 1177 | case SM501_DC_CRT_H_TOT: |
64f1603b BZ |
1178 | ret = s->dc_crt_h_total; |
1179 | break; | |
ffd39257 | 1180 | case SM501_DC_CRT_H_SYNC: |
64f1603b BZ |
1181 | ret = s->dc_crt_h_sync; |
1182 | break; | |
ffd39257 | 1183 | case SM501_DC_CRT_V_TOT: |
64f1603b BZ |
1184 | ret = s->dc_crt_v_total; |
1185 | break; | |
ffd39257 | 1186 | case SM501_DC_CRT_V_SYNC: |
64f1603b BZ |
1187 | ret = s->dc_crt_v_sync; |
1188 | break; | |
ffd39257 BS |
1189 | |
1190 | case SM501_DC_CRT_HWC_ADDR: | |
64f1603b BZ |
1191 | ret = s->dc_crt_hwc_addr; |
1192 | break; | |
ffd39257 | 1193 | case SM501_DC_CRT_HWC_LOC: |
64f1603b BZ |
1194 | ret = s->dc_crt_hwc_location; |
1195 | break; | |
ffd39257 | 1196 | case SM501_DC_CRT_HWC_COLOR_1_2: |
64f1603b BZ |
1197 | ret = s->dc_crt_hwc_color_1_2; |
1198 | break; | |
ffd39257 | 1199 | case SM501_DC_CRT_HWC_COLOR_3: |
64f1603b BZ |
1200 | ret = s->dc_crt_hwc_color_3; |
1201 | break; | |
ffd39257 | 1202 | |
64f1603b | 1203 | case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4: |
486579de AZ |
1204 | ret = sm501_palette_read(opaque, addr - SM501_DC_PANEL_PALETTE); |
1205 | break; | |
1206 | ||
ffd39257 | 1207 | default: |
e29da77e BZ |
1208 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register " |
1209 | "read. addr=%" HWADDR_PRIx "\n", addr); | |
ffd39257 BS |
1210 | } |
1211 | ||
1212 | return ret; | |
1213 | } | |
1214 | ||
a8170e5e | 1215 | static void sm501_disp_ctrl_write(void *opaque, hwaddr addr, |
25793bfa | 1216 | uint64_t value, unsigned size) |
ffd39257 | 1217 | { |
64f1603b | 1218 | SM501State *s = (SM501State *)opaque; |
8da3ff18 | 1219 | SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, val=%x\n", |
64f1603b | 1220 | (unsigned)addr, (unsigned)value); |
ffd39257 | 1221 | |
64f1603b | 1222 | switch (addr) { |
ffd39257 | 1223 | case SM501_DC_PANEL_CONTROL: |
64f1603b BZ |
1224 | s->dc_panel_control = value & 0x0FFF73FF; |
1225 | break; | |
ffd39257 | 1226 | case SM501_DC_PANEL_PANNING_CONTROL: |
64f1603b BZ |
1227 | s->dc_panel_panning_control = value & 0xFF3FFF3F; |
1228 | break; | |
5690d9ec BZ |
1229 | case SM501_DC_PANEL_COLOR_KEY: |
1230 | /* Not implemented yet */ | |
1231 | break; | |
ffd39257 | 1232 | case SM501_DC_PANEL_FB_ADDR: |
64f1603b | 1233 | s->dc_panel_fb_addr = value & 0x8FFFFFF0; |
33159dd7 BZ |
1234 | if (value & 0x8000000) { |
1235 | qemu_log_mask(LOG_UNIMP, "Panel external memory not supported\n"); | |
1236 | } | |
593a1cdd | 1237 | s->do_full_update = true; |
64f1603b | 1238 | break; |
ffd39257 | 1239 | case SM501_DC_PANEL_FB_OFFSET: |
64f1603b BZ |
1240 | s->dc_panel_fb_offset = value & 0x3FF03FF0; |
1241 | break; | |
ffd39257 | 1242 | case SM501_DC_PANEL_FB_WIDTH: |
64f1603b BZ |
1243 | s->dc_panel_fb_width = value & 0x0FFF0FFF; |
1244 | break; | |
ffd39257 | 1245 | case SM501_DC_PANEL_FB_HEIGHT: |
64f1603b BZ |
1246 | s->dc_panel_fb_height = value & 0x0FFF0FFF; |
1247 | break; | |
ffd39257 | 1248 | case SM501_DC_PANEL_TL_LOC: |
64f1603b BZ |
1249 | s->dc_panel_tl_location = value & 0x07FF07FF; |
1250 | break; | |
ffd39257 | 1251 | case SM501_DC_PANEL_BR_LOC: |
64f1603b BZ |
1252 | s->dc_panel_br_location = value & 0x07FF07FF; |
1253 | break; | |
ffd39257 BS |
1254 | |
1255 | case SM501_DC_PANEL_H_TOT: | |
64f1603b BZ |
1256 | s->dc_panel_h_total = value & 0x0FFF0FFF; |
1257 | break; | |
ffd39257 | 1258 | case SM501_DC_PANEL_H_SYNC: |
64f1603b BZ |
1259 | s->dc_panel_h_sync = value & 0x00FF0FFF; |
1260 | break; | |
ffd39257 | 1261 | case SM501_DC_PANEL_V_TOT: |
64f1603b BZ |
1262 | s->dc_panel_v_total = value & 0x0FFF0FFF; |
1263 | break; | |
ffd39257 | 1264 | case SM501_DC_PANEL_V_SYNC: |
64f1603b BZ |
1265 | s->dc_panel_v_sync = value & 0x003F0FFF; |
1266 | break; | |
ffd39257 BS |
1267 | |
1268 | case SM501_DC_PANEL_HWC_ADDR: | |
6a2a5aae BZ |
1269 | value &= 0x8FFFFFF0; |
1270 | if (value != s->dc_panel_hwc_addr) { | |
1271 | hwc_invalidate(s, 0); | |
1272 | s->dc_panel_hwc_addr = value; | |
1273 | } | |
64f1603b | 1274 | break; |
ffd39257 | 1275 | case SM501_DC_PANEL_HWC_LOC: |
6a2a5aae BZ |
1276 | value &= 0x0FFF0FFF; |
1277 | if (value != s->dc_panel_hwc_location) { | |
1278 | hwc_invalidate(s, 0); | |
1279 | s->dc_panel_hwc_location = value; | |
1280 | } | |
64f1603b | 1281 | break; |
ffd39257 | 1282 | case SM501_DC_PANEL_HWC_COLOR_1_2: |
64f1603b BZ |
1283 | s->dc_panel_hwc_color_1_2 = value; |
1284 | break; | |
ffd39257 | 1285 | case SM501_DC_PANEL_HWC_COLOR_3: |
64f1603b BZ |
1286 | s->dc_panel_hwc_color_3 = value & 0x0000FFFF; |
1287 | break; | |
ffd39257 | 1288 | |
b612a49d BZ |
1289 | case SM501_DC_VIDEO_CONTROL: |
1290 | s->dc_video_control = value & 0x00037FFF; | |
1291 | break; | |
1292 | ||
ffd39257 | 1293 | case SM501_DC_CRT_CONTROL: |
64f1603b BZ |
1294 | s->dc_crt_control = value & 0x0003FFFF; |
1295 | break; | |
ffd39257 | 1296 | case SM501_DC_CRT_FB_ADDR: |
64f1603b | 1297 | s->dc_crt_fb_addr = value & 0x8FFFFFF0; |
33159dd7 BZ |
1298 | if (value & 0x8000000) { |
1299 | qemu_log_mask(LOG_UNIMP, "CRT external memory not supported\n"); | |
1300 | } | |
593a1cdd | 1301 | s->do_full_update = true; |
64f1603b | 1302 | break; |
ffd39257 | 1303 | case SM501_DC_CRT_FB_OFFSET: |
64f1603b BZ |
1304 | s->dc_crt_fb_offset = value & 0x3FF03FF0; |
1305 | break; | |
ffd39257 | 1306 | case SM501_DC_CRT_H_TOT: |
64f1603b BZ |
1307 | s->dc_crt_h_total = value & 0x0FFF0FFF; |
1308 | break; | |
ffd39257 | 1309 | case SM501_DC_CRT_H_SYNC: |
64f1603b BZ |
1310 | s->dc_crt_h_sync = value & 0x00FF0FFF; |
1311 | break; | |
ffd39257 | 1312 | case SM501_DC_CRT_V_TOT: |
64f1603b BZ |
1313 | s->dc_crt_v_total = value & 0x0FFF0FFF; |
1314 | break; | |
ffd39257 | 1315 | case SM501_DC_CRT_V_SYNC: |
64f1603b BZ |
1316 | s->dc_crt_v_sync = value & 0x003F0FFF; |
1317 | break; | |
ffd39257 BS |
1318 | |
1319 | case SM501_DC_CRT_HWC_ADDR: | |
6a2a5aae BZ |
1320 | value &= 0x8FFFFFF0; |
1321 | if (value != s->dc_crt_hwc_addr) { | |
1322 | hwc_invalidate(s, 1); | |
1323 | s->dc_crt_hwc_addr = value; | |
1324 | } | |
64f1603b | 1325 | break; |
ffd39257 | 1326 | case SM501_DC_CRT_HWC_LOC: |
6a2a5aae BZ |
1327 | value &= 0x0FFF0FFF; |
1328 | if (value != s->dc_crt_hwc_location) { | |
1329 | hwc_invalidate(s, 1); | |
1330 | s->dc_crt_hwc_location = value; | |
1331 | } | |
64f1603b | 1332 | break; |
ffd39257 | 1333 | case SM501_DC_CRT_HWC_COLOR_1_2: |
64f1603b BZ |
1334 | s->dc_crt_hwc_color_1_2 = value; |
1335 | break; | |
ffd39257 | 1336 | case SM501_DC_CRT_HWC_COLOR_3: |
64f1603b BZ |
1337 | s->dc_crt_hwc_color_3 = value & 0x0000FFFF; |
1338 | break; | |
ffd39257 | 1339 | |
64f1603b | 1340 | case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4: |
486579de AZ |
1341 | sm501_palette_write(opaque, addr - SM501_DC_PANEL_PALETTE, value); |
1342 | break; | |
1343 | ||
ffd39257 | 1344 | default: |
e29da77e BZ |
1345 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register " |
1346 | "write. addr=%" HWADDR_PRIx | |
1347 | ", val=%" PRIx64 "\n", addr, value); | |
ffd39257 BS |
1348 | } |
1349 | } | |
1350 | ||
25793bfa AK |
1351 | static const MemoryRegionOps sm501_disp_ctrl_ops = { |
1352 | .read = sm501_disp_ctrl_read, | |
1353 | .write = sm501_disp_ctrl_write, | |
1354 | .valid = { | |
1355 | .min_access_size = 4, | |
1356 | .max_access_size = 4, | |
1357 | }, | |
afef2e1d | 1358 | .endianness = DEVICE_LITTLE_ENDIAN, |
ffd39257 BS |
1359 | }; |
1360 | ||
a8170e5e | 1361 | static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr, |
25793bfa | 1362 | unsigned size) |
604be200 | 1363 | { |
64f1603b | 1364 | SM501State *s = (SM501State *)opaque; |
604be200 SK |
1365 | uint32_t ret = 0; |
1366 | SM501_DPRINTF("sm501 2d engine regs : read addr=%x\n", (int)addr); | |
1367 | ||
64f1603b | 1368 | switch (addr) { |
b612a49d BZ |
1369 | case SM501_2D_SOURCE: |
1370 | ret = s->twoD_source; | |
1371 | break; | |
1372 | case SM501_2D_DESTINATION: | |
1373 | ret = s->twoD_destination; | |
1374 | break; | |
1375 | case SM501_2D_DIMENSION: | |
1376 | ret = s->twoD_dimension; | |
1377 | break; | |
1378 | case SM501_2D_CONTROL: | |
1379 | ret = s->twoD_control; | |
1380 | break; | |
1381 | case SM501_2D_PITCH: | |
1382 | ret = s->twoD_pitch; | |
1383 | break; | |
1384 | case SM501_2D_FOREGROUND: | |
1385 | ret = s->twoD_foreground; | |
1386 | break; | |
1387 | case SM501_2D_BACKGROUND: | |
1388 | ret = s->twoD_background; | |
1389 | break; | |
1390 | case SM501_2D_STRETCH: | |
1391 | ret = s->twoD_stretch; | |
1392 | break; | |
1393 | case SM501_2D_COLOR_COMPARE: | |
1394 | ret = s->twoD_color_compare; | |
1395 | break; | |
1396 | case SM501_2D_COLOR_COMPARE_MASK: | |
1397 | ret = s->twoD_color_compare_mask; | |
1398 | break; | |
1399 | case SM501_2D_MASK: | |
1400 | ret = s->twoD_mask; | |
1401 | break; | |
1402 | case SM501_2D_CLIP_TL: | |
1403 | ret = s->twoD_clip_tl; | |
1404 | break; | |
1405 | case SM501_2D_CLIP_BR: | |
1406 | ret = s->twoD_clip_br; | |
1407 | break; | |
1408 | case SM501_2D_MONO_PATTERN_LOW: | |
1409 | ret = s->twoD_mono_pattern_low; | |
1410 | break; | |
1411 | case SM501_2D_MONO_PATTERN_HIGH: | |
1412 | ret = s->twoD_mono_pattern_high; | |
1413 | break; | |
1414 | case SM501_2D_WINDOW_WIDTH: | |
1415 | ret = s->twoD_window_width; | |
1416 | break; | |
604be200 SK |
1417 | case SM501_2D_SOURCE_BASE: |
1418 | ret = s->twoD_source_base; | |
1419 | break; | |
b612a49d BZ |
1420 | case SM501_2D_DESTINATION_BASE: |
1421 | ret = s->twoD_destination_base; | |
1422 | break; | |
1423 | case SM501_2D_ALPHA: | |
1424 | ret = s->twoD_alpha; | |
1425 | break; | |
1426 | case SM501_2D_WRAP: | |
1427 | ret = s->twoD_wrap; | |
1428 | break; | |
1429 | case SM501_2D_STATUS: | |
1430 | ret = 0; /* Should return interrupt status */ | |
1431 | break; | |
604be200 | 1432 | default: |
e29da77e BZ |
1433 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register " |
1434 | "read. addr=%" HWADDR_PRIx "\n", addr); | |
604be200 SK |
1435 | } |
1436 | ||
1437 | return ret; | |
1438 | } | |
1439 | ||
a8170e5e | 1440 | static void sm501_2d_engine_write(void *opaque, hwaddr addr, |
25793bfa | 1441 | uint64_t value, unsigned size) |
604be200 | 1442 | { |
64f1603b | 1443 | SM501State *s = (SM501State *)opaque; |
604be200 | 1444 | SM501_DPRINTF("sm501 2d engine regs : write addr=%x, val=%x\n", |
25793bfa | 1445 | (unsigned)addr, (unsigned)value); |
604be200 | 1446 | |
64f1603b | 1447 | switch (addr) { |
07d8a50c AJ |
1448 | case SM501_2D_SOURCE: |
1449 | s->twoD_source = value; | |
1450 | break; | |
604be200 SK |
1451 | case SM501_2D_DESTINATION: |
1452 | s->twoD_destination = value; | |
1453 | break; | |
1454 | case SM501_2D_DIMENSION: | |
1455 | s->twoD_dimension = value; | |
1456 | break; | |
1457 | case SM501_2D_CONTROL: | |
1458 | s->twoD_control = value; | |
1459 | ||
1460 | /* do 2d operation if start flag is set. */ | |
1461 | if (value & 0x80000000) { | |
1462 | sm501_2d_operation(s); | |
1463 | s->twoD_control &= ~0x80000000; /* start flag down */ | |
1464 | } | |
1465 | ||
1466 | break; | |
1467 | case SM501_2D_PITCH: | |
1468 | s->twoD_pitch = value; | |
1469 | break; | |
1470 | case SM501_2D_FOREGROUND: | |
1471 | s->twoD_foreground = value; | |
1472 | break; | |
b612a49d BZ |
1473 | case SM501_2D_BACKGROUND: |
1474 | s->twoD_background = value; | |
1475 | break; | |
604be200 SK |
1476 | case SM501_2D_STRETCH: |
1477 | s->twoD_stretch = value; | |
1478 | break; | |
b612a49d BZ |
1479 | case SM501_2D_COLOR_COMPARE: |
1480 | s->twoD_color_compare = value; | |
1481 | break; | |
604be200 SK |
1482 | case SM501_2D_COLOR_COMPARE_MASK: |
1483 | s->twoD_color_compare_mask = value; | |
1484 | break; | |
1485 | case SM501_2D_MASK: | |
1486 | s->twoD_mask = value; | |
1487 | break; | |
b612a49d BZ |
1488 | case SM501_2D_CLIP_TL: |
1489 | s->twoD_clip_tl = value; | |
1490 | break; | |
1491 | case SM501_2D_CLIP_BR: | |
1492 | s->twoD_clip_br = value; | |
1493 | break; | |
1494 | case SM501_2D_MONO_PATTERN_LOW: | |
1495 | s->twoD_mono_pattern_low = value; | |
1496 | break; | |
1497 | case SM501_2D_MONO_PATTERN_HIGH: | |
1498 | s->twoD_mono_pattern_high = value; | |
1499 | break; | |
604be200 SK |
1500 | case SM501_2D_WINDOW_WIDTH: |
1501 | s->twoD_window_width = value; | |
1502 | break; | |
1503 | case SM501_2D_SOURCE_BASE: | |
1504 | s->twoD_source_base = value; | |
1505 | break; | |
1506 | case SM501_2D_DESTINATION_BASE: | |
1507 | s->twoD_destination_base = value; | |
1508 | break; | |
b612a49d BZ |
1509 | case SM501_2D_ALPHA: |
1510 | s->twoD_alpha = value; | |
1511 | break; | |
1512 | case SM501_2D_WRAP: | |
1513 | s->twoD_wrap = value; | |
1514 | break; | |
1515 | case SM501_2D_STATUS: | |
1516 | /* ignored, writing 0 should clear interrupt status */ | |
1517 | break; | |
604be200 | 1518 | default: |
e29da77e BZ |
1519 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented 2d engine register " |
1520 | "write. addr=%" HWADDR_PRIx | |
1521 | ", val=%" PRIx64 "\n", addr, value); | |
604be200 SK |
1522 | } |
1523 | } | |
1524 | ||
25793bfa AK |
1525 | static const MemoryRegionOps sm501_2d_engine_ops = { |
1526 | .read = sm501_2d_engine_read, | |
1527 | .write = sm501_2d_engine_write, | |
1528 | .valid = { | |
1529 | .min_access_size = 4, | |
1530 | .max_access_size = 4, | |
1531 | }, | |
afef2e1d | 1532 | .endianness = DEVICE_LITTLE_ENDIAN, |
604be200 SK |
1533 | }; |
1534 | ||
ffd39257 BS |
1535 | /* draw line functions for all console modes */ |
1536 | ||
ffd39257 | 1537 | typedef void draw_line_func(uint8_t *d, const uint8_t *s, |
64f1603b | 1538 | int width, const uint32_t *pal); |
ffd39257 | 1539 | |
6a2a5aae BZ |
1540 | typedef void draw_hwc_line_func(uint8_t *d, const uint8_t *s, |
1541 | int width, const uint8_t *palette, | |
1542 | int c_x, int c_y); | |
0a4e7cd2 | 1543 | |
ffd39257 | 1544 | #define DEPTH 8 |
47b43a1f | 1545 | #include "sm501_template.h" |
ffd39257 BS |
1546 | |
1547 | #define DEPTH 15 | |
47b43a1f | 1548 | #include "sm501_template.h" |
ffd39257 BS |
1549 | |
1550 | #define BGR_FORMAT | |
1551 | #define DEPTH 15 | |
47b43a1f | 1552 | #include "sm501_template.h" |
ffd39257 BS |
1553 | |
1554 | #define DEPTH 16 | |
47b43a1f | 1555 | #include "sm501_template.h" |
ffd39257 BS |
1556 | |
1557 | #define BGR_FORMAT | |
1558 | #define DEPTH 16 | |
47b43a1f | 1559 | #include "sm501_template.h" |
ffd39257 BS |
1560 | |
1561 | #define DEPTH 32 | |
47b43a1f | 1562 | #include "sm501_template.h" |
ffd39257 BS |
1563 | |
1564 | #define BGR_FORMAT | |
1565 | #define DEPTH 32 | |
47b43a1f | 1566 | #include "sm501_template.h" |
ffd39257 | 1567 | |
64f1603b | 1568 | static draw_line_func *draw_line8_funcs[] = { |
ffd39257 BS |
1569 | draw_line8_8, |
1570 | draw_line8_15, | |
1571 | draw_line8_16, | |
1572 | draw_line8_32, | |
1573 | draw_line8_32bgr, | |
1574 | draw_line8_15bgr, | |
1575 | draw_line8_16bgr, | |
1576 | }; | |
1577 | ||
64f1603b | 1578 | static draw_line_func *draw_line16_funcs[] = { |
ffd39257 BS |
1579 | draw_line16_8, |
1580 | draw_line16_15, | |
1581 | draw_line16_16, | |
1582 | draw_line16_32, | |
1583 | draw_line16_32bgr, | |
1584 | draw_line16_15bgr, | |
1585 | draw_line16_16bgr, | |
1586 | }; | |
1587 | ||
64f1603b | 1588 | static draw_line_func *draw_line32_funcs[] = { |
ffd39257 BS |
1589 | draw_line32_8, |
1590 | draw_line32_15, | |
1591 | draw_line32_16, | |
1592 | draw_line32_32, | |
1593 | draw_line32_32bgr, | |
1594 | draw_line32_15bgr, | |
1595 | draw_line32_16bgr, | |
1596 | }; | |
1597 | ||
64f1603b | 1598 | static draw_hwc_line_func *draw_hwc_line_funcs[] = { |
0a4e7cd2 SK |
1599 | draw_hwc_line_8, |
1600 | draw_hwc_line_15, | |
1601 | draw_hwc_line_16, | |
1602 | draw_hwc_line_32, | |
1603 | draw_hwc_line_32bgr, | |
1604 | draw_hwc_line_15bgr, | |
1605 | draw_hwc_line_16bgr, | |
1606 | }; | |
1607 | ||
c78f7137 | 1608 | static inline int get_depth_index(DisplaySurface *surface) |
ffd39257 | 1609 | { |
c78f7137 | 1610 | switch (surface_bits_per_pixel(surface)) { |
ffd39257 BS |
1611 | default: |
1612 | case 8: | |
64f1603b | 1613 | return 0; |
ffd39257 | 1614 | case 15: |
8927bcfd | 1615 | return 1; |
ffd39257 | 1616 | case 16: |
8927bcfd | 1617 | return 2; |
ffd39257 | 1618 | case 32: |
c78f7137 GH |
1619 | if (is_surface_bgr(surface)) { |
1620 | return 4; | |
1621 | } else { | |
1622 | return 3; | |
1623 | } | |
ffd39257 BS |
1624 | } |
1625 | } | |
1626 | ||
1ae5e6eb | 1627 | static void sm501_update_display(void *opaque) |
ffd39257 | 1628 | { |
1ae5e6eb | 1629 | SM501State *s = (SM501State *)opaque; |
c78f7137 | 1630 | DisplaySurface *surface = qemu_console_surface(s->con); |
ca7f5441 | 1631 | DirtyBitmapSnapshot *snap; |
6a2a5aae | 1632 | int y, c_x = 0, c_y = 0; |
1ae5e6eb BZ |
1633 | int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0; |
1634 | int width = get_width(s, crt); | |
1635 | int height = get_height(s, crt); | |
1636 | int src_bpp = get_bpp(s, crt); | |
c78f7137 | 1637 | int dst_bpp = surface_bytes_per_pixel(surface); |
01d2d584 | 1638 | int dst_depth_index = get_depth_index(surface); |
64f1603b BZ |
1639 | draw_line_func *draw_line = NULL; |
1640 | draw_hwc_line_func *draw_hwc_line = NULL; | |
ffd39257 BS |
1641 | int full_update = 0; |
1642 | int y_start = -1; | |
33159dd7 | 1643 | ram_addr_t offset; |
1ae5e6eb BZ |
1644 | uint32_t *palette; |
1645 | uint8_t hwc_palette[3 * 3]; | |
1646 | uint8_t *hwc_src = NULL; | |
1647 | ||
1648 | if (!((crt ? s->dc_crt_control : s->dc_panel_control) | |
1649 | & SM501_DC_CRT_CONTROL_ENABLE)) { | |
1650 | return; | |
1651 | } | |
1652 | ||
1653 | palette = (uint32_t *)(crt ? &s->dc_palette[SM501_DC_CRT_PALETTE - | |
1654 | SM501_DC_PANEL_PALETTE] | |
1655 | : &s->dc_palette[0]); | |
ffd39257 BS |
1656 | |
1657 | /* choose draw_line function */ | |
6a2a5aae BZ |
1658 | switch (src_bpp) { |
1659 | case 1: | |
01d2d584 | 1660 | draw_line = draw_line8_funcs[dst_depth_index]; |
64f1603b | 1661 | break; |
6a2a5aae | 1662 | case 2: |
01d2d584 | 1663 | draw_line = draw_line16_funcs[dst_depth_index]; |
64f1603b | 1664 | break; |
6a2a5aae | 1665 | case 4: |
01d2d584 | 1666 | draw_line = draw_line32_funcs[dst_depth_index]; |
64f1603b | 1667 | break; |
ffd39257 | 1668 | default: |
e29da77e BZ |
1669 | qemu_log_mask(LOG_GUEST_ERROR, "sm501: update display" |
1670 | "invalid control register value.\n"); | |
1671 | return; | |
ffd39257 BS |
1672 | } |
1673 | ||
0a4e7cd2 | 1674 | /* set up to draw hardware cursor */ |
1ae5e6eb | 1675 | if (is_hwc_enabled(s, crt)) { |
0a4e7cd2 | 1676 | /* choose cursor draw line function */ |
01d2d584 | 1677 | draw_hwc_line = draw_hwc_line_funcs[dst_depth_index]; |
1ae5e6eb BZ |
1678 | hwc_src = get_hwc_address(s, crt); |
1679 | c_x = get_hwc_x(s, crt); | |
1680 | c_y = get_hwc_y(s, crt); | |
1681 | get_hwc_palette(s, crt, hwc_palette); | |
0a4e7cd2 SK |
1682 | } |
1683 | ||
ffd39257 BS |
1684 | /* adjust console size */ |
1685 | if (s->last_width != width || s->last_height != height) { | |
c78f7137 GH |
1686 | qemu_console_resize(s->con, width, height); |
1687 | surface = qemu_console_surface(s->con); | |
64f1603b BZ |
1688 | s->last_width = width; |
1689 | s->last_height = height; | |
1690 | full_update = 1; | |
ffd39257 BS |
1691 | } |
1692 | ||
d2733559 SB |
1693 | /* someone else requested a full update */ |
1694 | if (s->do_full_update) { | |
1695 | s->do_full_update = false; | |
1696 | full_update = 1; | |
1697 | } | |
1698 | ||
ffd39257 | 1699 | /* draw each line according to conditions */ |
33159dd7 | 1700 | offset = get_fb_addr(s, crt); |
ca7f5441 GH |
1701 | snap = memory_region_snapshot_and_clear_dirty(&s->local_mem_region, |
1702 | offset, width * height * src_bpp, DIRTY_MEMORY_VGA); | |
33159dd7 | 1703 | for (y = 0; y < height; y++, offset += width * src_bpp) { |
6a2a5aae | 1704 | int update, update_hwc; |
ffd39257 | 1705 | |
6a2a5aae BZ |
1706 | /* check if hardware cursor is enabled and we're within its range */ |
1707 | update_hwc = draw_hwc_line && c_y <= y && y < c_y + SM501_HWC_HEIGHT; | |
1708 | update = full_update || update_hwc; | |
64f1603b | 1709 | /* check dirty flags for each line */ |
ca7f5441 GH |
1710 | update |= memory_region_snapshot_get_dirty(&s->local_mem_region, snap, |
1711 | offset, width * src_bpp); | |
ffd39257 | 1712 | |
64f1603b BZ |
1713 | /* draw line and change status */ |
1714 | if (update) { | |
c78f7137 GH |
1715 | uint8_t *d = surface_data(surface); |
1716 | d += y * width * dst_bpp; | |
0a4e7cd2 SK |
1717 | |
1718 | /* draw graphics layer */ | |
1ae5e6eb | 1719 | draw_line(d, s->local_mem + offset, width, palette); |
0a4e7cd2 | 1720 | |
64f1603b | 1721 | /* draw hardware cursor */ |
0a4e7cd2 | 1722 | if (update_hwc) { |
6a2a5aae | 1723 | draw_hwc_line(d, hwc_src, width, hwc_palette, c_x, y - c_y); |
0a4e7cd2 SK |
1724 | } |
1725 | ||
64f1603b BZ |
1726 | if (y_start < 0) { |
1727 | y_start = y; | |
1728 | } | |
64f1603b BZ |
1729 | } else { |
1730 | if (y_start >= 0) { | |
1731 | /* flush to display */ | |
c78f7137 | 1732 | dpy_gfx_update(s->con, 0, y_start, width, y - y_start); |
64f1603b BZ |
1733 | y_start = -1; |
1734 | } | |
1735 | } | |
ffd39257 | 1736 | } |
ca7f5441 | 1737 | g_free(snap); |
ffd39257 BS |
1738 | |
1739 | /* complete flush to display */ | |
64f1603b | 1740 | if (y_start >= 0) { |
c78f7137 | 1741 | dpy_gfx_update(s->con, 0, y_start, width, y - y_start); |
64f1603b | 1742 | } |
ffd39257 BS |
1743 | } |
1744 | ||
380cd056 GH |
1745 | static const GraphicHwOps sm501_ops = { |
1746 | .gfx_update = sm501_update_display, | |
1747 | }; | |
1748 | ||
ca8a1104 | 1749 | static void sm501_reset(SM501State *s) |
ffd39257 | 1750 | { |
e2ee8476 BZ |
1751 | s->system_control = 0x00100000; /* 2D engine FIFO empty */ |
1752 | /* Bits 17 (SH), 7 (CDR), 6:5 (Test), 2:0 (Bus) are all supposed | |
1753 | * to be determined at reset by GPIO lines which set config bits. | |
1754 | * We hardwire them: | |
1755 | * SH = 0 : Hitachi Ready Polarity == Active Low | |
1756 | * CDR = 0 : do not reset clock divider | |
1757 | * TEST = 0 : Normal mode (not testing the silicon) | |
1758 | * BUS = 0 : Hitachi SH3/SH4 | |
1759 | */ | |
1760 | s->misc_control = SM501_MISC_DAC_POWER; | |
ca8a1104 BZ |
1761 | s->gpio_31_0_control = 0; |
1762 | s->gpio_63_32_control = 0; | |
1763 | s->dram_control = 0; | |
70e46ca8 | 1764 | s->arbitration_control = 0x05146732; |
ca8a1104 BZ |
1765 | s->irq_mask = 0; |
1766 | s->misc_timing = 0; | |
1767 | s->power_mode_control = 0; | |
4a1f253a BZ |
1768 | s->i2c_byte_count = 0; |
1769 | s->i2c_status = 0; | |
1770 | s->i2c_addr = 0; | |
1771 | memset(s->i2c_data, 0, 16); | |
e2ee8476 | 1772 | s->dc_panel_control = 0x00010000; /* FIFO level 3 */ |
b612a49d | 1773 | s->dc_video_control = 0; |
ffd39257 | 1774 | s->dc_crt_control = 0x00010000; |
b612a49d BZ |
1775 | s->twoD_source = 0; |
1776 | s->twoD_destination = 0; | |
1777 | s->twoD_dimension = 0; | |
ca8a1104 | 1778 | s->twoD_control = 0; |
b612a49d BZ |
1779 | s->twoD_pitch = 0; |
1780 | s->twoD_foreground = 0; | |
1781 | s->twoD_background = 0; | |
1782 | s->twoD_stretch = 0; | |
1783 | s->twoD_color_compare = 0; | |
1784 | s->twoD_color_compare_mask = 0; | |
1785 | s->twoD_mask = 0; | |
1786 | s->twoD_clip_tl = 0; | |
1787 | s->twoD_clip_br = 0; | |
1788 | s->twoD_mono_pattern_low = 0; | |
1789 | s->twoD_mono_pattern_high = 0; | |
1790 | s->twoD_window_width = 0; | |
1791 | s->twoD_source_base = 0; | |
1792 | s->twoD_destination_base = 0; | |
1793 | s->twoD_alpha = 0; | |
1794 | s->twoD_wrap = 0; | |
ca8a1104 | 1795 | } |
ffd39257 | 1796 | |
c795fa84 | 1797 | static void sm501_init(SM501State *s, DeviceState *dev, |
ca8a1104 BZ |
1798 | uint32_t local_mem_bytes) |
1799 | { | |
ca8a1104 BZ |
1800 | s->local_mem_size_index = get_local_mem_size_index(local_mem_bytes); |
1801 | SM501_DPRINTF("sm501 local mem size=%x. index=%d\n", get_local_mem_size(s), | |
1802 | s->local_mem_size_index); | |
1803 | ||
1804 | /* local memory */ | |
4c4414a4 | 1805 | memory_region_init_ram(&s->local_mem_region, OBJECT(dev), "sm501.local", |
ca8a1104 | 1806 | get_local_mem_size(s), &error_fatal); |
74259ae5 | 1807 | memory_region_set_log(&s->local_mem_region, true, DIRTY_MEMORY_VGA); |
25793bfa | 1808 | s->local_mem = memory_region_get_ram_ptr(&s->local_mem_region); |
ca8a1104 | 1809 | |
4a1f253a BZ |
1810 | /* i2c */ |
1811 | s->i2c_bus = i2c_init_bus(dev, "sm501.i2c"); | |
1812 | /* ddc */ | |
1813 | I2CDDCState *ddc = I2CDDC(qdev_create(BUS(s->i2c_bus), TYPE_I2CDDC)); | |
1814 | i2c_set_slave_address(I2C_SLAVE(ddc), 0x50); | |
1815 | ||
ca8a1104 BZ |
1816 | /* mmio */ |
1817 | memory_region_init(&s->mmio_region, OBJECT(dev), "sm501.mmio", MMIO_SIZE); | |
1818 | memory_region_init_io(&s->system_config_region, OBJECT(dev), | |
1819 | &sm501_system_config_ops, s, | |
1820 | "sm501-system-config", 0x6c); | |
1821 | memory_region_add_subregion(&s->mmio_region, SM501_SYS_CONFIG, | |
1822 | &s->system_config_region); | |
4a1f253a BZ |
1823 | memory_region_init_io(&s->i2c_region, OBJECT(dev), &sm501_i2c_ops, s, |
1824 | "sm501-i2c", 0x14); | |
1825 | memory_region_add_subregion(&s->mmio_region, SM501_I2C, &s->i2c_region); | |
ca8a1104 BZ |
1826 | memory_region_init_io(&s->disp_ctrl_region, OBJECT(dev), |
1827 | &sm501_disp_ctrl_ops, s, | |
25793bfa | 1828 | "sm501-disp-ctrl", 0x1000); |
ca8a1104 BZ |
1829 | memory_region_add_subregion(&s->mmio_region, SM501_DC, |
1830 | &s->disp_ctrl_region); | |
1831 | memory_region_init_io(&s->twoD_engine_region, OBJECT(dev), | |
1832 | &sm501_2d_engine_ops, s, | |
25793bfa | 1833 | "sm501-2d-engine", 0x54); |
ca8a1104 BZ |
1834 | memory_region_add_subregion(&s->mmio_region, SM501_2D_ENGINE, |
1835 | &s->twoD_engine_region); | |
1836 | ||
1837 | /* create qemu graphic console */ | |
8e5c952b | 1838 | s->con = graphic_console_init(dev, 0, &sm501_ops, s); |
ca8a1104 BZ |
1839 | } |
1840 | ||
2edd6e4a BZ |
1841 | static const VMStateDescription vmstate_sm501_state = { |
1842 | .name = "sm501-state", | |
1843 | .version_id = 1, | |
1844 | .minimum_version_id = 1, | |
1845 | .fields = (VMStateField[]) { | |
1846 | VMSTATE_UINT32(local_mem_size_index, SM501State), | |
1847 | VMSTATE_UINT32(system_control, SM501State), | |
1848 | VMSTATE_UINT32(misc_control, SM501State), | |
1849 | VMSTATE_UINT32(gpio_31_0_control, SM501State), | |
1850 | VMSTATE_UINT32(gpio_63_32_control, SM501State), | |
1851 | VMSTATE_UINT32(dram_control, SM501State), | |
1852 | VMSTATE_UINT32(arbitration_control, SM501State), | |
1853 | VMSTATE_UINT32(irq_mask, SM501State), | |
1854 | VMSTATE_UINT32(misc_timing, SM501State), | |
1855 | VMSTATE_UINT32(power_mode_control, SM501State), | |
1856 | VMSTATE_UINT32(uart0_ier, SM501State), | |
1857 | VMSTATE_UINT32(uart0_lcr, SM501State), | |
1858 | VMSTATE_UINT32(uart0_mcr, SM501State), | |
1859 | VMSTATE_UINT32(uart0_scr, SM501State), | |
1860 | VMSTATE_UINT8_ARRAY(dc_palette, SM501State, DC_PALETTE_ENTRIES), | |
1861 | VMSTATE_UINT32(dc_panel_control, SM501State), | |
1862 | VMSTATE_UINT32(dc_panel_panning_control, SM501State), | |
1863 | VMSTATE_UINT32(dc_panel_fb_addr, SM501State), | |
1864 | VMSTATE_UINT32(dc_panel_fb_offset, SM501State), | |
1865 | VMSTATE_UINT32(dc_panel_fb_width, SM501State), | |
1866 | VMSTATE_UINT32(dc_panel_fb_height, SM501State), | |
1867 | VMSTATE_UINT32(dc_panel_tl_location, SM501State), | |
1868 | VMSTATE_UINT32(dc_panel_br_location, SM501State), | |
1869 | VMSTATE_UINT32(dc_panel_h_total, SM501State), | |
1870 | VMSTATE_UINT32(dc_panel_h_sync, SM501State), | |
1871 | VMSTATE_UINT32(dc_panel_v_total, SM501State), | |
1872 | VMSTATE_UINT32(dc_panel_v_sync, SM501State), | |
1873 | VMSTATE_UINT32(dc_panel_hwc_addr, SM501State), | |
1874 | VMSTATE_UINT32(dc_panel_hwc_location, SM501State), | |
1875 | VMSTATE_UINT32(dc_panel_hwc_color_1_2, SM501State), | |
1876 | VMSTATE_UINT32(dc_panel_hwc_color_3, SM501State), | |
1877 | VMSTATE_UINT32(dc_video_control, SM501State), | |
1878 | VMSTATE_UINT32(dc_crt_control, SM501State), | |
1879 | VMSTATE_UINT32(dc_crt_fb_addr, SM501State), | |
1880 | VMSTATE_UINT32(dc_crt_fb_offset, SM501State), | |
1881 | VMSTATE_UINT32(dc_crt_h_total, SM501State), | |
1882 | VMSTATE_UINT32(dc_crt_h_sync, SM501State), | |
1883 | VMSTATE_UINT32(dc_crt_v_total, SM501State), | |
1884 | VMSTATE_UINT32(dc_crt_v_sync, SM501State), | |
1885 | VMSTATE_UINT32(dc_crt_hwc_addr, SM501State), | |
1886 | VMSTATE_UINT32(dc_crt_hwc_location, SM501State), | |
1887 | VMSTATE_UINT32(dc_crt_hwc_color_1_2, SM501State), | |
1888 | VMSTATE_UINT32(dc_crt_hwc_color_3, SM501State), | |
1889 | VMSTATE_UINT32(twoD_source, SM501State), | |
1890 | VMSTATE_UINT32(twoD_destination, SM501State), | |
1891 | VMSTATE_UINT32(twoD_dimension, SM501State), | |
1892 | VMSTATE_UINT32(twoD_control, SM501State), | |
1893 | VMSTATE_UINT32(twoD_pitch, SM501State), | |
1894 | VMSTATE_UINT32(twoD_foreground, SM501State), | |
1895 | VMSTATE_UINT32(twoD_background, SM501State), | |
1896 | VMSTATE_UINT32(twoD_stretch, SM501State), | |
1897 | VMSTATE_UINT32(twoD_color_compare, SM501State), | |
1898 | VMSTATE_UINT32(twoD_color_compare_mask, SM501State), | |
1899 | VMSTATE_UINT32(twoD_mask, SM501State), | |
1900 | VMSTATE_UINT32(twoD_clip_tl, SM501State), | |
1901 | VMSTATE_UINT32(twoD_clip_br, SM501State), | |
1902 | VMSTATE_UINT32(twoD_mono_pattern_low, SM501State), | |
1903 | VMSTATE_UINT32(twoD_mono_pattern_high, SM501State), | |
1904 | VMSTATE_UINT32(twoD_window_width, SM501State), | |
1905 | VMSTATE_UINT32(twoD_source_base, SM501State), | |
1906 | VMSTATE_UINT32(twoD_destination_base, SM501State), | |
1907 | VMSTATE_UINT32(twoD_alpha, SM501State), | |
1908 | VMSTATE_UINT32(twoD_wrap, SM501State), | |
4a1f253a BZ |
1909 | /* Added in version 2 */ |
1910 | VMSTATE_UINT8(i2c_byte_count, SM501State), | |
1911 | VMSTATE_UINT8(i2c_status, SM501State), | |
1912 | VMSTATE_UINT8(i2c_addr, SM501State), | |
1913 | VMSTATE_UINT8_ARRAY(i2c_data, SM501State, 16), | |
2edd6e4a BZ |
1914 | VMSTATE_END_OF_LIST() |
1915 | } | |
1916 | }; | |
1917 | ||
ca8a1104 BZ |
1918 | #define TYPE_SYSBUS_SM501 "sysbus-sm501" |
1919 | #define SYSBUS_SM501(obj) \ | |
1920 | OBJECT_CHECK(SM501SysBusState, (obj), TYPE_SYSBUS_SM501) | |
1921 | ||
1922 | typedef struct { | |
1923 | /*< private >*/ | |
1924 | SysBusDevice parent_obj; | |
1925 | /*< public >*/ | |
1926 | SM501State state; | |
1927 | uint32_t vram_size; | |
1928 | uint32_t base; | |
0ed40f16 | 1929 | SerialMM serial; |
ca8a1104 BZ |
1930 | } SM501SysBusState; |
1931 | ||
1932 | static void sm501_realize_sysbus(DeviceState *dev, Error **errp) | |
1933 | { | |
1934 | SM501SysBusState *s = SYSBUS_SM501(dev); | |
1935 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
1936 | DeviceState *usb_dev; | |
0ed40f16 | 1937 | MemoryRegion *mr; |
ca8a1104 | 1938 | |
c795fa84 | 1939 | sm501_init(&s->state, dev, s->vram_size); |
ca8a1104 BZ |
1940 | if (get_local_mem_size(&s->state) != s->vram_size) { |
1941 | error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32, | |
1942 | get_local_mem_size(&s->state)); | |
1943 | return; | |
1944 | } | |
1945 | sysbus_init_mmio(sbd, &s->state.local_mem_region); | |
1946 | sysbus_init_mmio(sbd, &s->state.mmio_region); | |
ffd39257 | 1947 | |
ac611340 | 1948 | /* bridge to usb host emulation module */ |
ca8a1104 BZ |
1949 | usb_dev = qdev_create(NULL, "sysbus-ohci"); |
1950 | qdev_prop_set_uint32(usb_dev, "num-ports", 2); | |
1951 | qdev_prop_set_uint64(usb_dev, "dma-offset", s->base); | |
1952 | qdev_init_nofail(usb_dev); | |
1953 | memory_region_add_subregion(&s->state.mmio_region, SM501_USB_HOST, | |
1954 | sysbus_mmio_get_region(SYS_BUS_DEVICE(usb_dev), 0)); | |
1955 | sysbus_pass_irq(sbd, SYS_BUS_DEVICE(usb_dev)); | |
ac611340 | 1956 | |
ffd39257 | 1957 | /* bridge to serial emulation module */ |
0ed40f16 MAL |
1958 | qdev_init_nofail(DEVICE(&s->serial)); |
1959 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->serial), 0); | |
1960 | memory_region_add_subregion(&s->state.mmio_region, SM501_UART0, mr); | |
1961 | /* TODO : chain irq to IRL */ | |
ca8a1104 | 1962 | } |
ffd39257 | 1963 | |
ca8a1104 BZ |
1964 | static Property sm501_sysbus_properties[] = { |
1965 | DEFINE_PROP_UINT32("vram-size", SM501SysBusState, vram_size, 0), | |
1966 | DEFINE_PROP_UINT32("base", SM501SysBusState, base, 0), | |
ca8a1104 BZ |
1967 | DEFINE_PROP_END_OF_LIST(), |
1968 | }; | |
1969 | ||
1970 | static void sm501_reset_sysbus(DeviceState *dev) | |
1971 | { | |
1972 | SM501SysBusState *s = SYSBUS_SM501(dev); | |
1973 | sm501_reset(&s->state); | |
ffd39257 | 1974 | } |
ca8a1104 | 1975 | |
2edd6e4a BZ |
1976 | static const VMStateDescription vmstate_sm501_sysbus = { |
1977 | .name = TYPE_SYSBUS_SM501, | |
4a1f253a BZ |
1978 | .version_id = 2, |
1979 | .minimum_version_id = 2, | |
2edd6e4a BZ |
1980 | .fields = (VMStateField[]) { |
1981 | VMSTATE_STRUCT(state, SM501SysBusState, 1, | |
1982 | vmstate_sm501_state, SM501State), | |
1983 | VMSTATE_END_OF_LIST() | |
1984 | } | |
1985 | }; | |
1986 | ||
ca8a1104 BZ |
1987 | static void sm501_sysbus_class_init(ObjectClass *klass, void *data) |
1988 | { | |
1989 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1990 | ||
1991 | dc->realize = sm501_realize_sysbus; | |
1992 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); | |
1993 | dc->desc = "SM501 Multimedia Companion"; | |
4f67d30b | 1994 | device_class_set_props(dc, sm501_sysbus_properties); |
ca8a1104 | 1995 | dc->reset = sm501_reset_sysbus; |
2edd6e4a | 1996 | dc->vmsd = &vmstate_sm501_sysbus; |
0ed40f16 MAL |
1997 | } |
1998 | ||
1999 | static void sm501_sysbus_init(Object *o) | |
2000 | { | |
2001 | SM501SysBusState *sm501 = SYSBUS_SM501(o); | |
2002 | SerialMM *smm = &sm501->serial; | |
2003 | ||
2004 | sysbus_init_child_obj(o, "serial", smm, sizeof(SerialMM), TYPE_SERIAL_MM); | |
2005 | qdev_set_legacy_instance_id(DEVICE(smm), SM501_UART0, 2); | |
2006 | qdev_prop_set_uint8(DEVICE(smm), "regshift", 2); | |
2007 | qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN); | |
2008 | ||
2009 | object_property_add_alias(o, "chardev", | |
d2623129 | 2010 | OBJECT(smm), "chardev"); |
ca8a1104 BZ |
2011 | } |
2012 | ||
2013 | static const TypeInfo sm501_sysbus_info = { | |
2014 | .name = TYPE_SYSBUS_SM501, | |
2015 | .parent = TYPE_SYS_BUS_DEVICE, | |
2016 | .instance_size = sizeof(SM501SysBusState), | |
2017 | .class_init = sm501_sysbus_class_init, | |
0ed40f16 | 2018 | .instance_init = sm501_sysbus_init, |
ca8a1104 BZ |
2019 | }; |
2020 | ||
efae2784 BZ |
2021 | #define TYPE_PCI_SM501 "sm501" |
2022 | #define PCI_SM501(obj) OBJECT_CHECK(SM501PCIState, (obj), TYPE_PCI_SM501) | |
2023 | ||
2024 | typedef struct { | |
2025 | /*< private >*/ | |
2026 | PCIDevice parent_obj; | |
2027 | /*< public >*/ | |
2028 | SM501State state; | |
2029 | uint32_t vram_size; | |
2030 | } SM501PCIState; | |
2031 | ||
2032 | static void sm501_realize_pci(PCIDevice *dev, Error **errp) | |
2033 | { | |
2034 | SM501PCIState *s = PCI_SM501(dev); | |
2035 | ||
2036 | sm501_init(&s->state, DEVICE(dev), s->vram_size); | |
2037 | if (get_local_mem_size(&s->state) != s->vram_size) { | |
2038 | error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32, | |
2039 | get_local_mem_size(&s->state)); | |
2040 | return; | |
2041 | } | |
2042 | pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, | |
2043 | &s->state.local_mem_region); | |
2044 | pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, | |
2045 | &s->state.mmio_region); | |
2046 | } | |
2047 | ||
2048 | static Property sm501_pci_properties[] = { | |
d23b6caa | 2049 | DEFINE_PROP_UINT32("vram-size", SM501PCIState, vram_size, 64 * MiB), |
efae2784 BZ |
2050 | DEFINE_PROP_END_OF_LIST(), |
2051 | }; | |
2052 | ||
2053 | static void sm501_reset_pci(DeviceState *dev) | |
2054 | { | |
2055 | SM501PCIState *s = PCI_SM501(dev); | |
2056 | sm501_reset(&s->state); | |
2057 | /* Bits 2:0 of misc_control register is 001 for PCI */ | |
2058 | s->state.misc_control |= 1; | |
2059 | } | |
2060 | ||
2edd6e4a BZ |
2061 | static const VMStateDescription vmstate_sm501_pci = { |
2062 | .name = TYPE_PCI_SM501, | |
4a1f253a BZ |
2063 | .version_id = 2, |
2064 | .minimum_version_id = 2, | |
2edd6e4a BZ |
2065 | .fields = (VMStateField[]) { |
2066 | VMSTATE_PCI_DEVICE(parent_obj, SM501PCIState), | |
2067 | VMSTATE_STRUCT(state, SM501PCIState, 1, | |
2068 | vmstate_sm501_state, SM501State), | |
2069 | VMSTATE_END_OF_LIST() | |
2070 | } | |
2071 | }; | |
2072 | ||
efae2784 BZ |
2073 | static void sm501_pci_class_init(ObjectClass *klass, void *data) |
2074 | { | |
2075 | DeviceClass *dc = DEVICE_CLASS(klass); | |
2076 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
2077 | ||
2078 | k->realize = sm501_realize_pci; | |
2079 | k->vendor_id = PCI_VENDOR_ID_SILICON_MOTION; | |
2080 | k->device_id = PCI_DEVICE_ID_SM501; | |
2081 | k->class_id = PCI_CLASS_DISPLAY_OTHER; | |
2082 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); | |
2083 | dc->desc = "SM501 Display Controller"; | |
4f67d30b | 2084 | device_class_set_props(dc, sm501_pci_properties); |
efae2784 BZ |
2085 | dc->reset = sm501_reset_pci; |
2086 | dc->hotpluggable = false; | |
2edd6e4a | 2087 | dc->vmsd = &vmstate_sm501_pci; |
efae2784 BZ |
2088 | } |
2089 | ||
2090 | static const TypeInfo sm501_pci_info = { | |
2091 | .name = TYPE_PCI_SM501, | |
2092 | .parent = TYPE_PCI_DEVICE, | |
2093 | .instance_size = sizeof(SM501PCIState), | |
2094 | .class_init = sm501_pci_class_init, | |
fd3b02c8 EH |
2095 | .interfaces = (InterfaceInfo[]) { |
2096 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
2097 | { }, | |
2098 | }, | |
efae2784 BZ |
2099 | }; |
2100 | ||
ca8a1104 BZ |
2101 | static void sm501_register_types(void) |
2102 | { | |
2103 | type_register_static(&sm501_sysbus_info); | |
efae2784 | 2104 | type_register_static(&sm501_pci_info); |
ca8a1104 BZ |
2105 | } |
2106 | ||
2107 | type_init(sm501_register_types) |