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1 | /* |
2 | * QEMU SM501 Device | |
3 | * | |
4 | * Copyright (c) 2008 Shin-ichiro KAWASAKI | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
47df5154 | 25 | #include "qemu/osdep.h" |
e2ee8476 | 26 | #include "qemu/cutils.h" |
da34e65c | 27 | #include "qapi/error.h" |
4771d756 PB |
28 | #include "qemu-common.h" |
29 | #include "cpu.h" | |
83c9f4ca | 30 | #include "hw/hw.h" |
0d09e41a | 31 | #include "hw/char/serial.h" |
28ecbaee | 32 | #include "ui/console.h" |
bd2be150 | 33 | #include "hw/devices.h" |
83c9f4ca | 34 | #include "hw/sysbus.h" |
efae2784 | 35 | #include "hw/pci/pci.h" |
1de7afc9 | 36 | #include "qemu/range.h" |
28ecbaee | 37 | #include "ui/pixel_ops.h" |
2c17449b | 38 | #include "exec/address-spaces.h" |
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39 | |
40 | /* | |
604be200 | 41 | * Status: 2010/05/07 |
ffd39257 | 42 | * - Minimum implementation for Linux console : mmio regs and CRT layer. |
64f1603b | 43 | * - 2D graphics acceleration partially supported : only fill rectangle. |
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44 | * |
45 | * TODO: | |
46 | * - Panel support | |
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47 | * - Touch panel support |
48 | * - USB support | |
49 | * - UART support | |
604be200 | 50 | * - More 2D graphics engine support |
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51 | * - Performance tuning |
52 | */ | |
53 | ||
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54 | /*#define DEBUG_SM501*/ |
55 | /*#define DEBUG_BITBLT*/ | |
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56 | |
57 | #ifdef DEBUG_SM501 | |
001faf32 | 58 | #define SM501_DPRINTF(fmt, ...) printf(fmt, ## __VA_ARGS__) |
ffd39257 | 59 | #else |
64f1603b | 60 | #define SM501_DPRINTF(fmt, ...) do {} while (0) |
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61 | #endif |
62 | ||
ffd39257 | 63 | #define MMIO_BASE_OFFSET 0x3e00000 |
ca8a1104 | 64 | #define MMIO_SIZE 0x200000 |
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65 | |
66 | /* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */ | |
67 | ||
68 | /* System Configuration area */ | |
69 | /* System config base */ | |
64f1603b | 70 | #define SM501_SYS_CONFIG (0x000000) |
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71 | |
72 | /* config 1 */ | |
64f1603b | 73 | #define SM501_SYSTEM_CONTROL (0x000000) |
ffd39257 | 74 | |
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75 | #define SM501_SYSCTRL_PANEL_TRISTATE (1 << 0) |
76 | #define SM501_SYSCTRL_MEM_TRISTATE (1 << 1) | |
77 | #define SM501_SYSCTRL_CRT_TRISTATE (1 << 2) | |
ffd39257 | 78 | |
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79 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3 << 4) |
80 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0 << 4) | |
81 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1 << 4) | |
82 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2 << 4) | |
83 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3 << 4) | |
ffd39257 | 84 | |
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85 | #define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1 << 6) |
86 | #define SM501_SYSCTRL_PCI_RETRY_DISABLE (1 << 7) | |
87 | #define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1 << 11) | |
88 | #define SM501_SYSCTRL_PCI_BURST_READ_EN (1 << 15) | |
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89 | |
90 | /* miscellaneous control */ | |
91 | ||
64f1603b | 92 | #define SM501_MISC_CONTROL (0x000004) |
ffd39257 | 93 | |
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94 | #define SM501_MISC_BUS_SH (0x0) |
95 | #define SM501_MISC_BUS_PCI (0x1) | |
96 | #define SM501_MISC_BUS_XSCALE (0x2) | |
97 | #define SM501_MISC_BUS_NEC (0x6) | |
98 | #define SM501_MISC_BUS_MASK (0x7) | |
ffd39257 | 99 | |
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100 | #define SM501_MISC_VR_62MB (1 << 3) |
101 | #define SM501_MISC_CDR_RESET (1 << 7) | |
102 | #define SM501_MISC_USB_LB (1 << 8) | |
103 | #define SM501_MISC_USB_SLAVE (1 << 9) | |
104 | #define SM501_MISC_BL_1 (1 << 10) | |
105 | #define SM501_MISC_MC (1 << 11) | |
106 | #define SM501_MISC_DAC_POWER (1 << 12) | |
107 | #define SM501_MISC_IRQ_INVERT (1 << 16) | |
108 | #define SM501_MISC_SH (1 << 17) | |
ffd39257 | 109 | |
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110 | #define SM501_MISC_HOLD_EMPTY (0 << 18) |
111 | #define SM501_MISC_HOLD_8 (1 << 18) | |
112 | #define SM501_MISC_HOLD_16 (2 << 18) | |
113 | #define SM501_MISC_HOLD_24 (3 << 18) | |
114 | #define SM501_MISC_HOLD_32 (4 << 18) | |
115 | #define SM501_MISC_HOLD_MASK (7 << 18) | |
ffd39257 | 116 | |
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117 | #define SM501_MISC_FREQ_12 (1 << 24) |
118 | #define SM501_MISC_PNL_24BIT (1 << 25) | |
119 | #define SM501_MISC_8051_LE (1 << 26) | |
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120 | |
121 | ||
122 | ||
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123 | #define SM501_GPIO31_0_CONTROL (0x000008) |
124 | #define SM501_GPIO63_32_CONTROL (0x00000C) | |
125 | #define SM501_DRAM_CONTROL (0x000010) | |
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126 | |
127 | /* command list */ | |
64f1603b | 128 | #define SM501_ARBTRTN_CONTROL (0x000014) |
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129 | |
130 | /* command list */ | |
64f1603b | 131 | #define SM501_COMMAND_LIST_STATUS (0x000024) |
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132 | |
133 | /* interrupt debug */ | |
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134 | #define SM501_RAW_IRQ_STATUS (0x000028) |
135 | #define SM501_RAW_IRQ_CLEAR (0x000028) | |
136 | #define SM501_IRQ_STATUS (0x00002C) | |
137 | #define SM501_IRQ_MASK (0x000030) | |
138 | #define SM501_DEBUG_CONTROL (0x000034) | |
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139 | |
140 | /* power management */ | |
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141 | #define SM501_POWERMODE_P2X_SRC (1 << 29) |
142 | #define SM501_POWERMODE_V2X_SRC (1 << 20) | |
143 | #define SM501_POWERMODE_M_SRC (1 << 12) | |
144 | #define SM501_POWERMODE_M1_SRC (1 << 4) | |
145 | ||
146 | #define SM501_CURRENT_GATE (0x000038) | |
147 | #define SM501_CURRENT_CLOCK (0x00003C) | |
148 | #define SM501_POWER_MODE_0_GATE (0x000040) | |
149 | #define SM501_POWER_MODE_0_CLOCK (0x000044) | |
150 | #define SM501_POWER_MODE_1_GATE (0x000048) | |
151 | #define SM501_POWER_MODE_1_CLOCK (0x00004C) | |
152 | #define SM501_SLEEP_MODE_GATE (0x000050) | |
153 | #define SM501_POWER_MODE_CONTROL (0x000054) | |
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154 | |
155 | /* power gates for units within the 501 */ | |
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156 | #define SM501_GATE_HOST (0) |
157 | #define SM501_GATE_MEMORY (1) | |
158 | #define SM501_GATE_DISPLAY (2) | |
159 | #define SM501_GATE_2D_ENGINE (3) | |
160 | #define SM501_GATE_CSC (4) | |
161 | #define SM501_GATE_ZVPORT (5) | |
162 | #define SM501_GATE_GPIO (6) | |
163 | #define SM501_GATE_UART0 (7) | |
164 | #define SM501_GATE_UART1 (8) | |
165 | #define SM501_GATE_SSP (10) | |
166 | #define SM501_GATE_USB_HOST (11) | |
167 | #define SM501_GATE_USB_GADGET (12) | |
168 | #define SM501_GATE_UCONTROLLER (17) | |
169 | #define SM501_GATE_AC97 (18) | |
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170 | |
171 | /* panel clock */ | |
64f1603b | 172 | #define SM501_CLOCK_P2XCLK (24) |
ffd39257 | 173 | /* crt clock */ |
64f1603b | 174 | #define SM501_CLOCK_V2XCLK (16) |
ffd39257 | 175 | /* main clock */ |
64f1603b | 176 | #define SM501_CLOCK_MCLK (8) |
ffd39257 | 177 | /* SDRAM controller clock */ |
64f1603b | 178 | #define SM501_CLOCK_M1XCLK (0) |
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179 | |
180 | /* config 2 */ | |
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181 | #define SM501_PCI_MASTER_BASE (0x000058) |
182 | #define SM501_ENDIAN_CONTROL (0x00005C) | |
183 | #define SM501_DEVICEID (0x000060) | |
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184 | /* 0x050100A0 */ |
185 | ||
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186 | #define SM501_DEVICEID_SM501 (0x05010000) |
187 | #define SM501_DEVICEID_IDMASK (0xffff0000) | |
188 | #define SM501_DEVICEID_REVMASK (0x000000ff) | |
ffd39257 | 189 | |
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190 | #define SM501_PLLCLOCK_COUNT (0x000064) |
191 | #define SM501_MISC_TIMING (0x000068) | |
192 | #define SM501_CURRENT_SDRAM_CLOCK (0x00006C) | |
ffd39257 | 193 | |
64f1603b | 194 | #define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074) |
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195 | |
196 | /* GPIO base */ | |
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197 | #define SM501_GPIO (0x010000) |
198 | #define SM501_GPIO_DATA_LOW (0x00) | |
199 | #define SM501_GPIO_DATA_HIGH (0x04) | |
200 | #define SM501_GPIO_DDR_LOW (0x08) | |
201 | #define SM501_GPIO_DDR_HIGH (0x0C) | |
202 | #define SM501_GPIO_IRQ_SETUP (0x10) | |
203 | #define SM501_GPIO_IRQ_STATUS (0x14) | |
204 | #define SM501_GPIO_IRQ_RESET (0x14) | |
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205 | |
206 | /* I2C controller base */ | |
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207 | #define SM501_I2C (0x010040) |
208 | #define SM501_I2C_BYTE_COUNT (0x00) | |
209 | #define SM501_I2C_CONTROL (0x01) | |
210 | #define SM501_I2C_STATUS (0x02) | |
211 | #define SM501_I2C_RESET (0x02) | |
212 | #define SM501_I2C_SLAVE_ADDRESS (0x03) | |
213 | #define SM501_I2C_DATA (0x04) | |
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214 | |
215 | /* SSP base */ | |
64f1603b | 216 | #define SM501_SSP (0x020000) |
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217 | |
218 | /* Uart 0 base */ | |
64f1603b | 219 | #define SM501_UART0 (0x030000) |
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220 | |
221 | /* Uart 1 base */ | |
64f1603b | 222 | #define SM501_UART1 (0x030020) |
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223 | |
224 | /* USB host port base */ | |
64f1603b | 225 | #define SM501_USB_HOST (0x040000) |
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226 | |
227 | /* USB slave/gadget base */ | |
64f1603b | 228 | #define SM501_USB_GADGET (0x060000) |
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229 | |
230 | /* USB slave/gadget data port base */ | |
64f1603b | 231 | #define SM501_USB_GADGET_DATA (0x070000) |
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232 | |
233 | /* Display controller/video engine base */ | |
64f1603b | 234 | #define SM501_DC (0x080000) |
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235 | |
236 | /* common defines for the SM501 address registers */ | |
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237 | #define SM501_ADDR_FLIP (1 << 31) |
238 | #define SM501_ADDR_EXT (1 << 27) | |
239 | #define SM501_ADDR_CS1 (1 << 26) | |
240 | #define SM501_ADDR_MASK (0x3f << 26) | |
ffd39257 | 241 | |
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242 | #define SM501_FIFO_MASK (0x3 << 16) |
243 | #define SM501_FIFO_1 (0x0 << 16) | |
244 | #define SM501_FIFO_3 (0x1 << 16) | |
245 | #define SM501_FIFO_7 (0x2 << 16) | |
246 | #define SM501_FIFO_11 (0x3 << 16) | |
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247 | |
248 | /* common registers for panel and the crt */ | |
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249 | #define SM501_OFF_DC_H_TOT (0x000) |
250 | #define SM501_OFF_DC_V_TOT (0x008) | |
251 | #define SM501_OFF_DC_H_SYNC (0x004) | |
252 | #define SM501_OFF_DC_V_SYNC (0x00C) | |
253 | ||
254 | #define SM501_DC_PANEL_CONTROL (0x000) | |
255 | ||
256 | #define SM501_DC_PANEL_CONTROL_FPEN (1 << 27) | |
257 | #define SM501_DC_PANEL_CONTROL_BIAS (1 << 26) | |
258 | #define SM501_DC_PANEL_CONTROL_DATA (1 << 25) | |
259 | #define SM501_DC_PANEL_CONTROL_VDD (1 << 24) | |
260 | #define SM501_DC_PANEL_CONTROL_DP (1 << 23) | |
261 | ||
262 | #define SM501_DC_PANEL_CONTROL_TFT_888 (0 << 21) | |
263 | #define SM501_DC_PANEL_CONTROL_TFT_333 (1 << 21) | |
264 | #define SM501_DC_PANEL_CONTROL_TFT_444 (2 << 21) | |
265 | ||
266 | #define SM501_DC_PANEL_CONTROL_DE (1 << 20) | |
267 | ||
268 | #define SM501_DC_PANEL_CONTROL_LCD_TFT (0 << 18) | |
269 | #define SM501_DC_PANEL_CONTROL_LCD_STN8 (1 << 18) | |
270 | #define SM501_DC_PANEL_CONTROL_LCD_STN12 (2 << 18) | |
271 | ||
272 | #define SM501_DC_PANEL_CONTROL_CP (1 << 14) | |
273 | #define SM501_DC_PANEL_CONTROL_VSP (1 << 13) | |
274 | #define SM501_DC_PANEL_CONTROL_HSP (1 << 12) | |
275 | #define SM501_DC_PANEL_CONTROL_CK (1 << 9) | |
276 | #define SM501_DC_PANEL_CONTROL_TE (1 << 8) | |
277 | #define SM501_DC_PANEL_CONTROL_VPD (1 << 7) | |
278 | #define SM501_DC_PANEL_CONTROL_VP (1 << 6) | |
279 | #define SM501_DC_PANEL_CONTROL_HPD (1 << 5) | |
280 | #define SM501_DC_PANEL_CONTROL_HP (1 << 4) | |
281 | #define SM501_DC_PANEL_CONTROL_GAMMA (1 << 3) | |
282 | #define SM501_DC_PANEL_CONTROL_EN (1 << 2) | |
283 | ||
284 | #define SM501_DC_PANEL_CONTROL_8BPP (0 << 0) | |
285 | #define SM501_DC_PANEL_CONTROL_16BPP (1 << 0) | |
286 | #define SM501_DC_PANEL_CONTROL_32BPP (2 << 0) | |
287 | ||
288 | ||
289 | #define SM501_DC_PANEL_PANNING_CONTROL (0x004) | |
290 | #define SM501_DC_PANEL_COLOR_KEY (0x008) | |
291 | #define SM501_DC_PANEL_FB_ADDR (0x00C) | |
292 | #define SM501_DC_PANEL_FB_OFFSET (0x010) | |
293 | #define SM501_DC_PANEL_FB_WIDTH (0x014) | |
294 | #define SM501_DC_PANEL_FB_HEIGHT (0x018) | |
295 | #define SM501_DC_PANEL_TL_LOC (0x01C) | |
296 | #define SM501_DC_PANEL_BR_LOC (0x020) | |
297 | #define SM501_DC_PANEL_H_TOT (0x024) | |
298 | #define SM501_DC_PANEL_H_SYNC (0x028) | |
299 | #define SM501_DC_PANEL_V_TOT (0x02C) | |
300 | #define SM501_DC_PANEL_V_SYNC (0x030) | |
301 | #define SM501_DC_PANEL_CUR_LINE (0x034) | |
302 | ||
303 | #define SM501_DC_VIDEO_CONTROL (0x040) | |
304 | #define SM501_DC_VIDEO_FB0_ADDR (0x044) | |
305 | #define SM501_DC_VIDEO_FB_WIDTH (0x048) | |
306 | #define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C) | |
307 | #define SM501_DC_VIDEO_TL_LOC (0x050) | |
308 | #define SM501_DC_VIDEO_BR_LOC (0x054) | |
309 | #define SM501_DC_VIDEO_SCALE (0x058) | |
310 | #define SM501_DC_VIDEO_INIT_SCALE (0x05C) | |
311 | #define SM501_DC_VIDEO_YUV_CONSTANTS (0x060) | |
312 | #define SM501_DC_VIDEO_FB1_ADDR (0x064) | |
313 | #define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068) | |
314 | ||
315 | #define SM501_DC_VIDEO_ALPHA_CONTROL (0x080) | |
316 | #define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084) | |
317 | #define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088) | |
318 | #define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C) | |
319 | #define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090) | |
320 | #define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094) | |
321 | #define SM501_DC_VIDEO_ALPHA_SCALE (0x098) | |
322 | #define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C) | |
323 | #define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0) | |
324 | #define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4) | |
325 | ||
326 | #define SM501_DC_PANEL_HWC_BASE (0x0F0) | |
327 | #define SM501_DC_PANEL_HWC_ADDR (0x0F0) | |
328 | #define SM501_DC_PANEL_HWC_LOC (0x0F4) | |
329 | #define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8) | |
330 | #define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC) | |
331 | ||
332 | #define SM501_HWC_EN (1 << 31) | |
333 | ||
334 | #define SM501_OFF_HWC_ADDR (0x00) | |
335 | #define SM501_OFF_HWC_LOC (0x04) | |
336 | #define SM501_OFF_HWC_COLOR_1_2 (0x08) | |
337 | #define SM501_OFF_HWC_COLOR_3 (0x0C) | |
338 | ||
339 | #define SM501_DC_ALPHA_CONTROL (0x100) | |
340 | #define SM501_DC_ALPHA_FB_ADDR (0x104) | |
341 | #define SM501_DC_ALPHA_FB_OFFSET (0x108) | |
342 | #define SM501_DC_ALPHA_TL_LOC (0x10C) | |
343 | #define SM501_DC_ALPHA_BR_LOC (0x110) | |
344 | #define SM501_DC_ALPHA_CHROMA_KEY (0x114) | |
345 | #define SM501_DC_ALPHA_COLOR_LOOKUP (0x118) | |
346 | ||
347 | #define SM501_DC_CRT_CONTROL (0x200) | |
348 | ||
349 | #define SM501_DC_CRT_CONTROL_TVP (1 << 15) | |
350 | #define SM501_DC_CRT_CONTROL_CP (1 << 14) | |
351 | #define SM501_DC_CRT_CONTROL_VSP (1 << 13) | |
352 | #define SM501_DC_CRT_CONTROL_HSP (1 << 12) | |
353 | #define SM501_DC_CRT_CONTROL_VS (1 << 11) | |
354 | #define SM501_DC_CRT_CONTROL_BLANK (1 << 10) | |
355 | #define SM501_DC_CRT_CONTROL_SEL (1 << 9) | |
356 | #define SM501_DC_CRT_CONTROL_TE (1 << 8) | |
ffd39257 | 357 | #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4) |
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358 | #define SM501_DC_CRT_CONTROL_GAMMA (1 << 3) |
359 | #define SM501_DC_CRT_CONTROL_ENABLE (1 << 2) | |
ffd39257 | 360 | |
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361 | #define SM501_DC_CRT_CONTROL_8BPP (0 << 0) |
362 | #define SM501_DC_CRT_CONTROL_16BPP (1 << 0) | |
363 | #define SM501_DC_CRT_CONTROL_32BPP (2 << 0) | |
ffd39257 | 364 | |
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365 | #define SM501_DC_CRT_FB_ADDR (0x204) |
366 | #define SM501_DC_CRT_FB_OFFSET (0x208) | |
367 | #define SM501_DC_CRT_H_TOT (0x20C) | |
368 | #define SM501_DC_CRT_H_SYNC (0x210) | |
369 | #define SM501_DC_CRT_V_TOT (0x214) | |
370 | #define SM501_DC_CRT_V_SYNC (0x218) | |
371 | #define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C) | |
372 | #define SM501_DC_CRT_CUR_LINE (0x220) | |
373 | #define SM501_DC_CRT_MONITOR_DETECT (0x224) | |
ffd39257 | 374 | |
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375 | #define SM501_DC_CRT_HWC_BASE (0x230) |
376 | #define SM501_DC_CRT_HWC_ADDR (0x230) | |
377 | #define SM501_DC_CRT_HWC_LOC (0x234) | |
378 | #define SM501_DC_CRT_HWC_COLOR_1_2 (0x238) | |
379 | #define SM501_DC_CRT_HWC_COLOR_3 (0x23C) | |
ffd39257 | 380 | |
64f1603b | 381 | #define SM501_DC_PANEL_PALETTE (0x400) |
ffd39257 | 382 | |
64f1603b | 383 | #define SM501_DC_VIDEO_PALETTE (0x800) |
ffd39257 | 384 | |
64f1603b | 385 | #define SM501_DC_CRT_PALETTE (0xC00) |
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386 | |
387 | /* Zoom Video port base */ | |
64f1603b | 388 | #define SM501_ZVPORT (0x090000) |
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389 | |
390 | /* AC97/I2S base */ | |
64f1603b | 391 | #define SM501_AC97 (0x0A0000) |
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392 | |
393 | /* 8051 micro controller base */ | |
64f1603b | 394 | #define SM501_UCONTROLLER (0x0B0000) |
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395 | |
396 | /* 8051 micro controller SRAM base */ | |
64f1603b | 397 | #define SM501_UCONTROLLER_SRAM (0x0C0000) |
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398 | |
399 | /* DMA base */ | |
64f1603b | 400 | #define SM501_DMA (0x0D0000) |
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401 | |
402 | /* 2d engine base */ | |
64f1603b BZ |
403 | #define SM501_2D_ENGINE (0x100000) |
404 | #define SM501_2D_SOURCE (0x00) | |
405 | #define SM501_2D_DESTINATION (0x04) | |
406 | #define SM501_2D_DIMENSION (0x08) | |
407 | #define SM501_2D_CONTROL (0x0C) | |
408 | #define SM501_2D_PITCH (0x10) | |
409 | #define SM501_2D_FOREGROUND (0x14) | |
410 | #define SM501_2D_BACKGROUND (0x18) | |
411 | #define SM501_2D_STRETCH (0x1C) | |
412 | #define SM501_2D_COLOR_COMPARE (0x20) | |
413 | #define SM501_2D_COLOR_COMPARE_MASK (0x24) | |
414 | #define SM501_2D_MASK (0x28) | |
415 | #define SM501_2D_CLIP_TL (0x2C) | |
416 | #define SM501_2D_CLIP_BR (0x30) | |
417 | #define SM501_2D_MONO_PATTERN_LOW (0x34) | |
418 | #define SM501_2D_MONO_PATTERN_HIGH (0x38) | |
419 | #define SM501_2D_WINDOW_WIDTH (0x3C) | |
420 | #define SM501_2D_SOURCE_BASE (0x40) | |
421 | #define SM501_2D_DESTINATION_BASE (0x44) | |
422 | #define SM501_2D_ALPHA (0x48) | |
423 | #define SM501_2D_WRAP (0x4C) | |
424 | #define SM501_2D_STATUS (0x50) | |
425 | ||
426 | #define SM501_CSC_Y_SOURCE_BASE (0xC8) | |
427 | #define SM501_CSC_CONSTANTS (0xCC) | |
428 | #define SM501_CSC_Y_SOURCE_X (0xD0) | |
429 | #define SM501_CSC_Y_SOURCE_Y (0xD4) | |
430 | #define SM501_CSC_U_SOURCE_BASE (0xD8) | |
431 | #define SM501_CSC_V_SOURCE_BASE (0xDC) | |
432 | #define SM501_CSC_SOURCE_DIMENSION (0xE0) | |
433 | #define SM501_CSC_SOURCE_PITCH (0xE4) | |
434 | #define SM501_CSC_DESTINATION (0xE8) | |
435 | #define SM501_CSC_DESTINATION_DIMENSION (0xEC) | |
436 | #define SM501_CSC_DESTINATION_PITCH (0xF0) | |
437 | #define SM501_CSC_SCALE_FACTOR (0xF4) | |
438 | #define SM501_CSC_DESTINATION_BASE (0xF8) | |
439 | #define SM501_CSC_CONTROL (0xFC) | |
ffd39257 BS |
440 | |
441 | /* 2d engine data port base */ | |
64f1603b | 442 | #define SM501_2D_ENGINE_DATA (0x110000) |
ffd39257 BS |
443 | |
444 | /* end of register definitions */ | |
445 | ||
0a4e7cd2 SK |
446 | #define SM501_HWC_WIDTH (64) |
447 | #define SM501_HWC_HEIGHT (64) | |
ffd39257 BS |
448 | |
449 | /* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */ | |
450 | static const uint32_t sm501_mem_local_size[] = { | |
e2ee8476 BZ |
451 | [0] = 4 * M_BYTE, |
452 | [1] = 8 * M_BYTE, | |
453 | [2] = 16 * M_BYTE, | |
454 | [3] = 32 * M_BYTE, | |
455 | [4] = 64 * M_BYTE, | |
456 | [5] = 2 * M_BYTE, | |
ffd39257 BS |
457 | }; |
458 | #define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index] | |
459 | ||
460 | typedef struct SM501State { | |
461 | /* graphic console status */ | |
c78f7137 | 462 | QemuConsole *con; |
ffd39257 BS |
463 | |
464 | /* status & internal resources */ | |
ffd39257 | 465 | uint32_t local_mem_size_index; |
64f1603b | 466 | uint8_t *local_mem; |
25793bfa | 467 | MemoryRegion local_mem_region; |
ca8a1104 BZ |
468 | MemoryRegion mmio_region; |
469 | MemoryRegion system_config_region; | |
470 | MemoryRegion disp_ctrl_region; | |
471 | MemoryRegion twoD_engine_region; | |
ffd39257 BS |
472 | uint32_t last_width; |
473 | uint32_t last_height; | |
474 | ||
475 | /* mmio registers */ | |
476 | uint32_t system_control; | |
477 | uint32_t misc_control; | |
478 | uint32_t gpio_31_0_control; | |
479 | uint32_t gpio_63_32_control; | |
480 | uint32_t dram_control; | |
70e46ca8 | 481 | uint32_t arbitration_control; |
ffd39257 BS |
482 | uint32_t irq_mask; |
483 | uint32_t misc_timing; | |
484 | uint32_t power_mode_control; | |
485 | ||
486 | uint32_t uart0_ier; | |
487 | uint32_t uart0_lcr; | |
488 | uint32_t uart0_mcr; | |
489 | uint32_t uart0_scr; | |
490 | ||
491 | uint8_t dc_palette[0x400 * 3]; | |
492 | ||
493 | uint32_t dc_panel_control; | |
494 | uint32_t dc_panel_panning_control; | |
495 | uint32_t dc_panel_fb_addr; | |
496 | uint32_t dc_panel_fb_offset; | |
497 | uint32_t dc_panel_fb_width; | |
498 | uint32_t dc_panel_fb_height; | |
499 | uint32_t dc_panel_tl_location; | |
500 | uint32_t dc_panel_br_location; | |
501 | uint32_t dc_panel_h_total; | |
502 | uint32_t dc_panel_h_sync; | |
503 | uint32_t dc_panel_v_total; | |
504 | uint32_t dc_panel_v_sync; | |
505 | ||
506 | uint32_t dc_panel_hwc_addr; | |
507 | uint32_t dc_panel_hwc_location; | |
508 | uint32_t dc_panel_hwc_color_1_2; | |
509 | uint32_t dc_panel_hwc_color_3; | |
510 | ||
511 | uint32_t dc_crt_control; | |
512 | uint32_t dc_crt_fb_addr; | |
513 | uint32_t dc_crt_fb_offset; | |
514 | uint32_t dc_crt_h_total; | |
515 | uint32_t dc_crt_h_sync; | |
516 | uint32_t dc_crt_v_total; | |
517 | uint32_t dc_crt_v_sync; | |
518 | ||
519 | uint32_t dc_crt_hwc_addr; | |
520 | uint32_t dc_crt_hwc_location; | |
521 | uint32_t dc_crt_hwc_color_1_2; | |
522 | uint32_t dc_crt_hwc_color_3; | |
523 | ||
07d8a50c | 524 | uint32_t twoD_source; |
604be200 SK |
525 | uint32_t twoD_destination; |
526 | uint32_t twoD_dimension; | |
527 | uint32_t twoD_control; | |
528 | uint32_t twoD_pitch; | |
529 | uint32_t twoD_foreground; | |
530 | uint32_t twoD_stretch; | |
531 | uint32_t twoD_color_compare_mask; | |
532 | uint32_t twoD_mask; | |
533 | uint32_t twoD_window_width; | |
534 | uint32_t twoD_source_base; | |
535 | uint32_t twoD_destination_base; | |
536 | ||
ffd39257 BS |
537 | } SM501State; |
538 | ||
539 | static uint32_t get_local_mem_size_index(uint32_t size) | |
540 | { | |
541 | uint32_t norm_size = 0; | |
542 | int i, index = 0; | |
543 | ||
b1503cda | 544 | for (i = 0; i < ARRAY_SIZE(sm501_mem_local_size); i++) { |
64f1603b BZ |
545 | uint32_t new_size = sm501_mem_local_size[i]; |
546 | if (new_size >= size) { | |
547 | if (norm_size == 0 || norm_size > new_size) { | |
548 | norm_size = new_size; | |
549 | index = i; | |
550 | } | |
551 | } | |
ffd39257 BS |
552 | } |
553 | ||
554 | return index; | |
555 | } | |
556 | ||
6a2a5aae BZ |
557 | static inline int get_width(SM501State *s, int crt) |
558 | { | |
559 | int width = crt ? s->dc_crt_h_total : s->dc_panel_h_total; | |
560 | return (width & 0x00000FFF) + 1; | |
561 | } | |
562 | ||
563 | static inline int get_height(SM501State *s, int crt) | |
564 | { | |
565 | int height = crt ? s->dc_crt_v_total : s->dc_panel_v_total; | |
566 | return (height & 0x00000FFF) + 1; | |
567 | } | |
568 | ||
569 | static inline int get_bpp(SM501State *s, int crt) | |
570 | { | |
571 | int bpp = crt ? s->dc_crt_control : s->dc_panel_control; | |
572 | return 1 << (bpp & 3); | |
573 | } | |
574 | ||
0a4e7cd2 SK |
575 | /** |
576 | * Check the availability of hardware cursor. | |
577 | * @param crt 0 for PANEL, 1 for CRT. | |
578 | */ | |
579 | static inline int is_hwc_enabled(SM501State *state, int crt) | |
580 | { | |
581 | uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr; | |
e2ee8476 | 582 | return addr & SM501_HWC_EN; |
0a4e7cd2 SK |
583 | } |
584 | ||
585 | /** | |
586 | * Get the address which holds cursor pattern data. | |
587 | * @param crt 0 for PANEL, 1 for CRT. | |
588 | */ | |
6a2a5aae | 589 | static inline uint8_t *get_hwc_address(SM501State *state, int crt) |
0a4e7cd2 SK |
590 | { |
591 | uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr; | |
6a2a5aae | 592 | return state->local_mem + (addr & 0x03FFFFF0); |
0a4e7cd2 SK |
593 | } |
594 | ||
595 | /** | |
596 | * Get the cursor position in y coordinate. | |
597 | * @param crt 0 for PANEL, 1 for CRT. | |
598 | */ | |
599 | static inline uint32_t get_hwc_y(SM501State *state, int crt) | |
600 | { | |
601 | uint32_t location = crt ? state->dc_crt_hwc_location | |
602 | : state->dc_panel_hwc_location; | |
603 | return (location & 0x07FF0000) >> 16; | |
604 | } | |
605 | ||
606 | /** | |
607 | * Get the cursor position in x coordinate. | |
608 | * @param crt 0 for PANEL, 1 for CRT. | |
609 | */ | |
610 | static inline uint32_t get_hwc_x(SM501State *state, int crt) | |
611 | { | |
612 | uint32_t location = crt ? state->dc_crt_hwc_location | |
613 | : state->dc_panel_hwc_location; | |
614 | return location & 0x000007FF; | |
615 | } | |
616 | ||
617 | /** | |
6a2a5aae | 618 | * Get the hardware cursor palette. |
0a4e7cd2 | 619 | * @param crt 0 for PANEL, 1 for CRT. |
6a2a5aae | 620 | * @param palette pointer to a [3 * 3] array to store color values in |
0a4e7cd2 | 621 | */ |
6a2a5aae | 622 | static inline void get_hwc_palette(SM501State *state, int crt, uint8_t *palette) |
0a4e7cd2 | 623 | { |
6a2a5aae BZ |
624 | int i; |
625 | uint32_t color_reg; | |
626 | uint16_t rgb565; | |
627 | ||
628 | for (i = 0; i < 3; i++) { | |
629 | if (i + 1 == 3) { | |
630 | color_reg = crt ? state->dc_crt_hwc_color_3 | |
631 | : state->dc_panel_hwc_color_3; | |
632 | } else { | |
633 | color_reg = crt ? state->dc_crt_hwc_color_1_2 | |
634 | : state->dc_panel_hwc_color_1_2; | |
635 | } | |
0a4e7cd2 | 636 | |
6a2a5aae BZ |
637 | if (i + 1 == 2) { |
638 | rgb565 = (color_reg >> 16) & 0xFFFF; | |
639 | } else { | |
640 | rgb565 = color_reg & 0xFFFF; | |
641 | } | |
642 | palette[i * 3 + 0] = (rgb565 << 3) & 0xf8; /* red */ | |
643 | palette[i * 3 + 1] = (rgb565 >> 3) & 0xfc; /* green */ | |
644 | palette[i * 3 + 2] = (rgb565 >> 8) & 0xf8; /* blue */ | |
0a4e7cd2 | 645 | } |
0a4e7cd2 SK |
646 | } |
647 | ||
6a2a5aae | 648 | static inline void hwc_invalidate(SM501State *s, int crt) |
0a4e7cd2 | 649 | { |
6a2a5aae BZ |
650 | int w = get_width(s, crt); |
651 | int h = get_height(s, crt); | |
652 | int bpp = get_bpp(s, crt); | |
653 | int start = get_hwc_y(s, crt); | |
654 | int end = MIN(h, start + SM501_HWC_HEIGHT) + 1; | |
655 | ||
656 | start *= w * bpp; | |
657 | end *= w * bpp; | |
658 | ||
659 | memory_region_set_dirty(&s->local_mem_region, start, end - start); | |
0a4e7cd2 SK |
660 | } |
661 | ||
64f1603b | 662 | static void sm501_2d_operation(SM501State *s) |
604be200 SK |
663 | { |
664 | /* obtain operation parameters */ | |
665 | int operation = (s->twoD_control >> 16) & 0x1f; | |
07d8a50c AJ |
666 | int rtl = s->twoD_control & 0x8000000; |
667 | int src_x = (s->twoD_source >> 16) & 0x01FFF; | |
668 | int src_y = s->twoD_source & 0xFFFF; | |
604be200 SK |
669 | int dst_x = (s->twoD_destination >> 16) & 0x01FFF; |
670 | int dst_y = s->twoD_destination & 0xFFFF; | |
671 | int operation_width = (s->twoD_dimension >> 16) & 0x1FFF; | |
672 | int operation_height = s->twoD_dimension & 0xFFFF; | |
673 | uint32_t color = s->twoD_foreground; | |
674 | int format_flags = (s->twoD_stretch >> 20) & 0x3; | |
675 | int addressing = (s->twoD_stretch >> 16) & 0xF; | |
676 | ||
677 | /* get frame buffer info */ | |
64f1603b BZ |
678 | uint8_t *src = s->local_mem + (s->twoD_source_base & 0x03FFFFFF); |
679 | uint8_t *dst = s->local_mem + (s->twoD_destination_base & 0x03FFFFFF); | |
07d8a50c | 680 | int src_width = (s->dc_crt_h_total & 0x00000FFF) + 1; |
604be200 SK |
681 | int dst_width = (s->dc_crt_h_total & 0x00000FFF) + 1; |
682 | ||
683 | if (addressing != 0x0) { | |
684 | printf("%s: only XY addressing is supported.\n", __func__); | |
685 | abort(); | |
686 | } | |
687 | ||
688 | if ((s->twoD_source_base & 0x08000000) || | |
689 | (s->twoD_destination_base & 0x08000000)) { | |
690 | printf("%s: only local memory is supported.\n", __func__); | |
691 | abort(); | |
692 | } | |
693 | ||
694 | switch (operation) { | |
07d8a50c | 695 | case 0x00: /* copy area */ |
64f1603b BZ |
696 | #define COPY_AREA(_bpp, _pixel_type, rtl) { \ |
697 | int y, x, index_d, index_s; \ | |
698 | for (y = 0; y < operation_height; y++) { \ | |
699 | for (x = 0; x < operation_width; x++) { \ | |
700 | if (rtl) { \ | |
701 | index_s = ((src_y - y) * src_width + src_x - x) * _bpp; \ | |
702 | index_d = ((dst_y - y) * dst_width + dst_x - x) * _bpp; \ | |
703 | } else { \ | |
704 | index_s = ((src_y + y) * src_width + src_x + x) * _bpp; \ | |
705 | index_d = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \ | |
706 | } \ | |
707 | *(_pixel_type *)&dst[index_d] = *(_pixel_type *)&src[index_s];\ | |
708 | } \ | |
709 | } \ | |
07d8a50c AJ |
710 | } |
711 | switch (format_flags) { | |
712 | case 0: | |
713 | COPY_AREA(1, uint8_t, rtl); | |
714 | break; | |
715 | case 1: | |
716 | COPY_AREA(2, uint16_t, rtl); | |
717 | break; | |
718 | case 2: | |
719 | COPY_AREA(4, uint32_t, rtl); | |
720 | break; | |
721 | } | |
722 | break; | |
604be200 | 723 | |
07d8a50c | 724 | case 0x01: /* fill rectangle */ |
604be200 SK |
725 | #define FILL_RECT(_bpp, _pixel_type) { \ |
726 | int y, x; \ | |
727 | for (y = 0; y < operation_height; y++) { \ | |
728 | for (x = 0; x < operation_width; x++) { \ | |
729 | int index = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \ | |
64f1603b | 730 | *(_pixel_type *)&dst[index] = (_pixel_type)color; \ |
604be200 SK |
731 | } \ |
732 | } \ | |
733 | } | |
734 | ||
735 | switch (format_flags) { | |
736 | case 0: | |
737 | FILL_RECT(1, uint8_t); | |
738 | break; | |
739 | case 1: | |
740 | FILL_RECT(2, uint16_t); | |
741 | break; | |
742 | case 2: | |
743 | FILL_RECT(4, uint32_t); | |
744 | break; | |
745 | } | |
746 | break; | |
747 | ||
748 | default: | |
749 | printf("non-implemented SM501 2D operation. %d\n", operation); | |
750 | abort(); | |
751 | break; | |
752 | } | |
753 | } | |
754 | ||
a8170e5e | 755 | static uint64_t sm501_system_config_read(void *opaque, hwaddr addr, |
25793bfa | 756 | unsigned size) |
ffd39257 | 757 | { |
64f1603b | 758 | SM501State *s = (SM501State *)opaque; |
ffd39257 | 759 | uint32_t ret = 0; |
8da3ff18 | 760 | SM501_DPRINTF("sm501 system config regs : read addr=%x\n", (int)addr); |
ffd39257 | 761 | |
64f1603b | 762 | switch (addr) { |
ffd39257 | 763 | case SM501_SYSTEM_CONTROL: |
64f1603b BZ |
764 | ret = s->system_control; |
765 | break; | |
ffd39257 | 766 | case SM501_MISC_CONTROL: |
64f1603b BZ |
767 | ret = s->misc_control; |
768 | break; | |
ffd39257 | 769 | case SM501_GPIO31_0_CONTROL: |
64f1603b BZ |
770 | ret = s->gpio_31_0_control; |
771 | break; | |
ffd39257 | 772 | case SM501_GPIO63_32_CONTROL: |
64f1603b BZ |
773 | ret = s->gpio_63_32_control; |
774 | break; | |
ffd39257 | 775 | case SM501_DEVICEID: |
64f1603b BZ |
776 | ret = 0x050100A0; |
777 | break; | |
ffd39257 | 778 | case SM501_DRAM_CONTROL: |
64f1603b BZ |
779 | ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13; |
780 | break; | |
70e46ca8 BZ |
781 | case SM501_ARBTRTN_CONTROL: |
782 | ret = s->arbitration_control; | |
783 | break; | |
ffd39257 | 784 | case SM501_IRQ_MASK: |
64f1603b BZ |
785 | ret = s->irq_mask; |
786 | break; | |
ffd39257 | 787 | case SM501_MISC_TIMING: |
64f1603b BZ |
788 | /* TODO : simulate gate control */ |
789 | ret = s->misc_timing; | |
790 | break; | |
ffd39257 | 791 | case SM501_CURRENT_GATE: |
64f1603b BZ |
792 | /* TODO : simulate gate control */ |
793 | ret = 0x00021807; | |
794 | break; | |
ffd39257 | 795 | case SM501_CURRENT_CLOCK: |
64f1603b BZ |
796 | ret = 0x2A1A0A09; |
797 | break; | |
ffd39257 | 798 | case SM501_POWER_MODE_CONTROL: |
64f1603b BZ |
799 | ret = s->power_mode_control; |
800 | break; | |
ffd39257 BS |
801 | |
802 | default: | |
64f1603b BZ |
803 | printf("sm501 system config : not implemented register read." |
804 | " addr=%x\n", (int)addr); | |
43dc2a64 | 805 | abort(); |
ffd39257 BS |
806 | } |
807 | ||
808 | return ret; | |
809 | } | |
810 | ||
a8170e5e | 811 | static void sm501_system_config_write(void *opaque, hwaddr addr, |
25793bfa | 812 | uint64_t value, unsigned size) |
ffd39257 | 813 | { |
64f1603b | 814 | SM501State *s = (SM501State *)opaque; |
8da3ff18 | 815 | SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n", |
64f1603b | 816 | (uint32_t)addr, (uint32_t)value); |
ffd39257 | 817 | |
64f1603b | 818 | switch (addr) { |
ffd39257 | 819 | case SM501_SYSTEM_CONTROL: |
64f1603b BZ |
820 | s->system_control = value & 0xE300B8F7; |
821 | break; | |
ffd39257 | 822 | case SM501_MISC_CONTROL: |
64f1603b BZ |
823 | s->misc_control = value & 0xFF7FFF20; |
824 | break; | |
ffd39257 | 825 | case SM501_GPIO31_0_CONTROL: |
64f1603b BZ |
826 | s->gpio_31_0_control = value; |
827 | break; | |
ffd39257 | 828 | case SM501_GPIO63_32_CONTROL: |
64f1603b BZ |
829 | s->gpio_63_32_control = value; |
830 | break; | |
ffd39257 | 831 | case SM501_DRAM_CONTROL: |
64f1603b BZ |
832 | s->local_mem_size_index = (value >> 13) & 0x7; |
833 | /* TODO : check validity of size change */ | |
834 | s->dram_control |= value & 0x7FFFFFC3; | |
835 | break; | |
70e46ca8 BZ |
836 | case SM501_ARBTRTN_CONTROL: |
837 | s->arbitration_control = value & 0x37777777; | |
838 | break; | |
ffd39257 | 839 | case SM501_IRQ_MASK: |
64f1603b BZ |
840 | s->irq_mask = value; |
841 | break; | |
ffd39257 | 842 | case SM501_MISC_TIMING: |
64f1603b BZ |
843 | s->misc_timing = value & 0xF31F1FFF; |
844 | break; | |
ffd39257 BS |
845 | case SM501_POWER_MODE_0_GATE: |
846 | case SM501_POWER_MODE_1_GATE: | |
847 | case SM501_POWER_MODE_0_CLOCK: | |
848 | case SM501_POWER_MODE_1_CLOCK: | |
64f1603b BZ |
849 | /* TODO : simulate gate & clock control */ |
850 | break; | |
ffd39257 | 851 | case SM501_POWER_MODE_CONTROL: |
64f1603b BZ |
852 | s->power_mode_control = value & 0x00000003; |
853 | break; | |
ffd39257 BS |
854 | |
855 | default: | |
64f1603b BZ |
856 | printf("sm501 system config : not implemented register write." |
857 | " addr=%x, val=%x\n", (int)addr, (uint32_t)value); | |
43dc2a64 | 858 | abort(); |
ffd39257 BS |
859 | } |
860 | } | |
861 | ||
25793bfa AK |
862 | static const MemoryRegionOps sm501_system_config_ops = { |
863 | .read = sm501_system_config_read, | |
864 | .write = sm501_system_config_write, | |
865 | .valid = { | |
866 | .min_access_size = 4, | |
867 | .max_access_size = 4, | |
868 | }, | |
afef2e1d | 869 | .endianness = DEVICE_LITTLE_ENDIAN, |
ffd39257 BS |
870 | }; |
871 | ||
a8170e5e | 872 | static uint32_t sm501_palette_read(void *opaque, hwaddr addr) |
486579de | 873 | { |
64f1603b | 874 | SM501State *s = (SM501State *)opaque; |
486579de AZ |
875 | SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr); |
876 | ||
877 | /* TODO : consider BYTE/WORD access */ | |
878 | /* TODO : consider endian */ | |
879 | ||
45416789 | 880 | assert(range_covers_byte(0, 0x400 * 3, addr)); |
64f1603b | 881 | return *(uint32_t *)&s->dc_palette[addr]; |
486579de AZ |
882 | } |
883 | ||
64f1603b BZ |
884 | static void sm501_palette_write(void *opaque, hwaddr addr, |
885 | uint32_t value) | |
486579de | 886 | { |
64f1603b | 887 | SM501State *s = (SM501State *)opaque; |
486579de | 888 | SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n", |
64f1603b | 889 | (int)addr, value); |
486579de AZ |
890 | |
891 | /* TODO : consider BYTE/WORD access */ | |
892 | /* TODO : consider endian */ | |
893 | ||
45416789 | 894 | assert(range_covers_byte(0, 0x400 * 3, addr)); |
64f1603b | 895 | *(uint32_t *)&s->dc_palette[addr] = value; |
486579de AZ |
896 | } |
897 | ||
a8170e5e | 898 | static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr, |
25793bfa | 899 | unsigned size) |
ffd39257 | 900 | { |
64f1603b | 901 | SM501State *s = (SM501State *)opaque; |
ffd39257 | 902 | uint32_t ret = 0; |
8da3ff18 | 903 | SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x\n", (int)addr); |
ffd39257 | 904 | |
64f1603b | 905 | switch (addr) { |
ffd39257 BS |
906 | |
907 | case SM501_DC_PANEL_CONTROL: | |
64f1603b BZ |
908 | ret = s->dc_panel_control; |
909 | break; | |
ffd39257 | 910 | case SM501_DC_PANEL_PANNING_CONTROL: |
64f1603b BZ |
911 | ret = s->dc_panel_panning_control; |
912 | break; | |
ffd39257 | 913 | case SM501_DC_PANEL_FB_ADDR: |
64f1603b BZ |
914 | ret = s->dc_panel_fb_addr; |
915 | break; | |
ffd39257 | 916 | case SM501_DC_PANEL_FB_OFFSET: |
64f1603b BZ |
917 | ret = s->dc_panel_fb_offset; |
918 | break; | |
ffd39257 | 919 | case SM501_DC_PANEL_FB_WIDTH: |
64f1603b BZ |
920 | ret = s->dc_panel_fb_width; |
921 | break; | |
ffd39257 | 922 | case SM501_DC_PANEL_FB_HEIGHT: |
64f1603b BZ |
923 | ret = s->dc_panel_fb_height; |
924 | break; | |
ffd39257 | 925 | case SM501_DC_PANEL_TL_LOC: |
64f1603b BZ |
926 | ret = s->dc_panel_tl_location; |
927 | break; | |
ffd39257 | 928 | case SM501_DC_PANEL_BR_LOC: |
64f1603b BZ |
929 | ret = s->dc_panel_br_location; |
930 | break; | |
ffd39257 BS |
931 | |
932 | case SM501_DC_PANEL_H_TOT: | |
64f1603b BZ |
933 | ret = s->dc_panel_h_total; |
934 | break; | |
ffd39257 | 935 | case SM501_DC_PANEL_H_SYNC: |
64f1603b BZ |
936 | ret = s->dc_panel_h_sync; |
937 | break; | |
ffd39257 | 938 | case SM501_DC_PANEL_V_TOT: |
64f1603b BZ |
939 | ret = s->dc_panel_v_total; |
940 | break; | |
ffd39257 | 941 | case SM501_DC_PANEL_V_SYNC: |
64f1603b BZ |
942 | ret = s->dc_panel_v_sync; |
943 | break; | |
ffd39257 BS |
944 | |
945 | case SM501_DC_CRT_CONTROL: | |
64f1603b BZ |
946 | ret = s->dc_crt_control; |
947 | break; | |
ffd39257 | 948 | case SM501_DC_CRT_FB_ADDR: |
64f1603b BZ |
949 | ret = s->dc_crt_fb_addr; |
950 | break; | |
ffd39257 | 951 | case SM501_DC_CRT_FB_OFFSET: |
64f1603b BZ |
952 | ret = s->dc_crt_fb_offset; |
953 | break; | |
ffd39257 | 954 | case SM501_DC_CRT_H_TOT: |
64f1603b BZ |
955 | ret = s->dc_crt_h_total; |
956 | break; | |
ffd39257 | 957 | case SM501_DC_CRT_H_SYNC: |
64f1603b BZ |
958 | ret = s->dc_crt_h_sync; |
959 | break; | |
ffd39257 | 960 | case SM501_DC_CRT_V_TOT: |
64f1603b BZ |
961 | ret = s->dc_crt_v_total; |
962 | break; | |
ffd39257 | 963 | case SM501_DC_CRT_V_SYNC: |
64f1603b BZ |
964 | ret = s->dc_crt_v_sync; |
965 | break; | |
ffd39257 BS |
966 | |
967 | case SM501_DC_CRT_HWC_ADDR: | |
64f1603b BZ |
968 | ret = s->dc_crt_hwc_addr; |
969 | break; | |
ffd39257 | 970 | case SM501_DC_CRT_HWC_LOC: |
64f1603b BZ |
971 | ret = s->dc_crt_hwc_location; |
972 | break; | |
ffd39257 | 973 | case SM501_DC_CRT_HWC_COLOR_1_2: |
64f1603b BZ |
974 | ret = s->dc_crt_hwc_color_1_2; |
975 | break; | |
ffd39257 | 976 | case SM501_DC_CRT_HWC_COLOR_3: |
64f1603b BZ |
977 | ret = s->dc_crt_hwc_color_3; |
978 | break; | |
ffd39257 | 979 | |
64f1603b | 980 | case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4: |
486579de AZ |
981 | ret = sm501_palette_read(opaque, addr - SM501_DC_PANEL_PALETTE); |
982 | break; | |
983 | ||
ffd39257 | 984 | default: |
64f1603b BZ |
985 | printf("sm501 disp ctrl : not implemented register read." |
986 | " addr=%x\n", (int)addr); | |
43dc2a64 | 987 | abort(); |
ffd39257 BS |
988 | } |
989 | ||
990 | return ret; | |
991 | } | |
992 | ||
a8170e5e | 993 | static void sm501_disp_ctrl_write(void *opaque, hwaddr addr, |
25793bfa | 994 | uint64_t value, unsigned size) |
ffd39257 | 995 | { |
64f1603b | 996 | SM501State *s = (SM501State *)opaque; |
8da3ff18 | 997 | SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, val=%x\n", |
64f1603b | 998 | (unsigned)addr, (unsigned)value); |
ffd39257 | 999 | |
64f1603b | 1000 | switch (addr) { |
ffd39257 | 1001 | case SM501_DC_PANEL_CONTROL: |
64f1603b BZ |
1002 | s->dc_panel_control = value & 0x0FFF73FF; |
1003 | break; | |
ffd39257 | 1004 | case SM501_DC_PANEL_PANNING_CONTROL: |
64f1603b BZ |
1005 | s->dc_panel_panning_control = value & 0xFF3FFF3F; |
1006 | break; | |
ffd39257 | 1007 | case SM501_DC_PANEL_FB_ADDR: |
64f1603b BZ |
1008 | s->dc_panel_fb_addr = value & 0x8FFFFFF0; |
1009 | break; | |
ffd39257 | 1010 | case SM501_DC_PANEL_FB_OFFSET: |
64f1603b BZ |
1011 | s->dc_panel_fb_offset = value & 0x3FF03FF0; |
1012 | break; | |
ffd39257 | 1013 | case SM501_DC_PANEL_FB_WIDTH: |
64f1603b BZ |
1014 | s->dc_panel_fb_width = value & 0x0FFF0FFF; |
1015 | break; | |
ffd39257 | 1016 | case SM501_DC_PANEL_FB_HEIGHT: |
64f1603b BZ |
1017 | s->dc_panel_fb_height = value & 0x0FFF0FFF; |
1018 | break; | |
ffd39257 | 1019 | case SM501_DC_PANEL_TL_LOC: |
64f1603b BZ |
1020 | s->dc_panel_tl_location = value & 0x07FF07FF; |
1021 | break; | |
ffd39257 | 1022 | case SM501_DC_PANEL_BR_LOC: |
64f1603b BZ |
1023 | s->dc_panel_br_location = value & 0x07FF07FF; |
1024 | break; | |
ffd39257 BS |
1025 | |
1026 | case SM501_DC_PANEL_H_TOT: | |
64f1603b BZ |
1027 | s->dc_panel_h_total = value & 0x0FFF0FFF; |
1028 | break; | |
ffd39257 | 1029 | case SM501_DC_PANEL_H_SYNC: |
64f1603b BZ |
1030 | s->dc_panel_h_sync = value & 0x00FF0FFF; |
1031 | break; | |
ffd39257 | 1032 | case SM501_DC_PANEL_V_TOT: |
64f1603b BZ |
1033 | s->dc_panel_v_total = value & 0x0FFF0FFF; |
1034 | break; | |
ffd39257 | 1035 | case SM501_DC_PANEL_V_SYNC: |
64f1603b BZ |
1036 | s->dc_panel_v_sync = value & 0x003F0FFF; |
1037 | break; | |
ffd39257 BS |
1038 | |
1039 | case SM501_DC_PANEL_HWC_ADDR: | |
6a2a5aae BZ |
1040 | value &= 0x8FFFFFF0; |
1041 | if (value != s->dc_panel_hwc_addr) { | |
1042 | hwc_invalidate(s, 0); | |
1043 | s->dc_panel_hwc_addr = value; | |
1044 | } | |
64f1603b | 1045 | break; |
ffd39257 | 1046 | case SM501_DC_PANEL_HWC_LOC: |
6a2a5aae BZ |
1047 | value &= 0x0FFF0FFF; |
1048 | if (value != s->dc_panel_hwc_location) { | |
1049 | hwc_invalidate(s, 0); | |
1050 | s->dc_panel_hwc_location = value; | |
1051 | } | |
64f1603b | 1052 | break; |
ffd39257 | 1053 | case SM501_DC_PANEL_HWC_COLOR_1_2: |
64f1603b BZ |
1054 | s->dc_panel_hwc_color_1_2 = value; |
1055 | break; | |
ffd39257 | 1056 | case SM501_DC_PANEL_HWC_COLOR_3: |
64f1603b BZ |
1057 | s->dc_panel_hwc_color_3 = value & 0x0000FFFF; |
1058 | break; | |
ffd39257 BS |
1059 | |
1060 | case SM501_DC_CRT_CONTROL: | |
64f1603b BZ |
1061 | s->dc_crt_control = value & 0x0003FFFF; |
1062 | break; | |
ffd39257 | 1063 | case SM501_DC_CRT_FB_ADDR: |
64f1603b BZ |
1064 | s->dc_crt_fb_addr = value & 0x8FFFFFF0; |
1065 | break; | |
ffd39257 | 1066 | case SM501_DC_CRT_FB_OFFSET: |
64f1603b BZ |
1067 | s->dc_crt_fb_offset = value & 0x3FF03FF0; |
1068 | break; | |
ffd39257 | 1069 | case SM501_DC_CRT_H_TOT: |
64f1603b BZ |
1070 | s->dc_crt_h_total = value & 0x0FFF0FFF; |
1071 | break; | |
ffd39257 | 1072 | case SM501_DC_CRT_H_SYNC: |
64f1603b BZ |
1073 | s->dc_crt_h_sync = value & 0x00FF0FFF; |
1074 | break; | |
ffd39257 | 1075 | case SM501_DC_CRT_V_TOT: |
64f1603b BZ |
1076 | s->dc_crt_v_total = value & 0x0FFF0FFF; |
1077 | break; | |
ffd39257 | 1078 | case SM501_DC_CRT_V_SYNC: |
64f1603b BZ |
1079 | s->dc_crt_v_sync = value & 0x003F0FFF; |
1080 | break; | |
ffd39257 BS |
1081 | |
1082 | case SM501_DC_CRT_HWC_ADDR: | |
6a2a5aae BZ |
1083 | value &= 0x8FFFFFF0; |
1084 | if (value != s->dc_crt_hwc_addr) { | |
1085 | hwc_invalidate(s, 1); | |
1086 | s->dc_crt_hwc_addr = value; | |
1087 | } | |
64f1603b | 1088 | break; |
ffd39257 | 1089 | case SM501_DC_CRT_HWC_LOC: |
6a2a5aae BZ |
1090 | value &= 0x0FFF0FFF; |
1091 | if (value != s->dc_crt_hwc_location) { | |
1092 | hwc_invalidate(s, 1); | |
1093 | s->dc_crt_hwc_location = value; | |
1094 | } | |
64f1603b | 1095 | break; |
ffd39257 | 1096 | case SM501_DC_CRT_HWC_COLOR_1_2: |
64f1603b BZ |
1097 | s->dc_crt_hwc_color_1_2 = value; |
1098 | break; | |
ffd39257 | 1099 | case SM501_DC_CRT_HWC_COLOR_3: |
64f1603b BZ |
1100 | s->dc_crt_hwc_color_3 = value & 0x0000FFFF; |
1101 | break; | |
ffd39257 | 1102 | |
64f1603b | 1103 | case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4: |
486579de AZ |
1104 | sm501_palette_write(opaque, addr - SM501_DC_PANEL_PALETTE, value); |
1105 | break; | |
1106 | ||
ffd39257 | 1107 | default: |
64f1603b BZ |
1108 | printf("sm501 disp ctrl : not implemented register write." |
1109 | " addr=%x, val=%x\n", (int)addr, (unsigned)value); | |
43dc2a64 | 1110 | abort(); |
ffd39257 BS |
1111 | } |
1112 | } | |
1113 | ||
25793bfa AK |
1114 | static const MemoryRegionOps sm501_disp_ctrl_ops = { |
1115 | .read = sm501_disp_ctrl_read, | |
1116 | .write = sm501_disp_ctrl_write, | |
1117 | .valid = { | |
1118 | .min_access_size = 4, | |
1119 | .max_access_size = 4, | |
1120 | }, | |
afef2e1d | 1121 | .endianness = DEVICE_LITTLE_ENDIAN, |
ffd39257 BS |
1122 | }; |
1123 | ||
a8170e5e | 1124 | static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr, |
25793bfa | 1125 | unsigned size) |
604be200 | 1126 | { |
64f1603b | 1127 | SM501State *s = (SM501State *)opaque; |
604be200 SK |
1128 | uint32_t ret = 0; |
1129 | SM501_DPRINTF("sm501 2d engine regs : read addr=%x\n", (int)addr); | |
1130 | ||
64f1603b | 1131 | switch (addr) { |
604be200 SK |
1132 | case SM501_2D_SOURCE_BASE: |
1133 | ret = s->twoD_source_base; | |
1134 | break; | |
1135 | default: | |
1136 | printf("sm501 disp ctrl : not implemented register read." | |
1137 | " addr=%x\n", (int)addr); | |
1138 | abort(); | |
1139 | } | |
1140 | ||
1141 | return ret; | |
1142 | } | |
1143 | ||
a8170e5e | 1144 | static void sm501_2d_engine_write(void *opaque, hwaddr addr, |
25793bfa | 1145 | uint64_t value, unsigned size) |
604be200 | 1146 | { |
64f1603b | 1147 | SM501State *s = (SM501State *)opaque; |
604be200 | 1148 | SM501_DPRINTF("sm501 2d engine regs : write addr=%x, val=%x\n", |
25793bfa | 1149 | (unsigned)addr, (unsigned)value); |
604be200 | 1150 | |
64f1603b | 1151 | switch (addr) { |
07d8a50c AJ |
1152 | case SM501_2D_SOURCE: |
1153 | s->twoD_source = value; | |
1154 | break; | |
604be200 SK |
1155 | case SM501_2D_DESTINATION: |
1156 | s->twoD_destination = value; | |
1157 | break; | |
1158 | case SM501_2D_DIMENSION: | |
1159 | s->twoD_dimension = value; | |
1160 | break; | |
1161 | case SM501_2D_CONTROL: | |
1162 | s->twoD_control = value; | |
1163 | ||
1164 | /* do 2d operation if start flag is set. */ | |
1165 | if (value & 0x80000000) { | |
1166 | sm501_2d_operation(s); | |
1167 | s->twoD_control &= ~0x80000000; /* start flag down */ | |
1168 | } | |
1169 | ||
1170 | break; | |
1171 | case SM501_2D_PITCH: | |
1172 | s->twoD_pitch = value; | |
1173 | break; | |
1174 | case SM501_2D_FOREGROUND: | |
1175 | s->twoD_foreground = value; | |
1176 | break; | |
1177 | case SM501_2D_STRETCH: | |
1178 | s->twoD_stretch = value; | |
1179 | break; | |
1180 | case SM501_2D_COLOR_COMPARE_MASK: | |
1181 | s->twoD_color_compare_mask = value; | |
1182 | break; | |
1183 | case SM501_2D_MASK: | |
1184 | s->twoD_mask = value; | |
1185 | break; | |
1186 | case SM501_2D_WINDOW_WIDTH: | |
1187 | s->twoD_window_width = value; | |
1188 | break; | |
1189 | case SM501_2D_SOURCE_BASE: | |
1190 | s->twoD_source_base = value; | |
1191 | break; | |
1192 | case SM501_2D_DESTINATION_BASE: | |
1193 | s->twoD_destination_base = value; | |
1194 | break; | |
1195 | default: | |
1196 | printf("sm501 2d engine : not implemented register write." | |
25793bfa | 1197 | " addr=%x, val=%x\n", (int)addr, (unsigned)value); |
604be200 SK |
1198 | abort(); |
1199 | } | |
1200 | } | |
1201 | ||
25793bfa AK |
1202 | static const MemoryRegionOps sm501_2d_engine_ops = { |
1203 | .read = sm501_2d_engine_read, | |
1204 | .write = sm501_2d_engine_write, | |
1205 | .valid = { | |
1206 | .min_access_size = 4, | |
1207 | .max_access_size = 4, | |
1208 | }, | |
afef2e1d | 1209 | .endianness = DEVICE_LITTLE_ENDIAN, |
604be200 SK |
1210 | }; |
1211 | ||
ffd39257 BS |
1212 | /* draw line functions for all console modes */ |
1213 | ||
ffd39257 | 1214 | typedef void draw_line_func(uint8_t *d, const uint8_t *s, |
64f1603b | 1215 | int width, const uint32_t *pal); |
ffd39257 | 1216 | |
6a2a5aae BZ |
1217 | typedef void draw_hwc_line_func(uint8_t *d, const uint8_t *s, |
1218 | int width, const uint8_t *palette, | |
1219 | int c_x, int c_y); | |
0a4e7cd2 | 1220 | |
ffd39257 | 1221 | #define DEPTH 8 |
47b43a1f | 1222 | #include "sm501_template.h" |
ffd39257 BS |
1223 | |
1224 | #define DEPTH 15 | |
47b43a1f | 1225 | #include "sm501_template.h" |
ffd39257 BS |
1226 | |
1227 | #define BGR_FORMAT | |
1228 | #define DEPTH 15 | |
47b43a1f | 1229 | #include "sm501_template.h" |
ffd39257 BS |
1230 | |
1231 | #define DEPTH 16 | |
47b43a1f | 1232 | #include "sm501_template.h" |
ffd39257 BS |
1233 | |
1234 | #define BGR_FORMAT | |
1235 | #define DEPTH 16 | |
47b43a1f | 1236 | #include "sm501_template.h" |
ffd39257 BS |
1237 | |
1238 | #define DEPTH 32 | |
47b43a1f | 1239 | #include "sm501_template.h" |
ffd39257 BS |
1240 | |
1241 | #define BGR_FORMAT | |
1242 | #define DEPTH 32 | |
47b43a1f | 1243 | #include "sm501_template.h" |
ffd39257 | 1244 | |
64f1603b | 1245 | static draw_line_func *draw_line8_funcs[] = { |
ffd39257 BS |
1246 | draw_line8_8, |
1247 | draw_line8_15, | |
1248 | draw_line8_16, | |
1249 | draw_line8_32, | |
1250 | draw_line8_32bgr, | |
1251 | draw_line8_15bgr, | |
1252 | draw_line8_16bgr, | |
1253 | }; | |
1254 | ||
64f1603b | 1255 | static draw_line_func *draw_line16_funcs[] = { |
ffd39257 BS |
1256 | draw_line16_8, |
1257 | draw_line16_15, | |
1258 | draw_line16_16, | |
1259 | draw_line16_32, | |
1260 | draw_line16_32bgr, | |
1261 | draw_line16_15bgr, | |
1262 | draw_line16_16bgr, | |
1263 | }; | |
1264 | ||
64f1603b | 1265 | static draw_line_func *draw_line32_funcs[] = { |
ffd39257 BS |
1266 | draw_line32_8, |
1267 | draw_line32_15, | |
1268 | draw_line32_16, | |
1269 | draw_line32_32, | |
1270 | draw_line32_32bgr, | |
1271 | draw_line32_15bgr, | |
1272 | draw_line32_16bgr, | |
1273 | }; | |
1274 | ||
64f1603b | 1275 | static draw_hwc_line_func *draw_hwc_line_funcs[] = { |
0a4e7cd2 SK |
1276 | draw_hwc_line_8, |
1277 | draw_hwc_line_15, | |
1278 | draw_hwc_line_16, | |
1279 | draw_hwc_line_32, | |
1280 | draw_hwc_line_32bgr, | |
1281 | draw_hwc_line_15bgr, | |
1282 | draw_hwc_line_16bgr, | |
1283 | }; | |
1284 | ||
c78f7137 | 1285 | static inline int get_depth_index(DisplaySurface *surface) |
ffd39257 | 1286 | { |
c78f7137 | 1287 | switch (surface_bits_per_pixel(surface)) { |
ffd39257 BS |
1288 | default: |
1289 | case 8: | |
64f1603b | 1290 | return 0; |
ffd39257 | 1291 | case 15: |
8927bcfd | 1292 | return 1; |
ffd39257 | 1293 | case 16: |
8927bcfd | 1294 | return 2; |
ffd39257 | 1295 | case 32: |
c78f7137 GH |
1296 | if (is_surface_bgr(surface)) { |
1297 | return 4; | |
1298 | } else { | |
1299 | return 3; | |
1300 | } | |
ffd39257 BS |
1301 | } |
1302 | } | |
1303 | ||
64f1603b | 1304 | static void sm501_draw_crt(SM501State *s) |
ffd39257 | 1305 | { |
c78f7137 | 1306 | DisplaySurface *surface = qemu_console_surface(s->con); |
6a2a5aae BZ |
1307 | int y, c_x = 0, c_y = 0; |
1308 | uint8_t *hwc_src = NULL, *src = s->local_mem; | |
1309 | int width = get_width(s, 1); | |
1310 | int height = get_height(s, 1); | |
1311 | int src_bpp = get_bpp(s, 1); | |
c78f7137 | 1312 | int dst_bpp = surface_bytes_per_pixel(surface); |
64f1603b BZ |
1313 | uint32_t *palette = (uint32_t *)&s->dc_palette[SM501_DC_CRT_PALETTE - |
1314 | SM501_DC_PANEL_PALETTE]; | |
0a4e7cd2 | 1315 | uint8_t hwc_palette[3 * 3]; |
01d2d584 | 1316 | int dst_depth_index = get_depth_index(surface); |
64f1603b BZ |
1317 | draw_line_func *draw_line = NULL; |
1318 | draw_hwc_line_func *draw_hwc_line = NULL; | |
ffd39257 BS |
1319 | int full_update = 0; |
1320 | int y_start = -1; | |
543c4c94 AJ |
1321 | ram_addr_t page_min = ~0l; |
1322 | ram_addr_t page_max = 0l; | |
25793bfa | 1323 | ram_addr_t offset = 0; |
ffd39257 BS |
1324 | |
1325 | /* choose draw_line function */ | |
6a2a5aae BZ |
1326 | switch (src_bpp) { |
1327 | case 1: | |
01d2d584 | 1328 | draw_line = draw_line8_funcs[dst_depth_index]; |
64f1603b | 1329 | break; |
6a2a5aae | 1330 | case 2: |
01d2d584 | 1331 | draw_line = draw_line16_funcs[dst_depth_index]; |
64f1603b | 1332 | break; |
6a2a5aae | 1333 | case 4: |
01d2d584 | 1334 | draw_line = draw_line32_funcs[dst_depth_index]; |
64f1603b | 1335 | break; |
ffd39257 | 1336 | default: |
64f1603b BZ |
1337 | printf("sm501 draw crt : invalid DC_CRT_CONTROL=%x.\n", |
1338 | s->dc_crt_control); | |
43dc2a64 | 1339 | abort(); |
64f1603b | 1340 | break; |
ffd39257 BS |
1341 | } |
1342 | ||
0a4e7cd2 SK |
1343 | /* set up to draw hardware cursor */ |
1344 | if (is_hwc_enabled(s, 1)) { | |
0a4e7cd2 | 1345 | /* choose cursor draw line function */ |
01d2d584 | 1346 | draw_hwc_line = draw_hwc_line_funcs[dst_depth_index]; |
6a2a5aae BZ |
1347 | hwc_src = get_hwc_address(s, 1); |
1348 | c_x = get_hwc_x(s, 1); | |
1349 | c_y = get_hwc_y(s, 1); | |
1350 | get_hwc_palette(s, 1, hwc_palette); | |
0a4e7cd2 SK |
1351 | } |
1352 | ||
ffd39257 BS |
1353 | /* adjust console size */ |
1354 | if (s->last_width != width || s->last_height != height) { | |
c78f7137 GH |
1355 | qemu_console_resize(s->con, width, height); |
1356 | surface = qemu_console_surface(s->con); | |
64f1603b BZ |
1357 | s->last_width = width; |
1358 | s->last_height = height; | |
1359 | full_update = 1; | |
ffd39257 BS |
1360 | } |
1361 | ||
1362 | /* draw each line according to conditions */ | |
5299c0f2 | 1363 | memory_region_sync_dirty_bitmap(&s->local_mem_region); |
ffd39257 | 1364 | for (y = 0; y < height; y++) { |
6a2a5aae | 1365 | int update, update_hwc; |
cd7a45c9 BS |
1366 | ram_addr_t page0 = offset; |
1367 | ram_addr_t page1 = offset + width * src_bpp - 1; | |
ffd39257 | 1368 | |
6a2a5aae BZ |
1369 | /* check if hardware cursor is enabled and we're within its range */ |
1370 | update_hwc = draw_hwc_line && c_y <= y && y < c_y + SM501_HWC_HEIGHT; | |
1371 | update = full_update || update_hwc; | |
64f1603b | 1372 | /* check dirty flags for each line */ |
6a2a5aae BZ |
1373 | update |= memory_region_get_dirty(&s->local_mem_region, page0, |
1374 | page1 - page0, DIRTY_MEMORY_VGA); | |
ffd39257 | 1375 | |
64f1603b BZ |
1376 | /* draw line and change status */ |
1377 | if (update) { | |
c78f7137 GH |
1378 | uint8_t *d = surface_data(surface); |
1379 | d += y * width * dst_bpp; | |
0a4e7cd2 SK |
1380 | |
1381 | /* draw graphics layer */ | |
1382 | draw_line(d, src, width, palette); | |
1383 | ||
64f1603b | 1384 | /* draw hardware cursor */ |
0a4e7cd2 | 1385 | if (update_hwc) { |
6a2a5aae | 1386 | draw_hwc_line(d, hwc_src, width, hwc_palette, c_x, y - c_y); |
0a4e7cd2 SK |
1387 | } |
1388 | ||
64f1603b BZ |
1389 | if (y_start < 0) { |
1390 | y_start = y; | |
1391 | } | |
1392 | if (page0 < page_min) { | |
1393 | page_min = page0; | |
1394 | } | |
1395 | if (page1 > page_max) { | |
1396 | page_max = page1; | |
1397 | } | |
1398 | } else { | |
1399 | if (y_start >= 0) { | |
1400 | /* flush to display */ | |
c78f7137 | 1401 | dpy_gfx_update(s->con, 0, y_start, width, y - y_start); |
64f1603b BZ |
1402 | y_start = -1; |
1403 | } | |
1404 | } | |
ffd39257 | 1405 | |
64f1603b BZ |
1406 | src += width * src_bpp; |
1407 | offset += width * src_bpp; | |
ffd39257 BS |
1408 | } |
1409 | ||
1410 | /* complete flush to display */ | |
64f1603b | 1411 | if (y_start >= 0) { |
c78f7137 | 1412 | dpy_gfx_update(s->con, 0, y_start, width, y - y_start); |
64f1603b | 1413 | } |
ffd39257 BS |
1414 | |
1415 | /* clear dirty flags */ | |
543c4c94 | 1416 | if (page_min != ~0l) { |
64f1603b | 1417 | memory_region_reset_dirty(&s->local_mem_region, |
25793bfa AK |
1418 | page_min, page_max + TARGET_PAGE_SIZE, |
1419 | DIRTY_MEMORY_VGA); | |
543c4c94 | 1420 | } |
ffd39257 BS |
1421 | } |
1422 | ||
1423 | static void sm501_update_display(void *opaque) | |
1424 | { | |
64f1603b | 1425 | SM501State *s = (SM501State *)opaque; |
ffd39257 | 1426 | |
64f1603b BZ |
1427 | if (s->dc_crt_control & SM501_DC_CRT_CONTROL_ENABLE) { |
1428 | sm501_draw_crt(s); | |
1429 | } | |
ffd39257 BS |
1430 | } |
1431 | ||
380cd056 GH |
1432 | static const GraphicHwOps sm501_ops = { |
1433 | .gfx_update = sm501_update_display, | |
1434 | }; | |
1435 | ||
ca8a1104 | 1436 | static void sm501_reset(SM501State *s) |
ffd39257 | 1437 | { |
e2ee8476 BZ |
1438 | s->system_control = 0x00100000; /* 2D engine FIFO empty */ |
1439 | /* Bits 17 (SH), 7 (CDR), 6:5 (Test), 2:0 (Bus) are all supposed | |
1440 | * to be determined at reset by GPIO lines which set config bits. | |
1441 | * We hardwire them: | |
1442 | * SH = 0 : Hitachi Ready Polarity == Active Low | |
1443 | * CDR = 0 : do not reset clock divider | |
1444 | * TEST = 0 : Normal mode (not testing the silicon) | |
1445 | * BUS = 0 : Hitachi SH3/SH4 | |
1446 | */ | |
1447 | s->misc_control = SM501_MISC_DAC_POWER; | |
ca8a1104 BZ |
1448 | s->gpio_31_0_control = 0; |
1449 | s->gpio_63_32_control = 0; | |
1450 | s->dram_control = 0; | |
70e46ca8 | 1451 | s->arbitration_control = 0x05146732; |
ca8a1104 BZ |
1452 | s->irq_mask = 0; |
1453 | s->misc_timing = 0; | |
1454 | s->power_mode_control = 0; | |
e2ee8476 | 1455 | s->dc_panel_control = 0x00010000; /* FIFO level 3 */ |
ffd39257 | 1456 | s->dc_crt_control = 0x00010000; |
ca8a1104 BZ |
1457 | s->twoD_control = 0; |
1458 | } | |
ffd39257 | 1459 | |
c795fa84 | 1460 | static void sm501_init(SM501State *s, DeviceState *dev, |
ca8a1104 BZ |
1461 | uint32_t local_mem_bytes) |
1462 | { | |
ca8a1104 BZ |
1463 | s->local_mem_size_index = get_local_mem_size_index(local_mem_bytes); |
1464 | SM501_DPRINTF("sm501 local mem size=%x. index=%d\n", get_local_mem_size(s), | |
1465 | s->local_mem_size_index); | |
1466 | ||
1467 | /* local memory */ | |
1468 | memory_region_init_ram(&s->local_mem_region, OBJECT(dev), "sm501.local", | |
1469 | get_local_mem_size(s), &error_fatal); | |
c5705a77 | 1470 | vmstate_register_ram_global(&s->local_mem_region); |
74259ae5 | 1471 | memory_region_set_log(&s->local_mem_region, true, DIRTY_MEMORY_VGA); |
25793bfa | 1472 | s->local_mem = memory_region_get_ram_ptr(&s->local_mem_region); |
ca8a1104 BZ |
1473 | |
1474 | /* mmio */ | |
1475 | memory_region_init(&s->mmio_region, OBJECT(dev), "sm501.mmio", MMIO_SIZE); | |
1476 | memory_region_init_io(&s->system_config_region, OBJECT(dev), | |
1477 | &sm501_system_config_ops, s, | |
1478 | "sm501-system-config", 0x6c); | |
1479 | memory_region_add_subregion(&s->mmio_region, SM501_SYS_CONFIG, | |
1480 | &s->system_config_region); | |
1481 | memory_region_init_io(&s->disp_ctrl_region, OBJECT(dev), | |
1482 | &sm501_disp_ctrl_ops, s, | |
25793bfa | 1483 | "sm501-disp-ctrl", 0x1000); |
ca8a1104 BZ |
1484 | memory_region_add_subregion(&s->mmio_region, SM501_DC, |
1485 | &s->disp_ctrl_region); | |
1486 | memory_region_init_io(&s->twoD_engine_region, OBJECT(dev), | |
1487 | &sm501_2d_engine_ops, s, | |
25793bfa | 1488 | "sm501-2d-engine", 0x54); |
ca8a1104 BZ |
1489 | memory_region_add_subregion(&s->mmio_region, SM501_2D_ENGINE, |
1490 | &s->twoD_engine_region); | |
1491 | ||
1492 | /* create qemu graphic console */ | |
1493 | s->con = graphic_console_init(DEVICE(dev), 0, &sm501_ops, s); | |
1494 | } | |
1495 | ||
1496 | #define TYPE_SYSBUS_SM501 "sysbus-sm501" | |
1497 | #define SYSBUS_SM501(obj) \ | |
1498 | OBJECT_CHECK(SM501SysBusState, (obj), TYPE_SYSBUS_SM501) | |
1499 | ||
1500 | typedef struct { | |
1501 | /*< private >*/ | |
1502 | SysBusDevice parent_obj; | |
1503 | /*< public >*/ | |
1504 | SM501State state; | |
1505 | uint32_t vram_size; | |
1506 | uint32_t base; | |
1507 | void *chr_state; | |
1508 | } SM501SysBusState; | |
1509 | ||
1510 | static void sm501_realize_sysbus(DeviceState *dev, Error **errp) | |
1511 | { | |
1512 | SM501SysBusState *s = SYSBUS_SM501(dev); | |
1513 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
1514 | DeviceState *usb_dev; | |
1515 | ||
c795fa84 | 1516 | sm501_init(&s->state, dev, s->vram_size); |
ca8a1104 BZ |
1517 | if (get_local_mem_size(&s->state) != s->vram_size) { |
1518 | error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32, | |
1519 | get_local_mem_size(&s->state)); | |
1520 | return; | |
1521 | } | |
1522 | sysbus_init_mmio(sbd, &s->state.local_mem_region); | |
1523 | sysbus_init_mmio(sbd, &s->state.mmio_region); | |
ffd39257 | 1524 | |
ac611340 | 1525 | /* bridge to usb host emulation module */ |
ca8a1104 BZ |
1526 | usb_dev = qdev_create(NULL, "sysbus-ohci"); |
1527 | qdev_prop_set_uint32(usb_dev, "num-ports", 2); | |
1528 | qdev_prop_set_uint64(usb_dev, "dma-offset", s->base); | |
1529 | qdev_init_nofail(usb_dev); | |
1530 | memory_region_add_subregion(&s->state.mmio_region, SM501_USB_HOST, | |
1531 | sysbus_mmio_get_region(SYS_BUS_DEVICE(usb_dev), 0)); | |
1532 | sysbus_pass_irq(sbd, SYS_BUS_DEVICE(usb_dev)); | |
ac611340 | 1533 | |
ffd39257 | 1534 | /* bridge to serial emulation module */ |
ca8a1104 BZ |
1535 | if (s->chr_state) { |
1536 | serial_mm_init(&s->state.mmio_region, SM501_UART0, 2, | |
2d48377a | 1537 | NULL, /* TODO : chain irq to IRL */ |
afef2e1d | 1538 | 115200, s->chr_state, DEVICE_LITTLE_ENDIAN); |
2d48377a | 1539 | } |
ca8a1104 | 1540 | } |
ffd39257 | 1541 | |
ca8a1104 BZ |
1542 | static Property sm501_sysbus_properties[] = { |
1543 | DEFINE_PROP_UINT32("vram-size", SM501SysBusState, vram_size, 0), | |
1544 | DEFINE_PROP_UINT32("base", SM501SysBusState, base, 0), | |
1545 | DEFINE_PROP_PTR("chr-state", SM501SysBusState, chr_state), | |
1546 | DEFINE_PROP_END_OF_LIST(), | |
1547 | }; | |
1548 | ||
1549 | static void sm501_reset_sysbus(DeviceState *dev) | |
1550 | { | |
1551 | SM501SysBusState *s = SYSBUS_SM501(dev); | |
1552 | sm501_reset(&s->state); | |
ffd39257 | 1553 | } |
ca8a1104 BZ |
1554 | |
1555 | static void sm501_sysbus_class_init(ObjectClass *klass, void *data) | |
1556 | { | |
1557 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1558 | ||
1559 | dc->realize = sm501_realize_sysbus; | |
1560 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); | |
1561 | dc->desc = "SM501 Multimedia Companion"; | |
1562 | dc->props = sm501_sysbus_properties; | |
1563 | dc->reset = sm501_reset_sysbus; | |
1564 | /* Note: pointer property "chr-state" may remain null, thus | |
1565 | * no need for dc->cannot_instantiate_with_device_add_yet = true; | |
1566 | */ | |
1567 | } | |
1568 | ||
1569 | static const TypeInfo sm501_sysbus_info = { | |
1570 | .name = TYPE_SYSBUS_SM501, | |
1571 | .parent = TYPE_SYS_BUS_DEVICE, | |
1572 | .instance_size = sizeof(SM501SysBusState), | |
1573 | .class_init = sm501_sysbus_class_init, | |
1574 | }; | |
1575 | ||
efae2784 BZ |
1576 | #define TYPE_PCI_SM501 "sm501" |
1577 | #define PCI_SM501(obj) OBJECT_CHECK(SM501PCIState, (obj), TYPE_PCI_SM501) | |
1578 | ||
1579 | typedef struct { | |
1580 | /*< private >*/ | |
1581 | PCIDevice parent_obj; | |
1582 | /*< public >*/ | |
1583 | SM501State state; | |
1584 | uint32_t vram_size; | |
1585 | } SM501PCIState; | |
1586 | ||
1587 | static void sm501_realize_pci(PCIDevice *dev, Error **errp) | |
1588 | { | |
1589 | SM501PCIState *s = PCI_SM501(dev); | |
1590 | ||
1591 | sm501_init(&s->state, DEVICE(dev), s->vram_size); | |
1592 | if (get_local_mem_size(&s->state) != s->vram_size) { | |
1593 | error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32, | |
1594 | get_local_mem_size(&s->state)); | |
1595 | return; | |
1596 | } | |
1597 | pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, | |
1598 | &s->state.local_mem_region); | |
1599 | pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, | |
1600 | &s->state.mmio_region); | |
1601 | } | |
1602 | ||
1603 | static Property sm501_pci_properties[] = { | |
1604 | DEFINE_PROP_UINT32("vram-size", SM501PCIState, vram_size, 64 * M_BYTE), | |
1605 | DEFINE_PROP_END_OF_LIST(), | |
1606 | }; | |
1607 | ||
1608 | static void sm501_reset_pci(DeviceState *dev) | |
1609 | { | |
1610 | SM501PCIState *s = PCI_SM501(dev); | |
1611 | sm501_reset(&s->state); | |
1612 | /* Bits 2:0 of misc_control register is 001 for PCI */ | |
1613 | s->state.misc_control |= 1; | |
1614 | } | |
1615 | ||
1616 | static void sm501_pci_class_init(ObjectClass *klass, void *data) | |
1617 | { | |
1618 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1619 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
1620 | ||
1621 | k->realize = sm501_realize_pci; | |
1622 | k->vendor_id = PCI_VENDOR_ID_SILICON_MOTION; | |
1623 | k->device_id = PCI_DEVICE_ID_SM501; | |
1624 | k->class_id = PCI_CLASS_DISPLAY_OTHER; | |
1625 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); | |
1626 | dc->desc = "SM501 Display Controller"; | |
1627 | dc->props = sm501_pci_properties; | |
1628 | dc->reset = sm501_reset_pci; | |
1629 | dc->hotpluggable = false; | |
1630 | } | |
1631 | ||
1632 | static const TypeInfo sm501_pci_info = { | |
1633 | .name = TYPE_PCI_SM501, | |
1634 | .parent = TYPE_PCI_DEVICE, | |
1635 | .instance_size = sizeof(SM501PCIState), | |
1636 | .class_init = sm501_pci_class_init, | |
1637 | }; | |
1638 | ||
ca8a1104 BZ |
1639 | static void sm501_register_types(void) |
1640 | { | |
1641 | type_register_static(&sm501_sysbus_info); | |
efae2784 | 1642 | type_register_static(&sm501_pci_info); |
ca8a1104 BZ |
1643 | } |
1644 | ||
1645 | type_init(sm501_register_types) |