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1 | /* |
2 | * QEMU SM501 Device | |
3 | * | |
4 | * Copyright (c) 2008 Shin-ichiro KAWASAKI | |
fa0013a1 | 5 | * Copyright (c) 2016-2020 BALATON Zoltan |
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6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | ||
47df5154 | 26 | #include "qemu/osdep.h" |
fc6b3cf9 | 27 | #include "qemu/units.h" |
da34e65c | 28 | #include "qapi/error.h" |
4a1f253a | 29 | #include "qemu/log.h" |
0b8fa32f | 30 | #include "qemu/module.h" |
0d09e41a | 31 | #include "hw/char/serial.h" |
28ecbaee | 32 | #include "ui/console.h" |
83c9f4ca | 33 | #include "hw/sysbus.h" |
d6454270 | 34 | #include "migration/vmstate.h" |
efae2784 | 35 | #include "hw/pci/pci.h" |
a27bd6c7 | 36 | #include "hw/qdev-properties.h" |
4a1f253a | 37 | #include "hw/i2c/i2c.h" |
6306cae2 | 38 | #include "hw/display/i2c-ddc.h" |
1de7afc9 | 39 | #include "qemu/range.h" |
28ecbaee | 40 | #include "ui/pixel_ops.h" |
f3a60058 | 41 | #include "qemu/bswap.h" |
ffd39257 | 42 | |
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43 | /*#define DEBUG_SM501*/ |
44 | /*#define DEBUG_BITBLT*/ | |
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45 | |
46 | #ifdef DEBUG_SM501 | |
001faf32 | 47 | #define SM501_DPRINTF(fmt, ...) printf(fmt, ## __VA_ARGS__) |
ffd39257 | 48 | #else |
64f1603b | 49 | #define SM501_DPRINTF(fmt, ...) do {} while (0) |
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50 | #endif |
51 | ||
ffd39257 | 52 | #define MMIO_BASE_OFFSET 0x3e00000 |
ca8a1104 | 53 | #define MMIO_SIZE 0x200000 |
2edd6e4a | 54 | #define DC_PALETTE_ENTRIES (0x400 * 3) |
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55 | |
56 | /* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */ | |
57 | ||
58 | /* System Configuration area */ | |
59 | /* System config base */ | |
64f1603b | 60 | #define SM501_SYS_CONFIG (0x000000) |
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61 | |
62 | /* config 1 */ | |
64f1603b | 63 | #define SM501_SYSTEM_CONTROL (0x000000) |
ffd39257 | 64 | |
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65 | #define SM501_SYSCTRL_PANEL_TRISTATE (1 << 0) |
66 | #define SM501_SYSCTRL_MEM_TRISTATE (1 << 1) | |
67 | #define SM501_SYSCTRL_CRT_TRISTATE (1 << 2) | |
ffd39257 | 68 | |
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69 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3 << 4) |
70 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0 << 4) | |
71 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1 << 4) | |
72 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2 << 4) | |
73 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3 << 4) | |
ffd39257 | 74 | |
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75 | #define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1 << 6) |
76 | #define SM501_SYSCTRL_PCI_RETRY_DISABLE (1 << 7) | |
77 | #define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1 << 11) | |
78 | #define SM501_SYSCTRL_PCI_BURST_READ_EN (1 << 15) | |
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79 | |
80 | /* miscellaneous control */ | |
81 | ||
64f1603b | 82 | #define SM501_MISC_CONTROL (0x000004) |
ffd39257 | 83 | |
64f1603b BZ |
84 | #define SM501_MISC_BUS_SH (0x0) |
85 | #define SM501_MISC_BUS_PCI (0x1) | |
86 | #define SM501_MISC_BUS_XSCALE (0x2) | |
87 | #define SM501_MISC_BUS_NEC (0x6) | |
88 | #define SM501_MISC_BUS_MASK (0x7) | |
ffd39257 | 89 | |
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90 | #define SM501_MISC_VR_62MB (1 << 3) |
91 | #define SM501_MISC_CDR_RESET (1 << 7) | |
92 | #define SM501_MISC_USB_LB (1 << 8) | |
93 | #define SM501_MISC_USB_SLAVE (1 << 9) | |
94 | #define SM501_MISC_BL_1 (1 << 10) | |
95 | #define SM501_MISC_MC (1 << 11) | |
96 | #define SM501_MISC_DAC_POWER (1 << 12) | |
97 | #define SM501_MISC_IRQ_INVERT (1 << 16) | |
98 | #define SM501_MISC_SH (1 << 17) | |
ffd39257 | 99 | |
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100 | #define SM501_MISC_HOLD_EMPTY (0 << 18) |
101 | #define SM501_MISC_HOLD_8 (1 << 18) | |
102 | #define SM501_MISC_HOLD_16 (2 << 18) | |
103 | #define SM501_MISC_HOLD_24 (3 << 18) | |
104 | #define SM501_MISC_HOLD_32 (4 << 18) | |
105 | #define SM501_MISC_HOLD_MASK (7 << 18) | |
ffd39257 | 106 | |
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107 | #define SM501_MISC_FREQ_12 (1 << 24) |
108 | #define SM501_MISC_PNL_24BIT (1 << 25) | |
109 | #define SM501_MISC_8051_LE (1 << 26) | |
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110 | |
111 | ||
112 | ||
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113 | #define SM501_GPIO31_0_CONTROL (0x000008) |
114 | #define SM501_GPIO63_32_CONTROL (0x00000C) | |
115 | #define SM501_DRAM_CONTROL (0x000010) | |
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116 | |
117 | /* command list */ | |
64f1603b | 118 | #define SM501_ARBTRTN_CONTROL (0x000014) |
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119 | |
120 | /* command list */ | |
64f1603b | 121 | #define SM501_COMMAND_LIST_STATUS (0x000024) |
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122 | |
123 | /* interrupt debug */ | |
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124 | #define SM501_RAW_IRQ_STATUS (0x000028) |
125 | #define SM501_RAW_IRQ_CLEAR (0x000028) | |
126 | #define SM501_IRQ_STATUS (0x00002C) | |
127 | #define SM501_IRQ_MASK (0x000030) | |
128 | #define SM501_DEBUG_CONTROL (0x000034) | |
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129 | |
130 | /* power management */ | |
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131 | #define SM501_POWERMODE_P2X_SRC (1 << 29) |
132 | #define SM501_POWERMODE_V2X_SRC (1 << 20) | |
133 | #define SM501_POWERMODE_M_SRC (1 << 12) | |
134 | #define SM501_POWERMODE_M1_SRC (1 << 4) | |
135 | ||
136 | #define SM501_CURRENT_GATE (0x000038) | |
137 | #define SM501_CURRENT_CLOCK (0x00003C) | |
138 | #define SM501_POWER_MODE_0_GATE (0x000040) | |
139 | #define SM501_POWER_MODE_0_CLOCK (0x000044) | |
140 | #define SM501_POWER_MODE_1_GATE (0x000048) | |
141 | #define SM501_POWER_MODE_1_CLOCK (0x00004C) | |
142 | #define SM501_SLEEP_MODE_GATE (0x000050) | |
143 | #define SM501_POWER_MODE_CONTROL (0x000054) | |
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144 | |
145 | /* power gates for units within the 501 */ | |
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146 | #define SM501_GATE_HOST (0) |
147 | #define SM501_GATE_MEMORY (1) | |
148 | #define SM501_GATE_DISPLAY (2) | |
149 | #define SM501_GATE_2D_ENGINE (3) | |
150 | #define SM501_GATE_CSC (4) | |
151 | #define SM501_GATE_ZVPORT (5) | |
152 | #define SM501_GATE_GPIO (6) | |
153 | #define SM501_GATE_UART0 (7) | |
154 | #define SM501_GATE_UART1 (8) | |
155 | #define SM501_GATE_SSP (10) | |
156 | #define SM501_GATE_USB_HOST (11) | |
157 | #define SM501_GATE_USB_GADGET (12) | |
158 | #define SM501_GATE_UCONTROLLER (17) | |
159 | #define SM501_GATE_AC97 (18) | |
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160 | |
161 | /* panel clock */ | |
64f1603b | 162 | #define SM501_CLOCK_P2XCLK (24) |
ffd39257 | 163 | /* crt clock */ |
64f1603b | 164 | #define SM501_CLOCK_V2XCLK (16) |
ffd39257 | 165 | /* main clock */ |
64f1603b | 166 | #define SM501_CLOCK_MCLK (8) |
ffd39257 | 167 | /* SDRAM controller clock */ |
64f1603b | 168 | #define SM501_CLOCK_M1XCLK (0) |
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169 | |
170 | /* config 2 */ | |
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171 | #define SM501_PCI_MASTER_BASE (0x000058) |
172 | #define SM501_ENDIAN_CONTROL (0x00005C) | |
173 | #define SM501_DEVICEID (0x000060) | |
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174 | /* 0x050100A0 */ |
175 | ||
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176 | #define SM501_DEVICEID_SM501 (0x05010000) |
177 | #define SM501_DEVICEID_IDMASK (0xffff0000) | |
178 | #define SM501_DEVICEID_REVMASK (0x000000ff) | |
ffd39257 | 179 | |
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180 | #define SM501_PLLCLOCK_COUNT (0x000064) |
181 | #define SM501_MISC_TIMING (0x000068) | |
182 | #define SM501_CURRENT_SDRAM_CLOCK (0x00006C) | |
ffd39257 | 183 | |
64f1603b | 184 | #define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074) |
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185 | |
186 | /* GPIO base */ | |
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187 | #define SM501_GPIO (0x010000) |
188 | #define SM501_GPIO_DATA_LOW (0x00) | |
189 | #define SM501_GPIO_DATA_HIGH (0x04) | |
190 | #define SM501_GPIO_DDR_LOW (0x08) | |
191 | #define SM501_GPIO_DDR_HIGH (0x0C) | |
192 | #define SM501_GPIO_IRQ_SETUP (0x10) | |
193 | #define SM501_GPIO_IRQ_STATUS (0x14) | |
194 | #define SM501_GPIO_IRQ_RESET (0x14) | |
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195 | |
196 | /* I2C controller base */ | |
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197 | #define SM501_I2C (0x010040) |
198 | #define SM501_I2C_BYTE_COUNT (0x00) | |
199 | #define SM501_I2C_CONTROL (0x01) | |
200 | #define SM501_I2C_STATUS (0x02) | |
201 | #define SM501_I2C_RESET (0x02) | |
202 | #define SM501_I2C_SLAVE_ADDRESS (0x03) | |
203 | #define SM501_I2C_DATA (0x04) | |
ffd39257 | 204 | |
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205 | #define SM501_I2C_CONTROL_START (1 << 2) |
206 | #define SM501_I2C_CONTROL_ENABLE (1 << 0) | |
207 | ||
208 | #define SM501_I2C_STATUS_COMPLETE (1 << 3) | |
209 | #define SM501_I2C_STATUS_ERROR (1 << 2) | |
210 | ||
211 | #define SM501_I2C_RESET_ERROR (1 << 2) | |
212 | ||
ffd39257 | 213 | /* SSP base */ |
64f1603b | 214 | #define SM501_SSP (0x020000) |
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215 | |
216 | /* Uart 0 base */ | |
64f1603b | 217 | #define SM501_UART0 (0x030000) |
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218 | |
219 | /* Uart 1 base */ | |
64f1603b | 220 | #define SM501_UART1 (0x030020) |
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221 | |
222 | /* USB host port base */ | |
64f1603b | 223 | #define SM501_USB_HOST (0x040000) |
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224 | |
225 | /* USB slave/gadget base */ | |
64f1603b | 226 | #define SM501_USB_GADGET (0x060000) |
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227 | |
228 | /* USB slave/gadget data port base */ | |
64f1603b | 229 | #define SM501_USB_GADGET_DATA (0x070000) |
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230 | |
231 | /* Display controller/video engine base */ | |
64f1603b | 232 | #define SM501_DC (0x080000) |
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233 | |
234 | /* common defines for the SM501 address registers */ | |
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235 | #define SM501_ADDR_FLIP (1 << 31) |
236 | #define SM501_ADDR_EXT (1 << 27) | |
237 | #define SM501_ADDR_CS1 (1 << 26) | |
238 | #define SM501_ADDR_MASK (0x3f << 26) | |
ffd39257 | 239 | |
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240 | #define SM501_FIFO_MASK (0x3 << 16) |
241 | #define SM501_FIFO_1 (0x0 << 16) | |
242 | #define SM501_FIFO_3 (0x1 << 16) | |
243 | #define SM501_FIFO_7 (0x2 << 16) | |
244 | #define SM501_FIFO_11 (0x3 << 16) | |
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245 | |
246 | /* common registers for panel and the crt */ | |
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247 | #define SM501_OFF_DC_H_TOT (0x000) |
248 | #define SM501_OFF_DC_V_TOT (0x008) | |
249 | #define SM501_OFF_DC_H_SYNC (0x004) | |
250 | #define SM501_OFF_DC_V_SYNC (0x00C) | |
251 | ||
252 | #define SM501_DC_PANEL_CONTROL (0x000) | |
253 | ||
254 | #define SM501_DC_PANEL_CONTROL_FPEN (1 << 27) | |
255 | #define SM501_DC_PANEL_CONTROL_BIAS (1 << 26) | |
256 | #define SM501_DC_PANEL_CONTROL_DATA (1 << 25) | |
257 | #define SM501_DC_PANEL_CONTROL_VDD (1 << 24) | |
258 | #define SM501_DC_PANEL_CONTROL_DP (1 << 23) | |
259 | ||
260 | #define SM501_DC_PANEL_CONTROL_TFT_888 (0 << 21) | |
261 | #define SM501_DC_PANEL_CONTROL_TFT_333 (1 << 21) | |
262 | #define SM501_DC_PANEL_CONTROL_TFT_444 (2 << 21) | |
263 | ||
264 | #define SM501_DC_PANEL_CONTROL_DE (1 << 20) | |
265 | ||
266 | #define SM501_DC_PANEL_CONTROL_LCD_TFT (0 << 18) | |
267 | #define SM501_DC_PANEL_CONTROL_LCD_STN8 (1 << 18) | |
268 | #define SM501_DC_PANEL_CONTROL_LCD_STN12 (2 << 18) | |
269 | ||
270 | #define SM501_DC_PANEL_CONTROL_CP (1 << 14) | |
271 | #define SM501_DC_PANEL_CONTROL_VSP (1 << 13) | |
272 | #define SM501_DC_PANEL_CONTROL_HSP (1 << 12) | |
273 | #define SM501_DC_PANEL_CONTROL_CK (1 << 9) | |
274 | #define SM501_DC_PANEL_CONTROL_TE (1 << 8) | |
275 | #define SM501_DC_PANEL_CONTROL_VPD (1 << 7) | |
276 | #define SM501_DC_PANEL_CONTROL_VP (1 << 6) | |
277 | #define SM501_DC_PANEL_CONTROL_HPD (1 << 5) | |
278 | #define SM501_DC_PANEL_CONTROL_HP (1 << 4) | |
279 | #define SM501_DC_PANEL_CONTROL_GAMMA (1 << 3) | |
280 | #define SM501_DC_PANEL_CONTROL_EN (1 << 2) | |
281 | ||
282 | #define SM501_DC_PANEL_CONTROL_8BPP (0 << 0) | |
283 | #define SM501_DC_PANEL_CONTROL_16BPP (1 << 0) | |
284 | #define SM501_DC_PANEL_CONTROL_32BPP (2 << 0) | |
285 | ||
286 | ||
287 | #define SM501_DC_PANEL_PANNING_CONTROL (0x004) | |
288 | #define SM501_DC_PANEL_COLOR_KEY (0x008) | |
289 | #define SM501_DC_PANEL_FB_ADDR (0x00C) | |
290 | #define SM501_DC_PANEL_FB_OFFSET (0x010) | |
291 | #define SM501_DC_PANEL_FB_WIDTH (0x014) | |
292 | #define SM501_DC_PANEL_FB_HEIGHT (0x018) | |
293 | #define SM501_DC_PANEL_TL_LOC (0x01C) | |
294 | #define SM501_DC_PANEL_BR_LOC (0x020) | |
295 | #define SM501_DC_PANEL_H_TOT (0x024) | |
296 | #define SM501_DC_PANEL_H_SYNC (0x028) | |
297 | #define SM501_DC_PANEL_V_TOT (0x02C) | |
298 | #define SM501_DC_PANEL_V_SYNC (0x030) | |
299 | #define SM501_DC_PANEL_CUR_LINE (0x034) | |
300 | ||
301 | #define SM501_DC_VIDEO_CONTROL (0x040) | |
302 | #define SM501_DC_VIDEO_FB0_ADDR (0x044) | |
303 | #define SM501_DC_VIDEO_FB_WIDTH (0x048) | |
304 | #define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C) | |
305 | #define SM501_DC_VIDEO_TL_LOC (0x050) | |
306 | #define SM501_DC_VIDEO_BR_LOC (0x054) | |
307 | #define SM501_DC_VIDEO_SCALE (0x058) | |
308 | #define SM501_DC_VIDEO_INIT_SCALE (0x05C) | |
309 | #define SM501_DC_VIDEO_YUV_CONSTANTS (0x060) | |
310 | #define SM501_DC_VIDEO_FB1_ADDR (0x064) | |
311 | #define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068) | |
312 | ||
313 | #define SM501_DC_VIDEO_ALPHA_CONTROL (0x080) | |
314 | #define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084) | |
315 | #define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088) | |
316 | #define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C) | |
317 | #define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090) | |
318 | #define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094) | |
319 | #define SM501_DC_VIDEO_ALPHA_SCALE (0x098) | |
320 | #define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C) | |
321 | #define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0) | |
322 | #define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4) | |
323 | ||
324 | #define SM501_DC_PANEL_HWC_BASE (0x0F0) | |
325 | #define SM501_DC_PANEL_HWC_ADDR (0x0F0) | |
326 | #define SM501_DC_PANEL_HWC_LOC (0x0F4) | |
327 | #define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8) | |
328 | #define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC) | |
329 | ||
330 | #define SM501_HWC_EN (1 << 31) | |
331 | ||
332 | #define SM501_OFF_HWC_ADDR (0x00) | |
333 | #define SM501_OFF_HWC_LOC (0x04) | |
334 | #define SM501_OFF_HWC_COLOR_1_2 (0x08) | |
335 | #define SM501_OFF_HWC_COLOR_3 (0x0C) | |
336 | ||
337 | #define SM501_DC_ALPHA_CONTROL (0x100) | |
338 | #define SM501_DC_ALPHA_FB_ADDR (0x104) | |
339 | #define SM501_DC_ALPHA_FB_OFFSET (0x108) | |
340 | #define SM501_DC_ALPHA_TL_LOC (0x10C) | |
341 | #define SM501_DC_ALPHA_BR_LOC (0x110) | |
342 | #define SM501_DC_ALPHA_CHROMA_KEY (0x114) | |
343 | #define SM501_DC_ALPHA_COLOR_LOOKUP (0x118) | |
344 | ||
345 | #define SM501_DC_CRT_CONTROL (0x200) | |
346 | ||
347 | #define SM501_DC_CRT_CONTROL_TVP (1 << 15) | |
348 | #define SM501_DC_CRT_CONTROL_CP (1 << 14) | |
349 | #define SM501_DC_CRT_CONTROL_VSP (1 << 13) | |
350 | #define SM501_DC_CRT_CONTROL_HSP (1 << 12) | |
351 | #define SM501_DC_CRT_CONTROL_VS (1 << 11) | |
352 | #define SM501_DC_CRT_CONTROL_BLANK (1 << 10) | |
353 | #define SM501_DC_CRT_CONTROL_SEL (1 << 9) | |
354 | #define SM501_DC_CRT_CONTROL_TE (1 << 8) | |
ffd39257 | 355 | #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4) |
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356 | #define SM501_DC_CRT_CONTROL_GAMMA (1 << 3) |
357 | #define SM501_DC_CRT_CONTROL_ENABLE (1 << 2) | |
ffd39257 | 358 | |
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359 | #define SM501_DC_CRT_CONTROL_8BPP (0 << 0) |
360 | #define SM501_DC_CRT_CONTROL_16BPP (1 << 0) | |
361 | #define SM501_DC_CRT_CONTROL_32BPP (2 << 0) | |
ffd39257 | 362 | |
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363 | #define SM501_DC_CRT_FB_ADDR (0x204) |
364 | #define SM501_DC_CRT_FB_OFFSET (0x208) | |
365 | #define SM501_DC_CRT_H_TOT (0x20C) | |
366 | #define SM501_DC_CRT_H_SYNC (0x210) | |
367 | #define SM501_DC_CRT_V_TOT (0x214) | |
368 | #define SM501_DC_CRT_V_SYNC (0x218) | |
369 | #define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C) | |
370 | #define SM501_DC_CRT_CUR_LINE (0x220) | |
371 | #define SM501_DC_CRT_MONITOR_DETECT (0x224) | |
ffd39257 | 372 | |
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373 | #define SM501_DC_CRT_HWC_BASE (0x230) |
374 | #define SM501_DC_CRT_HWC_ADDR (0x230) | |
375 | #define SM501_DC_CRT_HWC_LOC (0x234) | |
376 | #define SM501_DC_CRT_HWC_COLOR_1_2 (0x238) | |
377 | #define SM501_DC_CRT_HWC_COLOR_3 (0x23C) | |
ffd39257 | 378 | |
64f1603b | 379 | #define SM501_DC_PANEL_PALETTE (0x400) |
ffd39257 | 380 | |
64f1603b | 381 | #define SM501_DC_VIDEO_PALETTE (0x800) |
ffd39257 | 382 | |
64f1603b | 383 | #define SM501_DC_CRT_PALETTE (0xC00) |
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384 | |
385 | /* Zoom Video port base */ | |
64f1603b | 386 | #define SM501_ZVPORT (0x090000) |
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387 | |
388 | /* AC97/I2S base */ | |
64f1603b | 389 | #define SM501_AC97 (0x0A0000) |
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390 | |
391 | /* 8051 micro controller base */ | |
64f1603b | 392 | #define SM501_UCONTROLLER (0x0B0000) |
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393 | |
394 | /* 8051 micro controller SRAM base */ | |
64f1603b | 395 | #define SM501_UCONTROLLER_SRAM (0x0C0000) |
ffd39257 BS |
396 | |
397 | /* DMA base */ | |
64f1603b | 398 | #define SM501_DMA (0x0D0000) |
ffd39257 BS |
399 | |
400 | /* 2d engine base */ | |
64f1603b BZ |
401 | #define SM501_2D_ENGINE (0x100000) |
402 | #define SM501_2D_SOURCE (0x00) | |
403 | #define SM501_2D_DESTINATION (0x04) | |
404 | #define SM501_2D_DIMENSION (0x08) | |
405 | #define SM501_2D_CONTROL (0x0C) | |
406 | #define SM501_2D_PITCH (0x10) | |
407 | #define SM501_2D_FOREGROUND (0x14) | |
408 | #define SM501_2D_BACKGROUND (0x18) | |
409 | #define SM501_2D_STRETCH (0x1C) | |
410 | #define SM501_2D_COLOR_COMPARE (0x20) | |
411 | #define SM501_2D_COLOR_COMPARE_MASK (0x24) | |
412 | #define SM501_2D_MASK (0x28) | |
413 | #define SM501_2D_CLIP_TL (0x2C) | |
414 | #define SM501_2D_CLIP_BR (0x30) | |
415 | #define SM501_2D_MONO_PATTERN_LOW (0x34) | |
416 | #define SM501_2D_MONO_PATTERN_HIGH (0x38) | |
417 | #define SM501_2D_WINDOW_WIDTH (0x3C) | |
418 | #define SM501_2D_SOURCE_BASE (0x40) | |
419 | #define SM501_2D_DESTINATION_BASE (0x44) | |
420 | #define SM501_2D_ALPHA (0x48) | |
421 | #define SM501_2D_WRAP (0x4C) | |
422 | #define SM501_2D_STATUS (0x50) | |
423 | ||
424 | #define SM501_CSC_Y_SOURCE_BASE (0xC8) | |
425 | #define SM501_CSC_CONSTANTS (0xCC) | |
426 | #define SM501_CSC_Y_SOURCE_X (0xD0) | |
427 | #define SM501_CSC_Y_SOURCE_Y (0xD4) | |
428 | #define SM501_CSC_U_SOURCE_BASE (0xD8) | |
429 | #define SM501_CSC_V_SOURCE_BASE (0xDC) | |
430 | #define SM501_CSC_SOURCE_DIMENSION (0xE0) | |
431 | #define SM501_CSC_SOURCE_PITCH (0xE4) | |
432 | #define SM501_CSC_DESTINATION (0xE8) | |
433 | #define SM501_CSC_DESTINATION_DIMENSION (0xEC) | |
434 | #define SM501_CSC_DESTINATION_PITCH (0xF0) | |
435 | #define SM501_CSC_SCALE_FACTOR (0xF4) | |
436 | #define SM501_CSC_DESTINATION_BASE (0xF8) | |
437 | #define SM501_CSC_CONTROL (0xFC) | |
ffd39257 BS |
438 | |
439 | /* 2d engine data port base */ | |
64f1603b | 440 | #define SM501_2D_ENGINE_DATA (0x110000) |
ffd39257 BS |
441 | |
442 | /* end of register definitions */ | |
443 | ||
0a4e7cd2 SK |
444 | #define SM501_HWC_WIDTH (64) |
445 | #define SM501_HWC_HEIGHT (64) | |
ffd39257 BS |
446 | |
447 | /* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */ | |
448 | static const uint32_t sm501_mem_local_size[] = { | |
d23b6caa PMD |
449 | [0] = 4 * MiB, |
450 | [1] = 8 * MiB, | |
451 | [2] = 16 * MiB, | |
452 | [3] = 32 * MiB, | |
453 | [4] = 64 * MiB, | |
454 | [5] = 2 * MiB, | |
ffd39257 BS |
455 | }; |
456 | #define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index] | |
457 | ||
458 | typedef struct SM501State { | |
459 | /* graphic console status */ | |
c78f7137 | 460 | QemuConsole *con; |
ffd39257 BS |
461 | |
462 | /* status & internal resources */ | |
ffd39257 | 463 | uint32_t local_mem_size_index; |
64f1603b | 464 | uint8_t *local_mem; |
25793bfa | 465 | MemoryRegion local_mem_region; |
ca8a1104 BZ |
466 | MemoryRegion mmio_region; |
467 | MemoryRegion system_config_region; | |
4a1f253a | 468 | MemoryRegion i2c_region; |
ca8a1104 BZ |
469 | MemoryRegion disp_ctrl_region; |
470 | MemoryRegion twoD_engine_region; | |
ffd39257 BS |
471 | uint32_t last_width; |
472 | uint32_t last_height; | |
d2733559 | 473 | bool do_full_update; /* perform a full update next time */ |
4a1f253a | 474 | I2CBus *i2c_bus; |
ffd39257 BS |
475 | |
476 | /* mmio registers */ | |
477 | uint32_t system_control; | |
478 | uint32_t misc_control; | |
479 | uint32_t gpio_31_0_control; | |
480 | uint32_t gpio_63_32_control; | |
481 | uint32_t dram_control; | |
70e46ca8 | 482 | uint32_t arbitration_control; |
ffd39257 BS |
483 | uint32_t irq_mask; |
484 | uint32_t misc_timing; | |
485 | uint32_t power_mode_control; | |
486 | ||
4a1f253a BZ |
487 | uint8_t i2c_byte_count; |
488 | uint8_t i2c_status; | |
489 | uint8_t i2c_addr; | |
490 | uint8_t i2c_data[16]; | |
491 | ||
ffd39257 BS |
492 | uint32_t uart0_ier; |
493 | uint32_t uart0_lcr; | |
494 | uint32_t uart0_mcr; | |
495 | uint32_t uart0_scr; | |
496 | ||
2edd6e4a | 497 | uint8_t dc_palette[DC_PALETTE_ENTRIES]; |
ffd39257 BS |
498 | |
499 | uint32_t dc_panel_control; | |
500 | uint32_t dc_panel_panning_control; | |
501 | uint32_t dc_panel_fb_addr; | |
502 | uint32_t dc_panel_fb_offset; | |
503 | uint32_t dc_panel_fb_width; | |
504 | uint32_t dc_panel_fb_height; | |
505 | uint32_t dc_panel_tl_location; | |
506 | uint32_t dc_panel_br_location; | |
507 | uint32_t dc_panel_h_total; | |
508 | uint32_t dc_panel_h_sync; | |
509 | uint32_t dc_panel_v_total; | |
510 | uint32_t dc_panel_v_sync; | |
511 | ||
512 | uint32_t dc_panel_hwc_addr; | |
513 | uint32_t dc_panel_hwc_location; | |
514 | uint32_t dc_panel_hwc_color_1_2; | |
515 | uint32_t dc_panel_hwc_color_3; | |
516 | ||
b612a49d BZ |
517 | uint32_t dc_video_control; |
518 | ||
ffd39257 BS |
519 | uint32_t dc_crt_control; |
520 | uint32_t dc_crt_fb_addr; | |
521 | uint32_t dc_crt_fb_offset; | |
522 | uint32_t dc_crt_h_total; | |
523 | uint32_t dc_crt_h_sync; | |
524 | uint32_t dc_crt_v_total; | |
525 | uint32_t dc_crt_v_sync; | |
526 | ||
527 | uint32_t dc_crt_hwc_addr; | |
528 | uint32_t dc_crt_hwc_location; | |
529 | uint32_t dc_crt_hwc_color_1_2; | |
530 | uint32_t dc_crt_hwc_color_3; | |
531 | ||
07d8a50c | 532 | uint32_t twoD_source; |
604be200 SK |
533 | uint32_t twoD_destination; |
534 | uint32_t twoD_dimension; | |
535 | uint32_t twoD_control; | |
536 | uint32_t twoD_pitch; | |
537 | uint32_t twoD_foreground; | |
b612a49d | 538 | uint32_t twoD_background; |
604be200 | 539 | uint32_t twoD_stretch; |
b612a49d | 540 | uint32_t twoD_color_compare; |
604be200 SK |
541 | uint32_t twoD_color_compare_mask; |
542 | uint32_t twoD_mask; | |
b612a49d BZ |
543 | uint32_t twoD_clip_tl; |
544 | uint32_t twoD_clip_br; | |
545 | uint32_t twoD_mono_pattern_low; | |
546 | uint32_t twoD_mono_pattern_high; | |
604be200 SK |
547 | uint32_t twoD_window_width; |
548 | uint32_t twoD_source_base; | |
549 | uint32_t twoD_destination_base; | |
b612a49d BZ |
550 | uint32_t twoD_alpha; |
551 | uint32_t twoD_wrap; | |
ffd39257 BS |
552 | } SM501State; |
553 | ||
554 | static uint32_t get_local_mem_size_index(uint32_t size) | |
555 | { | |
556 | uint32_t norm_size = 0; | |
557 | int i, index = 0; | |
558 | ||
b1503cda | 559 | for (i = 0; i < ARRAY_SIZE(sm501_mem_local_size); i++) { |
64f1603b BZ |
560 | uint32_t new_size = sm501_mem_local_size[i]; |
561 | if (new_size >= size) { | |
562 | if (norm_size == 0 || norm_size > new_size) { | |
563 | norm_size = new_size; | |
564 | index = i; | |
565 | } | |
566 | } | |
ffd39257 BS |
567 | } |
568 | ||
569 | return index; | |
570 | } | |
571 | ||
33159dd7 BZ |
572 | static ram_addr_t get_fb_addr(SM501State *s, int crt) |
573 | { | |
574 | return (crt ? s->dc_crt_fb_addr : s->dc_panel_fb_addr) & 0x3FFFFF0; | |
575 | } | |
576 | ||
6a2a5aae BZ |
577 | static inline int get_width(SM501State *s, int crt) |
578 | { | |
579 | int width = crt ? s->dc_crt_h_total : s->dc_panel_h_total; | |
580 | return (width & 0x00000FFF) + 1; | |
581 | } | |
582 | ||
583 | static inline int get_height(SM501State *s, int crt) | |
584 | { | |
585 | int height = crt ? s->dc_crt_v_total : s->dc_panel_v_total; | |
586 | return (height & 0x00000FFF) + 1; | |
587 | } | |
588 | ||
589 | static inline int get_bpp(SM501State *s, int crt) | |
590 | { | |
591 | int bpp = crt ? s->dc_crt_control : s->dc_panel_control; | |
592 | return 1 << (bpp & 3); | |
593 | } | |
594 | ||
0a4e7cd2 SK |
595 | /** |
596 | * Check the availability of hardware cursor. | |
597 | * @param crt 0 for PANEL, 1 for CRT. | |
598 | */ | |
599 | static inline int is_hwc_enabled(SM501State *state, int crt) | |
600 | { | |
601 | uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr; | |
e2ee8476 | 602 | return addr & SM501_HWC_EN; |
0a4e7cd2 SK |
603 | } |
604 | ||
605 | /** | |
606 | * Get the address which holds cursor pattern data. | |
607 | * @param crt 0 for PANEL, 1 for CRT. | |
608 | */ | |
6a2a5aae | 609 | static inline uint8_t *get_hwc_address(SM501State *state, int crt) |
0a4e7cd2 SK |
610 | { |
611 | uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr; | |
6a2a5aae | 612 | return state->local_mem + (addr & 0x03FFFFF0); |
0a4e7cd2 SK |
613 | } |
614 | ||
615 | /** | |
616 | * Get the cursor position in y coordinate. | |
617 | * @param crt 0 for PANEL, 1 for CRT. | |
618 | */ | |
619 | static inline uint32_t get_hwc_y(SM501State *state, int crt) | |
620 | { | |
621 | uint32_t location = crt ? state->dc_crt_hwc_location | |
622 | : state->dc_panel_hwc_location; | |
623 | return (location & 0x07FF0000) >> 16; | |
624 | } | |
625 | ||
626 | /** | |
627 | * Get the cursor position in x coordinate. | |
628 | * @param crt 0 for PANEL, 1 for CRT. | |
629 | */ | |
630 | static inline uint32_t get_hwc_x(SM501State *state, int crt) | |
631 | { | |
632 | uint32_t location = crt ? state->dc_crt_hwc_location | |
633 | : state->dc_panel_hwc_location; | |
634 | return location & 0x000007FF; | |
635 | } | |
636 | ||
637 | /** | |
6a2a5aae | 638 | * Get the hardware cursor palette. |
0a4e7cd2 | 639 | * @param crt 0 for PANEL, 1 for CRT. |
6a2a5aae | 640 | * @param palette pointer to a [3 * 3] array to store color values in |
0a4e7cd2 | 641 | */ |
6a2a5aae | 642 | static inline void get_hwc_palette(SM501State *state, int crt, uint8_t *palette) |
0a4e7cd2 | 643 | { |
6a2a5aae BZ |
644 | int i; |
645 | uint32_t color_reg; | |
646 | uint16_t rgb565; | |
647 | ||
648 | for (i = 0; i < 3; i++) { | |
649 | if (i + 1 == 3) { | |
650 | color_reg = crt ? state->dc_crt_hwc_color_3 | |
651 | : state->dc_panel_hwc_color_3; | |
652 | } else { | |
653 | color_reg = crt ? state->dc_crt_hwc_color_1_2 | |
654 | : state->dc_panel_hwc_color_1_2; | |
655 | } | |
0a4e7cd2 | 656 | |
6a2a5aae BZ |
657 | if (i + 1 == 2) { |
658 | rgb565 = (color_reg >> 16) & 0xFFFF; | |
659 | } else { | |
660 | rgb565 = color_reg & 0xFFFF; | |
661 | } | |
a69232e2 SB |
662 | palette[i * 3 + 0] = ((rgb565 >> 11) * 527 + 23) >> 6; /* r */ |
663 | palette[i * 3 + 1] = (((rgb565 >> 5) & 0x3f) * 259 + 33) >> 6; /* g */ | |
664 | palette[i * 3 + 2] = ((rgb565 & 0x1f) * 527 + 23) >> 6; /* b */ | |
0a4e7cd2 | 665 | } |
0a4e7cd2 SK |
666 | } |
667 | ||
6a2a5aae | 668 | static inline void hwc_invalidate(SM501State *s, int crt) |
0a4e7cd2 | 669 | { |
6a2a5aae BZ |
670 | int w = get_width(s, crt); |
671 | int h = get_height(s, crt); | |
672 | int bpp = get_bpp(s, crt); | |
673 | int start = get_hwc_y(s, crt); | |
674 | int end = MIN(h, start + SM501_HWC_HEIGHT) + 1; | |
675 | ||
676 | start *= w * bpp; | |
677 | end *= w * bpp; | |
678 | ||
33159dd7 BZ |
679 | memory_region_set_dirty(&s->local_mem_region, |
680 | get_fb_addr(s, crt) + start, end - start); | |
0a4e7cd2 SK |
681 | } |
682 | ||
64f1603b | 683 | static void sm501_2d_operation(SM501State *s) |
604be200 | 684 | { |
6f8183b5 | 685 | int cmd = (s->twoD_control >> 16) & 0x1F; |
2824809b | 686 | int rtl = s->twoD_control & BIT(27); |
6f8183b5 | 687 | int format = (s->twoD_stretch >> 20) & 0x3; |
debc7e7d | 688 | int rop_mode = (s->twoD_control >> 15) & 0x1; /* 1 for rop2, else rop3 */ |
06cb926a SB |
689 | /* 1 if rop2 source is the pattern, otherwise the source is the bitmap */ |
690 | int rop2_source_is_pattern = (s->twoD_control >> 14) & 0x1; | |
debc7e7d | 691 | int rop = s->twoD_control & 0xFF; |
b15a22bb BZ |
692 | unsigned int dst_x = (s->twoD_destination >> 16) & 0x01FFF; |
693 | unsigned int dst_y = s->twoD_destination & 0xFFFF; | |
694 | unsigned int width = (s->twoD_dimension >> 16) & 0x1FFF; | |
695 | unsigned int height = s->twoD_dimension & 0xFFFF; | |
eb76243c | 696 | uint32_t dst_base = s->twoD_destination_base & 0x03FFFFFF; |
b15a22bb | 697 | unsigned int dst_pitch = (s->twoD_pitch >> 16) & 0x1FFF; |
eb76243c BZ |
698 | int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0; |
699 | int fb_len = get_width(s, crt) * get_height(s, crt) * get_bpp(s, crt); | |
604be200 | 700 | |
6f8183b5 | 701 | if ((s->twoD_stretch >> 16) & 0xF) { |
e29da77e BZ |
702 | qemu_log_mask(LOG_UNIMP, "sm501: only XY addressing is supported.\n"); |
703 | return; | |
604be200 SK |
704 | } |
705 | ||
2824809b | 706 | if (s->twoD_source_base & BIT(27) || s->twoD_destination_base & BIT(27)) { |
e29da77e BZ |
707 | qemu_log_mask(LOG_UNIMP, "sm501: only local memory is supported.\n"); |
708 | return; | |
604be200 SK |
709 | } |
710 | ||
b15a22bb BZ |
711 | if (!dst_pitch) { |
712 | qemu_log_mask(LOG_GUEST_ERROR, "sm501: Zero dest pitch.\n"); | |
713 | return; | |
714 | } | |
715 | ||
716 | if (!width || !height) { | |
717 | qemu_log_mask(LOG_GUEST_ERROR, "sm501: Zero size 2D op.\n"); | |
718 | return; | |
719 | } | |
720 | ||
721 | if (rtl) { | |
722 | dst_x -= width - 1; | |
723 | dst_y -= height - 1; | |
724 | } | |
725 | ||
84ec3f94 BZ |
726 | if (dst_base >= get_local_mem_size(s) || |
727 | dst_base + (dst_x + width + (dst_y + height) * dst_pitch) * | |
b15a22bb BZ |
728 | (1 << format) >= get_local_mem_size(s)) { |
729 | qemu_log_mask(LOG_GUEST_ERROR, "sm501: 2D op dest is outside vram.\n"); | |
730 | return; | |
731 | } | |
732 | ||
6f8183b5 | 733 | switch (cmd) { |
b15a22bb | 734 | case 0: /* BitBlt */ |
3d0b0962 | 735 | { |
fa70c287 | 736 | static uint32_t tmp_buf[16384]; |
b15a22bb BZ |
737 | unsigned int src_x = (s->twoD_source >> 16) & 0x01FFF; |
738 | unsigned int src_y = s->twoD_source & 0xFFFF; | |
3d0b0962 | 739 | uint32_t src_base = s->twoD_source_base & 0x03FFFFFF; |
b15a22bb BZ |
740 | unsigned int src_pitch = s->twoD_pitch & 0x1FFF; |
741 | ||
742 | if (!src_pitch) { | |
743 | qemu_log_mask(LOG_GUEST_ERROR, "sm501: Zero src pitch.\n"); | |
744 | return; | |
745 | } | |
746 | ||
747 | if (rtl) { | |
748 | src_x -= width - 1; | |
749 | src_y -= height - 1; | |
750 | } | |
751 | ||
84ec3f94 BZ |
752 | if (src_base >= get_local_mem_size(s) || |
753 | src_base + (src_x + width + (src_y + height) * src_pitch) * | |
b15a22bb BZ |
754 | (1 << format) >= get_local_mem_size(s)) { |
755 | qemu_log_mask(LOG_GUEST_ERROR, | |
756 | "sm501: 2D op src is outside vram.\n"); | |
757 | return; | |
758 | } | |
759 | ||
760 | if ((rop_mode && rop == 0x5) || (!rop_mode && rop == 0x55)) { | |
761 | /* Invert dest, is there a way to do this with pixman? */ | |
762 | unsigned int x, y, i; | |
763 | uint8_t *d = s->local_mem + dst_base; | |
764 | ||
765 | for (y = 0; y < height; y++) { | |
766 | i = (dst_x + (dst_y + y) * dst_pitch) * (1 << format); | |
767 | for (x = 0; x < width; x++, i += (1 << format)) { | |
768 | switch (format) { | |
769 | case 0: | |
770 | d[i] = ~d[i]; | |
771 | break; | |
772 | case 1: | |
773 | *(uint16_t *)&d[i] = ~*(uint16_t *)&d[i]; | |
774 | break; | |
775 | case 2: | |
776 | *(uint32_t *)&d[i] = ~*(uint32_t *)&d[i]; | |
777 | break; | |
778 | } | |
779 | } | |
780 | } | |
781 | } else { | |
782 | /* Do copy src for unimplemented ops, better than unpainted area */ | |
783 | if ((rop_mode && (rop != 0xc || rop2_source_is_pattern)) || | |
784 | (!rop_mode && rop != 0xcc)) { | |
785 | qemu_log_mask(LOG_UNIMP, | |
786 | "sm501: rop%d op %x%s not implemented\n", | |
787 | (rop_mode ? 2 : 3), rop, | |
788 | (rop2_source_is_pattern ? | |
789 | " with pattern source" : "")); | |
790 | } | |
791 | /* Check for overlaps, this could be made more exact */ | |
792 | uint32_t sb, se, db, de; | |
793 | sb = src_base + src_x + src_y * (width + src_pitch); | |
794 | se = sb + width + height * (width + src_pitch); | |
795 | db = dst_base + dst_x + dst_y * (width + dst_pitch); | |
796 | de = db + width + height * (width + dst_pitch); | |
797 | if (rtl && ((db >= sb && db <= se) || (de >= sb && de <= se))) { | |
798 | /* regions may overlap: copy via temporary */ | |
4decaad9 | 799 | int llb = width * (1 << format); |
b15a22bb | 800 | int tmp_stride = DIV_ROUND_UP(llb, sizeof(uint32_t)); |
fa70c287 BZ |
801 | uint32_t *tmp = tmp_buf; |
802 | ||
803 | if (tmp_stride * sizeof(uint32_t) * height > sizeof(tmp_buf)) { | |
804 | tmp = g_malloc(tmp_stride * sizeof(uint32_t) * height); | |
fa70c287 | 805 | } |
b15a22bb BZ |
806 | pixman_blt((uint32_t *)&s->local_mem[src_base], tmp, |
807 | src_pitch * (1 << format) / sizeof(uint32_t), | |
808 | tmp_stride, 8 * (1 << format), 8 * (1 << format), | |
809 | src_x, src_y, 0, 0, width, height); | |
810 | pixman_blt(tmp, (uint32_t *)&s->local_mem[dst_base], | |
811 | tmp_stride, | |
812 | dst_pitch * (1 << format) / sizeof(uint32_t), | |
813 | 8 * (1 << format), 8 * (1 << format), | |
814 | 0, 0, dst_x, dst_y, width, height); | |
4decaad9 | 815 | if (tmp != tmp_buf) { |
fa70c287 BZ |
816 | g_free(tmp); |
817 | } | |
b15a22bb BZ |
818 | } else { |
819 | pixman_blt((uint32_t *)&s->local_mem[src_base], | |
820 | (uint32_t *)&s->local_mem[dst_base], | |
821 | src_pitch * (1 << format) / sizeof(uint32_t), | |
822 | dst_pitch * (1 << format) / sizeof(uint32_t), | |
823 | 8 * (1 << format), 8 * (1 << format), | |
824 | src_x, src_y, dst_x, dst_y, width, height); | |
825 | } | |
07d8a50c AJ |
826 | } |
827 | break; | |
3d0b0962 | 828 | } |
b15a22bb | 829 | case 1: /* Rectangle Fill */ |
3d0b0962 BZ |
830 | { |
831 | uint32_t color = s->twoD_foreground; | |
832 | ||
b15a22bb | 833 | if (format == 2) { |
f3a60058 | 834 | color = cpu_to_le32(color); |
b15a22bb BZ |
835 | } else if (format == 1) { |
836 | color = cpu_to_le16(color); | |
604be200 | 837 | } |
b15a22bb BZ |
838 | |
839 | pixman_fill((uint32_t *)&s->local_mem[dst_base], | |
840 | dst_pitch * (1 << format) / sizeof(uint32_t), | |
841 | 8 * (1 << format), dst_x, dst_y, width, height, color); | |
604be200 | 842 | break; |
3d0b0962 | 843 | } |
604be200 | 844 | default: |
e29da77e | 845 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented 2D operation: %d\n", |
6f8183b5 | 846 | cmd); |
e29da77e | 847 | return; |
604be200 | 848 | } |
eb76243c BZ |
849 | |
850 | if (dst_base >= get_fb_addr(s, crt) && | |
851 | dst_base <= get_fb_addr(s, crt) + fb_len) { | |
6f8183b5 BZ |
852 | int dst_len = MIN(fb_len, ((dst_y + height - 1) * dst_pitch + |
853 | dst_x + width) * (1 << format)); | |
eb76243c BZ |
854 | if (dst_len) { |
855 | memory_region_set_dirty(&s->local_mem_region, dst_base, dst_len); | |
856 | } | |
857 | } | |
604be200 SK |
858 | } |
859 | ||
a8170e5e | 860 | static uint64_t sm501_system_config_read(void *opaque, hwaddr addr, |
25793bfa | 861 | unsigned size) |
ffd39257 | 862 | { |
64f1603b | 863 | SM501State *s = (SM501State *)opaque; |
ffd39257 | 864 | uint32_t ret = 0; |
8da3ff18 | 865 | SM501_DPRINTF("sm501 system config regs : read addr=%x\n", (int)addr); |
ffd39257 | 866 | |
64f1603b | 867 | switch (addr) { |
ffd39257 | 868 | case SM501_SYSTEM_CONTROL: |
64f1603b BZ |
869 | ret = s->system_control; |
870 | break; | |
ffd39257 | 871 | case SM501_MISC_CONTROL: |
64f1603b BZ |
872 | ret = s->misc_control; |
873 | break; | |
ffd39257 | 874 | case SM501_GPIO31_0_CONTROL: |
64f1603b BZ |
875 | ret = s->gpio_31_0_control; |
876 | break; | |
ffd39257 | 877 | case SM501_GPIO63_32_CONTROL: |
64f1603b BZ |
878 | ret = s->gpio_63_32_control; |
879 | break; | |
ffd39257 | 880 | case SM501_DEVICEID: |
64f1603b BZ |
881 | ret = 0x050100A0; |
882 | break; | |
ffd39257 | 883 | case SM501_DRAM_CONTROL: |
64f1603b BZ |
884 | ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13; |
885 | break; | |
70e46ca8 BZ |
886 | case SM501_ARBTRTN_CONTROL: |
887 | ret = s->arbitration_control; | |
888 | break; | |
5690d9ec BZ |
889 | case SM501_COMMAND_LIST_STATUS: |
890 | ret = 0x00180002; /* FIFOs are empty, everything idle */ | |
cf4969ec | 891 | break; |
ffd39257 | 892 | case SM501_IRQ_MASK: |
64f1603b BZ |
893 | ret = s->irq_mask; |
894 | break; | |
ffd39257 | 895 | case SM501_MISC_TIMING: |
64f1603b BZ |
896 | /* TODO : simulate gate control */ |
897 | ret = s->misc_timing; | |
898 | break; | |
ffd39257 | 899 | case SM501_CURRENT_GATE: |
64f1603b BZ |
900 | /* TODO : simulate gate control */ |
901 | ret = 0x00021807; | |
902 | break; | |
ffd39257 | 903 | case SM501_CURRENT_CLOCK: |
64f1603b BZ |
904 | ret = 0x2A1A0A09; |
905 | break; | |
ffd39257 | 906 | case SM501_POWER_MODE_CONTROL: |
64f1603b BZ |
907 | ret = s->power_mode_control; |
908 | break; | |
5690d9ec BZ |
909 | case SM501_ENDIAN_CONTROL: |
910 | ret = 0; /* Only default little endian mode is supported */ | |
911 | break; | |
ffd39257 BS |
912 | |
913 | default: | |
e29da77e BZ |
914 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented system config" |
915 | "register read. addr=%" HWADDR_PRIx "\n", addr); | |
ffd39257 BS |
916 | } |
917 | ||
918 | return ret; | |
919 | } | |
920 | ||
a8170e5e | 921 | static void sm501_system_config_write(void *opaque, hwaddr addr, |
25793bfa | 922 | uint64_t value, unsigned size) |
ffd39257 | 923 | { |
64f1603b | 924 | SM501State *s = (SM501State *)opaque; |
8da3ff18 | 925 | SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n", |
64f1603b | 926 | (uint32_t)addr, (uint32_t)value); |
ffd39257 | 927 | |
64f1603b | 928 | switch (addr) { |
ffd39257 | 929 | case SM501_SYSTEM_CONTROL: |
2100b6b2 BZ |
930 | s->system_control &= 0x10DB0000; |
931 | s->system_control |= value & 0xEF00B8F7; | |
64f1603b | 932 | break; |
ffd39257 | 933 | case SM501_MISC_CONTROL: |
2100b6b2 BZ |
934 | s->misc_control &= 0xEF; |
935 | s->misc_control |= value & 0xFF7FFF10; | |
64f1603b | 936 | break; |
ffd39257 | 937 | case SM501_GPIO31_0_CONTROL: |
64f1603b BZ |
938 | s->gpio_31_0_control = value; |
939 | break; | |
ffd39257 | 940 | case SM501_GPIO63_32_CONTROL: |
2100b6b2 | 941 | s->gpio_63_32_control = value & 0xFF80FFFF; |
64f1603b | 942 | break; |
ffd39257 | 943 | case SM501_DRAM_CONTROL: |
64f1603b BZ |
944 | s->local_mem_size_index = (value >> 13) & 0x7; |
945 | /* TODO : check validity of size change */ | |
2100b6b2 BZ |
946 | s->dram_control &= 0x80000000; |
947 | s->dram_control |= value & 0x7FFFFFC3; | |
64f1603b | 948 | break; |
70e46ca8 | 949 | case SM501_ARBTRTN_CONTROL: |
2100b6b2 | 950 | s->arbitration_control = value & 0x37777777; |
70e46ca8 | 951 | break; |
ffd39257 | 952 | case SM501_IRQ_MASK: |
2100b6b2 | 953 | s->irq_mask = value & 0xFFDF3F5F; |
64f1603b | 954 | break; |
ffd39257 | 955 | case SM501_MISC_TIMING: |
64f1603b BZ |
956 | s->misc_timing = value & 0xF31F1FFF; |
957 | break; | |
ffd39257 BS |
958 | case SM501_POWER_MODE_0_GATE: |
959 | case SM501_POWER_MODE_1_GATE: | |
960 | case SM501_POWER_MODE_0_CLOCK: | |
961 | case SM501_POWER_MODE_1_CLOCK: | |
64f1603b BZ |
962 | /* TODO : simulate gate & clock control */ |
963 | break; | |
ffd39257 | 964 | case SM501_POWER_MODE_CONTROL: |
64f1603b BZ |
965 | s->power_mode_control = value & 0x00000003; |
966 | break; | |
5690d9ec BZ |
967 | case SM501_ENDIAN_CONTROL: |
968 | if (value & 0x00000001) { | |
e29da77e BZ |
969 | qemu_log_mask(LOG_UNIMP, "sm501: system config big endian mode not" |
970 | " implemented.\n"); | |
5690d9ec BZ |
971 | } |
972 | break; | |
ffd39257 BS |
973 | |
974 | default: | |
e29da77e BZ |
975 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented system config" |
976 | "register write. addr=%" HWADDR_PRIx | |
977 | ", val=%" PRIx64 "\n", addr, value); | |
ffd39257 BS |
978 | } |
979 | } | |
980 | ||
25793bfa AK |
981 | static const MemoryRegionOps sm501_system_config_ops = { |
982 | .read = sm501_system_config_read, | |
983 | .write = sm501_system_config_write, | |
984 | .valid = { | |
985 | .min_access_size = 4, | |
986 | .max_access_size = 4, | |
987 | }, | |
afef2e1d | 988 | .endianness = DEVICE_LITTLE_ENDIAN, |
ffd39257 BS |
989 | }; |
990 | ||
4a1f253a BZ |
991 | static uint64_t sm501_i2c_read(void *opaque, hwaddr addr, unsigned size) |
992 | { | |
993 | SM501State *s = (SM501State *)opaque; | |
994 | uint8_t ret = 0; | |
995 | ||
996 | switch (addr) { | |
997 | case SM501_I2C_BYTE_COUNT: | |
998 | ret = s->i2c_byte_count; | |
999 | break; | |
1000 | case SM501_I2C_STATUS: | |
1001 | ret = s->i2c_status; | |
1002 | break; | |
1003 | case SM501_I2C_SLAVE_ADDRESS: | |
1004 | ret = s->i2c_addr; | |
1005 | break; | |
1006 | case SM501_I2C_DATA ... SM501_I2C_DATA + 15: | |
1007 | ret = s->i2c_data[addr - SM501_I2C_DATA]; | |
1008 | break; | |
1009 | default: | |
1010 | qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register read." | |
1011 | " addr=0x%" HWADDR_PRIx "\n", addr); | |
1012 | } | |
1013 | ||
1014 | SM501_DPRINTF("sm501 i2c regs : read addr=%" HWADDR_PRIx " val=%x\n", | |
1015 | addr, ret); | |
1016 | return ret; | |
1017 | } | |
1018 | ||
1019 | static void sm501_i2c_write(void *opaque, hwaddr addr, uint64_t value, | |
1020 | unsigned size) | |
1021 | { | |
1022 | SM501State *s = (SM501State *)opaque; | |
1023 | SM501_DPRINTF("sm501 i2c regs : write addr=%" HWADDR_PRIx | |
1024 | " val=%" PRIx64 "\n", addr, value); | |
1025 | ||
1026 | switch (addr) { | |
1027 | case SM501_I2C_BYTE_COUNT: | |
1028 | s->i2c_byte_count = value & 0xf; | |
1029 | break; | |
1030 | case SM501_I2C_CONTROL: | |
1031 | if (value & SM501_I2C_CONTROL_ENABLE) { | |
1032 | if (value & SM501_I2C_CONTROL_START) { | |
1033 | int res = i2c_start_transfer(s->i2c_bus, | |
1034 | s->i2c_addr >> 1, | |
1035 | s->i2c_addr & 1); | |
1036 | s->i2c_status |= (res ? SM501_I2C_STATUS_ERROR : 0); | |
1037 | if (!res) { | |
1038 | int i; | |
1039 | SM501_DPRINTF("sm501 i2c : transferring %d bytes to 0x%x\n", | |
1040 | s->i2c_byte_count + 1, s->i2c_addr >> 1); | |
1041 | for (i = 0; i <= s->i2c_byte_count; i++) { | |
1042 | res = i2c_send_recv(s->i2c_bus, &s->i2c_data[i], | |
1043 | !(s->i2c_addr & 1)); | |
1044 | if (res) { | |
1045 | SM501_DPRINTF("sm501 i2c : transfer failed" | |
1046 | " i=%d, res=%d\n", i, res); | |
6730df05 | 1047 | s->i2c_status |= SM501_I2C_STATUS_ERROR; |
4a1f253a BZ |
1048 | return; |
1049 | } | |
1050 | } | |
1051 | if (i) { | |
1052 | SM501_DPRINTF("sm501 i2c : transferred %d bytes\n", i); | |
1053 | s->i2c_status = SM501_I2C_STATUS_COMPLETE; | |
1054 | } | |
1055 | } | |
1056 | } else { | |
1057 | SM501_DPRINTF("sm501 i2c : end transfer\n"); | |
1058 | i2c_end_transfer(s->i2c_bus); | |
1059 | s->i2c_status &= ~SM501_I2C_STATUS_ERROR; | |
1060 | } | |
1061 | } | |
1062 | break; | |
1063 | case SM501_I2C_RESET: | |
1064 | if ((value & SM501_I2C_RESET_ERROR) == 0) { | |
1065 | s->i2c_status &= ~SM501_I2C_STATUS_ERROR; | |
1066 | } | |
1067 | break; | |
1068 | case SM501_I2C_SLAVE_ADDRESS: | |
1069 | s->i2c_addr = value & 0xff; | |
1070 | break; | |
1071 | case SM501_I2C_DATA ... SM501_I2C_DATA + 15: | |
1072 | s->i2c_data[addr - SM501_I2C_DATA] = value & 0xff; | |
1073 | break; | |
1074 | default: | |
1075 | qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register write. " | |
1076 | "addr=0x%" HWADDR_PRIx " val=%" PRIx64 "\n", addr, value); | |
1077 | } | |
1078 | } | |
1079 | ||
1080 | static const MemoryRegionOps sm501_i2c_ops = { | |
1081 | .read = sm501_i2c_read, | |
1082 | .write = sm501_i2c_write, | |
1083 | .valid = { | |
1084 | .min_access_size = 1, | |
1085 | .max_access_size = 1, | |
1086 | }, | |
1087 | .impl = { | |
1088 | .min_access_size = 1, | |
1089 | .max_access_size = 1, | |
1090 | }, | |
1091 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1092 | }; | |
1093 | ||
a8170e5e | 1094 | static uint32_t sm501_palette_read(void *opaque, hwaddr addr) |
486579de | 1095 | { |
64f1603b | 1096 | SM501State *s = (SM501State *)opaque; |
486579de AZ |
1097 | SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr); |
1098 | ||
1099 | /* TODO : consider BYTE/WORD access */ | |
1100 | /* TODO : consider endian */ | |
1101 | ||
45416789 | 1102 | assert(range_covers_byte(0, 0x400 * 3, addr)); |
64f1603b | 1103 | return *(uint32_t *)&s->dc_palette[addr]; |
486579de AZ |
1104 | } |
1105 | ||
64f1603b BZ |
1106 | static void sm501_palette_write(void *opaque, hwaddr addr, |
1107 | uint32_t value) | |
486579de | 1108 | { |
64f1603b | 1109 | SM501State *s = (SM501State *)opaque; |
486579de | 1110 | SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n", |
64f1603b | 1111 | (int)addr, value); |
486579de AZ |
1112 | |
1113 | /* TODO : consider BYTE/WORD access */ | |
1114 | /* TODO : consider endian */ | |
1115 | ||
45416789 | 1116 | assert(range_covers_byte(0, 0x400 * 3, addr)); |
64f1603b | 1117 | *(uint32_t *)&s->dc_palette[addr] = value; |
d2733559 | 1118 | s->do_full_update = true; |
486579de AZ |
1119 | } |
1120 | ||
a8170e5e | 1121 | static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr, |
25793bfa | 1122 | unsigned size) |
ffd39257 | 1123 | { |
64f1603b | 1124 | SM501State *s = (SM501State *)opaque; |
ffd39257 | 1125 | uint32_t ret = 0; |
8da3ff18 | 1126 | SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x\n", (int)addr); |
ffd39257 | 1127 | |
64f1603b | 1128 | switch (addr) { |
ffd39257 BS |
1129 | |
1130 | case SM501_DC_PANEL_CONTROL: | |
64f1603b BZ |
1131 | ret = s->dc_panel_control; |
1132 | break; | |
ffd39257 | 1133 | case SM501_DC_PANEL_PANNING_CONTROL: |
64f1603b BZ |
1134 | ret = s->dc_panel_panning_control; |
1135 | break; | |
5690d9ec BZ |
1136 | case SM501_DC_PANEL_COLOR_KEY: |
1137 | /* Not implemented yet */ | |
1138 | break; | |
ffd39257 | 1139 | case SM501_DC_PANEL_FB_ADDR: |
64f1603b BZ |
1140 | ret = s->dc_panel_fb_addr; |
1141 | break; | |
ffd39257 | 1142 | case SM501_DC_PANEL_FB_OFFSET: |
64f1603b BZ |
1143 | ret = s->dc_panel_fb_offset; |
1144 | break; | |
ffd39257 | 1145 | case SM501_DC_PANEL_FB_WIDTH: |
64f1603b BZ |
1146 | ret = s->dc_panel_fb_width; |
1147 | break; | |
ffd39257 | 1148 | case SM501_DC_PANEL_FB_HEIGHT: |
64f1603b BZ |
1149 | ret = s->dc_panel_fb_height; |
1150 | break; | |
ffd39257 | 1151 | case SM501_DC_PANEL_TL_LOC: |
64f1603b BZ |
1152 | ret = s->dc_panel_tl_location; |
1153 | break; | |
ffd39257 | 1154 | case SM501_DC_PANEL_BR_LOC: |
64f1603b BZ |
1155 | ret = s->dc_panel_br_location; |
1156 | break; | |
ffd39257 BS |
1157 | |
1158 | case SM501_DC_PANEL_H_TOT: | |
64f1603b BZ |
1159 | ret = s->dc_panel_h_total; |
1160 | break; | |
ffd39257 | 1161 | case SM501_DC_PANEL_H_SYNC: |
64f1603b BZ |
1162 | ret = s->dc_panel_h_sync; |
1163 | break; | |
ffd39257 | 1164 | case SM501_DC_PANEL_V_TOT: |
64f1603b BZ |
1165 | ret = s->dc_panel_v_total; |
1166 | break; | |
ffd39257 | 1167 | case SM501_DC_PANEL_V_SYNC: |
64f1603b BZ |
1168 | ret = s->dc_panel_v_sync; |
1169 | break; | |
ffd39257 | 1170 | |
a45de179 BZ |
1171 | case SM501_DC_PANEL_HWC_ADDR: |
1172 | ret = s->dc_panel_hwc_addr; | |
1173 | break; | |
1174 | case SM501_DC_PANEL_HWC_LOC: | |
1175 | ret = s->dc_panel_hwc_location; | |
1176 | break; | |
1177 | case SM501_DC_PANEL_HWC_COLOR_1_2: | |
1178 | ret = s->dc_panel_hwc_color_1_2; | |
1179 | break; | |
1180 | case SM501_DC_PANEL_HWC_COLOR_3: | |
1181 | ret = s->dc_panel_hwc_color_3; | |
1182 | break; | |
1183 | ||
b612a49d BZ |
1184 | case SM501_DC_VIDEO_CONTROL: |
1185 | ret = s->dc_video_control; | |
1186 | break; | |
1187 | ||
ffd39257 | 1188 | case SM501_DC_CRT_CONTROL: |
64f1603b BZ |
1189 | ret = s->dc_crt_control; |
1190 | break; | |
ffd39257 | 1191 | case SM501_DC_CRT_FB_ADDR: |
64f1603b BZ |
1192 | ret = s->dc_crt_fb_addr; |
1193 | break; | |
ffd39257 | 1194 | case SM501_DC_CRT_FB_OFFSET: |
64f1603b BZ |
1195 | ret = s->dc_crt_fb_offset; |
1196 | break; | |
ffd39257 | 1197 | case SM501_DC_CRT_H_TOT: |
64f1603b BZ |
1198 | ret = s->dc_crt_h_total; |
1199 | break; | |
ffd39257 | 1200 | case SM501_DC_CRT_H_SYNC: |
64f1603b BZ |
1201 | ret = s->dc_crt_h_sync; |
1202 | break; | |
ffd39257 | 1203 | case SM501_DC_CRT_V_TOT: |
64f1603b BZ |
1204 | ret = s->dc_crt_v_total; |
1205 | break; | |
ffd39257 | 1206 | case SM501_DC_CRT_V_SYNC: |
64f1603b BZ |
1207 | ret = s->dc_crt_v_sync; |
1208 | break; | |
ffd39257 BS |
1209 | |
1210 | case SM501_DC_CRT_HWC_ADDR: | |
64f1603b BZ |
1211 | ret = s->dc_crt_hwc_addr; |
1212 | break; | |
ffd39257 | 1213 | case SM501_DC_CRT_HWC_LOC: |
64f1603b BZ |
1214 | ret = s->dc_crt_hwc_location; |
1215 | break; | |
ffd39257 | 1216 | case SM501_DC_CRT_HWC_COLOR_1_2: |
64f1603b BZ |
1217 | ret = s->dc_crt_hwc_color_1_2; |
1218 | break; | |
ffd39257 | 1219 | case SM501_DC_CRT_HWC_COLOR_3: |
64f1603b BZ |
1220 | ret = s->dc_crt_hwc_color_3; |
1221 | break; | |
ffd39257 | 1222 | |
64f1603b | 1223 | case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4: |
486579de AZ |
1224 | ret = sm501_palette_read(opaque, addr - SM501_DC_PANEL_PALETTE); |
1225 | break; | |
1226 | ||
ffd39257 | 1227 | default: |
e29da77e BZ |
1228 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register " |
1229 | "read. addr=%" HWADDR_PRIx "\n", addr); | |
ffd39257 BS |
1230 | } |
1231 | ||
1232 | return ret; | |
1233 | } | |
1234 | ||
a8170e5e | 1235 | static void sm501_disp_ctrl_write(void *opaque, hwaddr addr, |
25793bfa | 1236 | uint64_t value, unsigned size) |
ffd39257 | 1237 | { |
64f1603b | 1238 | SM501State *s = (SM501State *)opaque; |
8da3ff18 | 1239 | SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, val=%x\n", |
64f1603b | 1240 | (unsigned)addr, (unsigned)value); |
ffd39257 | 1241 | |
64f1603b | 1242 | switch (addr) { |
ffd39257 | 1243 | case SM501_DC_PANEL_CONTROL: |
64f1603b BZ |
1244 | s->dc_panel_control = value & 0x0FFF73FF; |
1245 | break; | |
ffd39257 | 1246 | case SM501_DC_PANEL_PANNING_CONTROL: |
64f1603b BZ |
1247 | s->dc_panel_panning_control = value & 0xFF3FFF3F; |
1248 | break; | |
5690d9ec BZ |
1249 | case SM501_DC_PANEL_COLOR_KEY: |
1250 | /* Not implemented yet */ | |
1251 | break; | |
ffd39257 | 1252 | case SM501_DC_PANEL_FB_ADDR: |
64f1603b | 1253 | s->dc_panel_fb_addr = value & 0x8FFFFFF0; |
33159dd7 BZ |
1254 | if (value & 0x8000000) { |
1255 | qemu_log_mask(LOG_UNIMP, "Panel external memory not supported\n"); | |
1256 | } | |
593a1cdd | 1257 | s->do_full_update = true; |
64f1603b | 1258 | break; |
ffd39257 | 1259 | case SM501_DC_PANEL_FB_OFFSET: |
64f1603b BZ |
1260 | s->dc_panel_fb_offset = value & 0x3FF03FF0; |
1261 | break; | |
ffd39257 | 1262 | case SM501_DC_PANEL_FB_WIDTH: |
64f1603b BZ |
1263 | s->dc_panel_fb_width = value & 0x0FFF0FFF; |
1264 | break; | |
ffd39257 | 1265 | case SM501_DC_PANEL_FB_HEIGHT: |
64f1603b BZ |
1266 | s->dc_panel_fb_height = value & 0x0FFF0FFF; |
1267 | break; | |
ffd39257 | 1268 | case SM501_DC_PANEL_TL_LOC: |
64f1603b BZ |
1269 | s->dc_panel_tl_location = value & 0x07FF07FF; |
1270 | break; | |
ffd39257 | 1271 | case SM501_DC_PANEL_BR_LOC: |
64f1603b BZ |
1272 | s->dc_panel_br_location = value & 0x07FF07FF; |
1273 | break; | |
ffd39257 BS |
1274 | |
1275 | case SM501_DC_PANEL_H_TOT: | |
64f1603b BZ |
1276 | s->dc_panel_h_total = value & 0x0FFF0FFF; |
1277 | break; | |
ffd39257 | 1278 | case SM501_DC_PANEL_H_SYNC: |
64f1603b BZ |
1279 | s->dc_panel_h_sync = value & 0x00FF0FFF; |
1280 | break; | |
ffd39257 | 1281 | case SM501_DC_PANEL_V_TOT: |
64f1603b BZ |
1282 | s->dc_panel_v_total = value & 0x0FFF0FFF; |
1283 | break; | |
ffd39257 | 1284 | case SM501_DC_PANEL_V_SYNC: |
64f1603b BZ |
1285 | s->dc_panel_v_sync = value & 0x003F0FFF; |
1286 | break; | |
ffd39257 BS |
1287 | |
1288 | case SM501_DC_PANEL_HWC_ADDR: | |
6a2a5aae BZ |
1289 | value &= 0x8FFFFFF0; |
1290 | if (value != s->dc_panel_hwc_addr) { | |
1291 | hwc_invalidate(s, 0); | |
1292 | s->dc_panel_hwc_addr = value; | |
1293 | } | |
64f1603b | 1294 | break; |
ffd39257 | 1295 | case SM501_DC_PANEL_HWC_LOC: |
6a2a5aae BZ |
1296 | value &= 0x0FFF0FFF; |
1297 | if (value != s->dc_panel_hwc_location) { | |
1298 | hwc_invalidate(s, 0); | |
1299 | s->dc_panel_hwc_location = value; | |
1300 | } | |
64f1603b | 1301 | break; |
ffd39257 | 1302 | case SM501_DC_PANEL_HWC_COLOR_1_2: |
64f1603b BZ |
1303 | s->dc_panel_hwc_color_1_2 = value; |
1304 | break; | |
ffd39257 | 1305 | case SM501_DC_PANEL_HWC_COLOR_3: |
64f1603b BZ |
1306 | s->dc_panel_hwc_color_3 = value & 0x0000FFFF; |
1307 | break; | |
ffd39257 | 1308 | |
b612a49d BZ |
1309 | case SM501_DC_VIDEO_CONTROL: |
1310 | s->dc_video_control = value & 0x00037FFF; | |
1311 | break; | |
1312 | ||
ffd39257 | 1313 | case SM501_DC_CRT_CONTROL: |
64f1603b BZ |
1314 | s->dc_crt_control = value & 0x0003FFFF; |
1315 | break; | |
ffd39257 | 1316 | case SM501_DC_CRT_FB_ADDR: |
64f1603b | 1317 | s->dc_crt_fb_addr = value & 0x8FFFFFF0; |
33159dd7 BZ |
1318 | if (value & 0x8000000) { |
1319 | qemu_log_mask(LOG_UNIMP, "CRT external memory not supported\n"); | |
1320 | } | |
593a1cdd | 1321 | s->do_full_update = true; |
64f1603b | 1322 | break; |
ffd39257 | 1323 | case SM501_DC_CRT_FB_OFFSET: |
64f1603b BZ |
1324 | s->dc_crt_fb_offset = value & 0x3FF03FF0; |
1325 | break; | |
ffd39257 | 1326 | case SM501_DC_CRT_H_TOT: |
64f1603b BZ |
1327 | s->dc_crt_h_total = value & 0x0FFF0FFF; |
1328 | break; | |
ffd39257 | 1329 | case SM501_DC_CRT_H_SYNC: |
64f1603b BZ |
1330 | s->dc_crt_h_sync = value & 0x00FF0FFF; |
1331 | break; | |
ffd39257 | 1332 | case SM501_DC_CRT_V_TOT: |
64f1603b BZ |
1333 | s->dc_crt_v_total = value & 0x0FFF0FFF; |
1334 | break; | |
ffd39257 | 1335 | case SM501_DC_CRT_V_SYNC: |
64f1603b BZ |
1336 | s->dc_crt_v_sync = value & 0x003F0FFF; |
1337 | break; | |
ffd39257 BS |
1338 | |
1339 | case SM501_DC_CRT_HWC_ADDR: | |
6a2a5aae BZ |
1340 | value &= 0x8FFFFFF0; |
1341 | if (value != s->dc_crt_hwc_addr) { | |
1342 | hwc_invalidate(s, 1); | |
1343 | s->dc_crt_hwc_addr = value; | |
1344 | } | |
64f1603b | 1345 | break; |
ffd39257 | 1346 | case SM501_DC_CRT_HWC_LOC: |
6a2a5aae BZ |
1347 | value &= 0x0FFF0FFF; |
1348 | if (value != s->dc_crt_hwc_location) { | |
1349 | hwc_invalidate(s, 1); | |
1350 | s->dc_crt_hwc_location = value; | |
1351 | } | |
64f1603b | 1352 | break; |
ffd39257 | 1353 | case SM501_DC_CRT_HWC_COLOR_1_2: |
64f1603b BZ |
1354 | s->dc_crt_hwc_color_1_2 = value; |
1355 | break; | |
ffd39257 | 1356 | case SM501_DC_CRT_HWC_COLOR_3: |
64f1603b BZ |
1357 | s->dc_crt_hwc_color_3 = value & 0x0000FFFF; |
1358 | break; | |
ffd39257 | 1359 | |
64f1603b | 1360 | case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4: |
486579de AZ |
1361 | sm501_palette_write(opaque, addr - SM501_DC_PANEL_PALETTE, value); |
1362 | break; | |
1363 | ||
ffd39257 | 1364 | default: |
e29da77e BZ |
1365 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register " |
1366 | "write. addr=%" HWADDR_PRIx | |
1367 | ", val=%" PRIx64 "\n", addr, value); | |
ffd39257 BS |
1368 | } |
1369 | } | |
1370 | ||
25793bfa AK |
1371 | static const MemoryRegionOps sm501_disp_ctrl_ops = { |
1372 | .read = sm501_disp_ctrl_read, | |
1373 | .write = sm501_disp_ctrl_write, | |
1374 | .valid = { | |
1375 | .min_access_size = 4, | |
1376 | .max_access_size = 4, | |
1377 | }, | |
afef2e1d | 1378 | .endianness = DEVICE_LITTLE_ENDIAN, |
ffd39257 BS |
1379 | }; |
1380 | ||
a8170e5e | 1381 | static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr, |
25793bfa | 1382 | unsigned size) |
604be200 | 1383 | { |
64f1603b | 1384 | SM501State *s = (SM501State *)opaque; |
604be200 SK |
1385 | uint32_t ret = 0; |
1386 | SM501_DPRINTF("sm501 2d engine regs : read addr=%x\n", (int)addr); | |
1387 | ||
64f1603b | 1388 | switch (addr) { |
b612a49d BZ |
1389 | case SM501_2D_SOURCE: |
1390 | ret = s->twoD_source; | |
1391 | break; | |
1392 | case SM501_2D_DESTINATION: | |
1393 | ret = s->twoD_destination; | |
1394 | break; | |
1395 | case SM501_2D_DIMENSION: | |
1396 | ret = s->twoD_dimension; | |
1397 | break; | |
1398 | case SM501_2D_CONTROL: | |
1399 | ret = s->twoD_control; | |
1400 | break; | |
1401 | case SM501_2D_PITCH: | |
1402 | ret = s->twoD_pitch; | |
1403 | break; | |
1404 | case SM501_2D_FOREGROUND: | |
1405 | ret = s->twoD_foreground; | |
1406 | break; | |
1407 | case SM501_2D_BACKGROUND: | |
1408 | ret = s->twoD_background; | |
1409 | break; | |
1410 | case SM501_2D_STRETCH: | |
1411 | ret = s->twoD_stretch; | |
1412 | break; | |
1413 | case SM501_2D_COLOR_COMPARE: | |
1414 | ret = s->twoD_color_compare; | |
1415 | break; | |
1416 | case SM501_2D_COLOR_COMPARE_MASK: | |
1417 | ret = s->twoD_color_compare_mask; | |
1418 | break; | |
1419 | case SM501_2D_MASK: | |
1420 | ret = s->twoD_mask; | |
1421 | break; | |
1422 | case SM501_2D_CLIP_TL: | |
1423 | ret = s->twoD_clip_tl; | |
1424 | break; | |
1425 | case SM501_2D_CLIP_BR: | |
1426 | ret = s->twoD_clip_br; | |
1427 | break; | |
1428 | case SM501_2D_MONO_PATTERN_LOW: | |
1429 | ret = s->twoD_mono_pattern_low; | |
1430 | break; | |
1431 | case SM501_2D_MONO_PATTERN_HIGH: | |
1432 | ret = s->twoD_mono_pattern_high; | |
1433 | break; | |
1434 | case SM501_2D_WINDOW_WIDTH: | |
1435 | ret = s->twoD_window_width; | |
1436 | break; | |
604be200 SK |
1437 | case SM501_2D_SOURCE_BASE: |
1438 | ret = s->twoD_source_base; | |
1439 | break; | |
b612a49d BZ |
1440 | case SM501_2D_DESTINATION_BASE: |
1441 | ret = s->twoD_destination_base; | |
1442 | break; | |
1443 | case SM501_2D_ALPHA: | |
1444 | ret = s->twoD_alpha; | |
1445 | break; | |
1446 | case SM501_2D_WRAP: | |
1447 | ret = s->twoD_wrap; | |
1448 | break; | |
1449 | case SM501_2D_STATUS: | |
1450 | ret = 0; /* Should return interrupt status */ | |
1451 | break; | |
604be200 | 1452 | default: |
e29da77e BZ |
1453 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register " |
1454 | "read. addr=%" HWADDR_PRIx "\n", addr); | |
604be200 SK |
1455 | } |
1456 | ||
1457 | return ret; | |
1458 | } | |
1459 | ||
a8170e5e | 1460 | static void sm501_2d_engine_write(void *opaque, hwaddr addr, |
25793bfa | 1461 | uint64_t value, unsigned size) |
604be200 | 1462 | { |
64f1603b | 1463 | SM501State *s = (SM501State *)opaque; |
604be200 | 1464 | SM501_DPRINTF("sm501 2d engine regs : write addr=%x, val=%x\n", |
25793bfa | 1465 | (unsigned)addr, (unsigned)value); |
604be200 | 1466 | |
64f1603b | 1467 | switch (addr) { |
07d8a50c AJ |
1468 | case SM501_2D_SOURCE: |
1469 | s->twoD_source = value; | |
1470 | break; | |
604be200 SK |
1471 | case SM501_2D_DESTINATION: |
1472 | s->twoD_destination = value; | |
1473 | break; | |
1474 | case SM501_2D_DIMENSION: | |
1475 | s->twoD_dimension = value; | |
1476 | break; | |
1477 | case SM501_2D_CONTROL: | |
1478 | s->twoD_control = value; | |
1479 | ||
1480 | /* do 2d operation if start flag is set. */ | |
1481 | if (value & 0x80000000) { | |
1482 | sm501_2d_operation(s); | |
1483 | s->twoD_control &= ~0x80000000; /* start flag down */ | |
1484 | } | |
1485 | ||
1486 | break; | |
1487 | case SM501_2D_PITCH: | |
1488 | s->twoD_pitch = value; | |
1489 | break; | |
1490 | case SM501_2D_FOREGROUND: | |
1491 | s->twoD_foreground = value; | |
1492 | break; | |
b612a49d BZ |
1493 | case SM501_2D_BACKGROUND: |
1494 | s->twoD_background = value; | |
1495 | break; | |
604be200 SK |
1496 | case SM501_2D_STRETCH: |
1497 | s->twoD_stretch = value; | |
1498 | break; | |
b612a49d BZ |
1499 | case SM501_2D_COLOR_COMPARE: |
1500 | s->twoD_color_compare = value; | |
1501 | break; | |
604be200 SK |
1502 | case SM501_2D_COLOR_COMPARE_MASK: |
1503 | s->twoD_color_compare_mask = value; | |
1504 | break; | |
1505 | case SM501_2D_MASK: | |
1506 | s->twoD_mask = value; | |
1507 | break; | |
b612a49d BZ |
1508 | case SM501_2D_CLIP_TL: |
1509 | s->twoD_clip_tl = value; | |
1510 | break; | |
1511 | case SM501_2D_CLIP_BR: | |
1512 | s->twoD_clip_br = value; | |
1513 | break; | |
1514 | case SM501_2D_MONO_PATTERN_LOW: | |
1515 | s->twoD_mono_pattern_low = value; | |
1516 | break; | |
1517 | case SM501_2D_MONO_PATTERN_HIGH: | |
1518 | s->twoD_mono_pattern_high = value; | |
1519 | break; | |
604be200 SK |
1520 | case SM501_2D_WINDOW_WIDTH: |
1521 | s->twoD_window_width = value; | |
1522 | break; | |
1523 | case SM501_2D_SOURCE_BASE: | |
1524 | s->twoD_source_base = value; | |
1525 | break; | |
1526 | case SM501_2D_DESTINATION_BASE: | |
1527 | s->twoD_destination_base = value; | |
1528 | break; | |
b612a49d BZ |
1529 | case SM501_2D_ALPHA: |
1530 | s->twoD_alpha = value; | |
1531 | break; | |
1532 | case SM501_2D_WRAP: | |
1533 | s->twoD_wrap = value; | |
1534 | break; | |
1535 | case SM501_2D_STATUS: | |
1536 | /* ignored, writing 0 should clear interrupt status */ | |
1537 | break; | |
604be200 | 1538 | default: |
e29da77e BZ |
1539 | qemu_log_mask(LOG_UNIMP, "sm501: not implemented 2d engine register " |
1540 | "write. addr=%" HWADDR_PRIx | |
1541 | ", val=%" PRIx64 "\n", addr, value); | |
604be200 SK |
1542 | } |
1543 | } | |
1544 | ||
25793bfa AK |
1545 | static const MemoryRegionOps sm501_2d_engine_ops = { |
1546 | .read = sm501_2d_engine_read, | |
1547 | .write = sm501_2d_engine_write, | |
1548 | .valid = { | |
1549 | .min_access_size = 4, | |
1550 | .max_access_size = 4, | |
1551 | }, | |
afef2e1d | 1552 | .endianness = DEVICE_LITTLE_ENDIAN, |
604be200 SK |
1553 | }; |
1554 | ||
ffd39257 BS |
1555 | /* draw line functions for all console modes */ |
1556 | ||
ffd39257 | 1557 | typedef void draw_line_func(uint8_t *d, const uint8_t *s, |
64f1603b | 1558 | int width, const uint32_t *pal); |
ffd39257 | 1559 | |
6a2a5aae BZ |
1560 | typedef void draw_hwc_line_func(uint8_t *d, const uint8_t *s, |
1561 | int width, const uint8_t *palette, | |
1562 | int c_x, int c_y); | |
0a4e7cd2 | 1563 | |
ffd39257 | 1564 | #define DEPTH 8 |
47b43a1f | 1565 | #include "sm501_template.h" |
ffd39257 BS |
1566 | |
1567 | #define DEPTH 15 | |
47b43a1f | 1568 | #include "sm501_template.h" |
ffd39257 BS |
1569 | |
1570 | #define BGR_FORMAT | |
1571 | #define DEPTH 15 | |
47b43a1f | 1572 | #include "sm501_template.h" |
ffd39257 BS |
1573 | |
1574 | #define DEPTH 16 | |
47b43a1f | 1575 | #include "sm501_template.h" |
ffd39257 BS |
1576 | |
1577 | #define BGR_FORMAT | |
1578 | #define DEPTH 16 | |
47b43a1f | 1579 | #include "sm501_template.h" |
ffd39257 BS |
1580 | |
1581 | #define DEPTH 32 | |
47b43a1f | 1582 | #include "sm501_template.h" |
ffd39257 BS |
1583 | |
1584 | #define BGR_FORMAT | |
1585 | #define DEPTH 32 | |
47b43a1f | 1586 | #include "sm501_template.h" |
ffd39257 | 1587 | |
64f1603b | 1588 | static draw_line_func *draw_line8_funcs[] = { |
ffd39257 BS |
1589 | draw_line8_8, |
1590 | draw_line8_15, | |
1591 | draw_line8_16, | |
1592 | draw_line8_32, | |
1593 | draw_line8_32bgr, | |
1594 | draw_line8_15bgr, | |
1595 | draw_line8_16bgr, | |
1596 | }; | |
1597 | ||
64f1603b | 1598 | static draw_line_func *draw_line16_funcs[] = { |
ffd39257 BS |
1599 | draw_line16_8, |
1600 | draw_line16_15, | |
1601 | draw_line16_16, | |
1602 | draw_line16_32, | |
1603 | draw_line16_32bgr, | |
1604 | draw_line16_15bgr, | |
1605 | draw_line16_16bgr, | |
1606 | }; | |
1607 | ||
64f1603b | 1608 | static draw_line_func *draw_line32_funcs[] = { |
ffd39257 BS |
1609 | draw_line32_8, |
1610 | draw_line32_15, | |
1611 | draw_line32_16, | |
1612 | draw_line32_32, | |
1613 | draw_line32_32bgr, | |
1614 | draw_line32_15bgr, | |
1615 | draw_line32_16bgr, | |
1616 | }; | |
1617 | ||
64f1603b | 1618 | static draw_hwc_line_func *draw_hwc_line_funcs[] = { |
0a4e7cd2 SK |
1619 | draw_hwc_line_8, |
1620 | draw_hwc_line_15, | |
1621 | draw_hwc_line_16, | |
1622 | draw_hwc_line_32, | |
1623 | draw_hwc_line_32bgr, | |
1624 | draw_hwc_line_15bgr, | |
1625 | draw_hwc_line_16bgr, | |
1626 | }; | |
1627 | ||
c78f7137 | 1628 | static inline int get_depth_index(DisplaySurface *surface) |
ffd39257 | 1629 | { |
c78f7137 | 1630 | switch (surface_bits_per_pixel(surface)) { |
ffd39257 BS |
1631 | default: |
1632 | case 8: | |
64f1603b | 1633 | return 0; |
ffd39257 | 1634 | case 15: |
8927bcfd | 1635 | return 1; |
ffd39257 | 1636 | case 16: |
8927bcfd | 1637 | return 2; |
ffd39257 | 1638 | case 32: |
c78f7137 GH |
1639 | if (is_surface_bgr(surface)) { |
1640 | return 4; | |
1641 | } else { | |
1642 | return 3; | |
1643 | } | |
ffd39257 BS |
1644 | } |
1645 | } | |
1646 | ||
1ae5e6eb | 1647 | static void sm501_update_display(void *opaque) |
ffd39257 | 1648 | { |
1ae5e6eb | 1649 | SM501State *s = (SM501State *)opaque; |
c78f7137 | 1650 | DisplaySurface *surface = qemu_console_surface(s->con); |
ca7f5441 | 1651 | DirtyBitmapSnapshot *snap; |
6a2a5aae | 1652 | int y, c_x = 0, c_y = 0; |
1ae5e6eb BZ |
1653 | int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0; |
1654 | int width = get_width(s, crt); | |
1655 | int height = get_height(s, crt); | |
1656 | int src_bpp = get_bpp(s, crt); | |
c78f7137 | 1657 | int dst_bpp = surface_bytes_per_pixel(surface); |
01d2d584 | 1658 | int dst_depth_index = get_depth_index(surface); |
64f1603b BZ |
1659 | draw_line_func *draw_line = NULL; |
1660 | draw_hwc_line_func *draw_hwc_line = NULL; | |
ffd39257 BS |
1661 | int full_update = 0; |
1662 | int y_start = -1; | |
33159dd7 | 1663 | ram_addr_t offset; |
1ae5e6eb BZ |
1664 | uint32_t *palette; |
1665 | uint8_t hwc_palette[3 * 3]; | |
1666 | uint8_t *hwc_src = NULL; | |
1667 | ||
1668 | if (!((crt ? s->dc_crt_control : s->dc_panel_control) | |
1669 | & SM501_DC_CRT_CONTROL_ENABLE)) { | |
1670 | return; | |
1671 | } | |
1672 | ||
1673 | palette = (uint32_t *)(crt ? &s->dc_palette[SM501_DC_CRT_PALETTE - | |
1674 | SM501_DC_PANEL_PALETTE] | |
1675 | : &s->dc_palette[0]); | |
ffd39257 BS |
1676 | |
1677 | /* choose draw_line function */ | |
6a2a5aae BZ |
1678 | switch (src_bpp) { |
1679 | case 1: | |
01d2d584 | 1680 | draw_line = draw_line8_funcs[dst_depth_index]; |
64f1603b | 1681 | break; |
6a2a5aae | 1682 | case 2: |
01d2d584 | 1683 | draw_line = draw_line16_funcs[dst_depth_index]; |
64f1603b | 1684 | break; |
6a2a5aae | 1685 | case 4: |
01d2d584 | 1686 | draw_line = draw_line32_funcs[dst_depth_index]; |
64f1603b | 1687 | break; |
ffd39257 | 1688 | default: |
e29da77e BZ |
1689 | qemu_log_mask(LOG_GUEST_ERROR, "sm501: update display" |
1690 | "invalid control register value.\n"); | |
1691 | return; | |
ffd39257 BS |
1692 | } |
1693 | ||
0a4e7cd2 | 1694 | /* set up to draw hardware cursor */ |
1ae5e6eb | 1695 | if (is_hwc_enabled(s, crt)) { |
0a4e7cd2 | 1696 | /* choose cursor draw line function */ |
01d2d584 | 1697 | draw_hwc_line = draw_hwc_line_funcs[dst_depth_index]; |
1ae5e6eb BZ |
1698 | hwc_src = get_hwc_address(s, crt); |
1699 | c_x = get_hwc_x(s, crt); | |
1700 | c_y = get_hwc_y(s, crt); | |
1701 | get_hwc_palette(s, crt, hwc_palette); | |
0a4e7cd2 SK |
1702 | } |
1703 | ||
ffd39257 BS |
1704 | /* adjust console size */ |
1705 | if (s->last_width != width || s->last_height != height) { | |
c78f7137 GH |
1706 | qemu_console_resize(s->con, width, height); |
1707 | surface = qemu_console_surface(s->con); | |
64f1603b BZ |
1708 | s->last_width = width; |
1709 | s->last_height = height; | |
1710 | full_update = 1; | |
ffd39257 BS |
1711 | } |
1712 | ||
d2733559 SB |
1713 | /* someone else requested a full update */ |
1714 | if (s->do_full_update) { | |
1715 | s->do_full_update = false; | |
1716 | full_update = 1; | |
1717 | } | |
1718 | ||
ffd39257 | 1719 | /* draw each line according to conditions */ |
33159dd7 | 1720 | offset = get_fb_addr(s, crt); |
ca7f5441 GH |
1721 | snap = memory_region_snapshot_and_clear_dirty(&s->local_mem_region, |
1722 | offset, width * height * src_bpp, DIRTY_MEMORY_VGA); | |
33159dd7 | 1723 | for (y = 0; y < height; y++, offset += width * src_bpp) { |
6a2a5aae | 1724 | int update, update_hwc; |
ffd39257 | 1725 | |
6a2a5aae BZ |
1726 | /* check if hardware cursor is enabled and we're within its range */ |
1727 | update_hwc = draw_hwc_line && c_y <= y && y < c_y + SM501_HWC_HEIGHT; | |
1728 | update = full_update || update_hwc; | |
64f1603b | 1729 | /* check dirty flags for each line */ |
ca7f5441 GH |
1730 | update |= memory_region_snapshot_get_dirty(&s->local_mem_region, snap, |
1731 | offset, width * src_bpp); | |
ffd39257 | 1732 | |
64f1603b BZ |
1733 | /* draw line and change status */ |
1734 | if (update) { | |
c78f7137 GH |
1735 | uint8_t *d = surface_data(surface); |
1736 | d += y * width * dst_bpp; | |
0a4e7cd2 SK |
1737 | |
1738 | /* draw graphics layer */ | |
1ae5e6eb | 1739 | draw_line(d, s->local_mem + offset, width, palette); |
0a4e7cd2 | 1740 | |
64f1603b | 1741 | /* draw hardware cursor */ |
0a4e7cd2 | 1742 | if (update_hwc) { |
6a2a5aae | 1743 | draw_hwc_line(d, hwc_src, width, hwc_palette, c_x, y - c_y); |
0a4e7cd2 SK |
1744 | } |
1745 | ||
64f1603b BZ |
1746 | if (y_start < 0) { |
1747 | y_start = y; | |
1748 | } | |
64f1603b BZ |
1749 | } else { |
1750 | if (y_start >= 0) { | |
1751 | /* flush to display */ | |
c78f7137 | 1752 | dpy_gfx_update(s->con, 0, y_start, width, y - y_start); |
64f1603b BZ |
1753 | y_start = -1; |
1754 | } | |
1755 | } | |
ffd39257 | 1756 | } |
ca7f5441 | 1757 | g_free(snap); |
ffd39257 BS |
1758 | |
1759 | /* complete flush to display */ | |
64f1603b | 1760 | if (y_start >= 0) { |
c78f7137 | 1761 | dpy_gfx_update(s->con, 0, y_start, width, y - y_start); |
64f1603b | 1762 | } |
ffd39257 BS |
1763 | } |
1764 | ||
380cd056 GH |
1765 | static const GraphicHwOps sm501_ops = { |
1766 | .gfx_update = sm501_update_display, | |
1767 | }; | |
1768 | ||
ca8a1104 | 1769 | static void sm501_reset(SM501State *s) |
ffd39257 | 1770 | { |
e2ee8476 BZ |
1771 | s->system_control = 0x00100000; /* 2D engine FIFO empty */ |
1772 | /* Bits 17 (SH), 7 (CDR), 6:5 (Test), 2:0 (Bus) are all supposed | |
1773 | * to be determined at reset by GPIO lines which set config bits. | |
1774 | * We hardwire them: | |
1775 | * SH = 0 : Hitachi Ready Polarity == Active Low | |
1776 | * CDR = 0 : do not reset clock divider | |
1777 | * TEST = 0 : Normal mode (not testing the silicon) | |
1778 | * BUS = 0 : Hitachi SH3/SH4 | |
1779 | */ | |
1780 | s->misc_control = SM501_MISC_DAC_POWER; | |
ca8a1104 BZ |
1781 | s->gpio_31_0_control = 0; |
1782 | s->gpio_63_32_control = 0; | |
1783 | s->dram_control = 0; | |
70e46ca8 | 1784 | s->arbitration_control = 0x05146732; |
ca8a1104 BZ |
1785 | s->irq_mask = 0; |
1786 | s->misc_timing = 0; | |
1787 | s->power_mode_control = 0; | |
4a1f253a BZ |
1788 | s->i2c_byte_count = 0; |
1789 | s->i2c_status = 0; | |
1790 | s->i2c_addr = 0; | |
1791 | memset(s->i2c_data, 0, 16); | |
e2ee8476 | 1792 | s->dc_panel_control = 0x00010000; /* FIFO level 3 */ |
b612a49d | 1793 | s->dc_video_control = 0; |
ffd39257 | 1794 | s->dc_crt_control = 0x00010000; |
b612a49d BZ |
1795 | s->twoD_source = 0; |
1796 | s->twoD_destination = 0; | |
1797 | s->twoD_dimension = 0; | |
ca8a1104 | 1798 | s->twoD_control = 0; |
b612a49d BZ |
1799 | s->twoD_pitch = 0; |
1800 | s->twoD_foreground = 0; | |
1801 | s->twoD_background = 0; | |
1802 | s->twoD_stretch = 0; | |
1803 | s->twoD_color_compare = 0; | |
1804 | s->twoD_color_compare_mask = 0; | |
1805 | s->twoD_mask = 0; | |
1806 | s->twoD_clip_tl = 0; | |
1807 | s->twoD_clip_br = 0; | |
1808 | s->twoD_mono_pattern_low = 0; | |
1809 | s->twoD_mono_pattern_high = 0; | |
1810 | s->twoD_window_width = 0; | |
1811 | s->twoD_source_base = 0; | |
1812 | s->twoD_destination_base = 0; | |
1813 | s->twoD_alpha = 0; | |
1814 | s->twoD_wrap = 0; | |
ca8a1104 | 1815 | } |
ffd39257 | 1816 | |
c795fa84 | 1817 | static void sm501_init(SM501State *s, DeviceState *dev, |
ca8a1104 BZ |
1818 | uint32_t local_mem_bytes) |
1819 | { | |
ca8a1104 BZ |
1820 | s->local_mem_size_index = get_local_mem_size_index(local_mem_bytes); |
1821 | SM501_DPRINTF("sm501 local mem size=%x. index=%d\n", get_local_mem_size(s), | |
1822 | s->local_mem_size_index); | |
1823 | ||
1824 | /* local memory */ | |
4c4414a4 | 1825 | memory_region_init_ram(&s->local_mem_region, OBJECT(dev), "sm501.local", |
ca8a1104 | 1826 | get_local_mem_size(s), &error_fatal); |
74259ae5 | 1827 | memory_region_set_log(&s->local_mem_region, true, DIRTY_MEMORY_VGA); |
25793bfa | 1828 | s->local_mem = memory_region_get_ram_ptr(&s->local_mem_region); |
ca8a1104 | 1829 | |
4a1f253a BZ |
1830 | /* i2c */ |
1831 | s->i2c_bus = i2c_init_bus(dev, "sm501.i2c"); | |
1832 | /* ddc */ | |
df707969 | 1833 | I2CDDCState *ddc = I2CDDC(qdev_new(TYPE_I2CDDC)); |
4a1f253a | 1834 | i2c_set_slave_address(I2C_SLAVE(ddc), 0x50); |
df707969 | 1835 | qdev_realize_and_unref(DEVICE(ddc), BUS(s->i2c_bus), &error_abort); |
4a1f253a | 1836 | |
ca8a1104 BZ |
1837 | /* mmio */ |
1838 | memory_region_init(&s->mmio_region, OBJECT(dev), "sm501.mmio", MMIO_SIZE); | |
1839 | memory_region_init_io(&s->system_config_region, OBJECT(dev), | |
1840 | &sm501_system_config_ops, s, | |
1841 | "sm501-system-config", 0x6c); | |
1842 | memory_region_add_subregion(&s->mmio_region, SM501_SYS_CONFIG, | |
1843 | &s->system_config_region); | |
4a1f253a BZ |
1844 | memory_region_init_io(&s->i2c_region, OBJECT(dev), &sm501_i2c_ops, s, |
1845 | "sm501-i2c", 0x14); | |
1846 | memory_region_add_subregion(&s->mmio_region, SM501_I2C, &s->i2c_region); | |
ca8a1104 BZ |
1847 | memory_region_init_io(&s->disp_ctrl_region, OBJECT(dev), |
1848 | &sm501_disp_ctrl_ops, s, | |
25793bfa | 1849 | "sm501-disp-ctrl", 0x1000); |
ca8a1104 BZ |
1850 | memory_region_add_subregion(&s->mmio_region, SM501_DC, |
1851 | &s->disp_ctrl_region); | |
1852 | memory_region_init_io(&s->twoD_engine_region, OBJECT(dev), | |
1853 | &sm501_2d_engine_ops, s, | |
25793bfa | 1854 | "sm501-2d-engine", 0x54); |
ca8a1104 BZ |
1855 | memory_region_add_subregion(&s->mmio_region, SM501_2D_ENGINE, |
1856 | &s->twoD_engine_region); | |
1857 | ||
1858 | /* create qemu graphic console */ | |
8e5c952b | 1859 | s->con = graphic_console_init(dev, 0, &sm501_ops, s); |
ca8a1104 BZ |
1860 | } |
1861 | ||
2edd6e4a BZ |
1862 | static const VMStateDescription vmstate_sm501_state = { |
1863 | .name = "sm501-state", | |
1864 | .version_id = 1, | |
1865 | .minimum_version_id = 1, | |
1866 | .fields = (VMStateField[]) { | |
1867 | VMSTATE_UINT32(local_mem_size_index, SM501State), | |
1868 | VMSTATE_UINT32(system_control, SM501State), | |
1869 | VMSTATE_UINT32(misc_control, SM501State), | |
1870 | VMSTATE_UINT32(gpio_31_0_control, SM501State), | |
1871 | VMSTATE_UINT32(gpio_63_32_control, SM501State), | |
1872 | VMSTATE_UINT32(dram_control, SM501State), | |
1873 | VMSTATE_UINT32(arbitration_control, SM501State), | |
1874 | VMSTATE_UINT32(irq_mask, SM501State), | |
1875 | VMSTATE_UINT32(misc_timing, SM501State), | |
1876 | VMSTATE_UINT32(power_mode_control, SM501State), | |
1877 | VMSTATE_UINT32(uart0_ier, SM501State), | |
1878 | VMSTATE_UINT32(uart0_lcr, SM501State), | |
1879 | VMSTATE_UINT32(uart0_mcr, SM501State), | |
1880 | VMSTATE_UINT32(uart0_scr, SM501State), | |
1881 | VMSTATE_UINT8_ARRAY(dc_palette, SM501State, DC_PALETTE_ENTRIES), | |
1882 | VMSTATE_UINT32(dc_panel_control, SM501State), | |
1883 | VMSTATE_UINT32(dc_panel_panning_control, SM501State), | |
1884 | VMSTATE_UINT32(dc_panel_fb_addr, SM501State), | |
1885 | VMSTATE_UINT32(dc_panel_fb_offset, SM501State), | |
1886 | VMSTATE_UINT32(dc_panel_fb_width, SM501State), | |
1887 | VMSTATE_UINT32(dc_panel_fb_height, SM501State), | |
1888 | VMSTATE_UINT32(dc_panel_tl_location, SM501State), | |
1889 | VMSTATE_UINT32(dc_panel_br_location, SM501State), | |
1890 | VMSTATE_UINT32(dc_panel_h_total, SM501State), | |
1891 | VMSTATE_UINT32(dc_panel_h_sync, SM501State), | |
1892 | VMSTATE_UINT32(dc_panel_v_total, SM501State), | |
1893 | VMSTATE_UINT32(dc_panel_v_sync, SM501State), | |
1894 | VMSTATE_UINT32(dc_panel_hwc_addr, SM501State), | |
1895 | VMSTATE_UINT32(dc_panel_hwc_location, SM501State), | |
1896 | VMSTATE_UINT32(dc_panel_hwc_color_1_2, SM501State), | |
1897 | VMSTATE_UINT32(dc_panel_hwc_color_3, SM501State), | |
1898 | VMSTATE_UINT32(dc_video_control, SM501State), | |
1899 | VMSTATE_UINT32(dc_crt_control, SM501State), | |
1900 | VMSTATE_UINT32(dc_crt_fb_addr, SM501State), | |
1901 | VMSTATE_UINT32(dc_crt_fb_offset, SM501State), | |
1902 | VMSTATE_UINT32(dc_crt_h_total, SM501State), | |
1903 | VMSTATE_UINT32(dc_crt_h_sync, SM501State), | |
1904 | VMSTATE_UINT32(dc_crt_v_total, SM501State), | |
1905 | VMSTATE_UINT32(dc_crt_v_sync, SM501State), | |
1906 | VMSTATE_UINT32(dc_crt_hwc_addr, SM501State), | |
1907 | VMSTATE_UINT32(dc_crt_hwc_location, SM501State), | |
1908 | VMSTATE_UINT32(dc_crt_hwc_color_1_2, SM501State), | |
1909 | VMSTATE_UINT32(dc_crt_hwc_color_3, SM501State), | |
1910 | VMSTATE_UINT32(twoD_source, SM501State), | |
1911 | VMSTATE_UINT32(twoD_destination, SM501State), | |
1912 | VMSTATE_UINT32(twoD_dimension, SM501State), | |
1913 | VMSTATE_UINT32(twoD_control, SM501State), | |
1914 | VMSTATE_UINT32(twoD_pitch, SM501State), | |
1915 | VMSTATE_UINT32(twoD_foreground, SM501State), | |
1916 | VMSTATE_UINT32(twoD_background, SM501State), | |
1917 | VMSTATE_UINT32(twoD_stretch, SM501State), | |
1918 | VMSTATE_UINT32(twoD_color_compare, SM501State), | |
1919 | VMSTATE_UINT32(twoD_color_compare_mask, SM501State), | |
1920 | VMSTATE_UINT32(twoD_mask, SM501State), | |
1921 | VMSTATE_UINT32(twoD_clip_tl, SM501State), | |
1922 | VMSTATE_UINT32(twoD_clip_br, SM501State), | |
1923 | VMSTATE_UINT32(twoD_mono_pattern_low, SM501State), | |
1924 | VMSTATE_UINT32(twoD_mono_pattern_high, SM501State), | |
1925 | VMSTATE_UINT32(twoD_window_width, SM501State), | |
1926 | VMSTATE_UINT32(twoD_source_base, SM501State), | |
1927 | VMSTATE_UINT32(twoD_destination_base, SM501State), | |
1928 | VMSTATE_UINT32(twoD_alpha, SM501State), | |
1929 | VMSTATE_UINT32(twoD_wrap, SM501State), | |
4a1f253a BZ |
1930 | /* Added in version 2 */ |
1931 | VMSTATE_UINT8(i2c_byte_count, SM501State), | |
1932 | VMSTATE_UINT8(i2c_status, SM501State), | |
1933 | VMSTATE_UINT8(i2c_addr, SM501State), | |
1934 | VMSTATE_UINT8_ARRAY(i2c_data, SM501State, 16), | |
2edd6e4a BZ |
1935 | VMSTATE_END_OF_LIST() |
1936 | } | |
1937 | }; | |
1938 | ||
ca8a1104 BZ |
1939 | #define TYPE_SYSBUS_SM501 "sysbus-sm501" |
1940 | #define SYSBUS_SM501(obj) \ | |
1941 | OBJECT_CHECK(SM501SysBusState, (obj), TYPE_SYSBUS_SM501) | |
1942 | ||
1943 | typedef struct { | |
1944 | /*< private >*/ | |
1945 | SysBusDevice parent_obj; | |
1946 | /*< public >*/ | |
1947 | SM501State state; | |
1948 | uint32_t vram_size; | |
1949 | uint32_t base; | |
0ed40f16 | 1950 | SerialMM serial; |
ca8a1104 BZ |
1951 | } SM501SysBusState; |
1952 | ||
1953 | static void sm501_realize_sysbus(DeviceState *dev, Error **errp) | |
1954 | { | |
1955 | SM501SysBusState *s = SYSBUS_SM501(dev); | |
1956 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
1957 | DeviceState *usb_dev; | |
0ed40f16 | 1958 | MemoryRegion *mr; |
ca8a1104 | 1959 | |
c795fa84 | 1960 | sm501_init(&s->state, dev, s->vram_size); |
ca8a1104 BZ |
1961 | if (get_local_mem_size(&s->state) != s->vram_size) { |
1962 | error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32, | |
1963 | get_local_mem_size(&s->state)); | |
1964 | return; | |
1965 | } | |
1966 | sysbus_init_mmio(sbd, &s->state.local_mem_region); | |
1967 | sysbus_init_mmio(sbd, &s->state.mmio_region); | |
ffd39257 | 1968 | |
ac611340 | 1969 | /* bridge to usb host emulation module */ |
3e80f690 | 1970 | usb_dev = qdev_new("sysbus-ohci"); |
ca8a1104 BZ |
1971 | qdev_prop_set_uint32(usb_dev, "num-ports", 2); |
1972 | qdev_prop_set_uint64(usb_dev, "dma-offset", s->base); | |
3c6ef471 | 1973 | sysbus_realize_and_unref(SYS_BUS_DEVICE(usb_dev), &error_fatal); |
ca8a1104 BZ |
1974 | memory_region_add_subregion(&s->state.mmio_region, SM501_USB_HOST, |
1975 | sysbus_mmio_get_region(SYS_BUS_DEVICE(usb_dev), 0)); | |
1976 | sysbus_pass_irq(sbd, SYS_BUS_DEVICE(usb_dev)); | |
ac611340 | 1977 | |
ffd39257 | 1978 | /* bridge to serial emulation module */ |
5a147c8c | 1979 | sysbus_realize(SYS_BUS_DEVICE(&s->serial), &error_fatal); |
0ed40f16 MAL |
1980 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->serial), 0); |
1981 | memory_region_add_subregion(&s->state.mmio_region, SM501_UART0, mr); | |
1982 | /* TODO : chain irq to IRL */ | |
ca8a1104 | 1983 | } |
ffd39257 | 1984 | |
ca8a1104 BZ |
1985 | static Property sm501_sysbus_properties[] = { |
1986 | DEFINE_PROP_UINT32("vram-size", SM501SysBusState, vram_size, 0), | |
1987 | DEFINE_PROP_UINT32("base", SM501SysBusState, base, 0), | |
ca8a1104 BZ |
1988 | DEFINE_PROP_END_OF_LIST(), |
1989 | }; | |
1990 | ||
1991 | static void sm501_reset_sysbus(DeviceState *dev) | |
1992 | { | |
1993 | SM501SysBusState *s = SYSBUS_SM501(dev); | |
1994 | sm501_reset(&s->state); | |
ffd39257 | 1995 | } |
ca8a1104 | 1996 | |
2edd6e4a BZ |
1997 | static const VMStateDescription vmstate_sm501_sysbus = { |
1998 | .name = TYPE_SYSBUS_SM501, | |
4a1f253a BZ |
1999 | .version_id = 2, |
2000 | .minimum_version_id = 2, | |
2edd6e4a BZ |
2001 | .fields = (VMStateField[]) { |
2002 | VMSTATE_STRUCT(state, SM501SysBusState, 1, | |
2003 | vmstate_sm501_state, SM501State), | |
2004 | VMSTATE_END_OF_LIST() | |
2005 | } | |
2006 | }; | |
2007 | ||
ca8a1104 BZ |
2008 | static void sm501_sysbus_class_init(ObjectClass *klass, void *data) |
2009 | { | |
2010 | DeviceClass *dc = DEVICE_CLASS(klass); | |
2011 | ||
2012 | dc->realize = sm501_realize_sysbus; | |
2013 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); | |
2014 | dc->desc = "SM501 Multimedia Companion"; | |
4f67d30b | 2015 | device_class_set_props(dc, sm501_sysbus_properties); |
ca8a1104 | 2016 | dc->reset = sm501_reset_sysbus; |
2edd6e4a | 2017 | dc->vmsd = &vmstate_sm501_sysbus; |
0ed40f16 MAL |
2018 | } |
2019 | ||
2020 | static void sm501_sysbus_init(Object *o) | |
2021 | { | |
2022 | SM501SysBusState *sm501 = SYSBUS_SM501(o); | |
2023 | SerialMM *smm = &sm501->serial; | |
2024 | ||
5a147c8c | 2025 | object_initialize_child(o, "serial", smm, TYPE_SERIAL_MM); |
0ed40f16 MAL |
2026 | qdev_set_legacy_instance_id(DEVICE(smm), SM501_UART0, 2); |
2027 | qdev_prop_set_uint8(DEVICE(smm), "regshift", 2); | |
2028 | qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN); | |
2029 | ||
2030 | object_property_add_alias(o, "chardev", | |
d2623129 | 2031 | OBJECT(smm), "chardev"); |
ca8a1104 BZ |
2032 | } |
2033 | ||
2034 | static const TypeInfo sm501_sysbus_info = { | |
2035 | .name = TYPE_SYSBUS_SM501, | |
2036 | .parent = TYPE_SYS_BUS_DEVICE, | |
2037 | .instance_size = sizeof(SM501SysBusState), | |
2038 | .class_init = sm501_sysbus_class_init, | |
0ed40f16 | 2039 | .instance_init = sm501_sysbus_init, |
ca8a1104 BZ |
2040 | }; |
2041 | ||
efae2784 BZ |
2042 | #define TYPE_PCI_SM501 "sm501" |
2043 | #define PCI_SM501(obj) OBJECT_CHECK(SM501PCIState, (obj), TYPE_PCI_SM501) | |
2044 | ||
2045 | typedef struct { | |
2046 | /*< private >*/ | |
2047 | PCIDevice parent_obj; | |
2048 | /*< public >*/ | |
2049 | SM501State state; | |
2050 | uint32_t vram_size; | |
2051 | } SM501PCIState; | |
2052 | ||
2053 | static void sm501_realize_pci(PCIDevice *dev, Error **errp) | |
2054 | { | |
2055 | SM501PCIState *s = PCI_SM501(dev); | |
2056 | ||
2057 | sm501_init(&s->state, DEVICE(dev), s->vram_size); | |
2058 | if (get_local_mem_size(&s->state) != s->vram_size) { | |
2059 | error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32, | |
2060 | get_local_mem_size(&s->state)); | |
2061 | return; | |
2062 | } | |
2063 | pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, | |
2064 | &s->state.local_mem_region); | |
2065 | pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, | |
2066 | &s->state.mmio_region); | |
2067 | } | |
2068 | ||
2069 | static Property sm501_pci_properties[] = { | |
d23b6caa | 2070 | DEFINE_PROP_UINT32("vram-size", SM501PCIState, vram_size, 64 * MiB), |
efae2784 BZ |
2071 | DEFINE_PROP_END_OF_LIST(), |
2072 | }; | |
2073 | ||
2074 | static void sm501_reset_pci(DeviceState *dev) | |
2075 | { | |
2076 | SM501PCIState *s = PCI_SM501(dev); | |
2077 | sm501_reset(&s->state); | |
2078 | /* Bits 2:0 of misc_control register is 001 for PCI */ | |
2079 | s->state.misc_control |= 1; | |
2080 | } | |
2081 | ||
2edd6e4a BZ |
2082 | static const VMStateDescription vmstate_sm501_pci = { |
2083 | .name = TYPE_PCI_SM501, | |
4a1f253a BZ |
2084 | .version_id = 2, |
2085 | .minimum_version_id = 2, | |
2edd6e4a BZ |
2086 | .fields = (VMStateField[]) { |
2087 | VMSTATE_PCI_DEVICE(parent_obj, SM501PCIState), | |
2088 | VMSTATE_STRUCT(state, SM501PCIState, 1, | |
2089 | vmstate_sm501_state, SM501State), | |
2090 | VMSTATE_END_OF_LIST() | |
2091 | } | |
2092 | }; | |
2093 | ||
efae2784 BZ |
2094 | static void sm501_pci_class_init(ObjectClass *klass, void *data) |
2095 | { | |
2096 | DeviceClass *dc = DEVICE_CLASS(klass); | |
2097 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
2098 | ||
2099 | k->realize = sm501_realize_pci; | |
2100 | k->vendor_id = PCI_VENDOR_ID_SILICON_MOTION; | |
2101 | k->device_id = PCI_DEVICE_ID_SM501; | |
2102 | k->class_id = PCI_CLASS_DISPLAY_OTHER; | |
2103 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); | |
2104 | dc->desc = "SM501 Display Controller"; | |
4f67d30b | 2105 | device_class_set_props(dc, sm501_pci_properties); |
efae2784 BZ |
2106 | dc->reset = sm501_reset_pci; |
2107 | dc->hotpluggable = false; | |
2edd6e4a | 2108 | dc->vmsd = &vmstate_sm501_pci; |
efae2784 BZ |
2109 | } |
2110 | ||
2111 | static const TypeInfo sm501_pci_info = { | |
2112 | .name = TYPE_PCI_SM501, | |
2113 | .parent = TYPE_PCI_DEVICE, | |
2114 | .instance_size = sizeof(SM501PCIState), | |
2115 | .class_init = sm501_pci_class_init, | |
fd3b02c8 EH |
2116 | .interfaces = (InterfaceInfo[]) { |
2117 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
2118 | { }, | |
2119 | }, | |
efae2784 BZ |
2120 | }; |
2121 | ||
ca8a1104 BZ |
2122 | static void sm501_register_types(void) |
2123 | { | |
2124 | type_register_static(&sm501_sysbus_info); | |
efae2784 | 2125 | type_register_static(&sm501_pci_info); |
ca8a1104 BZ |
2126 | } |
2127 | ||
2128 | type_init(sm501_register_types) |