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1 | /* |
2 | * QEMU SM501 Device | |
3 | * | |
4 | * Copyright (c) 2008 Shin-ichiro KAWASAKI | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
47df5154 | 25 | #include "qemu/osdep.h" |
e2ee8476 | 26 | #include "qemu/cutils.h" |
da34e65c | 27 | #include "qapi/error.h" |
4771d756 PB |
28 | #include "qemu-common.h" |
29 | #include "cpu.h" | |
83c9f4ca | 30 | #include "hw/hw.h" |
0d09e41a | 31 | #include "hw/char/serial.h" |
28ecbaee | 32 | #include "ui/console.h" |
bd2be150 | 33 | #include "hw/devices.h" |
83c9f4ca | 34 | #include "hw/sysbus.h" |
1de7afc9 | 35 | #include "qemu/range.h" |
28ecbaee | 36 | #include "ui/pixel_ops.h" |
2c17449b | 37 | #include "exec/address-spaces.h" |
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38 | |
39 | /* | |
604be200 | 40 | * Status: 2010/05/07 |
ffd39257 | 41 | * - Minimum implementation for Linux console : mmio regs and CRT layer. |
64f1603b | 42 | * - 2D graphics acceleration partially supported : only fill rectangle. |
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43 | * |
44 | * TODO: | |
45 | * - Panel support | |
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46 | * - Touch panel support |
47 | * - USB support | |
48 | * - UART support | |
604be200 | 49 | * - More 2D graphics engine support |
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50 | * - Performance tuning |
51 | */ | |
52 | ||
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53 | /*#define DEBUG_SM501*/ |
54 | /*#define DEBUG_BITBLT*/ | |
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55 | |
56 | #ifdef DEBUG_SM501 | |
001faf32 | 57 | #define SM501_DPRINTF(fmt, ...) printf(fmt, ## __VA_ARGS__) |
ffd39257 | 58 | #else |
64f1603b | 59 | #define SM501_DPRINTF(fmt, ...) do {} while (0) |
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60 | #endif |
61 | ||
62 | ||
63 | #define MMIO_BASE_OFFSET 0x3e00000 | |
64 | ||
65 | /* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */ | |
66 | ||
67 | /* System Configuration area */ | |
68 | /* System config base */ | |
64f1603b | 69 | #define SM501_SYS_CONFIG (0x000000) |
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70 | |
71 | /* config 1 */ | |
64f1603b | 72 | #define SM501_SYSTEM_CONTROL (0x000000) |
ffd39257 | 73 | |
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74 | #define SM501_SYSCTRL_PANEL_TRISTATE (1 << 0) |
75 | #define SM501_SYSCTRL_MEM_TRISTATE (1 << 1) | |
76 | #define SM501_SYSCTRL_CRT_TRISTATE (1 << 2) | |
ffd39257 | 77 | |
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78 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3 << 4) |
79 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0 << 4) | |
80 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1 << 4) | |
81 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2 << 4) | |
82 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3 << 4) | |
ffd39257 | 83 | |
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84 | #define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1 << 6) |
85 | #define SM501_SYSCTRL_PCI_RETRY_DISABLE (1 << 7) | |
86 | #define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1 << 11) | |
87 | #define SM501_SYSCTRL_PCI_BURST_READ_EN (1 << 15) | |
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88 | |
89 | /* miscellaneous control */ | |
90 | ||
64f1603b | 91 | #define SM501_MISC_CONTROL (0x000004) |
ffd39257 | 92 | |
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93 | #define SM501_MISC_BUS_SH (0x0) |
94 | #define SM501_MISC_BUS_PCI (0x1) | |
95 | #define SM501_MISC_BUS_XSCALE (0x2) | |
96 | #define SM501_MISC_BUS_NEC (0x6) | |
97 | #define SM501_MISC_BUS_MASK (0x7) | |
ffd39257 | 98 | |
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99 | #define SM501_MISC_VR_62MB (1 << 3) |
100 | #define SM501_MISC_CDR_RESET (1 << 7) | |
101 | #define SM501_MISC_USB_LB (1 << 8) | |
102 | #define SM501_MISC_USB_SLAVE (1 << 9) | |
103 | #define SM501_MISC_BL_1 (1 << 10) | |
104 | #define SM501_MISC_MC (1 << 11) | |
105 | #define SM501_MISC_DAC_POWER (1 << 12) | |
106 | #define SM501_MISC_IRQ_INVERT (1 << 16) | |
107 | #define SM501_MISC_SH (1 << 17) | |
ffd39257 | 108 | |
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109 | #define SM501_MISC_HOLD_EMPTY (0 << 18) |
110 | #define SM501_MISC_HOLD_8 (1 << 18) | |
111 | #define SM501_MISC_HOLD_16 (2 << 18) | |
112 | #define SM501_MISC_HOLD_24 (3 << 18) | |
113 | #define SM501_MISC_HOLD_32 (4 << 18) | |
114 | #define SM501_MISC_HOLD_MASK (7 << 18) | |
ffd39257 | 115 | |
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116 | #define SM501_MISC_FREQ_12 (1 << 24) |
117 | #define SM501_MISC_PNL_24BIT (1 << 25) | |
118 | #define SM501_MISC_8051_LE (1 << 26) | |
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119 | |
120 | ||
121 | ||
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122 | #define SM501_GPIO31_0_CONTROL (0x000008) |
123 | #define SM501_GPIO63_32_CONTROL (0x00000C) | |
124 | #define SM501_DRAM_CONTROL (0x000010) | |
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125 | |
126 | /* command list */ | |
64f1603b | 127 | #define SM501_ARBTRTN_CONTROL (0x000014) |
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128 | |
129 | /* command list */ | |
64f1603b | 130 | #define SM501_COMMAND_LIST_STATUS (0x000024) |
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131 | |
132 | /* interrupt debug */ | |
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133 | #define SM501_RAW_IRQ_STATUS (0x000028) |
134 | #define SM501_RAW_IRQ_CLEAR (0x000028) | |
135 | #define SM501_IRQ_STATUS (0x00002C) | |
136 | #define SM501_IRQ_MASK (0x000030) | |
137 | #define SM501_DEBUG_CONTROL (0x000034) | |
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138 | |
139 | /* power management */ | |
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140 | #define SM501_POWERMODE_P2X_SRC (1 << 29) |
141 | #define SM501_POWERMODE_V2X_SRC (1 << 20) | |
142 | #define SM501_POWERMODE_M_SRC (1 << 12) | |
143 | #define SM501_POWERMODE_M1_SRC (1 << 4) | |
144 | ||
145 | #define SM501_CURRENT_GATE (0x000038) | |
146 | #define SM501_CURRENT_CLOCK (0x00003C) | |
147 | #define SM501_POWER_MODE_0_GATE (0x000040) | |
148 | #define SM501_POWER_MODE_0_CLOCK (0x000044) | |
149 | #define SM501_POWER_MODE_1_GATE (0x000048) | |
150 | #define SM501_POWER_MODE_1_CLOCK (0x00004C) | |
151 | #define SM501_SLEEP_MODE_GATE (0x000050) | |
152 | #define SM501_POWER_MODE_CONTROL (0x000054) | |
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153 | |
154 | /* power gates for units within the 501 */ | |
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155 | #define SM501_GATE_HOST (0) |
156 | #define SM501_GATE_MEMORY (1) | |
157 | #define SM501_GATE_DISPLAY (2) | |
158 | #define SM501_GATE_2D_ENGINE (3) | |
159 | #define SM501_GATE_CSC (4) | |
160 | #define SM501_GATE_ZVPORT (5) | |
161 | #define SM501_GATE_GPIO (6) | |
162 | #define SM501_GATE_UART0 (7) | |
163 | #define SM501_GATE_UART1 (8) | |
164 | #define SM501_GATE_SSP (10) | |
165 | #define SM501_GATE_USB_HOST (11) | |
166 | #define SM501_GATE_USB_GADGET (12) | |
167 | #define SM501_GATE_UCONTROLLER (17) | |
168 | #define SM501_GATE_AC97 (18) | |
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169 | |
170 | /* panel clock */ | |
64f1603b | 171 | #define SM501_CLOCK_P2XCLK (24) |
ffd39257 | 172 | /* crt clock */ |
64f1603b | 173 | #define SM501_CLOCK_V2XCLK (16) |
ffd39257 | 174 | /* main clock */ |
64f1603b | 175 | #define SM501_CLOCK_MCLK (8) |
ffd39257 | 176 | /* SDRAM controller clock */ |
64f1603b | 177 | #define SM501_CLOCK_M1XCLK (0) |
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178 | |
179 | /* config 2 */ | |
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180 | #define SM501_PCI_MASTER_BASE (0x000058) |
181 | #define SM501_ENDIAN_CONTROL (0x00005C) | |
182 | #define SM501_DEVICEID (0x000060) | |
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183 | /* 0x050100A0 */ |
184 | ||
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185 | #define SM501_DEVICEID_SM501 (0x05010000) |
186 | #define SM501_DEVICEID_IDMASK (0xffff0000) | |
187 | #define SM501_DEVICEID_REVMASK (0x000000ff) | |
ffd39257 | 188 | |
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189 | #define SM501_PLLCLOCK_COUNT (0x000064) |
190 | #define SM501_MISC_TIMING (0x000068) | |
191 | #define SM501_CURRENT_SDRAM_CLOCK (0x00006C) | |
ffd39257 | 192 | |
64f1603b | 193 | #define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074) |
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194 | |
195 | /* GPIO base */ | |
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196 | #define SM501_GPIO (0x010000) |
197 | #define SM501_GPIO_DATA_LOW (0x00) | |
198 | #define SM501_GPIO_DATA_HIGH (0x04) | |
199 | #define SM501_GPIO_DDR_LOW (0x08) | |
200 | #define SM501_GPIO_DDR_HIGH (0x0C) | |
201 | #define SM501_GPIO_IRQ_SETUP (0x10) | |
202 | #define SM501_GPIO_IRQ_STATUS (0x14) | |
203 | #define SM501_GPIO_IRQ_RESET (0x14) | |
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204 | |
205 | /* I2C controller base */ | |
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206 | #define SM501_I2C (0x010040) |
207 | #define SM501_I2C_BYTE_COUNT (0x00) | |
208 | #define SM501_I2C_CONTROL (0x01) | |
209 | #define SM501_I2C_STATUS (0x02) | |
210 | #define SM501_I2C_RESET (0x02) | |
211 | #define SM501_I2C_SLAVE_ADDRESS (0x03) | |
212 | #define SM501_I2C_DATA (0x04) | |
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213 | |
214 | /* SSP base */ | |
64f1603b | 215 | #define SM501_SSP (0x020000) |
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216 | |
217 | /* Uart 0 base */ | |
64f1603b | 218 | #define SM501_UART0 (0x030000) |
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219 | |
220 | /* Uart 1 base */ | |
64f1603b | 221 | #define SM501_UART1 (0x030020) |
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222 | |
223 | /* USB host port base */ | |
64f1603b | 224 | #define SM501_USB_HOST (0x040000) |
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225 | |
226 | /* USB slave/gadget base */ | |
64f1603b | 227 | #define SM501_USB_GADGET (0x060000) |
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228 | |
229 | /* USB slave/gadget data port base */ | |
64f1603b | 230 | #define SM501_USB_GADGET_DATA (0x070000) |
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231 | |
232 | /* Display controller/video engine base */ | |
64f1603b | 233 | #define SM501_DC (0x080000) |
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234 | |
235 | /* common defines for the SM501 address registers */ | |
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236 | #define SM501_ADDR_FLIP (1 << 31) |
237 | #define SM501_ADDR_EXT (1 << 27) | |
238 | #define SM501_ADDR_CS1 (1 << 26) | |
239 | #define SM501_ADDR_MASK (0x3f << 26) | |
ffd39257 | 240 | |
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241 | #define SM501_FIFO_MASK (0x3 << 16) |
242 | #define SM501_FIFO_1 (0x0 << 16) | |
243 | #define SM501_FIFO_3 (0x1 << 16) | |
244 | #define SM501_FIFO_7 (0x2 << 16) | |
245 | #define SM501_FIFO_11 (0x3 << 16) | |
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246 | |
247 | /* common registers for panel and the crt */ | |
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248 | #define SM501_OFF_DC_H_TOT (0x000) |
249 | #define SM501_OFF_DC_V_TOT (0x008) | |
250 | #define SM501_OFF_DC_H_SYNC (0x004) | |
251 | #define SM501_OFF_DC_V_SYNC (0x00C) | |
252 | ||
253 | #define SM501_DC_PANEL_CONTROL (0x000) | |
254 | ||
255 | #define SM501_DC_PANEL_CONTROL_FPEN (1 << 27) | |
256 | #define SM501_DC_PANEL_CONTROL_BIAS (1 << 26) | |
257 | #define SM501_DC_PANEL_CONTROL_DATA (1 << 25) | |
258 | #define SM501_DC_PANEL_CONTROL_VDD (1 << 24) | |
259 | #define SM501_DC_PANEL_CONTROL_DP (1 << 23) | |
260 | ||
261 | #define SM501_DC_PANEL_CONTROL_TFT_888 (0 << 21) | |
262 | #define SM501_DC_PANEL_CONTROL_TFT_333 (1 << 21) | |
263 | #define SM501_DC_PANEL_CONTROL_TFT_444 (2 << 21) | |
264 | ||
265 | #define SM501_DC_PANEL_CONTROL_DE (1 << 20) | |
266 | ||
267 | #define SM501_DC_PANEL_CONTROL_LCD_TFT (0 << 18) | |
268 | #define SM501_DC_PANEL_CONTROL_LCD_STN8 (1 << 18) | |
269 | #define SM501_DC_PANEL_CONTROL_LCD_STN12 (2 << 18) | |
270 | ||
271 | #define SM501_DC_PANEL_CONTROL_CP (1 << 14) | |
272 | #define SM501_DC_PANEL_CONTROL_VSP (1 << 13) | |
273 | #define SM501_DC_PANEL_CONTROL_HSP (1 << 12) | |
274 | #define SM501_DC_PANEL_CONTROL_CK (1 << 9) | |
275 | #define SM501_DC_PANEL_CONTROL_TE (1 << 8) | |
276 | #define SM501_DC_PANEL_CONTROL_VPD (1 << 7) | |
277 | #define SM501_DC_PANEL_CONTROL_VP (1 << 6) | |
278 | #define SM501_DC_PANEL_CONTROL_HPD (1 << 5) | |
279 | #define SM501_DC_PANEL_CONTROL_HP (1 << 4) | |
280 | #define SM501_DC_PANEL_CONTROL_GAMMA (1 << 3) | |
281 | #define SM501_DC_PANEL_CONTROL_EN (1 << 2) | |
282 | ||
283 | #define SM501_DC_PANEL_CONTROL_8BPP (0 << 0) | |
284 | #define SM501_DC_PANEL_CONTROL_16BPP (1 << 0) | |
285 | #define SM501_DC_PANEL_CONTROL_32BPP (2 << 0) | |
286 | ||
287 | ||
288 | #define SM501_DC_PANEL_PANNING_CONTROL (0x004) | |
289 | #define SM501_DC_PANEL_COLOR_KEY (0x008) | |
290 | #define SM501_DC_PANEL_FB_ADDR (0x00C) | |
291 | #define SM501_DC_PANEL_FB_OFFSET (0x010) | |
292 | #define SM501_DC_PANEL_FB_WIDTH (0x014) | |
293 | #define SM501_DC_PANEL_FB_HEIGHT (0x018) | |
294 | #define SM501_DC_PANEL_TL_LOC (0x01C) | |
295 | #define SM501_DC_PANEL_BR_LOC (0x020) | |
296 | #define SM501_DC_PANEL_H_TOT (0x024) | |
297 | #define SM501_DC_PANEL_H_SYNC (0x028) | |
298 | #define SM501_DC_PANEL_V_TOT (0x02C) | |
299 | #define SM501_DC_PANEL_V_SYNC (0x030) | |
300 | #define SM501_DC_PANEL_CUR_LINE (0x034) | |
301 | ||
302 | #define SM501_DC_VIDEO_CONTROL (0x040) | |
303 | #define SM501_DC_VIDEO_FB0_ADDR (0x044) | |
304 | #define SM501_DC_VIDEO_FB_WIDTH (0x048) | |
305 | #define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C) | |
306 | #define SM501_DC_VIDEO_TL_LOC (0x050) | |
307 | #define SM501_DC_VIDEO_BR_LOC (0x054) | |
308 | #define SM501_DC_VIDEO_SCALE (0x058) | |
309 | #define SM501_DC_VIDEO_INIT_SCALE (0x05C) | |
310 | #define SM501_DC_VIDEO_YUV_CONSTANTS (0x060) | |
311 | #define SM501_DC_VIDEO_FB1_ADDR (0x064) | |
312 | #define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068) | |
313 | ||
314 | #define SM501_DC_VIDEO_ALPHA_CONTROL (0x080) | |
315 | #define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084) | |
316 | #define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088) | |
317 | #define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C) | |
318 | #define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090) | |
319 | #define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094) | |
320 | #define SM501_DC_VIDEO_ALPHA_SCALE (0x098) | |
321 | #define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C) | |
322 | #define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0) | |
323 | #define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4) | |
324 | ||
325 | #define SM501_DC_PANEL_HWC_BASE (0x0F0) | |
326 | #define SM501_DC_PANEL_HWC_ADDR (0x0F0) | |
327 | #define SM501_DC_PANEL_HWC_LOC (0x0F4) | |
328 | #define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8) | |
329 | #define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC) | |
330 | ||
331 | #define SM501_HWC_EN (1 << 31) | |
332 | ||
333 | #define SM501_OFF_HWC_ADDR (0x00) | |
334 | #define SM501_OFF_HWC_LOC (0x04) | |
335 | #define SM501_OFF_HWC_COLOR_1_2 (0x08) | |
336 | #define SM501_OFF_HWC_COLOR_3 (0x0C) | |
337 | ||
338 | #define SM501_DC_ALPHA_CONTROL (0x100) | |
339 | #define SM501_DC_ALPHA_FB_ADDR (0x104) | |
340 | #define SM501_DC_ALPHA_FB_OFFSET (0x108) | |
341 | #define SM501_DC_ALPHA_TL_LOC (0x10C) | |
342 | #define SM501_DC_ALPHA_BR_LOC (0x110) | |
343 | #define SM501_DC_ALPHA_CHROMA_KEY (0x114) | |
344 | #define SM501_DC_ALPHA_COLOR_LOOKUP (0x118) | |
345 | ||
346 | #define SM501_DC_CRT_CONTROL (0x200) | |
347 | ||
348 | #define SM501_DC_CRT_CONTROL_TVP (1 << 15) | |
349 | #define SM501_DC_CRT_CONTROL_CP (1 << 14) | |
350 | #define SM501_DC_CRT_CONTROL_VSP (1 << 13) | |
351 | #define SM501_DC_CRT_CONTROL_HSP (1 << 12) | |
352 | #define SM501_DC_CRT_CONTROL_VS (1 << 11) | |
353 | #define SM501_DC_CRT_CONTROL_BLANK (1 << 10) | |
354 | #define SM501_DC_CRT_CONTROL_SEL (1 << 9) | |
355 | #define SM501_DC_CRT_CONTROL_TE (1 << 8) | |
ffd39257 | 356 | #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4) |
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357 | #define SM501_DC_CRT_CONTROL_GAMMA (1 << 3) |
358 | #define SM501_DC_CRT_CONTROL_ENABLE (1 << 2) | |
ffd39257 | 359 | |
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360 | #define SM501_DC_CRT_CONTROL_8BPP (0 << 0) |
361 | #define SM501_DC_CRT_CONTROL_16BPP (1 << 0) | |
362 | #define SM501_DC_CRT_CONTROL_32BPP (2 << 0) | |
ffd39257 | 363 | |
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364 | #define SM501_DC_CRT_FB_ADDR (0x204) |
365 | #define SM501_DC_CRT_FB_OFFSET (0x208) | |
366 | #define SM501_DC_CRT_H_TOT (0x20C) | |
367 | #define SM501_DC_CRT_H_SYNC (0x210) | |
368 | #define SM501_DC_CRT_V_TOT (0x214) | |
369 | #define SM501_DC_CRT_V_SYNC (0x218) | |
370 | #define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C) | |
371 | #define SM501_DC_CRT_CUR_LINE (0x220) | |
372 | #define SM501_DC_CRT_MONITOR_DETECT (0x224) | |
ffd39257 | 373 | |
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374 | #define SM501_DC_CRT_HWC_BASE (0x230) |
375 | #define SM501_DC_CRT_HWC_ADDR (0x230) | |
376 | #define SM501_DC_CRT_HWC_LOC (0x234) | |
377 | #define SM501_DC_CRT_HWC_COLOR_1_2 (0x238) | |
378 | #define SM501_DC_CRT_HWC_COLOR_3 (0x23C) | |
ffd39257 | 379 | |
64f1603b | 380 | #define SM501_DC_PANEL_PALETTE (0x400) |
ffd39257 | 381 | |
64f1603b | 382 | #define SM501_DC_VIDEO_PALETTE (0x800) |
ffd39257 | 383 | |
64f1603b | 384 | #define SM501_DC_CRT_PALETTE (0xC00) |
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385 | |
386 | /* Zoom Video port base */ | |
64f1603b | 387 | #define SM501_ZVPORT (0x090000) |
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388 | |
389 | /* AC97/I2S base */ | |
64f1603b | 390 | #define SM501_AC97 (0x0A0000) |
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391 | |
392 | /* 8051 micro controller base */ | |
64f1603b | 393 | #define SM501_UCONTROLLER (0x0B0000) |
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394 | |
395 | /* 8051 micro controller SRAM base */ | |
64f1603b | 396 | #define SM501_UCONTROLLER_SRAM (0x0C0000) |
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397 | |
398 | /* DMA base */ | |
64f1603b | 399 | #define SM501_DMA (0x0D0000) |
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400 | |
401 | /* 2d engine base */ | |
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402 | #define SM501_2D_ENGINE (0x100000) |
403 | #define SM501_2D_SOURCE (0x00) | |
404 | #define SM501_2D_DESTINATION (0x04) | |
405 | #define SM501_2D_DIMENSION (0x08) | |
406 | #define SM501_2D_CONTROL (0x0C) | |
407 | #define SM501_2D_PITCH (0x10) | |
408 | #define SM501_2D_FOREGROUND (0x14) | |
409 | #define SM501_2D_BACKGROUND (0x18) | |
410 | #define SM501_2D_STRETCH (0x1C) | |
411 | #define SM501_2D_COLOR_COMPARE (0x20) | |
412 | #define SM501_2D_COLOR_COMPARE_MASK (0x24) | |
413 | #define SM501_2D_MASK (0x28) | |
414 | #define SM501_2D_CLIP_TL (0x2C) | |
415 | #define SM501_2D_CLIP_BR (0x30) | |
416 | #define SM501_2D_MONO_PATTERN_LOW (0x34) | |
417 | #define SM501_2D_MONO_PATTERN_HIGH (0x38) | |
418 | #define SM501_2D_WINDOW_WIDTH (0x3C) | |
419 | #define SM501_2D_SOURCE_BASE (0x40) | |
420 | #define SM501_2D_DESTINATION_BASE (0x44) | |
421 | #define SM501_2D_ALPHA (0x48) | |
422 | #define SM501_2D_WRAP (0x4C) | |
423 | #define SM501_2D_STATUS (0x50) | |
424 | ||
425 | #define SM501_CSC_Y_SOURCE_BASE (0xC8) | |
426 | #define SM501_CSC_CONSTANTS (0xCC) | |
427 | #define SM501_CSC_Y_SOURCE_X (0xD0) | |
428 | #define SM501_CSC_Y_SOURCE_Y (0xD4) | |
429 | #define SM501_CSC_U_SOURCE_BASE (0xD8) | |
430 | #define SM501_CSC_V_SOURCE_BASE (0xDC) | |
431 | #define SM501_CSC_SOURCE_DIMENSION (0xE0) | |
432 | #define SM501_CSC_SOURCE_PITCH (0xE4) | |
433 | #define SM501_CSC_DESTINATION (0xE8) | |
434 | #define SM501_CSC_DESTINATION_DIMENSION (0xEC) | |
435 | #define SM501_CSC_DESTINATION_PITCH (0xF0) | |
436 | #define SM501_CSC_SCALE_FACTOR (0xF4) | |
437 | #define SM501_CSC_DESTINATION_BASE (0xF8) | |
438 | #define SM501_CSC_CONTROL (0xFC) | |
ffd39257 BS |
439 | |
440 | /* 2d engine data port base */ | |
64f1603b | 441 | #define SM501_2D_ENGINE_DATA (0x110000) |
ffd39257 BS |
442 | |
443 | /* end of register definitions */ | |
444 | ||
0a4e7cd2 SK |
445 | #define SM501_HWC_WIDTH (64) |
446 | #define SM501_HWC_HEIGHT (64) | |
ffd39257 BS |
447 | |
448 | /* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */ | |
449 | static const uint32_t sm501_mem_local_size[] = { | |
e2ee8476 BZ |
450 | [0] = 4 * M_BYTE, |
451 | [1] = 8 * M_BYTE, | |
452 | [2] = 16 * M_BYTE, | |
453 | [3] = 32 * M_BYTE, | |
454 | [4] = 64 * M_BYTE, | |
455 | [5] = 2 * M_BYTE, | |
ffd39257 BS |
456 | }; |
457 | #define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index] | |
458 | ||
459 | typedef struct SM501State { | |
460 | /* graphic console status */ | |
c78f7137 | 461 | QemuConsole *con; |
ffd39257 BS |
462 | |
463 | /* status & internal resources */ | |
a8170e5e | 464 | hwaddr base; |
ffd39257 | 465 | uint32_t local_mem_size_index; |
64f1603b | 466 | uint8_t *local_mem; |
25793bfa | 467 | MemoryRegion local_mem_region; |
ffd39257 BS |
468 | uint32_t last_width; |
469 | uint32_t last_height; | |
470 | ||
471 | /* mmio registers */ | |
472 | uint32_t system_control; | |
473 | uint32_t misc_control; | |
474 | uint32_t gpio_31_0_control; | |
475 | uint32_t gpio_63_32_control; | |
476 | uint32_t dram_control; | |
477 | uint32_t irq_mask; | |
478 | uint32_t misc_timing; | |
479 | uint32_t power_mode_control; | |
480 | ||
481 | uint32_t uart0_ier; | |
482 | uint32_t uart0_lcr; | |
483 | uint32_t uart0_mcr; | |
484 | uint32_t uart0_scr; | |
485 | ||
486 | uint8_t dc_palette[0x400 * 3]; | |
487 | ||
488 | uint32_t dc_panel_control; | |
489 | uint32_t dc_panel_panning_control; | |
490 | uint32_t dc_panel_fb_addr; | |
491 | uint32_t dc_panel_fb_offset; | |
492 | uint32_t dc_panel_fb_width; | |
493 | uint32_t dc_panel_fb_height; | |
494 | uint32_t dc_panel_tl_location; | |
495 | uint32_t dc_panel_br_location; | |
496 | uint32_t dc_panel_h_total; | |
497 | uint32_t dc_panel_h_sync; | |
498 | uint32_t dc_panel_v_total; | |
499 | uint32_t dc_panel_v_sync; | |
500 | ||
501 | uint32_t dc_panel_hwc_addr; | |
502 | uint32_t dc_panel_hwc_location; | |
503 | uint32_t dc_panel_hwc_color_1_2; | |
504 | uint32_t dc_panel_hwc_color_3; | |
505 | ||
506 | uint32_t dc_crt_control; | |
507 | uint32_t dc_crt_fb_addr; | |
508 | uint32_t dc_crt_fb_offset; | |
509 | uint32_t dc_crt_h_total; | |
510 | uint32_t dc_crt_h_sync; | |
511 | uint32_t dc_crt_v_total; | |
512 | uint32_t dc_crt_v_sync; | |
513 | ||
514 | uint32_t dc_crt_hwc_addr; | |
515 | uint32_t dc_crt_hwc_location; | |
516 | uint32_t dc_crt_hwc_color_1_2; | |
517 | uint32_t dc_crt_hwc_color_3; | |
518 | ||
07d8a50c | 519 | uint32_t twoD_source; |
604be200 SK |
520 | uint32_t twoD_destination; |
521 | uint32_t twoD_dimension; | |
522 | uint32_t twoD_control; | |
523 | uint32_t twoD_pitch; | |
524 | uint32_t twoD_foreground; | |
525 | uint32_t twoD_stretch; | |
526 | uint32_t twoD_color_compare_mask; | |
527 | uint32_t twoD_mask; | |
528 | uint32_t twoD_window_width; | |
529 | uint32_t twoD_source_base; | |
530 | uint32_t twoD_destination_base; | |
531 | ||
ffd39257 BS |
532 | } SM501State; |
533 | ||
534 | static uint32_t get_local_mem_size_index(uint32_t size) | |
535 | { | |
536 | uint32_t norm_size = 0; | |
537 | int i, index = 0; | |
538 | ||
b1503cda | 539 | for (i = 0; i < ARRAY_SIZE(sm501_mem_local_size); i++) { |
64f1603b BZ |
540 | uint32_t new_size = sm501_mem_local_size[i]; |
541 | if (new_size >= size) { | |
542 | if (norm_size == 0 || norm_size > new_size) { | |
543 | norm_size = new_size; | |
544 | index = i; | |
545 | } | |
546 | } | |
ffd39257 BS |
547 | } |
548 | ||
549 | return index; | |
550 | } | |
551 | ||
0a4e7cd2 SK |
552 | /** |
553 | * Check the availability of hardware cursor. | |
554 | * @param crt 0 for PANEL, 1 for CRT. | |
555 | */ | |
556 | static inline int is_hwc_enabled(SM501State *state, int crt) | |
557 | { | |
558 | uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr; | |
e2ee8476 | 559 | return addr & SM501_HWC_EN; |
0a4e7cd2 SK |
560 | } |
561 | ||
562 | /** | |
563 | * Get the address which holds cursor pattern data. | |
564 | * @param crt 0 for PANEL, 1 for CRT. | |
565 | */ | |
566 | static inline uint32_t get_hwc_address(SM501State *state, int crt) | |
567 | { | |
568 | uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr; | |
569 | return (addr & 0x03FFFFF0)/* >> 4*/; | |
570 | } | |
571 | ||
572 | /** | |
573 | * Get the cursor position in y coordinate. | |
574 | * @param crt 0 for PANEL, 1 for CRT. | |
575 | */ | |
576 | static inline uint32_t get_hwc_y(SM501State *state, int crt) | |
577 | { | |
578 | uint32_t location = crt ? state->dc_crt_hwc_location | |
579 | : state->dc_panel_hwc_location; | |
580 | return (location & 0x07FF0000) >> 16; | |
581 | } | |
582 | ||
583 | /** | |
584 | * Get the cursor position in x coordinate. | |
585 | * @param crt 0 for PANEL, 1 for CRT. | |
586 | */ | |
587 | static inline uint32_t get_hwc_x(SM501State *state, int crt) | |
588 | { | |
589 | uint32_t location = crt ? state->dc_crt_hwc_location | |
590 | : state->dc_panel_hwc_location; | |
591 | return location & 0x000007FF; | |
592 | } | |
593 | ||
594 | /** | |
595 | * Get the cursor position in x coordinate. | |
596 | * @param crt 0 for PANEL, 1 for CRT. | |
597 | * @param index 0, 1, 2 or 3 which specifies color of corsor dot. | |
598 | */ | |
599 | static inline uint16_t get_hwc_color(SM501State *state, int crt, int index) | |
600 | { | |
c2780865 | 601 | uint32_t color_reg = 0; |
0a4e7cd2 SK |
602 | uint16_t color_565 = 0; |
603 | ||
604 | if (index == 0) { | |
605 | return 0; | |
606 | } | |
607 | ||
608 | switch (index) { | |
609 | case 1: | |
610 | case 2: | |
611 | color_reg = crt ? state->dc_crt_hwc_color_1_2 | |
612 | : state->dc_panel_hwc_color_1_2; | |
613 | break; | |
614 | case 3: | |
615 | color_reg = crt ? state->dc_crt_hwc_color_3 | |
616 | : state->dc_panel_hwc_color_3; | |
617 | break; | |
618 | default: | |
619 | printf("invalid hw cursor color.\n"); | |
43dc2a64 | 620 | abort(); |
0a4e7cd2 SK |
621 | } |
622 | ||
623 | switch (index) { | |
624 | case 1: | |
625 | case 3: | |
626 | color_565 = (uint16_t)(color_reg & 0xFFFF); | |
627 | break; | |
628 | case 2: | |
629 | color_565 = (uint16_t)((color_reg >> 16) & 0xFFFF); | |
630 | break; | |
631 | } | |
632 | return color_565; | |
633 | } | |
634 | ||
635 | static int within_hwc_y_range(SM501State *state, int y, int crt) | |
636 | { | |
637 | int hwc_y = get_hwc_y(state, crt); | |
638 | return (hwc_y <= y && y < hwc_y + SM501_HWC_HEIGHT); | |
639 | } | |
640 | ||
64f1603b | 641 | static void sm501_2d_operation(SM501State *s) |
604be200 SK |
642 | { |
643 | /* obtain operation parameters */ | |
644 | int operation = (s->twoD_control >> 16) & 0x1f; | |
07d8a50c AJ |
645 | int rtl = s->twoD_control & 0x8000000; |
646 | int src_x = (s->twoD_source >> 16) & 0x01FFF; | |
647 | int src_y = s->twoD_source & 0xFFFF; | |
604be200 SK |
648 | int dst_x = (s->twoD_destination >> 16) & 0x01FFF; |
649 | int dst_y = s->twoD_destination & 0xFFFF; | |
650 | int operation_width = (s->twoD_dimension >> 16) & 0x1FFF; | |
651 | int operation_height = s->twoD_dimension & 0xFFFF; | |
652 | uint32_t color = s->twoD_foreground; | |
653 | int format_flags = (s->twoD_stretch >> 20) & 0x3; | |
654 | int addressing = (s->twoD_stretch >> 16) & 0xF; | |
655 | ||
656 | /* get frame buffer info */ | |
64f1603b BZ |
657 | uint8_t *src = s->local_mem + (s->twoD_source_base & 0x03FFFFFF); |
658 | uint8_t *dst = s->local_mem + (s->twoD_destination_base & 0x03FFFFFF); | |
07d8a50c | 659 | int src_width = (s->dc_crt_h_total & 0x00000FFF) + 1; |
604be200 SK |
660 | int dst_width = (s->dc_crt_h_total & 0x00000FFF) + 1; |
661 | ||
662 | if (addressing != 0x0) { | |
663 | printf("%s: only XY addressing is supported.\n", __func__); | |
664 | abort(); | |
665 | } | |
666 | ||
667 | if ((s->twoD_source_base & 0x08000000) || | |
668 | (s->twoD_destination_base & 0x08000000)) { | |
669 | printf("%s: only local memory is supported.\n", __func__); | |
670 | abort(); | |
671 | } | |
672 | ||
673 | switch (operation) { | |
07d8a50c | 674 | case 0x00: /* copy area */ |
64f1603b BZ |
675 | #define COPY_AREA(_bpp, _pixel_type, rtl) { \ |
676 | int y, x, index_d, index_s; \ | |
677 | for (y = 0; y < operation_height; y++) { \ | |
678 | for (x = 0; x < operation_width; x++) { \ | |
679 | if (rtl) { \ | |
680 | index_s = ((src_y - y) * src_width + src_x - x) * _bpp; \ | |
681 | index_d = ((dst_y - y) * dst_width + dst_x - x) * _bpp; \ | |
682 | } else { \ | |
683 | index_s = ((src_y + y) * src_width + src_x + x) * _bpp; \ | |
684 | index_d = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \ | |
685 | } \ | |
686 | *(_pixel_type *)&dst[index_d] = *(_pixel_type *)&src[index_s];\ | |
687 | } \ | |
688 | } \ | |
07d8a50c AJ |
689 | } |
690 | switch (format_flags) { | |
691 | case 0: | |
692 | COPY_AREA(1, uint8_t, rtl); | |
693 | break; | |
694 | case 1: | |
695 | COPY_AREA(2, uint16_t, rtl); | |
696 | break; | |
697 | case 2: | |
698 | COPY_AREA(4, uint32_t, rtl); | |
699 | break; | |
700 | } | |
701 | break; | |
604be200 | 702 | |
07d8a50c | 703 | case 0x01: /* fill rectangle */ |
604be200 SK |
704 | #define FILL_RECT(_bpp, _pixel_type) { \ |
705 | int y, x; \ | |
706 | for (y = 0; y < operation_height; y++) { \ | |
707 | for (x = 0; x < operation_width; x++) { \ | |
708 | int index = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \ | |
64f1603b | 709 | *(_pixel_type *)&dst[index] = (_pixel_type)color; \ |
604be200 SK |
710 | } \ |
711 | } \ | |
712 | } | |
713 | ||
714 | switch (format_flags) { | |
715 | case 0: | |
716 | FILL_RECT(1, uint8_t); | |
717 | break; | |
718 | case 1: | |
719 | FILL_RECT(2, uint16_t); | |
720 | break; | |
721 | case 2: | |
722 | FILL_RECT(4, uint32_t); | |
723 | break; | |
724 | } | |
725 | break; | |
726 | ||
727 | default: | |
728 | printf("non-implemented SM501 2D operation. %d\n", operation); | |
729 | abort(); | |
730 | break; | |
731 | } | |
732 | } | |
733 | ||
a8170e5e | 734 | static uint64_t sm501_system_config_read(void *opaque, hwaddr addr, |
25793bfa | 735 | unsigned size) |
ffd39257 | 736 | { |
64f1603b | 737 | SM501State *s = (SM501State *)opaque; |
ffd39257 | 738 | uint32_t ret = 0; |
8da3ff18 | 739 | SM501_DPRINTF("sm501 system config regs : read addr=%x\n", (int)addr); |
ffd39257 | 740 | |
64f1603b | 741 | switch (addr) { |
ffd39257 | 742 | case SM501_SYSTEM_CONTROL: |
64f1603b BZ |
743 | ret = s->system_control; |
744 | break; | |
ffd39257 | 745 | case SM501_MISC_CONTROL: |
64f1603b BZ |
746 | ret = s->misc_control; |
747 | break; | |
ffd39257 | 748 | case SM501_GPIO31_0_CONTROL: |
64f1603b BZ |
749 | ret = s->gpio_31_0_control; |
750 | break; | |
ffd39257 | 751 | case SM501_GPIO63_32_CONTROL: |
64f1603b BZ |
752 | ret = s->gpio_63_32_control; |
753 | break; | |
ffd39257 | 754 | case SM501_DEVICEID: |
64f1603b BZ |
755 | ret = 0x050100A0; |
756 | break; | |
ffd39257 | 757 | case SM501_DRAM_CONTROL: |
64f1603b BZ |
758 | ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13; |
759 | break; | |
ffd39257 | 760 | case SM501_IRQ_MASK: |
64f1603b BZ |
761 | ret = s->irq_mask; |
762 | break; | |
ffd39257 | 763 | case SM501_MISC_TIMING: |
64f1603b BZ |
764 | /* TODO : simulate gate control */ |
765 | ret = s->misc_timing; | |
766 | break; | |
ffd39257 | 767 | case SM501_CURRENT_GATE: |
64f1603b BZ |
768 | /* TODO : simulate gate control */ |
769 | ret = 0x00021807; | |
770 | break; | |
ffd39257 | 771 | case SM501_CURRENT_CLOCK: |
64f1603b BZ |
772 | ret = 0x2A1A0A09; |
773 | break; | |
ffd39257 | 774 | case SM501_POWER_MODE_CONTROL: |
64f1603b BZ |
775 | ret = s->power_mode_control; |
776 | break; | |
ffd39257 BS |
777 | |
778 | default: | |
64f1603b BZ |
779 | printf("sm501 system config : not implemented register read." |
780 | " addr=%x\n", (int)addr); | |
43dc2a64 | 781 | abort(); |
ffd39257 BS |
782 | } |
783 | ||
784 | return ret; | |
785 | } | |
786 | ||
a8170e5e | 787 | static void sm501_system_config_write(void *opaque, hwaddr addr, |
25793bfa | 788 | uint64_t value, unsigned size) |
ffd39257 | 789 | { |
64f1603b | 790 | SM501State *s = (SM501State *)opaque; |
8da3ff18 | 791 | SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n", |
64f1603b | 792 | (uint32_t)addr, (uint32_t)value); |
ffd39257 | 793 | |
64f1603b | 794 | switch (addr) { |
ffd39257 | 795 | case SM501_SYSTEM_CONTROL: |
64f1603b BZ |
796 | s->system_control = value & 0xE300B8F7; |
797 | break; | |
ffd39257 | 798 | case SM501_MISC_CONTROL: |
64f1603b BZ |
799 | s->misc_control = value & 0xFF7FFF20; |
800 | break; | |
ffd39257 | 801 | case SM501_GPIO31_0_CONTROL: |
64f1603b BZ |
802 | s->gpio_31_0_control = value; |
803 | break; | |
ffd39257 | 804 | case SM501_GPIO63_32_CONTROL: |
64f1603b BZ |
805 | s->gpio_63_32_control = value; |
806 | break; | |
ffd39257 | 807 | case SM501_DRAM_CONTROL: |
64f1603b BZ |
808 | s->local_mem_size_index = (value >> 13) & 0x7; |
809 | /* TODO : check validity of size change */ | |
810 | s->dram_control |= value & 0x7FFFFFC3; | |
811 | break; | |
ffd39257 | 812 | case SM501_IRQ_MASK: |
64f1603b BZ |
813 | s->irq_mask = value; |
814 | break; | |
ffd39257 | 815 | case SM501_MISC_TIMING: |
64f1603b BZ |
816 | s->misc_timing = value & 0xF31F1FFF; |
817 | break; | |
ffd39257 BS |
818 | case SM501_POWER_MODE_0_GATE: |
819 | case SM501_POWER_MODE_1_GATE: | |
820 | case SM501_POWER_MODE_0_CLOCK: | |
821 | case SM501_POWER_MODE_1_CLOCK: | |
64f1603b BZ |
822 | /* TODO : simulate gate & clock control */ |
823 | break; | |
ffd39257 | 824 | case SM501_POWER_MODE_CONTROL: |
64f1603b BZ |
825 | s->power_mode_control = value & 0x00000003; |
826 | break; | |
ffd39257 BS |
827 | |
828 | default: | |
64f1603b BZ |
829 | printf("sm501 system config : not implemented register write." |
830 | " addr=%x, val=%x\n", (int)addr, (uint32_t)value); | |
43dc2a64 | 831 | abort(); |
ffd39257 BS |
832 | } |
833 | } | |
834 | ||
25793bfa AK |
835 | static const MemoryRegionOps sm501_system_config_ops = { |
836 | .read = sm501_system_config_read, | |
837 | .write = sm501_system_config_write, | |
838 | .valid = { | |
839 | .min_access_size = 4, | |
840 | .max_access_size = 4, | |
841 | }, | |
842 | .endianness = DEVICE_NATIVE_ENDIAN, | |
ffd39257 BS |
843 | }; |
844 | ||
a8170e5e | 845 | static uint32_t sm501_palette_read(void *opaque, hwaddr addr) |
486579de | 846 | { |
64f1603b | 847 | SM501State *s = (SM501State *)opaque; |
486579de AZ |
848 | SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr); |
849 | ||
850 | /* TODO : consider BYTE/WORD access */ | |
851 | /* TODO : consider endian */ | |
852 | ||
45416789 | 853 | assert(range_covers_byte(0, 0x400 * 3, addr)); |
64f1603b | 854 | return *(uint32_t *)&s->dc_palette[addr]; |
486579de AZ |
855 | } |
856 | ||
64f1603b BZ |
857 | static void sm501_palette_write(void *opaque, hwaddr addr, |
858 | uint32_t value) | |
486579de | 859 | { |
64f1603b | 860 | SM501State *s = (SM501State *)opaque; |
486579de | 861 | SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n", |
64f1603b | 862 | (int)addr, value); |
486579de AZ |
863 | |
864 | /* TODO : consider BYTE/WORD access */ | |
865 | /* TODO : consider endian */ | |
866 | ||
45416789 | 867 | assert(range_covers_byte(0, 0x400 * 3, addr)); |
64f1603b | 868 | *(uint32_t *)&s->dc_palette[addr] = value; |
486579de AZ |
869 | } |
870 | ||
a8170e5e | 871 | static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr, |
25793bfa | 872 | unsigned size) |
ffd39257 | 873 | { |
64f1603b | 874 | SM501State *s = (SM501State *)opaque; |
ffd39257 | 875 | uint32_t ret = 0; |
8da3ff18 | 876 | SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x\n", (int)addr); |
ffd39257 | 877 | |
64f1603b | 878 | switch (addr) { |
ffd39257 BS |
879 | |
880 | case SM501_DC_PANEL_CONTROL: | |
64f1603b BZ |
881 | ret = s->dc_panel_control; |
882 | break; | |
ffd39257 | 883 | case SM501_DC_PANEL_PANNING_CONTROL: |
64f1603b BZ |
884 | ret = s->dc_panel_panning_control; |
885 | break; | |
ffd39257 | 886 | case SM501_DC_PANEL_FB_ADDR: |
64f1603b BZ |
887 | ret = s->dc_panel_fb_addr; |
888 | break; | |
ffd39257 | 889 | case SM501_DC_PANEL_FB_OFFSET: |
64f1603b BZ |
890 | ret = s->dc_panel_fb_offset; |
891 | break; | |
ffd39257 | 892 | case SM501_DC_PANEL_FB_WIDTH: |
64f1603b BZ |
893 | ret = s->dc_panel_fb_width; |
894 | break; | |
ffd39257 | 895 | case SM501_DC_PANEL_FB_HEIGHT: |
64f1603b BZ |
896 | ret = s->dc_panel_fb_height; |
897 | break; | |
ffd39257 | 898 | case SM501_DC_PANEL_TL_LOC: |
64f1603b BZ |
899 | ret = s->dc_panel_tl_location; |
900 | break; | |
ffd39257 | 901 | case SM501_DC_PANEL_BR_LOC: |
64f1603b BZ |
902 | ret = s->dc_panel_br_location; |
903 | break; | |
ffd39257 BS |
904 | |
905 | case SM501_DC_PANEL_H_TOT: | |
64f1603b BZ |
906 | ret = s->dc_panel_h_total; |
907 | break; | |
ffd39257 | 908 | case SM501_DC_PANEL_H_SYNC: |
64f1603b BZ |
909 | ret = s->dc_panel_h_sync; |
910 | break; | |
ffd39257 | 911 | case SM501_DC_PANEL_V_TOT: |
64f1603b BZ |
912 | ret = s->dc_panel_v_total; |
913 | break; | |
ffd39257 | 914 | case SM501_DC_PANEL_V_SYNC: |
64f1603b BZ |
915 | ret = s->dc_panel_v_sync; |
916 | break; | |
ffd39257 BS |
917 | |
918 | case SM501_DC_CRT_CONTROL: | |
64f1603b BZ |
919 | ret = s->dc_crt_control; |
920 | break; | |
ffd39257 | 921 | case SM501_DC_CRT_FB_ADDR: |
64f1603b BZ |
922 | ret = s->dc_crt_fb_addr; |
923 | break; | |
ffd39257 | 924 | case SM501_DC_CRT_FB_OFFSET: |
64f1603b BZ |
925 | ret = s->dc_crt_fb_offset; |
926 | break; | |
ffd39257 | 927 | case SM501_DC_CRT_H_TOT: |
64f1603b BZ |
928 | ret = s->dc_crt_h_total; |
929 | break; | |
ffd39257 | 930 | case SM501_DC_CRT_H_SYNC: |
64f1603b BZ |
931 | ret = s->dc_crt_h_sync; |
932 | break; | |
ffd39257 | 933 | case SM501_DC_CRT_V_TOT: |
64f1603b BZ |
934 | ret = s->dc_crt_v_total; |
935 | break; | |
ffd39257 | 936 | case SM501_DC_CRT_V_SYNC: |
64f1603b BZ |
937 | ret = s->dc_crt_v_sync; |
938 | break; | |
ffd39257 BS |
939 | |
940 | case SM501_DC_CRT_HWC_ADDR: | |
64f1603b BZ |
941 | ret = s->dc_crt_hwc_addr; |
942 | break; | |
ffd39257 | 943 | case SM501_DC_CRT_HWC_LOC: |
64f1603b BZ |
944 | ret = s->dc_crt_hwc_location; |
945 | break; | |
ffd39257 | 946 | case SM501_DC_CRT_HWC_COLOR_1_2: |
64f1603b BZ |
947 | ret = s->dc_crt_hwc_color_1_2; |
948 | break; | |
ffd39257 | 949 | case SM501_DC_CRT_HWC_COLOR_3: |
64f1603b BZ |
950 | ret = s->dc_crt_hwc_color_3; |
951 | break; | |
ffd39257 | 952 | |
64f1603b | 953 | case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4: |
486579de AZ |
954 | ret = sm501_palette_read(opaque, addr - SM501_DC_PANEL_PALETTE); |
955 | break; | |
956 | ||
ffd39257 | 957 | default: |
64f1603b BZ |
958 | printf("sm501 disp ctrl : not implemented register read." |
959 | " addr=%x\n", (int)addr); | |
43dc2a64 | 960 | abort(); |
ffd39257 BS |
961 | } |
962 | ||
963 | return ret; | |
964 | } | |
965 | ||
a8170e5e | 966 | static void sm501_disp_ctrl_write(void *opaque, hwaddr addr, |
25793bfa | 967 | uint64_t value, unsigned size) |
ffd39257 | 968 | { |
64f1603b | 969 | SM501State *s = (SM501State *)opaque; |
8da3ff18 | 970 | SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, val=%x\n", |
64f1603b | 971 | (unsigned)addr, (unsigned)value); |
ffd39257 | 972 | |
64f1603b | 973 | switch (addr) { |
ffd39257 | 974 | case SM501_DC_PANEL_CONTROL: |
64f1603b BZ |
975 | s->dc_panel_control = value & 0x0FFF73FF; |
976 | break; | |
ffd39257 | 977 | case SM501_DC_PANEL_PANNING_CONTROL: |
64f1603b BZ |
978 | s->dc_panel_panning_control = value & 0xFF3FFF3F; |
979 | break; | |
ffd39257 | 980 | case SM501_DC_PANEL_FB_ADDR: |
64f1603b BZ |
981 | s->dc_panel_fb_addr = value & 0x8FFFFFF0; |
982 | break; | |
ffd39257 | 983 | case SM501_DC_PANEL_FB_OFFSET: |
64f1603b BZ |
984 | s->dc_panel_fb_offset = value & 0x3FF03FF0; |
985 | break; | |
ffd39257 | 986 | case SM501_DC_PANEL_FB_WIDTH: |
64f1603b BZ |
987 | s->dc_panel_fb_width = value & 0x0FFF0FFF; |
988 | break; | |
ffd39257 | 989 | case SM501_DC_PANEL_FB_HEIGHT: |
64f1603b BZ |
990 | s->dc_panel_fb_height = value & 0x0FFF0FFF; |
991 | break; | |
ffd39257 | 992 | case SM501_DC_PANEL_TL_LOC: |
64f1603b BZ |
993 | s->dc_panel_tl_location = value & 0x07FF07FF; |
994 | break; | |
ffd39257 | 995 | case SM501_DC_PANEL_BR_LOC: |
64f1603b BZ |
996 | s->dc_panel_br_location = value & 0x07FF07FF; |
997 | break; | |
ffd39257 BS |
998 | |
999 | case SM501_DC_PANEL_H_TOT: | |
64f1603b BZ |
1000 | s->dc_panel_h_total = value & 0x0FFF0FFF; |
1001 | break; | |
ffd39257 | 1002 | case SM501_DC_PANEL_H_SYNC: |
64f1603b BZ |
1003 | s->dc_panel_h_sync = value & 0x00FF0FFF; |
1004 | break; | |
ffd39257 | 1005 | case SM501_DC_PANEL_V_TOT: |
64f1603b BZ |
1006 | s->dc_panel_v_total = value & 0x0FFF0FFF; |
1007 | break; | |
ffd39257 | 1008 | case SM501_DC_PANEL_V_SYNC: |
64f1603b BZ |
1009 | s->dc_panel_v_sync = value & 0x003F0FFF; |
1010 | break; | |
ffd39257 BS |
1011 | |
1012 | case SM501_DC_PANEL_HWC_ADDR: | |
64f1603b BZ |
1013 | s->dc_panel_hwc_addr = value & 0x8FFFFFF0; |
1014 | break; | |
ffd39257 | 1015 | case SM501_DC_PANEL_HWC_LOC: |
64f1603b BZ |
1016 | s->dc_panel_hwc_location = value & 0x0FFF0FFF; |
1017 | break; | |
ffd39257 | 1018 | case SM501_DC_PANEL_HWC_COLOR_1_2: |
64f1603b BZ |
1019 | s->dc_panel_hwc_color_1_2 = value; |
1020 | break; | |
ffd39257 | 1021 | case SM501_DC_PANEL_HWC_COLOR_3: |
64f1603b BZ |
1022 | s->dc_panel_hwc_color_3 = value & 0x0000FFFF; |
1023 | break; | |
ffd39257 BS |
1024 | |
1025 | case SM501_DC_CRT_CONTROL: | |
64f1603b BZ |
1026 | s->dc_crt_control = value & 0x0003FFFF; |
1027 | break; | |
ffd39257 | 1028 | case SM501_DC_CRT_FB_ADDR: |
64f1603b BZ |
1029 | s->dc_crt_fb_addr = value & 0x8FFFFFF0; |
1030 | break; | |
ffd39257 | 1031 | case SM501_DC_CRT_FB_OFFSET: |
64f1603b BZ |
1032 | s->dc_crt_fb_offset = value & 0x3FF03FF0; |
1033 | break; | |
ffd39257 | 1034 | case SM501_DC_CRT_H_TOT: |
64f1603b BZ |
1035 | s->dc_crt_h_total = value & 0x0FFF0FFF; |
1036 | break; | |
ffd39257 | 1037 | case SM501_DC_CRT_H_SYNC: |
64f1603b BZ |
1038 | s->dc_crt_h_sync = value & 0x00FF0FFF; |
1039 | break; | |
ffd39257 | 1040 | case SM501_DC_CRT_V_TOT: |
64f1603b BZ |
1041 | s->dc_crt_v_total = value & 0x0FFF0FFF; |
1042 | break; | |
ffd39257 | 1043 | case SM501_DC_CRT_V_SYNC: |
64f1603b BZ |
1044 | s->dc_crt_v_sync = value & 0x003F0FFF; |
1045 | break; | |
ffd39257 BS |
1046 | |
1047 | case SM501_DC_CRT_HWC_ADDR: | |
64f1603b BZ |
1048 | s->dc_crt_hwc_addr = value & 0x8FFFFFF0; |
1049 | break; | |
ffd39257 | 1050 | case SM501_DC_CRT_HWC_LOC: |
64f1603b BZ |
1051 | s->dc_crt_hwc_location = value & 0x0FFF0FFF; |
1052 | break; | |
ffd39257 | 1053 | case SM501_DC_CRT_HWC_COLOR_1_2: |
64f1603b BZ |
1054 | s->dc_crt_hwc_color_1_2 = value; |
1055 | break; | |
ffd39257 | 1056 | case SM501_DC_CRT_HWC_COLOR_3: |
64f1603b BZ |
1057 | s->dc_crt_hwc_color_3 = value & 0x0000FFFF; |
1058 | break; | |
ffd39257 | 1059 | |
64f1603b | 1060 | case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4: |
486579de AZ |
1061 | sm501_palette_write(opaque, addr - SM501_DC_PANEL_PALETTE, value); |
1062 | break; | |
1063 | ||
ffd39257 | 1064 | default: |
64f1603b BZ |
1065 | printf("sm501 disp ctrl : not implemented register write." |
1066 | " addr=%x, val=%x\n", (int)addr, (unsigned)value); | |
43dc2a64 | 1067 | abort(); |
ffd39257 BS |
1068 | } |
1069 | } | |
1070 | ||
25793bfa AK |
1071 | static const MemoryRegionOps sm501_disp_ctrl_ops = { |
1072 | .read = sm501_disp_ctrl_read, | |
1073 | .write = sm501_disp_ctrl_write, | |
1074 | .valid = { | |
1075 | .min_access_size = 4, | |
1076 | .max_access_size = 4, | |
1077 | }, | |
1078 | .endianness = DEVICE_NATIVE_ENDIAN, | |
ffd39257 BS |
1079 | }; |
1080 | ||
a8170e5e | 1081 | static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr, |
25793bfa | 1082 | unsigned size) |
604be200 | 1083 | { |
64f1603b | 1084 | SM501State *s = (SM501State *)opaque; |
604be200 SK |
1085 | uint32_t ret = 0; |
1086 | SM501_DPRINTF("sm501 2d engine regs : read addr=%x\n", (int)addr); | |
1087 | ||
64f1603b | 1088 | switch (addr) { |
604be200 SK |
1089 | case SM501_2D_SOURCE_BASE: |
1090 | ret = s->twoD_source_base; | |
1091 | break; | |
1092 | default: | |
1093 | printf("sm501 disp ctrl : not implemented register read." | |
1094 | " addr=%x\n", (int)addr); | |
1095 | abort(); | |
1096 | } | |
1097 | ||
1098 | return ret; | |
1099 | } | |
1100 | ||
a8170e5e | 1101 | static void sm501_2d_engine_write(void *opaque, hwaddr addr, |
25793bfa | 1102 | uint64_t value, unsigned size) |
604be200 | 1103 | { |
64f1603b | 1104 | SM501State *s = (SM501State *)opaque; |
604be200 | 1105 | SM501_DPRINTF("sm501 2d engine regs : write addr=%x, val=%x\n", |
25793bfa | 1106 | (unsigned)addr, (unsigned)value); |
604be200 | 1107 | |
64f1603b | 1108 | switch (addr) { |
07d8a50c AJ |
1109 | case SM501_2D_SOURCE: |
1110 | s->twoD_source = value; | |
1111 | break; | |
604be200 SK |
1112 | case SM501_2D_DESTINATION: |
1113 | s->twoD_destination = value; | |
1114 | break; | |
1115 | case SM501_2D_DIMENSION: | |
1116 | s->twoD_dimension = value; | |
1117 | break; | |
1118 | case SM501_2D_CONTROL: | |
1119 | s->twoD_control = value; | |
1120 | ||
1121 | /* do 2d operation if start flag is set. */ | |
1122 | if (value & 0x80000000) { | |
1123 | sm501_2d_operation(s); | |
1124 | s->twoD_control &= ~0x80000000; /* start flag down */ | |
1125 | } | |
1126 | ||
1127 | break; | |
1128 | case SM501_2D_PITCH: | |
1129 | s->twoD_pitch = value; | |
1130 | break; | |
1131 | case SM501_2D_FOREGROUND: | |
1132 | s->twoD_foreground = value; | |
1133 | break; | |
1134 | case SM501_2D_STRETCH: | |
1135 | s->twoD_stretch = value; | |
1136 | break; | |
1137 | case SM501_2D_COLOR_COMPARE_MASK: | |
1138 | s->twoD_color_compare_mask = value; | |
1139 | break; | |
1140 | case SM501_2D_MASK: | |
1141 | s->twoD_mask = value; | |
1142 | break; | |
1143 | case SM501_2D_WINDOW_WIDTH: | |
1144 | s->twoD_window_width = value; | |
1145 | break; | |
1146 | case SM501_2D_SOURCE_BASE: | |
1147 | s->twoD_source_base = value; | |
1148 | break; | |
1149 | case SM501_2D_DESTINATION_BASE: | |
1150 | s->twoD_destination_base = value; | |
1151 | break; | |
1152 | default: | |
1153 | printf("sm501 2d engine : not implemented register write." | |
25793bfa | 1154 | " addr=%x, val=%x\n", (int)addr, (unsigned)value); |
604be200 SK |
1155 | abort(); |
1156 | } | |
1157 | } | |
1158 | ||
25793bfa AK |
1159 | static const MemoryRegionOps sm501_2d_engine_ops = { |
1160 | .read = sm501_2d_engine_read, | |
1161 | .write = sm501_2d_engine_write, | |
1162 | .valid = { | |
1163 | .min_access_size = 4, | |
1164 | .max_access_size = 4, | |
1165 | }, | |
1166 | .endianness = DEVICE_NATIVE_ENDIAN, | |
604be200 SK |
1167 | }; |
1168 | ||
ffd39257 BS |
1169 | /* draw line functions for all console modes */ |
1170 | ||
ffd39257 | 1171 | typedef void draw_line_func(uint8_t *d, const uint8_t *s, |
64f1603b | 1172 | int width, const uint32_t *pal); |
ffd39257 | 1173 | |
64f1603b | 1174 | typedef void draw_hwc_line_func(SM501State *s, int crt, uint8_t *palette, |
0a4e7cd2 SK |
1175 | int c_y, uint8_t *d, int width); |
1176 | ||
ffd39257 | 1177 | #define DEPTH 8 |
47b43a1f | 1178 | #include "sm501_template.h" |
ffd39257 BS |
1179 | |
1180 | #define DEPTH 15 | |
47b43a1f | 1181 | #include "sm501_template.h" |
ffd39257 BS |
1182 | |
1183 | #define BGR_FORMAT | |
1184 | #define DEPTH 15 | |
47b43a1f | 1185 | #include "sm501_template.h" |
ffd39257 BS |
1186 | |
1187 | #define DEPTH 16 | |
47b43a1f | 1188 | #include "sm501_template.h" |
ffd39257 BS |
1189 | |
1190 | #define BGR_FORMAT | |
1191 | #define DEPTH 16 | |
47b43a1f | 1192 | #include "sm501_template.h" |
ffd39257 BS |
1193 | |
1194 | #define DEPTH 32 | |
47b43a1f | 1195 | #include "sm501_template.h" |
ffd39257 BS |
1196 | |
1197 | #define BGR_FORMAT | |
1198 | #define DEPTH 32 | |
47b43a1f | 1199 | #include "sm501_template.h" |
ffd39257 | 1200 | |
64f1603b | 1201 | static draw_line_func *draw_line8_funcs[] = { |
ffd39257 BS |
1202 | draw_line8_8, |
1203 | draw_line8_15, | |
1204 | draw_line8_16, | |
1205 | draw_line8_32, | |
1206 | draw_line8_32bgr, | |
1207 | draw_line8_15bgr, | |
1208 | draw_line8_16bgr, | |
1209 | }; | |
1210 | ||
64f1603b | 1211 | static draw_line_func *draw_line16_funcs[] = { |
ffd39257 BS |
1212 | draw_line16_8, |
1213 | draw_line16_15, | |
1214 | draw_line16_16, | |
1215 | draw_line16_32, | |
1216 | draw_line16_32bgr, | |
1217 | draw_line16_15bgr, | |
1218 | draw_line16_16bgr, | |
1219 | }; | |
1220 | ||
64f1603b | 1221 | static draw_line_func *draw_line32_funcs[] = { |
ffd39257 BS |
1222 | draw_line32_8, |
1223 | draw_line32_15, | |
1224 | draw_line32_16, | |
1225 | draw_line32_32, | |
1226 | draw_line32_32bgr, | |
1227 | draw_line32_15bgr, | |
1228 | draw_line32_16bgr, | |
1229 | }; | |
1230 | ||
64f1603b | 1231 | static draw_hwc_line_func *draw_hwc_line_funcs[] = { |
0a4e7cd2 SK |
1232 | draw_hwc_line_8, |
1233 | draw_hwc_line_15, | |
1234 | draw_hwc_line_16, | |
1235 | draw_hwc_line_32, | |
1236 | draw_hwc_line_32bgr, | |
1237 | draw_hwc_line_15bgr, | |
1238 | draw_hwc_line_16bgr, | |
1239 | }; | |
1240 | ||
c78f7137 | 1241 | static inline int get_depth_index(DisplaySurface *surface) |
ffd39257 | 1242 | { |
c78f7137 | 1243 | switch (surface_bits_per_pixel(surface)) { |
ffd39257 BS |
1244 | default: |
1245 | case 8: | |
64f1603b | 1246 | return 0; |
ffd39257 | 1247 | case 15: |
8927bcfd | 1248 | return 1; |
ffd39257 | 1249 | case 16: |
8927bcfd | 1250 | return 2; |
ffd39257 | 1251 | case 32: |
c78f7137 GH |
1252 | if (is_surface_bgr(surface)) { |
1253 | return 4; | |
1254 | } else { | |
1255 | return 3; | |
1256 | } | |
ffd39257 BS |
1257 | } |
1258 | } | |
1259 | ||
64f1603b | 1260 | static void sm501_draw_crt(SM501State *s) |
ffd39257 | 1261 | { |
c78f7137 | 1262 | DisplaySurface *surface = qemu_console_surface(s->con); |
ffd39257 BS |
1263 | int y; |
1264 | int width = (s->dc_crt_h_total & 0x00000FFF) + 1; | |
1265 | int height = (s->dc_crt_v_total & 0x00000FFF) + 1; | |
1266 | ||
64f1603b | 1267 | uint8_t *src = s->local_mem; |
ffd39257 | 1268 | int src_bpp = 0; |
c78f7137 | 1269 | int dst_bpp = surface_bytes_per_pixel(surface); |
64f1603b BZ |
1270 | uint32_t *palette = (uint32_t *)&s->dc_palette[SM501_DC_CRT_PALETTE - |
1271 | SM501_DC_PANEL_PALETTE]; | |
0a4e7cd2 | 1272 | uint8_t hwc_palette[3 * 3]; |
c78f7137 | 1273 | int ds_depth_index = get_depth_index(surface); |
64f1603b BZ |
1274 | draw_line_func *draw_line = NULL; |
1275 | draw_hwc_line_func *draw_hwc_line = NULL; | |
ffd39257 BS |
1276 | int full_update = 0; |
1277 | int y_start = -1; | |
543c4c94 AJ |
1278 | ram_addr_t page_min = ~0l; |
1279 | ram_addr_t page_max = 0l; | |
25793bfa | 1280 | ram_addr_t offset = 0; |
ffd39257 BS |
1281 | |
1282 | /* choose draw_line function */ | |
1283 | switch (s->dc_crt_control & 3) { | |
1284 | case SM501_DC_CRT_CONTROL_8BPP: | |
64f1603b BZ |
1285 | src_bpp = 1; |
1286 | draw_line = draw_line8_funcs[ds_depth_index]; | |
1287 | break; | |
ffd39257 | 1288 | case SM501_DC_CRT_CONTROL_16BPP: |
64f1603b BZ |
1289 | src_bpp = 2; |
1290 | draw_line = draw_line16_funcs[ds_depth_index]; | |
1291 | break; | |
ffd39257 | 1292 | case SM501_DC_CRT_CONTROL_32BPP: |
64f1603b BZ |
1293 | src_bpp = 4; |
1294 | draw_line = draw_line32_funcs[ds_depth_index]; | |
1295 | break; | |
ffd39257 | 1296 | default: |
64f1603b BZ |
1297 | printf("sm501 draw crt : invalid DC_CRT_CONTROL=%x.\n", |
1298 | s->dc_crt_control); | |
43dc2a64 | 1299 | abort(); |
64f1603b | 1300 | break; |
ffd39257 BS |
1301 | } |
1302 | ||
0a4e7cd2 SK |
1303 | /* set up to draw hardware cursor */ |
1304 | if (is_hwc_enabled(s, 1)) { | |
1305 | int i; | |
1306 | ||
1307 | /* get cursor palette */ | |
1308 | for (i = 0; i < 3; i++) { | |
1309 | uint16_t rgb565 = get_hwc_color(s, 1, i + 1); | |
1310 | hwc_palette[i * 3 + 0] = (rgb565 & 0xf800) >> 8; /* red */ | |
1311 | hwc_palette[i * 3 + 1] = (rgb565 & 0x07e0) >> 3; /* green */ | |
1312 | hwc_palette[i * 3 + 2] = (rgb565 & 0x001f) << 3; /* blue */ | |
1313 | } | |
1314 | ||
1315 | /* choose cursor draw line function */ | |
1316 | draw_hwc_line = draw_hwc_line_funcs[ds_depth_index]; | |
1317 | } | |
1318 | ||
ffd39257 BS |
1319 | /* adjust console size */ |
1320 | if (s->last_width != width || s->last_height != height) { | |
c78f7137 GH |
1321 | qemu_console_resize(s->con, width, height); |
1322 | surface = qemu_console_surface(s->con); | |
64f1603b BZ |
1323 | s->last_width = width; |
1324 | s->last_height = height; | |
1325 | full_update = 1; | |
ffd39257 BS |
1326 | } |
1327 | ||
1328 | /* draw each line according to conditions */ | |
5299c0f2 | 1329 | memory_region_sync_dirty_bitmap(&s->local_mem_region); |
ffd39257 | 1330 | for (y = 0; y < height; y++) { |
64f1603b BZ |
1331 | int update_hwc = draw_hwc_line ? within_hwc_y_range(s, y, 1) : 0; |
1332 | int update = full_update || update_hwc; | |
cd7a45c9 BS |
1333 | ram_addr_t page0 = offset; |
1334 | ram_addr_t page1 = offset + width * src_bpp - 1; | |
ffd39257 | 1335 | |
64f1603b | 1336 | /* check dirty flags for each line */ |
d1f3dd34 BS |
1337 | update = memory_region_get_dirty(&s->local_mem_region, page0, |
1338 | page1 - page0, DIRTY_MEMORY_VGA); | |
ffd39257 | 1339 | |
64f1603b BZ |
1340 | /* draw line and change status */ |
1341 | if (update) { | |
c78f7137 GH |
1342 | uint8_t *d = surface_data(surface); |
1343 | d += y * width * dst_bpp; | |
0a4e7cd2 SK |
1344 | |
1345 | /* draw graphics layer */ | |
1346 | draw_line(d, src, width, palette); | |
1347 | ||
64f1603b | 1348 | /* draw hardware cursor */ |
0a4e7cd2 SK |
1349 | if (update_hwc) { |
1350 | draw_hwc_line(s, 1, hwc_palette, y - get_hwc_y(s, 1), d, width); | |
1351 | } | |
1352 | ||
64f1603b BZ |
1353 | if (y_start < 0) { |
1354 | y_start = y; | |
1355 | } | |
1356 | if (page0 < page_min) { | |
1357 | page_min = page0; | |
1358 | } | |
1359 | if (page1 > page_max) { | |
1360 | page_max = page1; | |
1361 | } | |
1362 | } else { | |
1363 | if (y_start >= 0) { | |
1364 | /* flush to display */ | |
c78f7137 | 1365 | dpy_gfx_update(s->con, 0, y_start, width, y - y_start); |
64f1603b BZ |
1366 | y_start = -1; |
1367 | } | |
1368 | } | |
ffd39257 | 1369 | |
64f1603b BZ |
1370 | src += width * src_bpp; |
1371 | offset += width * src_bpp; | |
ffd39257 BS |
1372 | } |
1373 | ||
1374 | /* complete flush to display */ | |
64f1603b | 1375 | if (y_start >= 0) { |
c78f7137 | 1376 | dpy_gfx_update(s->con, 0, y_start, width, y - y_start); |
64f1603b | 1377 | } |
ffd39257 BS |
1378 | |
1379 | /* clear dirty flags */ | |
543c4c94 | 1380 | if (page_min != ~0l) { |
64f1603b | 1381 | memory_region_reset_dirty(&s->local_mem_region, |
25793bfa AK |
1382 | page_min, page_max + TARGET_PAGE_SIZE, |
1383 | DIRTY_MEMORY_VGA); | |
543c4c94 | 1384 | } |
ffd39257 BS |
1385 | } |
1386 | ||
1387 | static void sm501_update_display(void *opaque) | |
1388 | { | |
64f1603b | 1389 | SM501State *s = (SM501State *)opaque; |
ffd39257 | 1390 | |
64f1603b BZ |
1391 | if (s->dc_crt_control & SM501_DC_CRT_CONTROL_ENABLE) { |
1392 | sm501_draw_crt(s); | |
1393 | } | |
ffd39257 BS |
1394 | } |
1395 | ||
380cd056 GH |
1396 | static const GraphicHwOps sm501_ops = { |
1397 | .gfx_update = sm501_update_display, | |
1398 | }; | |
1399 | ||
27a9d2ea | 1400 | void sm501_init(MemoryRegion *address_space_mem, uint32_t base, |
0ec7b3e7 | 1401 | uint32_t local_mem_bytes, qemu_irq irq, Chardev *chr) |
ffd39257 | 1402 | { |
64f1603b | 1403 | SM501State *s; |
61d3cf93 | 1404 | DeviceState *dev; |
25793bfa AK |
1405 | MemoryRegion *sm501_system_config = g_new(MemoryRegion, 1); |
1406 | MemoryRegion *sm501_disp_ctrl = g_new(MemoryRegion, 1); | |
1407 | MemoryRegion *sm501_2d_engine = g_new(MemoryRegion, 1); | |
ffd39257 BS |
1408 | |
1409 | /* allocate management data region */ | |
64f1603b | 1410 | s = g_new0(SM501State, 1); |
ffd39257 | 1411 | s->base = base; |
64f1603b | 1412 | s->local_mem_size_index = get_local_mem_size_index(local_mem_bytes); |
ffd39257 | 1413 | SM501_DPRINTF("local mem size=%x. index=%d\n", get_local_mem_size(s), |
64f1603b | 1414 | s->local_mem_size_index); |
e2ee8476 BZ |
1415 | s->system_control = 0x00100000; /* 2D engine FIFO empty */ |
1416 | /* Bits 17 (SH), 7 (CDR), 6:5 (Test), 2:0 (Bus) are all supposed | |
1417 | * to be determined at reset by GPIO lines which set config bits. | |
1418 | * We hardwire them: | |
1419 | * SH = 0 : Hitachi Ready Polarity == Active Low | |
1420 | * CDR = 0 : do not reset clock divider | |
1421 | * TEST = 0 : Normal mode (not testing the silicon) | |
1422 | * BUS = 0 : Hitachi SH3/SH4 | |
1423 | */ | |
1424 | s->misc_control = SM501_MISC_DAC_POWER; | |
1425 | s->dc_panel_control = 0x00010000; /* FIFO level 3 */ | |
ffd39257 | 1426 | s->dc_crt_control = 0x00010000; |
ffd39257 BS |
1427 | |
1428 | /* allocate local memory */ | |
2c9b15ca | 1429 | memory_region_init_ram(&s->local_mem_region, NULL, "sm501.local", |
f8ed85ac | 1430 | local_mem_bytes, &error_fatal); |
c5705a77 | 1431 | vmstate_register_ram_global(&s->local_mem_region); |
74259ae5 | 1432 | memory_region_set_log(&s->local_mem_region, true, DIRTY_MEMORY_VGA); |
25793bfa AK |
1433 | s->local_mem = memory_region_get_ram_ptr(&s->local_mem_region); |
1434 | memory_region_add_subregion(address_space_mem, base, &s->local_mem_region); | |
ffd39257 BS |
1435 | |
1436 | /* map mmio */ | |
64f1603b BZ |
1437 | memory_region_init_io(sm501_system_config, NULL, &sm501_system_config_ops, |
1438 | s, "sm501-system-config", 0x6c); | |
25793bfa AK |
1439 | memory_region_add_subregion(address_space_mem, base + MMIO_BASE_OFFSET, |
1440 | sm501_system_config); | |
2c9b15ca | 1441 | memory_region_init_io(sm501_disp_ctrl, NULL, &sm501_disp_ctrl_ops, s, |
25793bfa AK |
1442 | "sm501-disp-ctrl", 0x1000); |
1443 | memory_region_add_subregion(address_space_mem, | |
1444 | base + MMIO_BASE_OFFSET + SM501_DC, | |
1445 | sm501_disp_ctrl); | |
2c9b15ca | 1446 | memory_region_init_io(sm501_2d_engine, NULL, &sm501_2d_engine_ops, s, |
25793bfa AK |
1447 | "sm501-2d-engine", 0x54); |
1448 | memory_region_add_subregion(address_space_mem, | |
1449 | base + MMIO_BASE_OFFSET + SM501_2D_ENGINE, | |
1450 | sm501_2d_engine); | |
ffd39257 | 1451 | |
ac611340 | 1452 | /* bridge to usb host emulation module */ |
61d3cf93 PB |
1453 | dev = qdev_create(NULL, "sysbus-ohci"); |
1454 | qdev_prop_set_uint32(dev, "num-ports", 2); | |
19298eca | 1455 | qdev_prop_set_uint64(dev, "dma-offset", base); |
61d3cf93 | 1456 | qdev_init_nofail(dev); |
1356b98d | 1457 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, |
61d3cf93 | 1458 | base + MMIO_BASE_OFFSET + SM501_USB_HOST); |
1356b98d | 1459 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq); |
ac611340 | 1460 | |
ffd39257 | 1461 | /* bridge to serial emulation module */ |
2d48377a | 1462 | if (chr) { |
27a9d2ea | 1463 | serial_mm_init(address_space_mem, |
39186d8a | 1464 | base + MMIO_BASE_OFFSET + SM501_UART0, 2, |
2d48377a | 1465 | NULL, /* TODO : chain irq to IRL */ |
2ff0c7c3 | 1466 | 115200, chr, DEVICE_NATIVE_ENDIAN); |
2d48377a | 1467 | } |
ffd39257 BS |
1468 | |
1469 | /* create qemu graphic console */ | |
5643706a | 1470 | s->con = graphic_console_init(DEVICE(dev), 0, &sm501_ops, s); |
ffd39257 | 1471 | } |