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Commit | Line | Data |
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9ee6e8bb PB |
1 | /* |
2 | * SSD0303 OLED controller with OSRAM Pictiva 96x16 display. | |
3 | * | |
4 | * Copyright (c) 2006-2007 CodeSourcery. | |
5 | * Written by Paul Brook | |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL. |
9ee6e8bb PB |
8 | */ |
9 | ||
10 | /* The controller can support a variety of different displays, but we only | |
11 | implement one. Most of the commends relating to brightness and geometry | |
12 | setup are ignored. */ | |
0b8fa32f | 13 | |
47df5154 | 14 | #include "qemu/osdep.h" |
0d09e41a | 15 | #include "hw/i2c/i2c.h" |
d6454270 | 16 | #include "migration/vmstate.h" |
0b8fa32f | 17 | #include "qemu/module.h" |
28ecbaee | 18 | #include "ui/console.h" |
db1015e9 | 19 | #include "qom/object.h" |
9ee6e8bb PB |
20 | |
21 | //#define DEBUG_SSD0303 1 | |
22 | ||
23 | #ifdef DEBUG_SSD0303 | |
001faf32 BS |
24 | #define DPRINTF(fmt, ...) \ |
25 | do { printf("ssd0303: " fmt , ## __VA_ARGS__); } while (0) | |
26 | #define BADF(fmt, ...) \ | |
27 | do { fprintf(stderr, "ssd0303: error: " fmt , ## __VA_ARGS__); exit(1);} while (0) | |
9ee6e8bb | 28 | #else |
001faf32 BS |
29 | #define DPRINTF(fmt, ...) do {} while(0) |
30 | #define BADF(fmt, ...) \ | |
31 | do { fprintf(stderr, "ssd0303: error: " fmt , ## __VA_ARGS__);} while (0) | |
9ee6e8bb PB |
32 | #endif |
33 | ||
34 | /* Scaling factor for pixels. */ | |
35 | #define MAGNIFY 4 | |
36 | ||
37 | enum ssd0303_mode | |
38 | { | |
39 | SSD0303_IDLE, | |
40 | SSD0303_DATA, | |
41 | SSD0303_CMD | |
42 | }; | |
43 | ||
44 | enum ssd0303_cmd { | |
45 | SSD0303_CMD_NONE, | |
46 | SSD0303_CMD_SKIP1 | |
47 | }; | |
48 | ||
b1be4515 | 49 | #define TYPE_SSD0303 "ssd0303" |
8063396b | 50 | OBJECT_DECLARE_SIMPLE_TYPE(ssd0303_state, SSD0303) |
b1be4515 | 51 | |
db1015e9 | 52 | struct ssd0303_state { |
b1be4515 AF |
53 | I2CSlave parent_obj; |
54 | ||
c78f7137 | 55 | QemuConsole *con; |
9ee6e8bb PB |
56 | int row; |
57 | int col; | |
58 | int start_line; | |
59 | int mirror; | |
60 | int flash; | |
61 | int enabled; | |
62 | int inverse; | |
63 | int redraw; | |
64 | enum ssd0303_mode mode; | |
65 | enum ssd0303_cmd cmd_state; | |
66 | uint8_t framebuffer[132*8]; | |
db1015e9 | 67 | }; |
9ee6e8bb | 68 | |
2ac4c5f4 | 69 | static uint8_t ssd0303_recv(I2CSlave *i2c) |
9ee6e8bb PB |
70 | { |
71 | BADF("Reads not implemented\n"); | |
2ac4c5f4 | 72 | return 0xff; |
9ee6e8bb PB |
73 | } |
74 | ||
9e07bdf8 | 75 | static int ssd0303_send(I2CSlave *i2c, uint8_t data) |
9ee6e8bb | 76 | { |
b1be4515 | 77 | ssd0303_state *s = SSD0303(i2c); |
9ee6e8bb | 78 | enum ssd0303_cmd old_cmd_state; |
b1be4515 | 79 | |
9ee6e8bb PB |
80 | switch (s->mode) { |
81 | case SSD0303_IDLE: | |
82 | DPRINTF("byte 0x%02x\n", data); | |
83 | if (data == 0x80) | |
84 | s->mode = SSD0303_CMD; | |
85 | else if (data == 0x40) | |
86 | s->mode = SSD0303_DATA; | |
87 | else | |
88 | BADF("Unexpected byte 0x%x\n", data); | |
89 | break; | |
90 | case SSD0303_DATA: | |
91 | DPRINTF("data 0x%02x\n", data); | |
92 | if (s->col < 132) { | |
93 | s->framebuffer[s->col + s->row * 132] = data; | |
94 | s->col++; | |
95 | s->redraw = 1; | |
96 | } | |
97 | break; | |
98 | case SSD0303_CMD: | |
99 | old_cmd_state = s->cmd_state; | |
100 | s->cmd_state = SSD0303_CMD_NONE; | |
101 | switch (old_cmd_state) { | |
102 | case SSD0303_CMD_NONE: | |
103 | DPRINTF("cmd 0x%02x\n", data); | |
104 | s->mode = SSD0303_IDLE; | |
105 | switch (data) { | |
4e9a0b5b | 106 | case 0x00 ... 0x0f: /* Set lower column address. */ |
9ee6e8bb PB |
107 | s->col = (s->col & 0xf0) | (data & 0xf); |
108 | break; | |
109 | case 0x10 ... 0x20: /* Set higher column address. */ | |
110 | s->col = (s->col & 0x0f) | ((data & 0xf) << 4); | |
111 | break; | |
112 | case 0x40 ... 0x7f: /* Set start line. */ | |
113 | s->start_line = 0; | |
114 | break; | |
115 | case 0x81: /* Set contrast (Ignored). */ | |
116 | s->cmd_state = SSD0303_CMD_SKIP1; | |
117 | break; | |
118 | case 0xa0: /* Mirror off. */ | |
119 | s->mirror = 0; | |
120 | break; | |
121 | case 0xa1: /* Mirror off. */ | |
122 | s->mirror = 1; | |
123 | break; | |
124 | case 0xa4: /* Entire display off. */ | |
125 | s->flash = 0; | |
126 | break; | |
127 | case 0xa5: /* Entire display on. */ | |
128 | s->flash = 1; | |
129 | break; | |
130 | case 0xa6: /* Inverse off. */ | |
131 | s->inverse = 0; | |
132 | break; | |
133 | case 0xa7: /* Inverse on. */ | |
134 | s->inverse = 1; | |
135 | break; | |
26404edc | 136 | case 0xa8: /* Set multiplied ratio (Ignored). */ |
9ee6e8bb PB |
137 | s->cmd_state = SSD0303_CMD_SKIP1; |
138 | break; | |
139 | case 0xad: /* DC-DC power control. */ | |
140 | s->cmd_state = SSD0303_CMD_SKIP1; | |
141 | break; | |
142 | case 0xae: /* Display off. */ | |
143 | s->enabled = 0; | |
144 | break; | |
145 | case 0xaf: /* Display on. */ | |
146 | s->enabled = 1; | |
147 | break; | |
148 | case 0xb0 ... 0xbf: /* Set Page address. */ | |
149 | s->row = data & 7; | |
150 | break; | |
151 | case 0xc0 ... 0xc8: /* Set COM output direction (Ignored). */ | |
152 | break; | |
153 | case 0xd3: /* Set display offset (Ignored). */ | |
154 | s->cmd_state = SSD0303_CMD_SKIP1; | |
155 | break; | |
156 | case 0xd5: /* Set display clock (Ignored). */ | |
157 | s->cmd_state = SSD0303_CMD_SKIP1; | |
158 | break; | |
159 | case 0xd8: /* Set color and power mode (Ignored). */ | |
160 | s->cmd_state = SSD0303_CMD_SKIP1; | |
161 | break; | |
162 | case 0xd9: /* Set pre-charge period (Ignored). */ | |
163 | s->cmd_state = SSD0303_CMD_SKIP1; | |
164 | break; | |
165 | case 0xda: /* Set COM pin configuration (Ignored). */ | |
166 | s->cmd_state = SSD0303_CMD_SKIP1; | |
167 | break; | |
168 | case 0xdb: /* Set VCOM dselect level (Ignored). */ | |
169 | s->cmd_state = SSD0303_CMD_SKIP1; | |
170 | break; | |
171 | case 0xe3: /* no-op. */ | |
172 | break; | |
173 | default: | |
174 | BADF("Unknown command: 0x%x\n", data); | |
175 | } | |
176 | break; | |
177 | case SSD0303_CMD_SKIP1: | |
178 | DPRINTF("skip 0x%02x\n", data); | |
179 | break; | |
180 | } | |
181 | break; | |
182 | } | |
183 | return 0; | |
184 | } | |
185 | ||
d307c28c | 186 | static int ssd0303_event(I2CSlave *i2c, enum i2c_event event) |
9ee6e8bb | 187 | { |
b1be4515 AF |
188 | ssd0303_state *s = SSD0303(i2c); |
189 | ||
9ee6e8bb PB |
190 | switch (event) { |
191 | case I2C_FINISH: | |
192 | s->mode = SSD0303_IDLE; | |
193 | break; | |
194 | case I2C_START_RECV: | |
195 | case I2C_START_SEND: | |
196 | case I2C_NACK: | |
197 | /* Nothing to do. */ | |
198 | break; | |
199 | } | |
d307c28c CM |
200 | |
201 | return 0; | |
9ee6e8bb PB |
202 | } |
203 | ||
204 | static void ssd0303_update_display(void *opaque) | |
205 | { | |
206 | ssd0303_state *s = (ssd0303_state *)opaque; | |
c78f7137 | 207 | DisplaySurface *surface = qemu_console_surface(s->con); |
9ee6e8bb PB |
208 | uint8_t *dest; |
209 | uint8_t *src; | |
210 | int x; | |
211 | int y; | |
212 | int line; | |
213 | char *colors[2]; | |
214 | char colortab[MAGNIFY * 8]; | |
215 | int dest_width; | |
216 | uint8_t mask; | |
217 | ||
b115bb3f PB |
218 | if (!s->redraw) |
219 | return; | |
220 | ||
c78f7137 | 221 | switch (surface_bits_per_pixel(surface)) { |
b115bb3f PB |
222 | case 0: |
223 | return; | |
224 | case 15: | |
225 | dest_width = 2; | |
226 | break; | |
227 | case 16: | |
228 | dest_width = 2; | |
229 | break; | |
230 | case 24: | |
231 | dest_width = 3; | |
232 | break; | |
233 | case 32: | |
234 | dest_width = 4; | |
235 | break; | |
236 | default: | |
237 | BADF("Bad color depth\n"); | |
238 | return; | |
239 | } | |
240 | dest_width *= MAGNIFY; | |
241 | memset(colortab, 0xff, dest_width); | |
242 | memset(colortab + dest_width, 0, dest_width); | |
243 | if (s->flash) { | |
244 | colors[0] = colortab; | |
245 | colors[1] = colortab; | |
246 | } else if (s->inverse) { | |
247 | colors[0] = colortab; | |
248 | colors[1] = colortab + dest_width; | |
249 | } else { | |
250 | colors[0] = colortab + dest_width; | |
251 | colors[1] = colortab; | |
252 | } | |
c78f7137 | 253 | dest = surface_data(surface); |
b115bb3f PB |
254 | for (y = 0; y < 16; y++) { |
255 | line = (y + s->start_line) & 63; | |
256 | src = s->framebuffer + 132 * (line >> 3) + 36; | |
257 | mask = 1 << (line & 7); | |
258 | for (x = 0; x < 96; x++) { | |
259 | memcpy(dest, colors[(*src & mask) != 0], dest_width); | |
260 | dest += dest_width; | |
261 | src++; | |
9ee6e8bb | 262 | } |
b115bb3f PB |
263 | for (x = 1; x < MAGNIFY; x++) { |
264 | memcpy(dest, dest - dest_width * 96, dest_width * 96); | |
265 | dest += dest_width * 96; | |
9ee6e8bb PB |
266 | } |
267 | } | |
b115bb3f | 268 | s->redraw = 0; |
c78f7137 | 269 | dpy_gfx_update(s->con, 0, 0, 96 * MAGNIFY, 16 * MAGNIFY); |
9ee6e8bb PB |
270 | } |
271 | ||
272 | static void ssd0303_invalidate_display(void * opaque) | |
273 | { | |
274 | ssd0303_state *s = (ssd0303_state *)opaque; | |
275 | s->redraw = 1; | |
276 | } | |
277 | ||
aed7278d JQ |
278 | static const VMStateDescription vmstate_ssd0303 = { |
279 | .name = "ssd0303_oled", | |
280 | .version_id = 1, | |
281 | .minimum_version_id = 1, | |
8f1e884b | 282 | .fields = (VMStateField[]) { |
aed7278d JQ |
283 | VMSTATE_INT32(row, ssd0303_state), |
284 | VMSTATE_INT32(col, ssd0303_state), | |
285 | VMSTATE_INT32(start_line, ssd0303_state), | |
286 | VMSTATE_INT32(mirror, ssd0303_state), | |
287 | VMSTATE_INT32(flash, ssd0303_state), | |
288 | VMSTATE_INT32(enabled, ssd0303_state), | |
289 | VMSTATE_INT32(inverse, ssd0303_state), | |
290 | VMSTATE_INT32(redraw, ssd0303_state), | |
291 | VMSTATE_UINT32(mode, ssd0303_state), | |
292 | VMSTATE_UINT32(cmd_state, ssd0303_state), | |
293 | VMSTATE_BUFFER(framebuffer, ssd0303_state), | |
b1be4515 | 294 | VMSTATE_I2C_SLAVE(parent_obj, ssd0303_state), |
aed7278d JQ |
295 | VMSTATE_END_OF_LIST() |
296 | } | |
297 | }; | |
23e39294 | 298 | |
380cd056 GH |
299 | static const GraphicHwOps ssd0303_ops = { |
300 | .invalidate = ssd0303_invalidate_display, | |
301 | .gfx_update = ssd0303_update_display, | |
302 | }; | |
303 | ||
c8c9e103 | 304 | static void ssd0303_realize(DeviceState *dev, Error **errp) |
9ee6e8bb | 305 | { |
c8c9e103 | 306 | ssd0303_state *s = SSD0303(dev); |
9ee6e8bb | 307 | |
c8c9e103 | 308 | s->con = graphic_console_init(dev, 0, &ssd0303_ops, s); |
c78f7137 | 309 | qemu_console_resize(s->con, 96 * MAGNIFY, 16 * MAGNIFY); |
9ee6e8bb | 310 | } |
d2199005 | 311 | |
b5ea9327 AL |
312 | static void ssd0303_class_init(ObjectClass *klass, void *data) |
313 | { | |
39bffca2 | 314 | DeviceClass *dc = DEVICE_CLASS(klass); |
b5ea9327 AL |
315 | I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); |
316 | ||
c8c9e103 | 317 | dc->realize = ssd0303_realize; |
b5ea9327 AL |
318 | k->event = ssd0303_event; |
319 | k->recv = ssd0303_recv; | |
320 | k->send = ssd0303_send; | |
39bffca2 | 321 | dc->vmsd = &vmstate_ssd0303; |
b5ea9327 AL |
322 | } |
323 | ||
8c43a6f0 | 324 | static const TypeInfo ssd0303_info = { |
b1be4515 | 325 | .name = TYPE_SSD0303, |
39bffca2 AL |
326 | .parent = TYPE_I2C_SLAVE, |
327 | .instance_size = sizeof(ssd0303_state), | |
328 | .class_init = ssd0303_class_init, | |
d2199005 PB |
329 | }; |
330 | ||
83f7d43a | 331 | static void ssd0303_register_types(void) |
d2199005 | 332 | { |
39bffca2 | 333 | type_register_static(&ssd0303_info); |
d2199005 PB |
334 | } |
335 | ||
83f7d43a | 336 | type_init(ssd0303_register_types) |