[mirror_qemu.git] / hw / display / ssd0323.c

/*
 * SSD0323 OLED controller with OSRAM Pictiva 128x64 display.
 *
 * Copyright (c) 2006-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

/* The controller can support a variety of different displays, but we only
   implement one.  Most of the commends relating to brightness and geometry
   setup are ignored. */
#include "qemu/osdep.h"
#include "hw/ssi/ssi.h"
#include "ui/console.h"

//#define DEBUG_SSD0323 1

#ifdef DEBUG_SSD0323
#define DPRINTF(fmt, ...) \
do { printf("ssd0323: " fmt , ## __VA_ARGS__); } while (0)
#define BADF(fmt, ...) \
do { \
    fprintf(stderr, "ssd0323: error: " fmt , ## __VA_ARGS__); abort(); \
} while (0)
#else
#define DPRINTF(fmt, ...) do {} while(0)
#define BADF(fmt, ...) \
do { fprintf(stderr, "ssd0323: error: " fmt , ## __VA_ARGS__);} while (0)
#endif

/* Scaling factor for pixels.  */
#define MAGNIFY 4

#define REMAP_SWAP_COLUMN 0x01
#define REMAP_SWAP_NYBBLE 0x02
#define REMAP_VERTICAL    0x04
#define REMAP_SWAP_COM    0x10
#define REMAP_SPLIT_COM   0x40

enum ssd0323_mode
{
    SSD0323_CMD,
    SSD0323_DATA
};

typedef struct {
    SSISlave ssidev;
    QemuConsole *con;

    uint32_t cmd_len;
    int32_t cmd;
    int32_t cmd_data[8];
    int32_t row;
    int32_t row_start;
    int32_t row_end;
    int32_t col;
    int32_t col_start;
    int32_t col_end;
    int32_t redraw;
    int32_t remap;
    uint32_t mode;
    uint8_t framebuffer[128 * 80 / 2];
} ssd0323_state;

static uint32_t ssd0323_transfer(SSISlave *dev, uint32_t data)
{
    ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, dev);

    switch (s->mode) {
    case SSD0323_DATA:
        DPRINTF("data 0x%02x\n", data);
        s->framebuffer[s->col + s->row * 64] = data;
        if (s->remap & REMAP_VERTICAL) {
            s->row++;
            if (s->row > s->row_end) {
                s->row = s->row_start;
                s->col++;
            }
            if (s->col > s->col_end) {
                s->col = s->col_start;
            }
        } else {
            s->col++;
            if (s->col > s->col_end) {
                s->row++;
                s->col = s->col_start;
            }
            if (s->row > s->row_end) {
                s->row = s->row_start;
            }
        }
        s->redraw = 1;
        break;
    case SSD0323_CMD:
        DPRINTF("cmd 0x%02x\n", data);
        if (s->cmd_len == 0) {
            s->cmd = data;
        } else {
            s->cmd_data[s->cmd_len - 1] = data;
        }
        s->cmd_len++;
        switch (s->cmd) {
#define DATA(x) if (s->cmd_len <= (x)) return 0
        case 0x15: /* Set column.  */
            DATA(2);
            s->col = s->col_start = s->cmd_data[0] % 64;
            s->col_end = s->cmd_data[1] % 64;
            break;
        case 0x75: /* Set row.  */
            DATA(2);
            s->row = s->row_start = s->cmd_data[0] % 80;
            s->row_end = s->cmd_data[1] % 80;
            break;
        case 0x81: /* Set contrast */
            DATA(1);
            break;
        case 0x84: case 0x85: case 0x86: /* Max current.  */
            DATA(0);
            break;
        case 0xa0: /* Set remapping.  */
            /* FIXME: Implement this.  */
            DATA(1);
            s->remap = s->cmd_data[0];
            break;
        case 0xa1: /* Set display start line.  */
        case 0xa2: /* Set display offset.  */
            /* FIXME: Implement these.  */
            DATA(1);
            break;
        case 0xa4: /* Normal mode.  */
        case 0xa5: /* All on.  */
        case 0xa6: /* All off.  */
        case 0xa7: /* Inverse.  */
            /* FIXME: Implement these.  */
            DATA(0);
            break;
        case 0xa8: /* Set multiplex ratio.  */
        case 0xad: /* Set DC-DC converter.  */
            DATA(1);
            /* Ignored.  Don't care.  */
            break;
        case 0xae: /* Display off.  */
        case 0xaf: /* Display on.  */
            DATA(0);
            /* TODO: Implement power control.  */
            break;
        case 0xb1: /* Set phase length.  */
        case 0xb2: /* Set row period.  */
        case 0xb3: /* Set clock rate.  */
        case 0xbc: /* Set precharge.  */
        case 0xbe: /* Set VCOMH.  */
        case 0xbf: /* Set segment low.  */
            DATA(1);
            /* Ignored.  Don't care.  */
            break;
        case 0xb8: /* Set grey scale table.  */
            /* FIXME: Implement this.  */
            DATA(8);
            break;
        case 0xe3: /* NOP.  */
            DATA(0);
            break;
        case 0xff: /* Nasty hack because we don't handle chip selects
                      properly.  */
            break;
        default:
            BADF("Unknown command: 0x%x\n", data);
        }
        s->cmd_len = 0;
        return 0;
    }
    return 0;
}

static void ssd0323_update_display(void *opaque)
{
    ssd0323_state *s = (ssd0323_state *)opaque;
    DisplaySurface *surface = qemu_console_surface(s->con);
    uint8_t *dest;
    uint8_t *src;
    int x;
    int y;
    int i;
    int line;
    char *colors[16];
    char colortab[MAGNIFY * 64];
    char *p;
    int dest_width;

    if (!s->redraw)
        return;

    switch (surface_bits_per_pixel(surface)) {
    case 0:
        return;
    case 15:
        dest_width = 2;
        break;
    case 16:
        dest_width = 2;
        break;
    case 24:
        dest_width = 3;
        break;
    case 32:
        dest_width = 4;
        break;
    default:
        BADF("Bad color depth\n");
        return;
    }
    p = colortab;
    for (i = 0; i < 16; i++) {
        int n;
        colors[i] = p;
        switch (surface_bits_per_pixel(surface)) {
        case 15:
            n = i * 2 + (i >> 3);
            p[0] = n | (n << 5);
            p[1] = (n << 2) | (n >> 3);
            break;
        case 16:
            n = i * 2 + (i >> 3);
            p[0] = n | (n << 6) | ((n << 1) & 0x20);
            p[1] = (n << 3) | (n >> 2);
            break;
        case 24:
        case 32:
            n = (i << 4) | i;
            p[0] = p[1] = p[2] = n;
            break;
        default:
            BADF("Bad color depth\n");
            return;
        }
        p += dest_width;
    }
    /* TODO: Implement row/column remapping.  */
    dest = surface_data(surface);
    for (y = 0; y < 64; y++) {
        line = y;
        src = s->framebuffer + 64 * line;
        for (x = 0; x < 64; x++) {
            int val;
            val = *src >> 4;
            for (i = 0; i < MAGNIFY; i++) {
                memcpy(dest, colors[val], dest_width);
                dest += dest_width;
            }
            val = *src & 0xf;
            for (i = 0; i < MAGNIFY; i++) {
                memcpy(dest, colors[val], dest_width);
                dest += dest_width;
            }
            src++;
        }
        for (i = 1; i < MAGNIFY; i++) {
            memcpy(dest, dest - dest_width * MAGNIFY * 128,
                   dest_width * 128 * MAGNIFY);
            dest += dest_width * 128 * MAGNIFY;
        }
    }
    s->redraw = 0;
    dpy_gfx_update(s->con, 0, 0, 128 * MAGNIFY, 64 * MAGNIFY);
}

static void ssd0323_invalidate_display(void * opaque)
{
    ssd0323_state *s = (ssd0323_state *)opaque;
    s->redraw = 1;
}

/* Command/data input.  */
static void ssd0323_cd(void *opaque, int n, int level)
{
    ssd0323_state *s = (ssd0323_state *)opaque;
    DPRINTF("%s mode\n", level ? "Data" : "Command");
    s->mode = level ? SSD0323_DATA : SSD0323_CMD;
}

static int ssd0323_post_load(void *opaque, int version_id)
{
    ssd0323_state *s = (ssd0323_state *)opaque;

    if (s->cmd_len > ARRAY_SIZE(s->cmd_data)) {
        return -EINVAL;
    }
    if (s->row < 0 || s->row >= 80) {
        return -EINVAL;
    }
    if (s->row_start < 0 || s->row_start >= 80) {
        return -EINVAL;
    }
    if (s->row_end < 0 || s->row_end >= 80) {
        return -EINVAL;
    }
    if (s->col < 0 || s->col >= 64) {
        return -EINVAL;
    }
    if (s->col_start < 0 || s->col_start >= 64) {
        return -EINVAL;
    }
    if (s->col_end < 0 || s->col_end >= 64) {
        return -EINVAL;
    }
    if (s->mode != SSD0323_CMD && s->mode != SSD0323_DATA) {
        return -EINVAL;
    }

    return 0;
}

static const VMStateDescription vmstate_ssd0323 = {
    .name = "ssd0323_oled",
    .version_id = 2,
    .minimum_version_id = 2,
    .post_load = ssd0323_post_load,
    .fields      = (VMStateField []) {
        VMSTATE_UINT32(cmd_len, ssd0323_state),
        VMSTATE_INT32(cmd, ssd0323_state),
        VMSTATE_INT32_ARRAY(cmd_data, ssd0323_state, 8),
        VMSTATE_INT32(row, ssd0323_state),
        VMSTATE_INT32(row_start, ssd0323_state),
        VMSTATE_INT32(row_end, ssd0323_state),
        VMSTATE_INT32(col, ssd0323_state),
        VMSTATE_INT32(col_start, ssd0323_state),
        VMSTATE_INT32(col_end, ssd0323_state),
        VMSTATE_INT32(redraw, ssd0323_state),
        VMSTATE_INT32(remap, ssd0323_state),
        VMSTATE_UINT32(mode, ssd0323_state),
        VMSTATE_BUFFER(framebuffer, ssd0323_state),
        VMSTATE_SSI_SLAVE(ssidev, ssd0323_state),
        VMSTATE_END_OF_LIST()
    }
};

static const GraphicHwOps ssd0323_ops = {
    .invalidate  = ssd0323_invalidate_display,
    .gfx_update  = ssd0323_update_display,
};

static void ssd0323_realize(SSISlave *d, Error **errp)
{
    DeviceState *dev = DEVICE(d);
    ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, d);

    s->col_end = 63;
    s->row_end = 79;
    s->con = graphic_console_init(dev, 0, &ssd0323_ops, s);
    qemu_console_resize(s->con, 128 * MAGNIFY, 64 * MAGNIFY);

    qdev_init_gpio_in(dev, ssd0323_cd, 1);
}

static void ssd0323_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SSISlaveClass *k = SSI_SLAVE_CLASS(klass);

    k->realize = ssd0323_realize;
    k->transfer = ssd0323_transfer;
    k->cs_polarity = SSI_CS_HIGH;
    dc->vmsd = &vmstate_ssd0323;
}

static const TypeInfo ssd0323_info = {
    .name          = "ssd0323",
    .parent        = TYPE_SSI_SLAVE,
    .instance_size = sizeof(ssd0323_state),
    .class_init    = ssd0323_class_init,
};

static void ssd03232_register_types(void)
{
    type_register_static(&ssd0323_info);
}

type_init(ssd03232_register_types)
Commit	Line	Data
9ee6e8bb PB	1	/*
	2	* SSD0323 OLED controller with OSRAM Pictiva 128x64 display.
	3	*
	4	* Copyright (c) 2006-2007 CodeSourcery.
	5	* Written by Paul Brook
	6	*
8e31bf38	7	* This code is licensed under the GPL.
9ee6e8bb PB	8	*/
	9
	10	/* The controller can support a variety of different displays, but we only
	11	implement one. Most of the commends relating to brightness and geometry
	12	setup are ignored. */
47df5154	13	#include "qemu/osdep.h"
8fd06719	14	#include "hw/ssi/ssi.h"
28ecbaee	15	#include "ui/console.h"
9ee6e8bb PB	16
	17	//#define DEBUG_SSD0323 1
	18
	19	#ifdef DEBUG_SSD0323
001faf32 BS	20	#define DPRINTF(fmt, ...) \
	21	do { printf("ssd0323: " fmt , ## __VA_ARGS__); } while (0)
	22	#define BADF(fmt, ...) \
b1c26542 PC	23	do { \
	24	fprintf(stderr, "ssd0323: error: " fmt , ## __VA_ARGS__); abort(); \
	25	} while (0)
9ee6e8bb	26	#else
001faf32 BS	27	#define DPRINTF(fmt, ...) do {} while(0)
	28	#define BADF(fmt, ...) \
	29	do { fprintf(stderr, "ssd0323: error: " fmt , ## __VA_ARGS__);} while (0)
9ee6e8bb PB	30	#endif
	31
	32	/* Scaling factor for pixels. */
	33	#define MAGNIFY 4
	34
7ac56ff0 PB	35	#define REMAP_SWAP_COLUMN 0x01
	36	#define REMAP_SWAP_NYBBLE 0x02
	37	#define REMAP_VERTICAL 0x04
	38	#define REMAP_SWAP_COM 0x10
	39	#define REMAP_SPLIT_COM 0x40
	40
9ee6e8bb PB	41	enum ssd0323_mode
	42	{
	43	SSD0323_CMD,
	44	SSD0323_DATA
	45	};
	46
	47	typedef struct {
5493e33f	48	SSISlave ssidev;
c78f7137	49	QemuConsole *con;
9ee6e8bb	50
e7f76c52 DDAG	51	uint32_t cmd_len;
	52	int32_t cmd;
	53	int32_t cmd_data[8];
	54	int32_t row;
	55	int32_t row_start;
	56	int32_t row_end;
	57	int32_t col;
	58	int32_t col_start;
	59	int32_t col_end;
	60	int32_t redraw;
	61	int32_t remap;
	62	uint32_t mode;
9ee6e8bb PB	63	uint8_t framebuffer[128 * 80 / 2];
	64	} ssd0323_state;
	65
5493e33f	66	static uint32_t ssd0323_transfer(SSISlave *dev, uint32_t data)
9ee6e8bb	67	{
5493e33f PB	68	ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, dev);
5493e33f PB	69
9ee6e8bb PB	70	switch (s->mode) {
	71	case SSD0323_DATA:
	72	DPRINTF("data 0x%02x\n", data);
	73	s->framebuffer[s->col + s->row * 64] = data;
7ac56ff0	74	if (s->remap & REMAP_VERTICAL) {
9ee6e8bb	75	s->row++;
7ac56ff0 PB	76	if (s->row > s->row_end) {
	77	s->row = s->row_start;
	78	s->col++;
	79	}
	80	if (s->col > s->col_end) {
	81	s->col = s->col_start;
	82	}
	83	} else {
	84	s->col++;
	85	if (s->col > s->col_end) {
	86	s->row++;
	87	s->col = s->col_start;
	88	}
	89	if (s->row > s->row_end) {
	90	s->row = s->row_start;
	91	}
9ee6e8bb PB	92	}
	93	s->redraw = 1;
	94	break;
	95	case SSD0323_CMD:
	96	DPRINTF("cmd 0x%02x\n", data);
	97	if (s->cmd_len == 0) {
	98	s->cmd = data;
	99	} else {
	100	s->cmd_data[s->cmd_len - 1] = data;
	101	}
	102	s->cmd_len++;
	103	switch (s->cmd) {
	104	#define DATA(x) if (s->cmd_len <= (x)) return 0
	105	case 0x15: /* Set column. */
	106	DATA(2);
7ac56ff0	107	s->col = s->col_start = s->cmd_data[0] % 64;
9ee6e8bb PB	108	s->col_end = s->cmd_data[1] % 64;
	109	break;
	110	case 0x75: /* Set row. */
	111	DATA(2);
7ac56ff0	112	s->row = s->row_start = s->cmd_data[0] % 80;
9ee6e8bb PB	113	s->row_end = s->cmd_data[1] % 80;
	114	break;
	115	case 0x81: /* Set contrast */
	116	DATA(1);
	117	break;
	118	case 0x84: case 0x85: case 0x86: /* Max current. */
	119	DATA(0);
	120	break;
	121	case 0xa0: /* Set remapping. */
	122	/* FIXME: Implement this. */
	123	DATA(1);
7ac56ff0	124	s->remap = s->cmd_data[0];
9ee6e8bb PB	125	break;
	126	case 0xa1: /* Set display start line. */
	127	case 0xa2: /* Set display offset. */
	128	/* FIXME: Implement these. */
	129	DATA(1);
	130	break;
	131	case 0xa4: /* Normal mode. */
	132	case 0xa5: /* All on. */
	133	case 0xa6: /* All off. */
	134	case 0xa7: /* Inverse. */
	135	/* FIXME: Implement these. */
	136	DATA(0);
	137	break;
	138	case 0xa8: /* Set multiplex ratio. */
	139	case 0xad: /* Set DC-DC converter. */
	140	DATA(1);
	141	/* Ignored. Don't care. */
	142	break;
	143	case 0xae: /* Display off. */
	144	case 0xaf: /* Display on. */
	145	DATA(0);
	146	/* TODO: Implement power control. */
	147	break;
	148	case 0xb1: /* Set phase length. */
	149	case 0xb2: /* Set row period. */
	150	case 0xb3: /* Set clock rate. */
	151	case 0xbc: /* Set precharge. */
	152	case 0xbe: /* Set VCOMH. */
	153	case 0xbf: /* Set segment low. */
	154	DATA(1);
	155	/* Ignored. Don't care. */
	156	break;
	157	case 0xb8: /* Set grey scale table. */
	158	/* FIXME: Implement this. */
	159	DATA(8);
	160	break;
	161	case 0xe3: /* NOP. */
	162	DATA(0);
	163	break;
775616c3 PB	164	case 0xff: /* Nasty hack because we don't handle chip selects
	165	properly. */
	166	break;
9ee6e8bb PB	167	default:
	168	BADF("Unknown command: 0x%x\n", data);
	169	}
	170	s->cmd_len = 0;
	171	return 0;
	172	}
	173	return 0;
	174	}
	175
	176	static void ssd0323_update_display(void *opaque)
	177	{
	178	ssd0323_state s = (ssd0323_state )opaque;
c78f7137	179	DisplaySurface *surface = qemu_console_surface(s->con);
9ee6e8bb PB	180	uint8_t *dest;
	181	uint8_t *src;
	182	int x;
	183	int y;
	184	int i;
	185	int line;
	186	char *colors[16];
	187	char colortab[MAGNIFY * 64];
	188	char *p;
	189	int dest_width;
	190
b115bb3f PB	191	if (!s->redraw)
	192	return;
	193
c78f7137	194	switch (surface_bits_per_pixel(surface)) {
b115bb3f PB	195	case 0:
	196	return;
	197	case 15:
	198	dest_width = 2;
	199	break;
	200	case 16:
	201	dest_width = 2;
	202	break;
	203	case 24:
	204	dest_width = 3;
	205	break;
	206	case 32:
	207	dest_width = 4;
	208	break;
	209	default:
	210	BADF("Bad color depth\n");
	211	return;
	212	}
	213	p = colortab;
	214	for (i = 0; i < 16; i++) {
	215	int n;
	216	colors[i] = p;
c78f7137	217	switch (surface_bits_per_pixel(surface)) {
9ee6e8bb	218	case 15:
b115bb3f PB	219	n = i * 2 + (i >> 3);
	220	p[0] = n \| (n << 5);
	221	p[1] = (n << 2) \| (n >> 3);
9ee6e8bb PB	222	break;
9ee6e8bb PB	223	case 16:
b115bb3f PB	224	n = i * 2 + (i >> 3);
	225	p[0] = n \| (n << 6) \| ((n << 1) & 0x20);
	226	p[1] = (n << 3) \| (n >> 2);
9ee6e8bb PB	227	break;
9ee6e8bb PB	228	case 24:
9ee6e8bb	229	case 32:
b115bb3f PB	230	n = (i << 4) \| i;
b115bb3f PB	231	p[0] = p[1] = p[2] = n;
9ee6e8bb PB	232	break;
	233	default:
	234	BADF("Bad color depth\n");
	235	return;
	236	}
b115bb3f PB	237	p += dest_width;
	238	}
	239	/* TODO: Implement row/column remapping. */
c78f7137	240	dest = surface_data(surface);
b115bb3f PB	241	for (y = 0; y < 64; y++) {
	242	line = y;
	243	src = s->framebuffer + 64 * line;
	244	for (x = 0; x < 64; x++) {
	245	int val;
	246	val = *src >> 4;
	247	for (i = 0; i < MAGNIFY; i++) {
	248	memcpy(dest, colors[val], dest_width);
	249	dest += dest_width;
9ee6e8bb	250	}
b115bb3f PB	251	val = *src & 0xf;
	252	for (i = 0; i < MAGNIFY; i++) {
	253	memcpy(dest, colors[val], dest_width);
	254	dest += dest_width;
9ee6e8bb	255	}
b115bb3f PB	256	src++;
	257	}
	258	for (i = 1; i < MAGNIFY; i++) {
	259	memcpy(dest, dest - dest_width * MAGNIFY * 128,
	260	dest_width * 128 * MAGNIFY);
	261	dest += dest_width * 128 * MAGNIFY;
9ee6e8bb PB	262	}
9ee6e8bb PB	263	}
b115bb3f	264	s->redraw = 0;
c78f7137	265	dpy_gfx_update(s->con, 0, 0, 128 * MAGNIFY, 64 * MAGNIFY);
9ee6e8bb PB	266	}
	267
	268	static void ssd0323_invalidate_display(void * opaque)
	269	{
	270	ssd0323_state s = (ssd0323_state )opaque;
	271	s->redraw = 1;
	272	}
	273
	274	/* Command/data input. */
	275	static void ssd0323_cd(void *opaque, int n, int level)
	276	{
	277	ssd0323_state s = (ssd0323_state )opaque;
	278	DPRINTF("%s mode\n", level ? "Data" : "Command");
	279	s->mode = level ? SSD0323_DATA : SSD0323_CMD;
	280	}
	281
e7f76c52	282	static int ssd0323_post_load(void *opaque, int version_id)
23e39294 PB	283	{
23e39294 PB	284	ssd0323_state s = (ssd0323_state )opaque;
23e39294	285
e7f76c52	286	if (s->cmd_len > ARRAY_SIZE(s->cmd_data)) {
ead7a57d MT	287	return -EINVAL;
ead7a57d MT	288	}
ead7a57d MT	289	if (s->row < 0 \|\| s->row >= 80) {
	290	return -EINVAL;
	291	}
ead7a57d MT	292	if (s->row_start < 0 \|\| s->row_start >= 80) {
	293	return -EINVAL;
	294	}
ead7a57d MT	295	if (s->row_end < 0 \|\| s->row_end >= 80) {
	296	return -EINVAL;
	297	}
ead7a57d MT	298	if (s->col < 0 \|\| s->col >= 64) {
	299	return -EINVAL;
	300	}
ead7a57d MT	301	if (s->col_start < 0 \|\| s->col_start >= 64) {
	302	return -EINVAL;
	303	}
ead7a57d MT	304	if (s->col_end < 0 \|\| s->col_end >= 64) {
	305	return -EINVAL;
	306	}
ead7a57d MT	307	if (s->mode != SSD0323_CMD && s->mode != SSD0323_DATA) {
	308	return -EINVAL;
	309	}
66530953	310
23e39294 PB	311	return 0;
	312	}
	313
e7f76c52 DDAG	314	static const VMStateDescription vmstate_ssd0323 = {
	315	.name = "ssd0323_oled",
	316	.version_id = 2,
	317	.minimum_version_id = 2,
	318	.post_load = ssd0323_post_load,
	319	.fields = (VMStateField []) {
	320	VMSTATE_UINT32(cmd_len, ssd0323_state),
	321	VMSTATE_INT32(cmd, ssd0323_state),
	322	VMSTATE_INT32_ARRAY(cmd_data, ssd0323_state, 8),
	323	VMSTATE_INT32(row, ssd0323_state),
	324	VMSTATE_INT32(row_start, ssd0323_state),
	325	VMSTATE_INT32(row_end, ssd0323_state),
	326	VMSTATE_INT32(col, ssd0323_state),
	327	VMSTATE_INT32(col_start, ssd0323_state),
	328	VMSTATE_INT32(col_end, ssd0323_state),
	329	VMSTATE_INT32(redraw, ssd0323_state),
	330	VMSTATE_INT32(remap, ssd0323_state),
	331	VMSTATE_UINT32(mode, ssd0323_state),
	332	VMSTATE_BUFFER(framebuffer, ssd0323_state),
	333	VMSTATE_SSI_SLAVE(ssidev, ssd0323_state),
	334	VMSTATE_END_OF_LIST()
	335	}
	336	};
	337
380cd056 GH	338	static const GraphicHwOps ssd0323_ops = {
	339	.invalidate = ssd0323_invalidate_display,
	340	.gfx_update = ssd0323_update_display,
	341	};
	342
7673bb4c	343	static void ssd0323_realize(SSISlave d, Error *errp)
9ee6e8bb	344	{
1a7d9ee6 PC	345	DeviceState *dev = DEVICE(d);
1a7d9ee6 PC	346	ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, d);
9ee6e8bb	347
9ee6e8bb PB	348	s->col_end = 63;
9ee6e8bb PB	349	s->row_end = 79;
1a7d9ee6	350	s->con = graphic_console_init(dev, 0, &ssd0323_ops, s);
c78f7137	351	qemu_console_resize(s->con, 128 * MAGNIFY, 64 * MAGNIFY);
9ee6e8bb	352
1a7d9ee6	353	qdev_init_gpio_in(dev, ssd0323_cd, 1);
5493e33f	354	}
23e39294	355
cd6c4cf2 AL	356	static void ssd0323_class_init(ObjectClass klass, void data)
cd6c4cf2 AL	357	{
e7f76c52	358	DeviceClass *dc = DEVICE_CLASS(klass);
cd6c4cf2 AL	359	SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
cd6c4cf2 AL	360
7673bb4c	361	k->realize = ssd0323_realize;
cd6c4cf2	362	k->transfer = ssd0323_transfer;
8120e714	363	k->cs_polarity = SSI_CS_HIGH;
e7f76c52	364	dc->vmsd = &vmstate_ssd0323;
cd6c4cf2 AL	365	}
cd6c4cf2 AL	366
8c43a6f0	367	static const TypeInfo ssd0323_info = {
39bffca2 AL	368	.name = "ssd0323",
	369	.parent = TYPE_SSI_SLAVE,
	370	.instance_size = sizeof(ssd0323_state),
	371	.class_init = ssd0323_class_init,
5493e33f PB	372	};
5493e33f PB	373
83f7d43a	374	static void ssd03232_register_types(void)
5493e33f	375	{
39bffca2	376	type_register_static(&ssd0323_info);
9ee6e8bb	377	}
5493e33f	378
83f7d43a	379	type_init(ssd03232_register_types)