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Commit | Line | Data |
---|---|---|
420557e8 | 1 | /* |
6f7e9aec | 2 | * QEMU TCX Frame buffer |
5fafdf24 | 3 | * |
6f7e9aec | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
5fafdf24 | 5 | * |
420557e8 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
f40070c3 | 24 | |
47df5154 | 25 | #include "qemu/osdep.h" |
a8d25326 | 26 | #include "qemu-common.h" |
da34e65c | 27 | #include "qapi/error.h" |
28ecbaee PB |
28 | #include "ui/console.h" |
29 | #include "ui/pixel_ops.h" | |
da87dd7b | 30 | #include "hw/loader.h" |
a27bd6c7 | 31 | #include "hw/qdev-properties.h" |
83c9f4ca | 32 | #include "hw/sysbus.h" |
d6454270 | 33 | #include "migration/vmstate.h" |
d49b6836 | 34 | #include "qemu/error-report.h" |
0b8fa32f | 35 | #include "qemu/module.h" |
420557e8 | 36 | |
da87dd7b MCA |
37 | #define TCX_ROM_FILE "QEMU,tcx.bin" |
38 | #define FCODE_MAX_ROM_SIZE 0x10000 | |
39 | ||
420557e8 FB |
40 | #define MAXX 1024 |
41 | #define MAXY 768 | |
55d7bfe2 MCA |
42 | #define TCX_DAC_NREGS 16 |
43 | #define TCX_THC_NREGS 0x1000 | |
44 | #define TCX_DHC_NREGS 0x4000 | |
8508b89e | 45 | #define TCX_TEC_NREGS 0x1000 |
55d7bfe2 MCA |
46 | #define TCX_ALT_NREGS 0x8000 |
47 | #define TCX_STIP_NREGS 0x800000 | |
48 | #define TCX_BLIT_NREGS 0x800000 | |
49 | #define TCX_RSTIP_NREGS 0x800000 | |
50 | #define TCX_RBLIT_NREGS 0x800000 | |
51 | ||
52 | #define TCX_THC_MISC 0x818 | |
53 | #define TCX_THC_CURSXY 0x8fc | |
54 | #define TCX_THC_CURSMASK 0x900 | |
55 | #define TCX_THC_CURSBITS 0x980 | |
420557e8 | 56 | |
01774ddb AF |
57 | #define TYPE_TCX "SUNW,tcx" |
58 | #define TCX(obj) OBJECT_CHECK(TCXState, (obj), TYPE_TCX) | |
59 | ||
420557e8 | 60 | typedef struct TCXState { |
01774ddb AF |
61 | SysBusDevice parent_obj; |
62 | ||
c78f7137 | 63 | QemuConsole *con; |
55d7bfe2 | 64 | qemu_irq irq; |
8d5f07fa | 65 | uint8_t *vram; |
eee0b836 | 66 | uint32_t *vram24, *cplane; |
da87dd7b MCA |
67 | hwaddr prom_addr; |
68 | MemoryRegion rom; | |
d08151bf AK |
69 | MemoryRegion vram_mem; |
70 | MemoryRegion vram_8bit; | |
71 | MemoryRegion vram_24bit; | |
55d7bfe2 MCA |
72 | MemoryRegion stip; |
73 | MemoryRegion blit; | |
d08151bf | 74 | MemoryRegion vram_cplane; |
55d7bfe2 MCA |
75 | MemoryRegion rstip; |
76 | MemoryRegion rblit; | |
d08151bf | 77 | MemoryRegion tec; |
55d7bfe2 MCA |
78 | MemoryRegion dac; |
79 | MemoryRegion thc; | |
80 | MemoryRegion dhc; | |
81 | MemoryRegion alt; | |
d08151bf | 82 | MemoryRegion thc24; |
55d7bfe2 | 83 | |
d08151bf | 84 | ram_addr_t vram24_offset, cplane_offset; |
55d7bfe2 | 85 | uint32_t tmpblit; |
ee6847d1 | 86 | uint32_t vram_size; |
55d7bfe2 MCA |
87 | uint32_t palette[260]; |
88 | uint8_t r[260], g[260], b[260]; | |
427a66c3 | 89 | uint16_t width, height, depth; |
6f7e9aec | 90 | uint8_t dac_index, dac_state; |
55d7bfe2 MCA |
91 | uint32_t thcmisc; |
92 | uint32_t cursmask[32]; | |
93 | uint32_t cursbits[32]; | |
94 | uint16_t cursx; | |
95 | uint16_t cursy; | |
420557e8 FB |
96 | } TCXState; |
97 | ||
9800b3c2 | 98 | static void tcx_set_dirty(TCXState *s, ram_addr_t addr, int len) |
d3ffcafe | 99 | { |
9800b3c2 | 100 | memory_region_set_dirty(&s->vram_mem, addr, len); |
4b865c28 MCA |
101 | |
102 | if (s->depth == 24) { | |
103 | memory_region_set_dirty(&s->vram_mem, s->vram24_offset + addr * 4, | |
104 | len * 4); | |
105 | memory_region_set_dirty(&s->vram_mem, s->cplane_offset + addr * 4, | |
106 | len * 4); | |
107 | } | |
d3ffcafe BS |
108 | } |
109 | ||
2dd285b5 MCA |
110 | static int tcx_check_dirty(TCXState *s, DirtyBitmapSnapshot *snap, |
111 | ram_addr_t addr, int len) | |
d3ffcafe | 112 | { |
55d7bfe2 MCA |
113 | int ret; |
114 | ||
2dd285b5 | 115 | ret = memory_region_snapshot_get_dirty(&s->vram_mem, snap, addr, len); |
427ee02b MCA |
116 | |
117 | if (s->depth == 24) { | |
2dd285b5 MCA |
118 | ret |= memory_region_snapshot_get_dirty(&s->vram_mem, snap, |
119 | s->vram24_offset + addr * 4, len * 4); | |
120 | ret |= memory_region_snapshot_get_dirty(&s->vram_mem, snap, | |
121 | s->cplane_offset + addr * 4, len * 4); | |
427ee02b MCA |
122 | } |
123 | ||
55d7bfe2 MCA |
124 | return ret; |
125 | } | |
126 | ||
21206a10 FB |
127 | static void update_palette_entries(TCXState *s, int start, int end) |
128 | { | |
c78f7137 | 129 | DisplaySurface *surface = qemu_console_surface(s->con); |
21206a10 | 130 | int i; |
c78f7137 GH |
131 | |
132 | for (i = start; i < end; i++) { | |
ee72bed0 MCA |
133 | if (is_surface_bgr(surface)) { |
134 | s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]); | |
135 | } else { | |
136 | s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); | |
21206a10 FB |
137 | } |
138 | } | |
9800b3c2 | 139 | tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem)); |
21206a10 FB |
140 | } |
141 | ||
5fafdf24 | 142 | static void tcx_draw_line32(TCXState *s1, uint8_t *d, |
f930d07e | 143 | const uint8_t *s, int width) |
420557e8 | 144 | { |
e80cfcfc FB |
145 | int x; |
146 | uint8_t val; | |
8bdc2159 | 147 | uint32_t *p = (uint32_t *)d; |
e80cfcfc | 148 | |
55d7bfe2 | 149 | for (x = 0; x < width; x++) { |
f930d07e | 150 | val = *s++; |
8bdc2159 | 151 | *p++ = s1->palette[val]; |
e80cfcfc | 152 | } |
420557e8 FB |
153 | } |
154 | ||
55d7bfe2 MCA |
155 | static void tcx_draw_cursor32(TCXState *s1, uint8_t *d, |
156 | int y, int width) | |
157 | { | |
158 | int x, len; | |
159 | uint32_t mask, bits; | |
160 | uint32_t *p = (uint32_t *)d; | |
161 | ||
162 | y = y - s1->cursy; | |
163 | mask = s1->cursmask[y]; | |
164 | bits = s1->cursbits[y]; | |
165 | len = MIN(width - s1->cursx, 32); | |
166 | p = &p[s1->cursx]; | |
167 | for (x = 0; x < len; x++) { | |
168 | if (mask & 0x80000000) { | |
169 | if (bits & 0x80000000) { | |
170 | *p = s1->palette[259]; | |
171 | } else { | |
172 | *p = s1->palette[258]; | |
173 | } | |
174 | } | |
175 | p++; | |
176 | mask <<= 1; | |
177 | bits <<= 1; | |
178 | } | |
179 | } | |
180 | ||
688ea2eb BS |
181 | /* |
182 | XXX Could be much more optimal: | |
183 | * detect if line/page/whole screen is in 24 bit mode | |
184 | * if destination is also BGR, use memcpy | |
185 | */ | |
eee0b836 BS |
186 | static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, |
187 | const uint8_t *s, int width, | |
188 | const uint32_t *cplane, | |
189 | const uint32_t *s24) | |
190 | { | |
c78f7137 | 191 | DisplaySurface *surface = qemu_console_surface(s1->con); |
7b5d76da | 192 | int x, bgr, r, g, b; |
688ea2eb | 193 | uint8_t val, *p8; |
eee0b836 BS |
194 | uint32_t *p = (uint32_t *)d; |
195 | uint32_t dval; | |
c78f7137 | 196 | bgr = is_surface_bgr(surface); |
eee0b836 | 197 | for(x = 0; x < width; x++, s++, s24++) { |
55d7bfe2 MCA |
198 | if (be32_to_cpu(*cplane) & 0x03000000) { |
199 | /* 24-bit direct, BGR order */ | |
688ea2eb BS |
200 | p8 = (uint8_t *)s24; |
201 | p8++; | |
202 | b = *p8++; | |
203 | g = *p8++; | |
f7e683b8 | 204 | r = *p8; |
7b5d76da AL |
205 | if (bgr) |
206 | dval = rgb_to_pixel32bgr(r, g, b); | |
207 | else | |
208 | dval = rgb_to_pixel32(r, g, b); | |
eee0b836 | 209 | } else { |
55d7bfe2 | 210 | /* 8-bit pseudocolor */ |
eee0b836 BS |
211 | val = *s; |
212 | dval = s1->palette[val]; | |
213 | } | |
214 | *p++ = dval; | |
55d7bfe2 | 215 | cplane++; |
eee0b836 BS |
216 | } |
217 | } | |
218 | ||
e80cfcfc FB |
219 | /* Fixed line length 1024 allows us to do nice tricks not possible on |
220 | VGA... */ | |
55d7bfe2 | 221 | |
95219897 | 222 | static void tcx_update_display(void *opaque) |
420557e8 | 223 | { |
e80cfcfc | 224 | TCXState *ts = opaque; |
c78f7137 | 225 | DisplaySurface *surface = qemu_console_surface(ts->con); |
2dd285b5 MCA |
226 | ram_addr_t page; |
227 | DirtyBitmapSnapshot *snap = NULL; | |
550be127 | 228 | int y, y_start, dd, ds; |
e80cfcfc | 229 | uint8_t *d, *s; |
e80cfcfc | 230 | |
ee72bed0 | 231 | if (surface_bits_per_pixel(surface) != 32) { |
f930d07e | 232 | return; |
c78f7137 GH |
233 | } |
234 | ||
d08151bf | 235 | page = 0; |
e80cfcfc | 236 | y_start = -1; |
c78f7137 | 237 | d = surface_data(surface); |
6f7e9aec | 238 | s = ts->vram; |
c78f7137 | 239 | dd = surface_stride(surface); |
e80cfcfc FB |
240 | ds = 1024; |
241 | ||
2dd285b5 MCA |
242 | snap = memory_region_snapshot_and_clear_dirty(&ts->vram_mem, 0x0, |
243 | memory_region_size(&ts->vram_mem), | |
244 | DIRTY_MEMORY_VGA); | |
245 | ||
0a97c6c4 | 246 | for (y = 0; y < ts->height; y++, page += ds) { |
2dd285b5 | 247 | if (tcx_check_dirty(ts, snap, page, ds)) { |
f930d07e | 248 | if (y_start < 0) |
e80cfcfc | 249 | y_start = y; |
55d7bfe2 | 250 | |
ee72bed0 | 251 | tcx_draw_line32(ts, d, s, ts->width); |
55d7bfe2 | 252 | if (y >= ts->cursy && y < ts->cursy + 32 && ts->cursx < ts->width) { |
ee72bed0 | 253 | tcx_draw_cursor32(ts, d, y, ts->width); |
55d7bfe2 | 254 | } |
f930d07e | 255 | } else { |
e80cfcfc FB |
256 | if (y_start >= 0) { |
257 | /* flush to display */ | |
c78f7137 | 258 | dpy_gfx_update(ts->con, 0, y_start, |
a93a4a22 | 259 | ts->width, y - y_start); |
e80cfcfc FB |
260 | y_start = -1; |
261 | } | |
f930d07e | 262 | } |
0a97c6c4 MCA |
263 | s += ds; |
264 | d += dd; | |
e80cfcfc FB |
265 | } |
266 | if (y_start >= 0) { | |
f930d07e | 267 | /* flush to display */ |
c78f7137 | 268 | dpy_gfx_update(ts->con, 0, y_start, |
a93a4a22 | 269 | ts->width, y - y_start); |
e80cfcfc | 270 | } |
2dd285b5 | 271 | g_free(snap); |
420557e8 FB |
272 | } |
273 | ||
eee0b836 BS |
274 | static void tcx24_update_display(void *opaque) |
275 | { | |
276 | TCXState *ts = opaque; | |
c78f7137 | 277 | DisplaySurface *surface = qemu_console_surface(ts->con); |
2dd285b5 MCA |
278 | ram_addr_t page; |
279 | DirtyBitmapSnapshot *snap = NULL; | |
eee0b836 BS |
280 | int y, y_start, dd, ds; |
281 | uint8_t *d, *s; | |
282 | uint32_t *cptr, *s24; | |
283 | ||
c78f7137 | 284 | if (surface_bits_per_pixel(surface) != 32) { |
eee0b836 | 285 | return; |
c78f7137 GH |
286 | } |
287 | ||
d08151bf | 288 | page = 0; |
eee0b836 | 289 | y_start = -1; |
c78f7137 | 290 | d = surface_data(surface); |
eee0b836 BS |
291 | s = ts->vram; |
292 | s24 = ts->vram24; | |
293 | cptr = ts->cplane; | |
c78f7137 | 294 | dd = surface_stride(surface); |
eee0b836 BS |
295 | ds = 1024; |
296 | ||
2dd285b5 MCA |
297 | snap = memory_region_snapshot_and_clear_dirty(&ts->vram_mem, 0x0, |
298 | memory_region_size(&ts->vram_mem), | |
299 | DIRTY_MEMORY_VGA); | |
300 | ||
d18e1012 | 301 | for (y = 0; y < ts->height; y++, page += ds) { |
2dd285b5 | 302 | if (tcx_check_dirty(ts, snap, page, ds)) { |
eee0b836 BS |
303 | if (y_start < 0) |
304 | y_start = y; | |
2dd285b5 | 305 | |
eee0b836 | 306 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
55d7bfe2 MCA |
307 | if (y >= ts->cursy && y < ts->cursy+32 && ts->cursx < ts->width) { |
308 | tcx_draw_cursor32(ts, d, y, ts->width); | |
309 | } | |
eee0b836 BS |
310 | } else { |
311 | if (y_start >= 0) { | |
312 | /* flush to display */ | |
c78f7137 | 313 | dpy_gfx_update(ts->con, 0, y_start, |
a93a4a22 | 314 | ts->width, y - y_start); |
eee0b836 BS |
315 | y_start = -1; |
316 | } | |
eee0b836 | 317 | } |
d18e1012 MCA |
318 | d += dd; |
319 | s += ds; | |
320 | cptr += ds; | |
321 | s24 += ds; | |
eee0b836 BS |
322 | } |
323 | if (y_start >= 0) { | |
324 | /* flush to display */ | |
c78f7137 | 325 | dpy_gfx_update(ts->con, 0, y_start, |
a93a4a22 | 326 | ts->width, y - y_start); |
eee0b836 | 327 | } |
2dd285b5 | 328 | g_free(snap); |
eee0b836 BS |
329 | } |
330 | ||
95219897 | 331 | static void tcx_invalidate_display(void *opaque) |
420557e8 | 332 | { |
e80cfcfc | 333 | TCXState *s = opaque; |
e80cfcfc | 334 | |
9800b3c2 | 335 | tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem)); |
c78f7137 | 336 | qemu_console_resize(s->con, s->width, s->height); |
420557e8 FB |
337 | } |
338 | ||
eee0b836 BS |
339 | static void tcx24_invalidate_display(void *opaque) |
340 | { | |
341 | TCXState *s = opaque; | |
eee0b836 | 342 | |
9800b3c2 | 343 | tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem)); |
c78f7137 | 344 | qemu_console_resize(s->con, s->width, s->height); |
eee0b836 BS |
345 | } |
346 | ||
e59fb374 | 347 | static int vmstate_tcx_post_load(void *opaque, int version_id) |
420557e8 FB |
348 | { |
349 | TCXState *s = opaque; | |
3b46e624 | 350 | |
21206a10 | 351 | update_palette_entries(s, 0, 256); |
9800b3c2 | 352 | tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem)); |
e80cfcfc | 353 | return 0; |
420557e8 FB |
354 | } |
355 | ||
c0c41a4b BS |
356 | static const VMStateDescription vmstate_tcx = { |
357 | .name ="tcx", | |
358 | .version_id = 4, | |
359 | .minimum_version_id = 4, | |
752ff2fa | 360 | .post_load = vmstate_tcx_post_load, |
35d08458 | 361 | .fields = (VMStateField[]) { |
c0c41a4b BS |
362 | VMSTATE_UINT16(height, TCXState), |
363 | VMSTATE_UINT16(width, TCXState), | |
364 | VMSTATE_UINT16(depth, TCXState), | |
365 | VMSTATE_BUFFER(r, TCXState), | |
366 | VMSTATE_BUFFER(g, TCXState), | |
367 | VMSTATE_BUFFER(b, TCXState), | |
368 | VMSTATE_UINT8(dac_index, TCXState), | |
369 | VMSTATE_UINT8(dac_state, TCXState), | |
370 | VMSTATE_END_OF_LIST() | |
371 | } | |
372 | }; | |
373 | ||
7f23f812 | 374 | static void tcx_reset(DeviceState *d) |
420557e8 | 375 | { |
01774ddb | 376 | TCXState *s = TCX(d); |
e80cfcfc FB |
377 | |
378 | /* Initialize palette */ | |
55d7bfe2 MCA |
379 | memset(s->r, 0, 260); |
380 | memset(s->g, 0, 260); | |
381 | memset(s->b, 0, 260); | |
e80cfcfc | 382 | s->r[255] = s->g[255] = s->b[255] = 255; |
55d7bfe2 MCA |
383 | s->r[256] = s->g[256] = s->b[256] = 255; |
384 | s->r[258] = s->g[258] = s->b[258] = 255; | |
385 | update_palette_entries(s, 0, 260); | |
e80cfcfc | 386 | memset(s->vram, 0, MAXX*MAXY); |
d08151bf AK |
387 | memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4), |
388 | DIRTY_MEMORY_VGA); | |
6f7e9aec FB |
389 | s->dac_index = 0; |
390 | s->dac_state = 0; | |
55d7bfe2 MCA |
391 | s->cursx = 0xf000; /* Put cursor off screen */ |
392 | s->cursy = 0xf000; | |
6f7e9aec FB |
393 | } |
394 | ||
a8170e5e | 395 | static uint64_t tcx_dac_readl(void *opaque, hwaddr addr, |
d08151bf | 396 | unsigned size) |
6f7e9aec | 397 | { |
55d7bfe2 MCA |
398 | TCXState *s = opaque; |
399 | uint32_t val = 0; | |
400 | ||
401 | switch (s->dac_state) { | |
402 | case 0: | |
403 | val = s->r[s->dac_index] << 24; | |
404 | s->dac_state++; | |
405 | break; | |
406 | case 1: | |
407 | val = s->g[s->dac_index] << 24; | |
408 | s->dac_state++; | |
409 | break; | |
410 | case 2: | |
411 | val = s->b[s->dac_index] << 24; | |
412 | s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */ | |
413 | default: | |
414 | s->dac_state = 0; | |
415 | break; | |
416 | } | |
417 | ||
418 | return val; | |
6f7e9aec FB |
419 | } |
420 | ||
a8170e5e | 421 | static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val, |
d08151bf | 422 | unsigned size) |
6f7e9aec FB |
423 | { |
424 | TCXState *s = opaque; | |
55d7bfe2 | 425 | unsigned index; |
6f7e9aec | 426 | |
e64d7d59 | 427 | switch (addr) { |
55d7bfe2 | 428 | case 0: /* Address */ |
f930d07e BS |
429 | s->dac_index = val >> 24; |
430 | s->dac_state = 0; | |
431 | break; | |
55d7bfe2 MCA |
432 | case 4: /* Pixel colours */ |
433 | case 12: /* Overlay (cursor) colours */ | |
434 | if (addr & 8) { | |
435 | index = (s->dac_index & 3) + 256; | |
436 | } else { | |
437 | index = s->dac_index; | |
438 | } | |
f930d07e BS |
439 | switch (s->dac_state) { |
440 | case 0: | |
55d7bfe2 MCA |
441 | s->r[index] = val >> 24; |
442 | update_palette_entries(s, index, index + 1); | |
f930d07e BS |
443 | s->dac_state++; |
444 | break; | |
445 | case 1: | |
55d7bfe2 MCA |
446 | s->g[index] = val >> 24; |
447 | update_palette_entries(s, index, index + 1); | |
f930d07e BS |
448 | s->dac_state++; |
449 | break; | |
450 | case 2: | |
55d7bfe2 MCA |
451 | s->b[index] = val >> 24; |
452 | update_palette_entries(s, index, index + 1); | |
453 | s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */ | |
f930d07e BS |
454 | default: |
455 | s->dac_state = 0; | |
456 | break; | |
457 | } | |
458 | break; | |
55d7bfe2 | 459 | default: /* Control registers */ |
f930d07e | 460 | break; |
6f7e9aec | 461 | } |
420557e8 FB |
462 | } |
463 | ||
d08151bf AK |
464 | static const MemoryRegionOps tcx_dac_ops = { |
465 | .read = tcx_dac_readl, | |
466 | .write = tcx_dac_writel, | |
467 | .endianness = DEVICE_NATIVE_ENDIAN, | |
468 | .valid = { | |
469 | .min_access_size = 4, | |
470 | .max_access_size = 4, | |
471 | }, | |
6f7e9aec FB |
472 | }; |
473 | ||
55d7bfe2 MCA |
474 | static uint64_t tcx_stip_readl(void *opaque, hwaddr addr, |
475 | unsigned size) | |
476 | { | |
477 | return 0; | |
478 | } | |
479 | ||
480 | static void tcx_stip_writel(void *opaque, hwaddr addr, | |
481 | uint64_t val, unsigned size) | |
482 | { | |
483 | TCXState *s = opaque; | |
484 | int i; | |
485 | uint32_t col; | |
486 | ||
487 | if (!(addr & 4)) { | |
488 | s->tmpblit = val; | |
489 | } else { | |
490 | addr = (addr >> 3) & 0xfffff; | |
491 | col = cpu_to_be32(s->tmpblit); | |
492 | if (s->depth == 24) { | |
493 | for (i = 0; i < 32; i++) { | |
494 | if (val & 0x80000000) { | |
495 | s->vram[addr + i] = s->tmpblit; | |
496 | s->vram24[addr + i] = col; | |
497 | } | |
498 | val <<= 1; | |
499 | } | |
500 | } else { | |
501 | for (i = 0; i < 32; i++) { | |
502 | if (val & 0x80000000) { | |
503 | s->vram[addr + i] = s->tmpblit; | |
504 | } | |
505 | val <<= 1; | |
506 | } | |
507 | } | |
97394580 | 508 | tcx_set_dirty(s, addr, 32); |
55d7bfe2 MCA |
509 | } |
510 | } | |
511 | ||
512 | static void tcx_rstip_writel(void *opaque, hwaddr addr, | |
513 | uint64_t val, unsigned size) | |
514 | { | |
515 | TCXState *s = opaque; | |
516 | int i; | |
517 | uint32_t col; | |
518 | ||
519 | if (!(addr & 4)) { | |
520 | s->tmpblit = val; | |
521 | } else { | |
522 | addr = (addr >> 3) & 0xfffff; | |
523 | col = cpu_to_be32(s->tmpblit); | |
524 | if (s->depth == 24) { | |
525 | for (i = 0; i < 32; i++) { | |
526 | if (val & 0x80000000) { | |
527 | s->vram[addr + i] = s->tmpblit; | |
528 | s->vram24[addr + i] = col; | |
529 | s->cplane[addr + i] = col; | |
530 | } | |
531 | val <<= 1; | |
532 | } | |
533 | } else { | |
534 | for (i = 0; i < 32; i++) { | |
535 | if (val & 0x80000000) { | |
536 | s->vram[addr + i] = s->tmpblit; | |
537 | } | |
538 | val <<= 1; | |
539 | } | |
540 | } | |
97394580 | 541 | tcx_set_dirty(s, addr, 32); |
55d7bfe2 MCA |
542 | } |
543 | } | |
544 | ||
545 | static const MemoryRegionOps tcx_stip_ops = { | |
546 | .read = tcx_stip_readl, | |
547 | .write = tcx_stip_writel, | |
548 | .endianness = DEVICE_NATIVE_ENDIAN, | |
549 | .valid = { | |
550 | .min_access_size = 4, | |
551 | .max_access_size = 4, | |
552 | }, | |
553 | }; | |
554 | ||
555 | static const MemoryRegionOps tcx_rstip_ops = { | |
556 | .read = tcx_stip_readl, | |
557 | .write = tcx_rstip_writel, | |
558 | .endianness = DEVICE_NATIVE_ENDIAN, | |
559 | .valid = { | |
560 | .min_access_size = 4, | |
561 | .max_access_size = 4, | |
562 | }, | |
563 | }; | |
564 | ||
565 | static uint64_t tcx_blit_readl(void *opaque, hwaddr addr, | |
566 | unsigned size) | |
567 | { | |
568 | return 0; | |
569 | } | |
570 | ||
571 | static void tcx_blit_writel(void *opaque, hwaddr addr, | |
572 | uint64_t val, unsigned size) | |
573 | { | |
574 | TCXState *s = opaque; | |
575 | uint32_t adsr, len; | |
576 | int i; | |
577 | ||
578 | if (!(addr & 4)) { | |
579 | s->tmpblit = val; | |
580 | } else { | |
581 | addr = (addr >> 3) & 0xfffff; | |
582 | adsr = val & 0xffffff; | |
583 | len = ((val >> 24) & 0x1f) + 1; | |
584 | if (adsr == 0xffffff) { | |
585 | memset(&s->vram[addr], s->tmpblit, len); | |
586 | if (s->depth == 24) { | |
587 | val = s->tmpblit & 0xffffff; | |
588 | val = cpu_to_be32(val); | |
589 | for (i = 0; i < len; i++) { | |
590 | s->vram24[addr + i] = val; | |
591 | } | |
592 | } | |
593 | } else { | |
594 | memcpy(&s->vram[addr], &s->vram[adsr], len); | |
595 | if (s->depth == 24) { | |
596 | memcpy(&s->vram24[addr], &s->vram24[adsr], len * 4); | |
597 | } | |
598 | } | |
97394580 | 599 | tcx_set_dirty(s, addr, len); |
55d7bfe2 MCA |
600 | } |
601 | } | |
602 | ||
603 | static void tcx_rblit_writel(void *opaque, hwaddr addr, | |
604 | uint64_t val, unsigned size) | |
605 | { | |
606 | TCXState *s = opaque; | |
607 | uint32_t adsr, len; | |
608 | int i; | |
609 | ||
610 | if (!(addr & 4)) { | |
611 | s->tmpblit = val; | |
612 | } else { | |
613 | addr = (addr >> 3) & 0xfffff; | |
614 | adsr = val & 0xffffff; | |
615 | len = ((val >> 24) & 0x1f) + 1; | |
616 | if (adsr == 0xffffff) { | |
617 | memset(&s->vram[addr], s->tmpblit, len); | |
618 | if (s->depth == 24) { | |
619 | val = s->tmpblit & 0xffffff; | |
620 | val = cpu_to_be32(val); | |
621 | for (i = 0; i < len; i++) { | |
622 | s->vram24[addr + i] = val; | |
623 | s->cplane[addr + i] = val; | |
624 | } | |
625 | } | |
626 | } else { | |
627 | memcpy(&s->vram[addr], &s->vram[adsr], len); | |
628 | if (s->depth == 24) { | |
629 | memcpy(&s->vram24[addr], &s->vram24[adsr], len * 4); | |
630 | memcpy(&s->cplane[addr], &s->cplane[adsr], len * 4); | |
631 | } | |
632 | } | |
97394580 | 633 | tcx_set_dirty(s, addr, len); |
55d7bfe2 MCA |
634 | } |
635 | } | |
636 | ||
637 | static const MemoryRegionOps tcx_blit_ops = { | |
638 | .read = tcx_blit_readl, | |
639 | .write = tcx_blit_writel, | |
640 | .endianness = DEVICE_NATIVE_ENDIAN, | |
641 | .valid = { | |
642 | .min_access_size = 4, | |
643 | .max_access_size = 4, | |
644 | }, | |
645 | }; | |
646 | ||
647 | static const MemoryRegionOps tcx_rblit_ops = { | |
648 | .read = tcx_blit_readl, | |
649 | .write = tcx_rblit_writel, | |
650 | .endianness = DEVICE_NATIVE_ENDIAN, | |
651 | .valid = { | |
652 | .min_access_size = 4, | |
653 | .max_access_size = 4, | |
654 | }, | |
655 | }; | |
656 | ||
657 | static void tcx_invalidate_cursor_position(TCXState *s) | |
658 | { | |
659 | int ymin, ymax, start, end; | |
660 | ||
661 | /* invalidate only near the cursor */ | |
662 | ymin = s->cursy; | |
663 | if (ymin >= s->height) { | |
664 | return; | |
665 | } | |
666 | ymax = MIN(s->height, ymin + 32); | |
667 | start = ymin * 1024; | |
668 | end = ymax * 1024; | |
669 | ||
97394580 | 670 | tcx_set_dirty(s, start, end - start); |
55d7bfe2 MCA |
671 | } |
672 | ||
673 | static uint64_t tcx_thc_readl(void *opaque, hwaddr addr, | |
674 | unsigned size) | |
675 | { | |
676 | TCXState *s = opaque; | |
677 | uint64_t val; | |
678 | ||
679 | if (addr == TCX_THC_MISC) { | |
680 | val = s->thcmisc | 0x02000000; | |
681 | } else { | |
682 | val = 0; | |
683 | } | |
684 | return val; | |
685 | } | |
686 | ||
687 | static void tcx_thc_writel(void *opaque, hwaddr addr, | |
688 | uint64_t val, unsigned size) | |
689 | { | |
690 | TCXState *s = opaque; | |
691 | ||
692 | if (addr == TCX_THC_CURSXY) { | |
693 | tcx_invalidate_cursor_position(s); | |
694 | s->cursx = val >> 16; | |
695 | s->cursy = val; | |
696 | tcx_invalidate_cursor_position(s); | |
697 | } else if (addr >= TCX_THC_CURSMASK && addr < TCX_THC_CURSMASK + 128) { | |
698 | s->cursmask[(addr - TCX_THC_CURSMASK) >> 2] = val; | |
699 | tcx_invalidate_cursor_position(s); | |
700 | } else if (addr >= TCX_THC_CURSBITS && addr < TCX_THC_CURSBITS + 128) { | |
701 | s->cursbits[(addr - TCX_THC_CURSBITS) >> 2] = val; | |
702 | tcx_invalidate_cursor_position(s); | |
703 | } else if (addr == TCX_THC_MISC) { | |
704 | s->thcmisc = val; | |
705 | } | |
706 | ||
707 | } | |
708 | ||
709 | static const MemoryRegionOps tcx_thc_ops = { | |
710 | .read = tcx_thc_readl, | |
711 | .write = tcx_thc_writel, | |
712 | .endianness = DEVICE_NATIVE_ENDIAN, | |
713 | .valid = { | |
714 | .min_access_size = 4, | |
715 | .max_access_size = 4, | |
716 | }, | |
717 | }; | |
718 | ||
719 | static uint64_t tcx_dummy_readl(void *opaque, hwaddr addr, | |
d08151bf | 720 | unsigned size) |
8508b89e BS |
721 | { |
722 | return 0; | |
723 | } | |
724 | ||
55d7bfe2 | 725 | static void tcx_dummy_writel(void *opaque, hwaddr addr, |
d08151bf | 726 | uint64_t val, unsigned size) |
8508b89e | 727 | { |
55d7bfe2 | 728 | return; |
8508b89e BS |
729 | } |
730 | ||
55d7bfe2 MCA |
731 | static const MemoryRegionOps tcx_dummy_ops = { |
732 | .read = tcx_dummy_readl, | |
733 | .write = tcx_dummy_writel, | |
d08151bf AK |
734 | .endianness = DEVICE_NATIVE_ENDIAN, |
735 | .valid = { | |
736 | .min_access_size = 4, | |
737 | .max_access_size = 4, | |
738 | }, | |
8508b89e BS |
739 | }; |
740 | ||
380cd056 GH |
741 | static const GraphicHwOps tcx_ops = { |
742 | .invalidate = tcx_invalidate_display, | |
743 | .gfx_update = tcx_update_display, | |
744 | }; | |
745 | ||
746 | static const GraphicHwOps tcx24_ops = { | |
747 | .invalidate = tcx24_invalidate_display, | |
748 | .gfx_update = tcx24_update_display, | |
749 | }; | |
750 | ||
01b91ac2 MCA |
751 | static void tcx_initfn(Object *obj) |
752 | { | |
753 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
754 | TCXState *s = TCX(obj); | |
755 | ||
1cfe48c1 | 756 | memory_region_init_ram_nomigrate(&s->rom, obj, "tcx.prom", FCODE_MAX_ROM_SIZE, |
f8ed85ac | 757 | &error_fatal); |
01b91ac2 MCA |
758 | memory_region_set_readonly(&s->rom, true); |
759 | sysbus_init_mmio(sbd, &s->rom); | |
760 | ||
55d7bfe2 | 761 | /* 2/STIP : Stippler */ |
b21de199 | 762 | memory_region_init_io(&s->stip, obj, &tcx_stip_ops, s, "tcx.stip", |
55d7bfe2 MCA |
763 | TCX_STIP_NREGS); |
764 | sysbus_init_mmio(sbd, &s->stip); | |
765 | ||
766 | /* 3/BLIT : Blitter */ | |
b21de199 | 767 | memory_region_init_io(&s->blit, obj, &tcx_blit_ops, s, "tcx.blit", |
55d7bfe2 MCA |
768 | TCX_BLIT_NREGS); |
769 | sysbus_init_mmio(sbd, &s->blit); | |
770 | ||
771 | /* 5/RSTIP : Raw Stippler */ | |
b21de199 | 772 | memory_region_init_io(&s->rstip, obj, &tcx_rstip_ops, s, "tcx.rstip", |
55d7bfe2 MCA |
773 | TCX_RSTIP_NREGS); |
774 | sysbus_init_mmio(sbd, &s->rstip); | |
775 | ||
776 | /* 6/RBLIT : Raw Blitter */ | |
b21de199 | 777 | memory_region_init_io(&s->rblit, obj, &tcx_rblit_ops, s, "tcx.rblit", |
55d7bfe2 MCA |
778 | TCX_RBLIT_NREGS); |
779 | sysbus_init_mmio(sbd, &s->rblit); | |
780 | ||
781 | /* 7/TEC : ??? */ | |
b21de199 TH |
782 | memory_region_init_io(&s->tec, obj, &tcx_dummy_ops, s, "tcx.tec", |
783 | TCX_TEC_NREGS); | |
55d7bfe2 MCA |
784 | sysbus_init_mmio(sbd, &s->tec); |
785 | ||
786 | /* 8/CMAP : DAC */ | |
b21de199 TH |
787 | memory_region_init_io(&s->dac, obj, &tcx_dac_ops, s, "tcx.dac", |
788 | TCX_DAC_NREGS); | |
01b91ac2 MCA |
789 | sysbus_init_mmio(sbd, &s->dac); |
790 | ||
55d7bfe2 | 791 | /* 9/THC : Cursor */ |
b21de199 | 792 | memory_region_init_io(&s->thc, obj, &tcx_thc_ops, s, "tcx.thc", |
55d7bfe2 MCA |
793 | TCX_THC_NREGS); |
794 | sysbus_init_mmio(sbd, &s->thc); | |
01b91ac2 | 795 | |
55d7bfe2 | 796 | /* 11/DHC : ??? */ |
b21de199 | 797 | memory_region_init_io(&s->dhc, obj, &tcx_dummy_ops, s, "tcx.dhc", |
55d7bfe2 MCA |
798 | TCX_DHC_NREGS); |
799 | sysbus_init_mmio(sbd, &s->dhc); | |
800 | ||
801 | /* 12/ALT : ??? */ | |
b21de199 | 802 | memory_region_init_io(&s->alt, obj, &tcx_dummy_ops, s, "tcx.alt", |
55d7bfe2 MCA |
803 | TCX_ALT_NREGS); |
804 | sysbus_init_mmio(sbd, &s->alt); | |
01b91ac2 MCA |
805 | } |
806 | ||
d4ad9dec | 807 | static void tcx_realizefn(DeviceState *dev, Error **errp) |
f40070c3 | 808 | { |
d4ad9dec | 809 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
01774ddb | 810 | TCXState *s = TCX(dev); |
d08151bf | 811 | ram_addr_t vram_offset = 0; |
da87dd7b | 812 | int size, ret; |
dc828ca1 | 813 | uint8_t *vram_base; |
da87dd7b | 814 | char *fcode_filename; |
dc828ca1 | 815 | |
1cfe48c1 | 816 | memory_region_init_ram_nomigrate(&s->vram_mem, OBJECT(s), "tcx.vram", |
f8ed85ac | 817 | s->vram_size * (1 + 4 + 4), &error_fatal); |
c5705a77 | 818 | vmstate_register_ram_global(&s->vram_mem); |
74259ae5 | 819 | memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA); |
d08151bf | 820 | vram_base = memory_region_get_ram_ptr(&s->vram_mem); |
eee0b836 | 821 | |
55d7bfe2 | 822 | /* 10/ROM : FCode ROM */ |
da87dd7b | 823 | vmstate_register_ram_global(&s->rom); |
da87dd7b MCA |
824 | fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, TCX_ROM_FILE); |
825 | if (fcode_filename) { | |
74976386 | 826 | ret = load_image_mr(fcode_filename, &s->rom); |
8684e85c | 827 | g_free(fcode_filename); |
da87dd7b | 828 | if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) { |
0765691e | 829 | warn_report("tcx: could not load prom '%s'", TCX_ROM_FILE); |
da87dd7b MCA |
830 | } |
831 | } | |
832 | ||
55d7bfe2 | 833 | /* 0/DFB8 : 8-bit plane */ |
eee0b836 | 834 | s->vram = vram_base; |
ee6847d1 | 835 | size = s->vram_size; |
3eadad55 | 836 | memory_region_init_alias(&s->vram_8bit, OBJECT(s), "tcx.vram.8bit", |
d08151bf | 837 | &s->vram_mem, vram_offset, size); |
d4ad9dec | 838 | sysbus_init_mmio(sbd, &s->vram_8bit); |
eee0b836 BS |
839 | vram_offset += size; |
840 | vram_base += size; | |
e80cfcfc | 841 | |
55d7bfe2 MCA |
842 | /* 1/DFB24 : 24bit plane */ |
843 | size = s->vram_size * 4; | |
844 | s->vram24 = (uint32_t *)vram_base; | |
845 | s->vram24_offset = vram_offset; | |
846 | memory_region_init_alias(&s->vram_24bit, OBJECT(s), "tcx.vram.24bit", | |
847 | &s->vram_mem, vram_offset, size); | |
848 | sysbus_init_mmio(sbd, &s->vram_24bit); | |
849 | vram_offset += size; | |
850 | vram_base += size; | |
851 | ||
852 | /* 4/RDFB32 : Raw Framebuffer */ | |
853 | size = s->vram_size * 4; | |
854 | s->cplane = (uint32_t *)vram_base; | |
855 | s->cplane_offset = vram_offset; | |
856 | memory_region_init_alias(&s->vram_cplane, OBJECT(s), "tcx.vram.cplane", | |
857 | &s->vram_mem, vram_offset, size); | |
858 | sysbus_init_mmio(sbd, &s->vram_cplane); | |
f40070c3 | 859 | |
55d7bfe2 MCA |
860 | /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ |
861 | if (s->depth == 8) { | |
862 | memory_region_init_io(&s->thc24, OBJECT(s), &tcx_dummy_ops, s, | |
863 | "tcx.thc24", TCX_THC_NREGS); | |
864 | sysbus_init_mmio(sbd, &s->thc24); | |
865 | } | |
866 | ||
867 | sysbus_init_irq(sbd, &s->irq); | |
f40070c3 | 868 | |
55d7bfe2 | 869 | if (s->depth == 8) { |
5643706a | 870 | s->con = graphic_console_init(DEVICE(dev), 0, &tcx_ops, s); |
55d7bfe2 MCA |
871 | } else { |
872 | s->con = graphic_console_init(DEVICE(dev), 0, &tcx24_ops, s); | |
eee0b836 | 873 | } |
55d7bfe2 | 874 | s->thcmisc = 0; |
e80cfcfc | 875 | |
c78f7137 | 876 | qemu_console_resize(s->con, s->width, s->height); |
420557e8 FB |
877 | } |
878 | ||
999e12bb | 879 | static Property tcx_properties[] = { |
c7bcc85d | 880 | DEFINE_PROP_UINT32("vram_size", TCXState, vram_size, -1), |
999e12bb AL |
881 | DEFINE_PROP_UINT16("width", TCXState, width, -1), |
882 | DEFINE_PROP_UINT16("height", TCXState, height, -1), | |
883 | DEFINE_PROP_UINT16("depth", TCXState, depth, -1), | |
884 | DEFINE_PROP_END_OF_LIST(), | |
885 | }; | |
886 | ||
887 | static void tcx_class_init(ObjectClass *klass, void *data) | |
888 | { | |
39bffca2 | 889 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 890 | |
d4ad9dec | 891 | dc->realize = tcx_realizefn; |
39bffca2 AL |
892 | dc->reset = tcx_reset; |
893 | dc->vmsd = &vmstate_tcx; | |
894 | dc->props = tcx_properties; | |
999e12bb AL |
895 | } |
896 | ||
8c43a6f0 | 897 | static const TypeInfo tcx_info = { |
01774ddb | 898 | .name = TYPE_TCX, |
39bffca2 AL |
899 | .parent = TYPE_SYS_BUS_DEVICE, |
900 | .instance_size = sizeof(TCXState), | |
01b91ac2 | 901 | .instance_init = tcx_initfn, |
39bffca2 | 902 | .class_init = tcx_class_init, |
ee6847d1 GH |
903 | }; |
904 | ||
83f7d43a | 905 | static void tcx_register_types(void) |
f40070c3 | 906 | { |
39bffca2 | 907 | type_register_static(&tcx_info); |
f40070c3 BS |
908 | } |
909 | ||
83f7d43a | 910 | type_init(tcx_register_types) |