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Commit | Line | Data |
---|---|---|
420557e8 | 1 | /* |
6f7e9aec | 2 | * QEMU TCX Frame buffer |
5fafdf24 | 3 | * |
6f7e9aec | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
5fafdf24 | 5 | * |
420557e8 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
f40070c3 | 24 | |
47df5154 | 25 | #include "qemu/osdep.h" |
a8d25326 | 26 | #include "qemu-common.h" |
2c65db5e | 27 | #include "qemu/datadir.h" |
da34e65c | 28 | #include "qapi/error.h" |
28ecbaee PB |
29 | #include "ui/console.h" |
30 | #include "ui/pixel_ops.h" | |
da87dd7b | 31 | #include "hw/loader.h" |
a27bd6c7 | 32 | #include "hw/qdev-properties.h" |
83c9f4ca | 33 | #include "hw/sysbus.h" |
d6454270 | 34 | #include "migration/vmstate.h" |
d49b6836 | 35 | #include "qemu/error-report.h" |
0b8fa32f | 36 | #include "qemu/module.h" |
db1015e9 | 37 | #include "qom/object.h" |
420557e8 | 38 | |
da87dd7b MCA |
39 | #define TCX_ROM_FILE "QEMU,tcx.bin" |
40 | #define FCODE_MAX_ROM_SIZE 0x10000 | |
41 | ||
420557e8 FB |
42 | #define MAXX 1024 |
43 | #define MAXY 768 | |
55d7bfe2 MCA |
44 | #define TCX_DAC_NREGS 16 |
45 | #define TCX_THC_NREGS 0x1000 | |
46 | #define TCX_DHC_NREGS 0x4000 | |
8508b89e | 47 | #define TCX_TEC_NREGS 0x1000 |
55d7bfe2 MCA |
48 | #define TCX_ALT_NREGS 0x8000 |
49 | #define TCX_STIP_NREGS 0x800000 | |
50 | #define TCX_BLIT_NREGS 0x800000 | |
51 | #define TCX_RSTIP_NREGS 0x800000 | |
52 | #define TCX_RBLIT_NREGS 0x800000 | |
53 | ||
54 | #define TCX_THC_MISC 0x818 | |
55 | #define TCX_THC_CURSXY 0x8fc | |
56 | #define TCX_THC_CURSMASK 0x900 | |
57 | #define TCX_THC_CURSBITS 0x980 | |
420557e8 | 58 | |
e178113f | 59 | #define TYPE_TCX "sun-tcx" |
8063396b | 60 | OBJECT_DECLARE_SIMPLE_TYPE(TCXState, TCX) |
01774ddb | 61 | |
db1015e9 | 62 | struct TCXState { |
01774ddb AF |
63 | SysBusDevice parent_obj; |
64 | ||
c78f7137 | 65 | QemuConsole *con; |
55d7bfe2 | 66 | qemu_irq irq; |
8d5f07fa | 67 | uint8_t *vram; |
eee0b836 | 68 | uint32_t *vram24, *cplane; |
da87dd7b MCA |
69 | hwaddr prom_addr; |
70 | MemoryRegion rom; | |
d08151bf AK |
71 | MemoryRegion vram_mem; |
72 | MemoryRegion vram_8bit; | |
73 | MemoryRegion vram_24bit; | |
55d7bfe2 MCA |
74 | MemoryRegion stip; |
75 | MemoryRegion blit; | |
d08151bf | 76 | MemoryRegion vram_cplane; |
55d7bfe2 MCA |
77 | MemoryRegion rstip; |
78 | MemoryRegion rblit; | |
d08151bf | 79 | MemoryRegion tec; |
55d7bfe2 MCA |
80 | MemoryRegion dac; |
81 | MemoryRegion thc; | |
82 | MemoryRegion dhc; | |
83 | MemoryRegion alt; | |
d08151bf | 84 | MemoryRegion thc24; |
55d7bfe2 | 85 | |
d08151bf | 86 | ram_addr_t vram24_offset, cplane_offset; |
55d7bfe2 | 87 | uint32_t tmpblit; |
ee6847d1 | 88 | uint32_t vram_size; |
55d7bfe2 MCA |
89 | uint32_t palette[260]; |
90 | uint8_t r[260], g[260], b[260]; | |
427a66c3 | 91 | uint16_t width, height, depth; |
6f7e9aec | 92 | uint8_t dac_index, dac_state; |
55d7bfe2 MCA |
93 | uint32_t thcmisc; |
94 | uint32_t cursmask[32]; | |
95 | uint32_t cursbits[32]; | |
96 | uint16_t cursx; | |
97 | uint16_t cursy; | |
db1015e9 | 98 | }; |
420557e8 | 99 | |
9800b3c2 | 100 | static void tcx_set_dirty(TCXState *s, ram_addr_t addr, int len) |
d3ffcafe | 101 | { |
9800b3c2 | 102 | memory_region_set_dirty(&s->vram_mem, addr, len); |
4b865c28 MCA |
103 | |
104 | if (s->depth == 24) { | |
105 | memory_region_set_dirty(&s->vram_mem, s->vram24_offset + addr * 4, | |
106 | len * 4); | |
107 | memory_region_set_dirty(&s->vram_mem, s->cplane_offset + addr * 4, | |
108 | len * 4); | |
109 | } | |
d3ffcafe BS |
110 | } |
111 | ||
2dd285b5 MCA |
112 | static int tcx_check_dirty(TCXState *s, DirtyBitmapSnapshot *snap, |
113 | ram_addr_t addr, int len) | |
d3ffcafe | 114 | { |
55d7bfe2 MCA |
115 | int ret; |
116 | ||
2dd285b5 | 117 | ret = memory_region_snapshot_get_dirty(&s->vram_mem, snap, addr, len); |
427ee02b MCA |
118 | |
119 | if (s->depth == 24) { | |
2dd285b5 MCA |
120 | ret |= memory_region_snapshot_get_dirty(&s->vram_mem, snap, |
121 | s->vram24_offset + addr * 4, len * 4); | |
122 | ret |= memory_region_snapshot_get_dirty(&s->vram_mem, snap, | |
123 | s->cplane_offset + addr * 4, len * 4); | |
427ee02b MCA |
124 | } |
125 | ||
55d7bfe2 MCA |
126 | return ret; |
127 | } | |
128 | ||
21206a10 FB |
129 | static void update_palette_entries(TCXState *s, int start, int end) |
130 | { | |
131 | int i; | |
c78f7137 GH |
132 | |
133 | for (i = start; i < end; i++) { | |
7713fff4 | 134 | s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); |
21206a10 | 135 | } |
9800b3c2 | 136 | tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem)); |
21206a10 FB |
137 | } |
138 | ||
5fafdf24 | 139 | static void tcx_draw_line32(TCXState *s1, uint8_t *d, |
f930d07e | 140 | const uint8_t *s, int width) |
420557e8 | 141 | { |
e80cfcfc FB |
142 | int x; |
143 | uint8_t val; | |
8bdc2159 | 144 | uint32_t *p = (uint32_t *)d; |
e80cfcfc | 145 | |
55d7bfe2 | 146 | for (x = 0; x < width; x++) { |
f930d07e | 147 | val = *s++; |
8bdc2159 | 148 | *p++ = s1->palette[val]; |
e80cfcfc | 149 | } |
420557e8 FB |
150 | } |
151 | ||
55d7bfe2 MCA |
152 | static void tcx_draw_cursor32(TCXState *s1, uint8_t *d, |
153 | int y, int width) | |
154 | { | |
155 | int x, len; | |
156 | uint32_t mask, bits; | |
157 | uint32_t *p = (uint32_t *)d; | |
158 | ||
159 | y = y - s1->cursy; | |
160 | mask = s1->cursmask[y]; | |
161 | bits = s1->cursbits[y]; | |
162 | len = MIN(width - s1->cursx, 32); | |
163 | p = &p[s1->cursx]; | |
164 | for (x = 0; x < len; x++) { | |
165 | if (mask & 0x80000000) { | |
166 | if (bits & 0x80000000) { | |
167 | *p = s1->palette[259]; | |
168 | } else { | |
169 | *p = s1->palette[258]; | |
170 | } | |
171 | } | |
172 | p++; | |
173 | mask <<= 1; | |
174 | bits <<= 1; | |
175 | } | |
176 | } | |
177 | ||
688ea2eb | 178 | /* |
7713fff4 PM |
179 | * XXX Could be much more optimal: |
180 | * detect if line/page/whole screen is in 24 bit mode | |
181 | */ | |
eee0b836 BS |
182 | static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, |
183 | const uint8_t *s, int width, | |
184 | const uint32_t *cplane, | |
185 | const uint32_t *s24) | |
186 | { | |
7713fff4 | 187 | int x, r, g, b; |
688ea2eb | 188 | uint8_t val, *p8; |
eee0b836 BS |
189 | uint32_t *p = (uint32_t *)d; |
190 | uint32_t dval; | |
eee0b836 | 191 | for(x = 0; x < width; x++, s++, s24++) { |
55d7bfe2 MCA |
192 | if (be32_to_cpu(*cplane) & 0x03000000) { |
193 | /* 24-bit direct, BGR order */ | |
688ea2eb BS |
194 | p8 = (uint8_t *)s24; |
195 | p8++; | |
196 | b = *p8++; | |
197 | g = *p8++; | |
f7e683b8 | 198 | r = *p8; |
7713fff4 | 199 | dval = rgb_to_pixel32(r, g, b); |
eee0b836 | 200 | } else { |
55d7bfe2 | 201 | /* 8-bit pseudocolor */ |
eee0b836 BS |
202 | val = *s; |
203 | dval = s1->palette[val]; | |
204 | } | |
205 | *p++ = dval; | |
55d7bfe2 | 206 | cplane++; |
eee0b836 BS |
207 | } |
208 | } | |
209 | ||
e80cfcfc FB |
210 | /* Fixed line length 1024 allows us to do nice tricks not possible on |
211 | VGA... */ | |
55d7bfe2 | 212 | |
95219897 | 213 | static void tcx_update_display(void *opaque) |
420557e8 | 214 | { |
e80cfcfc | 215 | TCXState *ts = opaque; |
c78f7137 | 216 | DisplaySurface *surface = qemu_console_surface(ts->con); |
2dd285b5 MCA |
217 | ram_addr_t page; |
218 | DirtyBitmapSnapshot *snap = NULL; | |
550be127 | 219 | int y, y_start, dd, ds; |
e80cfcfc | 220 | uint8_t *d, *s; |
e80cfcfc | 221 | |
7713fff4 | 222 | assert(surface_bits_per_pixel(surface) == 32); |
c78f7137 | 223 | |
d08151bf | 224 | page = 0; |
e80cfcfc | 225 | y_start = -1; |
c78f7137 | 226 | d = surface_data(surface); |
6f7e9aec | 227 | s = ts->vram; |
c78f7137 | 228 | dd = surface_stride(surface); |
e80cfcfc FB |
229 | ds = 1024; |
230 | ||
2dd285b5 MCA |
231 | snap = memory_region_snapshot_and_clear_dirty(&ts->vram_mem, 0x0, |
232 | memory_region_size(&ts->vram_mem), | |
233 | DIRTY_MEMORY_VGA); | |
234 | ||
0a97c6c4 | 235 | for (y = 0; y < ts->height; y++, page += ds) { |
2dd285b5 | 236 | if (tcx_check_dirty(ts, snap, page, ds)) { |
f930d07e | 237 | if (y_start < 0) |
e80cfcfc | 238 | y_start = y; |
55d7bfe2 | 239 | |
ee72bed0 | 240 | tcx_draw_line32(ts, d, s, ts->width); |
55d7bfe2 | 241 | if (y >= ts->cursy && y < ts->cursy + 32 && ts->cursx < ts->width) { |
ee72bed0 | 242 | tcx_draw_cursor32(ts, d, y, ts->width); |
55d7bfe2 | 243 | } |
f930d07e | 244 | } else { |
e80cfcfc FB |
245 | if (y_start >= 0) { |
246 | /* flush to display */ | |
c78f7137 | 247 | dpy_gfx_update(ts->con, 0, y_start, |
a93a4a22 | 248 | ts->width, y - y_start); |
e80cfcfc FB |
249 | y_start = -1; |
250 | } | |
f930d07e | 251 | } |
0a97c6c4 MCA |
252 | s += ds; |
253 | d += dd; | |
e80cfcfc FB |
254 | } |
255 | if (y_start >= 0) { | |
f930d07e | 256 | /* flush to display */ |
c78f7137 | 257 | dpy_gfx_update(ts->con, 0, y_start, |
a93a4a22 | 258 | ts->width, y - y_start); |
e80cfcfc | 259 | } |
2dd285b5 | 260 | g_free(snap); |
420557e8 FB |
261 | } |
262 | ||
eee0b836 BS |
263 | static void tcx24_update_display(void *opaque) |
264 | { | |
265 | TCXState *ts = opaque; | |
c78f7137 | 266 | DisplaySurface *surface = qemu_console_surface(ts->con); |
2dd285b5 MCA |
267 | ram_addr_t page; |
268 | DirtyBitmapSnapshot *snap = NULL; | |
eee0b836 BS |
269 | int y, y_start, dd, ds; |
270 | uint8_t *d, *s; | |
271 | uint32_t *cptr, *s24; | |
272 | ||
7713fff4 | 273 | assert(surface_bits_per_pixel(surface) == 32); |
c78f7137 | 274 | |
d08151bf | 275 | page = 0; |
eee0b836 | 276 | y_start = -1; |
c78f7137 | 277 | d = surface_data(surface); |
eee0b836 BS |
278 | s = ts->vram; |
279 | s24 = ts->vram24; | |
280 | cptr = ts->cplane; | |
c78f7137 | 281 | dd = surface_stride(surface); |
eee0b836 BS |
282 | ds = 1024; |
283 | ||
2dd285b5 MCA |
284 | snap = memory_region_snapshot_and_clear_dirty(&ts->vram_mem, 0x0, |
285 | memory_region_size(&ts->vram_mem), | |
286 | DIRTY_MEMORY_VGA); | |
287 | ||
d18e1012 | 288 | for (y = 0; y < ts->height; y++, page += ds) { |
2dd285b5 | 289 | if (tcx_check_dirty(ts, snap, page, ds)) { |
eee0b836 BS |
290 | if (y_start < 0) |
291 | y_start = y; | |
2dd285b5 | 292 | |
eee0b836 | 293 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
55d7bfe2 MCA |
294 | if (y >= ts->cursy && y < ts->cursy+32 && ts->cursx < ts->width) { |
295 | tcx_draw_cursor32(ts, d, y, ts->width); | |
296 | } | |
eee0b836 BS |
297 | } else { |
298 | if (y_start >= 0) { | |
299 | /* flush to display */ | |
c78f7137 | 300 | dpy_gfx_update(ts->con, 0, y_start, |
a93a4a22 | 301 | ts->width, y - y_start); |
eee0b836 BS |
302 | y_start = -1; |
303 | } | |
eee0b836 | 304 | } |
d18e1012 MCA |
305 | d += dd; |
306 | s += ds; | |
307 | cptr += ds; | |
308 | s24 += ds; | |
eee0b836 BS |
309 | } |
310 | if (y_start >= 0) { | |
311 | /* flush to display */ | |
c78f7137 | 312 | dpy_gfx_update(ts->con, 0, y_start, |
a93a4a22 | 313 | ts->width, y - y_start); |
eee0b836 | 314 | } |
2dd285b5 | 315 | g_free(snap); |
eee0b836 BS |
316 | } |
317 | ||
95219897 | 318 | static void tcx_invalidate_display(void *opaque) |
420557e8 | 319 | { |
e80cfcfc | 320 | TCXState *s = opaque; |
e80cfcfc | 321 | |
9800b3c2 | 322 | tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem)); |
c78f7137 | 323 | qemu_console_resize(s->con, s->width, s->height); |
420557e8 FB |
324 | } |
325 | ||
eee0b836 BS |
326 | static void tcx24_invalidate_display(void *opaque) |
327 | { | |
328 | TCXState *s = opaque; | |
eee0b836 | 329 | |
9800b3c2 | 330 | tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem)); |
c78f7137 | 331 | qemu_console_resize(s->con, s->width, s->height); |
eee0b836 BS |
332 | } |
333 | ||
e59fb374 | 334 | static int vmstate_tcx_post_load(void *opaque, int version_id) |
420557e8 FB |
335 | { |
336 | TCXState *s = opaque; | |
3b46e624 | 337 | |
21206a10 | 338 | update_palette_entries(s, 0, 256); |
9800b3c2 | 339 | tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem)); |
e80cfcfc | 340 | return 0; |
420557e8 FB |
341 | } |
342 | ||
c0c41a4b BS |
343 | static const VMStateDescription vmstate_tcx = { |
344 | .name ="tcx", | |
345 | .version_id = 4, | |
346 | .minimum_version_id = 4, | |
752ff2fa | 347 | .post_load = vmstate_tcx_post_load, |
35d08458 | 348 | .fields = (VMStateField[]) { |
c0c41a4b BS |
349 | VMSTATE_UINT16(height, TCXState), |
350 | VMSTATE_UINT16(width, TCXState), | |
351 | VMSTATE_UINT16(depth, TCXState), | |
352 | VMSTATE_BUFFER(r, TCXState), | |
353 | VMSTATE_BUFFER(g, TCXState), | |
354 | VMSTATE_BUFFER(b, TCXState), | |
355 | VMSTATE_UINT8(dac_index, TCXState), | |
356 | VMSTATE_UINT8(dac_state, TCXState), | |
357 | VMSTATE_END_OF_LIST() | |
358 | } | |
359 | }; | |
360 | ||
7f23f812 | 361 | static void tcx_reset(DeviceState *d) |
420557e8 | 362 | { |
01774ddb | 363 | TCXState *s = TCX(d); |
e80cfcfc FB |
364 | |
365 | /* Initialize palette */ | |
55d7bfe2 MCA |
366 | memset(s->r, 0, 260); |
367 | memset(s->g, 0, 260); | |
368 | memset(s->b, 0, 260); | |
e80cfcfc | 369 | s->r[255] = s->g[255] = s->b[255] = 255; |
55d7bfe2 MCA |
370 | s->r[256] = s->g[256] = s->b[256] = 255; |
371 | s->r[258] = s->g[258] = s->b[258] = 255; | |
372 | update_palette_entries(s, 0, 260); | |
e80cfcfc | 373 | memset(s->vram, 0, MAXX*MAXY); |
d08151bf AK |
374 | memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4), |
375 | DIRTY_MEMORY_VGA); | |
6f7e9aec FB |
376 | s->dac_index = 0; |
377 | s->dac_state = 0; | |
55d7bfe2 MCA |
378 | s->cursx = 0xf000; /* Put cursor off screen */ |
379 | s->cursy = 0xf000; | |
6f7e9aec FB |
380 | } |
381 | ||
a8170e5e | 382 | static uint64_t tcx_dac_readl(void *opaque, hwaddr addr, |
d08151bf | 383 | unsigned size) |
6f7e9aec | 384 | { |
55d7bfe2 MCA |
385 | TCXState *s = opaque; |
386 | uint32_t val = 0; | |
387 | ||
388 | switch (s->dac_state) { | |
389 | case 0: | |
390 | val = s->r[s->dac_index] << 24; | |
391 | s->dac_state++; | |
392 | break; | |
393 | case 1: | |
394 | val = s->g[s->dac_index] << 24; | |
395 | s->dac_state++; | |
396 | break; | |
397 | case 2: | |
398 | val = s->b[s->dac_index] << 24; | |
399 | s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */ | |
ada44065 | 400 | /* fall through */ |
55d7bfe2 MCA |
401 | default: |
402 | s->dac_state = 0; | |
403 | break; | |
404 | } | |
405 | ||
406 | return val; | |
6f7e9aec FB |
407 | } |
408 | ||
a8170e5e | 409 | static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val, |
d08151bf | 410 | unsigned size) |
6f7e9aec FB |
411 | { |
412 | TCXState *s = opaque; | |
55d7bfe2 | 413 | unsigned index; |
6f7e9aec | 414 | |
e64d7d59 | 415 | switch (addr) { |
55d7bfe2 | 416 | case 0: /* Address */ |
f930d07e BS |
417 | s->dac_index = val >> 24; |
418 | s->dac_state = 0; | |
419 | break; | |
55d7bfe2 MCA |
420 | case 4: /* Pixel colours */ |
421 | case 12: /* Overlay (cursor) colours */ | |
422 | if (addr & 8) { | |
423 | index = (s->dac_index & 3) + 256; | |
424 | } else { | |
425 | index = s->dac_index; | |
426 | } | |
f930d07e BS |
427 | switch (s->dac_state) { |
428 | case 0: | |
55d7bfe2 MCA |
429 | s->r[index] = val >> 24; |
430 | update_palette_entries(s, index, index + 1); | |
f930d07e BS |
431 | s->dac_state++; |
432 | break; | |
433 | case 1: | |
55d7bfe2 MCA |
434 | s->g[index] = val >> 24; |
435 | update_palette_entries(s, index, index + 1); | |
f930d07e BS |
436 | s->dac_state++; |
437 | break; | |
438 | case 2: | |
55d7bfe2 MCA |
439 | s->b[index] = val >> 24; |
440 | update_palette_entries(s, index, index + 1); | |
441 | s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */ | |
ada44065 | 442 | /* fall through */ |
f930d07e BS |
443 | default: |
444 | s->dac_state = 0; | |
445 | break; | |
446 | } | |
447 | break; | |
55d7bfe2 | 448 | default: /* Control registers */ |
f930d07e | 449 | break; |
6f7e9aec | 450 | } |
420557e8 FB |
451 | } |
452 | ||
d08151bf AK |
453 | static const MemoryRegionOps tcx_dac_ops = { |
454 | .read = tcx_dac_readl, | |
455 | .write = tcx_dac_writel, | |
456 | .endianness = DEVICE_NATIVE_ENDIAN, | |
457 | .valid = { | |
458 | .min_access_size = 4, | |
459 | .max_access_size = 4, | |
460 | }, | |
6f7e9aec FB |
461 | }; |
462 | ||
55d7bfe2 MCA |
463 | static uint64_t tcx_stip_readl(void *opaque, hwaddr addr, |
464 | unsigned size) | |
465 | { | |
466 | return 0; | |
467 | } | |
468 | ||
469 | static void tcx_stip_writel(void *opaque, hwaddr addr, | |
470 | uint64_t val, unsigned size) | |
471 | { | |
472 | TCXState *s = opaque; | |
473 | int i; | |
474 | uint32_t col; | |
475 | ||
476 | if (!(addr & 4)) { | |
477 | s->tmpblit = val; | |
478 | } else { | |
479 | addr = (addr >> 3) & 0xfffff; | |
480 | col = cpu_to_be32(s->tmpblit); | |
481 | if (s->depth == 24) { | |
482 | for (i = 0; i < 32; i++) { | |
483 | if (val & 0x80000000) { | |
484 | s->vram[addr + i] = s->tmpblit; | |
485 | s->vram24[addr + i] = col; | |
486 | } | |
487 | val <<= 1; | |
488 | } | |
489 | } else { | |
490 | for (i = 0; i < 32; i++) { | |
491 | if (val & 0x80000000) { | |
492 | s->vram[addr + i] = s->tmpblit; | |
493 | } | |
494 | val <<= 1; | |
495 | } | |
496 | } | |
97394580 | 497 | tcx_set_dirty(s, addr, 32); |
55d7bfe2 MCA |
498 | } |
499 | } | |
500 | ||
501 | static void tcx_rstip_writel(void *opaque, hwaddr addr, | |
502 | uint64_t val, unsigned size) | |
503 | { | |
504 | TCXState *s = opaque; | |
505 | int i; | |
506 | uint32_t col; | |
507 | ||
508 | if (!(addr & 4)) { | |
509 | s->tmpblit = val; | |
510 | } else { | |
511 | addr = (addr >> 3) & 0xfffff; | |
512 | col = cpu_to_be32(s->tmpblit); | |
513 | if (s->depth == 24) { | |
514 | for (i = 0; i < 32; i++) { | |
515 | if (val & 0x80000000) { | |
516 | s->vram[addr + i] = s->tmpblit; | |
517 | s->vram24[addr + i] = col; | |
518 | s->cplane[addr + i] = col; | |
519 | } | |
520 | val <<= 1; | |
521 | } | |
522 | } else { | |
523 | for (i = 0; i < 32; i++) { | |
524 | if (val & 0x80000000) { | |
525 | s->vram[addr + i] = s->tmpblit; | |
526 | } | |
527 | val <<= 1; | |
528 | } | |
529 | } | |
97394580 | 530 | tcx_set_dirty(s, addr, 32); |
55d7bfe2 MCA |
531 | } |
532 | } | |
533 | ||
534 | static const MemoryRegionOps tcx_stip_ops = { | |
535 | .read = tcx_stip_readl, | |
536 | .write = tcx_stip_writel, | |
537 | .endianness = DEVICE_NATIVE_ENDIAN, | |
ae5643ec | 538 | .impl = { |
55d7bfe2 MCA |
539 | .min_access_size = 4, |
540 | .max_access_size = 4, | |
541 | }, | |
ae5643ec PMD |
542 | .valid = { |
543 | .min_access_size = 4, | |
544 | .max_access_size = 8, | |
545 | }, | |
55d7bfe2 MCA |
546 | }; |
547 | ||
548 | static const MemoryRegionOps tcx_rstip_ops = { | |
549 | .read = tcx_stip_readl, | |
550 | .write = tcx_rstip_writel, | |
551 | .endianness = DEVICE_NATIVE_ENDIAN, | |
ae5643ec | 552 | .impl = { |
55d7bfe2 MCA |
553 | .min_access_size = 4, |
554 | .max_access_size = 4, | |
555 | }, | |
ae5643ec PMD |
556 | .valid = { |
557 | .min_access_size = 4, | |
558 | .max_access_size = 8, | |
559 | }, | |
55d7bfe2 MCA |
560 | }; |
561 | ||
562 | static uint64_t tcx_blit_readl(void *opaque, hwaddr addr, | |
563 | unsigned size) | |
564 | { | |
565 | return 0; | |
566 | } | |
567 | ||
568 | static void tcx_blit_writel(void *opaque, hwaddr addr, | |
569 | uint64_t val, unsigned size) | |
570 | { | |
571 | TCXState *s = opaque; | |
572 | uint32_t adsr, len; | |
573 | int i; | |
574 | ||
575 | if (!(addr & 4)) { | |
576 | s->tmpblit = val; | |
577 | } else { | |
578 | addr = (addr >> 3) & 0xfffff; | |
579 | adsr = val & 0xffffff; | |
580 | len = ((val >> 24) & 0x1f) + 1; | |
581 | if (adsr == 0xffffff) { | |
582 | memset(&s->vram[addr], s->tmpblit, len); | |
583 | if (s->depth == 24) { | |
584 | val = s->tmpblit & 0xffffff; | |
585 | val = cpu_to_be32(val); | |
586 | for (i = 0; i < len; i++) { | |
587 | s->vram24[addr + i] = val; | |
588 | } | |
589 | } | |
590 | } else { | |
591 | memcpy(&s->vram[addr], &s->vram[adsr], len); | |
592 | if (s->depth == 24) { | |
593 | memcpy(&s->vram24[addr], &s->vram24[adsr], len * 4); | |
594 | } | |
595 | } | |
97394580 | 596 | tcx_set_dirty(s, addr, len); |
55d7bfe2 MCA |
597 | } |
598 | } | |
599 | ||
600 | static void tcx_rblit_writel(void *opaque, hwaddr addr, | |
601 | uint64_t val, unsigned size) | |
602 | { | |
603 | TCXState *s = opaque; | |
604 | uint32_t adsr, len; | |
605 | int i; | |
606 | ||
607 | if (!(addr & 4)) { | |
608 | s->tmpblit = val; | |
609 | } else { | |
610 | addr = (addr >> 3) & 0xfffff; | |
611 | adsr = val & 0xffffff; | |
612 | len = ((val >> 24) & 0x1f) + 1; | |
613 | if (adsr == 0xffffff) { | |
614 | memset(&s->vram[addr], s->tmpblit, len); | |
615 | if (s->depth == 24) { | |
616 | val = s->tmpblit & 0xffffff; | |
617 | val = cpu_to_be32(val); | |
618 | for (i = 0; i < len; i++) { | |
619 | s->vram24[addr + i] = val; | |
620 | s->cplane[addr + i] = val; | |
621 | } | |
622 | } | |
623 | } else { | |
624 | memcpy(&s->vram[addr], &s->vram[adsr], len); | |
625 | if (s->depth == 24) { | |
626 | memcpy(&s->vram24[addr], &s->vram24[adsr], len * 4); | |
627 | memcpy(&s->cplane[addr], &s->cplane[adsr], len * 4); | |
628 | } | |
629 | } | |
97394580 | 630 | tcx_set_dirty(s, addr, len); |
55d7bfe2 MCA |
631 | } |
632 | } | |
633 | ||
634 | static const MemoryRegionOps tcx_blit_ops = { | |
635 | .read = tcx_blit_readl, | |
636 | .write = tcx_blit_writel, | |
637 | .endianness = DEVICE_NATIVE_ENDIAN, | |
48e5c7f3 | 638 | .impl = { |
55d7bfe2 MCA |
639 | .min_access_size = 4, |
640 | .max_access_size = 4, | |
641 | }, | |
48e5c7f3 MCA |
642 | .valid = { |
643 | .min_access_size = 4, | |
644 | .max_access_size = 8, | |
645 | }, | |
55d7bfe2 MCA |
646 | }; |
647 | ||
648 | static const MemoryRegionOps tcx_rblit_ops = { | |
649 | .read = tcx_blit_readl, | |
650 | .write = tcx_rblit_writel, | |
651 | .endianness = DEVICE_NATIVE_ENDIAN, | |
ae5643ec | 652 | .impl = { |
55d7bfe2 MCA |
653 | .min_access_size = 4, |
654 | .max_access_size = 4, | |
655 | }, | |
ae5643ec PMD |
656 | .valid = { |
657 | .min_access_size = 4, | |
658 | .max_access_size = 8, | |
659 | }, | |
55d7bfe2 MCA |
660 | }; |
661 | ||
662 | static void tcx_invalidate_cursor_position(TCXState *s) | |
663 | { | |
664 | int ymin, ymax, start, end; | |
665 | ||
666 | /* invalidate only near the cursor */ | |
667 | ymin = s->cursy; | |
668 | if (ymin >= s->height) { | |
669 | return; | |
670 | } | |
671 | ymax = MIN(s->height, ymin + 32); | |
672 | start = ymin * 1024; | |
673 | end = ymax * 1024; | |
674 | ||
97394580 | 675 | tcx_set_dirty(s, start, end - start); |
55d7bfe2 MCA |
676 | } |
677 | ||
678 | static uint64_t tcx_thc_readl(void *opaque, hwaddr addr, | |
679 | unsigned size) | |
680 | { | |
681 | TCXState *s = opaque; | |
682 | uint64_t val; | |
683 | ||
684 | if (addr == TCX_THC_MISC) { | |
685 | val = s->thcmisc | 0x02000000; | |
686 | } else { | |
687 | val = 0; | |
688 | } | |
689 | return val; | |
690 | } | |
691 | ||
692 | static void tcx_thc_writel(void *opaque, hwaddr addr, | |
693 | uint64_t val, unsigned size) | |
694 | { | |
695 | TCXState *s = opaque; | |
696 | ||
697 | if (addr == TCX_THC_CURSXY) { | |
698 | tcx_invalidate_cursor_position(s); | |
699 | s->cursx = val >> 16; | |
700 | s->cursy = val; | |
701 | tcx_invalidate_cursor_position(s); | |
702 | } else if (addr >= TCX_THC_CURSMASK && addr < TCX_THC_CURSMASK + 128) { | |
703 | s->cursmask[(addr - TCX_THC_CURSMASK) >> 2] = val; | |
704 | tcx_invalidate_cursor_position(s); | |
705 | } else if (addr >= TCX_THC_CURSBITS && addr < TCX_THC_CURSBITS + 128) { | |
706 | s->cursbits[(addr - TCX_THC_CURSBITS) >> 2] = val; | |
707 | tcx_invalidate_cursor_position(s); | |
708 | } else if (addr == TCX_THC_MISC) { | |
709 | s->thcmisc = val; | |
710 | } | |
711 | ||
712 | } | |
713 | ||
714 | static const MemoryRegionOps tcx_thc_ops = { | |
715 | .read = tcx_thc_readl, | |
716 | .write = tcx_thc_writel, | |
717 | .endianness = DEVICE_NATIVE_ENDIAN, | |
718 | .valid = { | |
719 | .min_access_size = 4, | |
720 | .max_access_size = 4, | |
721 | }, | |
722 | }; | |
723 | ||
724 | static uint64_t tcx_dummy_readl(void *opaque, hwaddr addr, | |
d08151bf | 725 | unsigned size) |
8508b89e BS |
726 | { |
727 | return 0; | |
728 | } | |
729 | ||
55d7bfe2 | 730 | static void tcx_dummy_writel(void *opaque, hwaddr addr, |
d08151bf | 731 | uint64_t val, unsigned size) |
8508b89e | 732 | { |
55d7bfe2 | 733 | return; |
8508b89e BS |
734 | } |
735 | ||
55d7bfe2 MCA |
736 | static const MemoryRegionOps tcx_dummy_ops = { |
737 | .read = tcx_dummy_readl, | |
738 | .write = tcx_dummy_writel, | |
d08151bf AK |
739 | .endianness = DEVICE_NATIVE_ENDIAN, |
740 | .valid = { | |
741 | .min_access_size = 4, | |
742 | .max_access_size = 4, | |
743 | }, | |
8508b89e BS |
744 | }; |
745 | ||
380cd056 GH |
746 | static const GraphicHwOps tcx_ops = { |
747 | .invalidate = tcx_invalidate_display, | |
748 | .gfx_update = tcx_update_display, | |
749 | }; | |
750 | ||
751 | static const GraphicHwOps tcx24_ops = { | |
752 | .invalidate = tcx24_invalidate_display, | |
753 | .gfx_update = tcx24_update_display, | |
754 | }; | |
755 | ||
01b91ac2 MCA |
756 | static void tcx_initfn(Object *obj) |
757 | { | |
758 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
759 | TCXState *s = TCX(obj); | |
760 | ||
52013bce PMD |
761 | memory_region_init_rom_nomigrate(&s->rom, obj, "tcx.prom", |
762 | FCODE_MAX_ROM_SIZE, &error_fatal); | |
01b91ac2 MCA |
763 | sysbus_init_mmio(sbd, &s->rom); |
764 | ||
55d7bfe2 | 765 | /* 2/STIP : Stippler */ |
b21de199 | 766 | memory_region_init_io(&s->stip, obj, &tcx_stip_ops, s, "tcx.stip", |
55d7bfe2 MCA |
767 | TCX_STIP_NREGS); |
768 | sysbus_init_mmio(sbd, &s->stip); | |
769 | ||
770 | /* 3/BLIT : Blitter */ | |
b21de199 | 771 | memory_region_init_io(&s->blit, obj, &tcx_blit_ops, s, "tcx.blit", |
55d7bfe2 MCA |
772 | TCX_BLIT_NREGS); |
773 | sysbus_init_mmio(sbd, &s->blit); | |
774 | ||
775 | /* 5/RSTIP : Raw Stippler */ | |
b21de199 | 776 | memory_region_init_io(&s->rstip, obj, &tcx_rstip_ops, s, "tcx.rstip", |
55d7bfe2 MCA |
777 | TCX_RSTIP_NREGS); |
778 | sysbus_init_mmio(sbd, &s->rstip); | |
779 | ||
780 | /* 6/RBLIT : Raw Blitter */ | |
b21de199 | 781 | memory_region_init_io(&s->rblit, obj, &tcx_rblit_ops, s, "tcx.rblit", |
55d7bfe2 MCA |
782 | TCX_RBLIT_NREGS); |
783 | sysbus_init_mmio(sbd, &s->rblit); | |
784 | ||
785 | /* 7/TEC : ??? */ | |
b21de199 TH |
786 | memory_region_init_io(&s->tec, obj, &tcx_dummy_ops, s, "tcx.tec", |
787 | TCX_TEC_NREGS); | |
55d7bfe2 MCA |
788 | sysbus_init_mmio(sbd, &s->tec); |
789 | ||
790 | /* 8/CMAP : DAC */ | |
b21de199 TH |
791 | memory_region_init_io(&s->dac, obj, &tcx_dac_ops, s, "tcx.dac", |
792 | TCX_DAC_NREGS); | |
01b91ac2 MCA |
793 | sysbus_init_mmio(sbd, &s->dac); |
794 | ||
55d7bfe2 | 795 | /* 9/THC : Cursor */ |
b21de199 | 796 | memory_region_init_io(&s->thc, obj, &tcx_thc_ops, s, "tcx.thc", |
55d7bfe2 MCA |
797 | TCX_THC_NREGS); |
798 | sysbus_init_mmio(sbd, &s->thc); | |
01b91ac2 | 799 | |
55d7bfe2 | 800 | /* 11/DHC : ??? */ |
b21de199 | 801 | memory_region_init_io(&s->dhc, obj, &tcx_dummy_ops, s, "tcx.dhc", |
55d7bfe2 MCA |
802 | TCX_DHC_NREGS); |
803 | sysbus_init_mmio(sbd, &s->dhc); | |
804 | ||
805 | /* 12/ALT : ??? */ | |
b21de199 | 806 | memory_region_init_io(&s->alt, obj, &tcx_dummy_ops, s, "tcx.alt", |
55d7bfe2 MCA |
807 | TCX_ALT_NREGS); |
808 | sysbus_init_mmio(sbd, &s->alt); | |
01b91ac2 MCA |
809 | } |
810 | ||
d4ad9dec | 811 | static void tcx_realizefn(DeviceState *dev, Error **errp) |
f40070c3 | 812 | { |
d4ad9dec | 813 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
01774ddb | 814 | TCXState *s = TCX(dev); |
d08151bf | 815 | ram_addr_t vram_offset = 0; |
da87dd7b | 816 | int size, ret; |
dc828ca1 | 817 | uint8_t *vram_base; |
da87dd7b | 818 | char *fcode_filename; |
dc828ca1 | 819 | |
1cfe48c1 | 820 | memory_region_init_ram_nomigrate(&s->vram_mem, OBJECT(s), "tcx.vram", |
f8ed85ac | 821 | s->vram_size * (1 + 4 + 4), &error_fatal); |
c5705a77 | 822 | vmstate_register_ram_global(&s->vram_mem); |
74259ae5 | 823 | memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA); |
d08151bf | 824 | vram_base = memory_region_get_ram_ptr(&s->vram_mem); |
eee0b836 | 825 | |
55d7bfe2 | 826 | /* 10/ROM : FCode ROM */ |
da87dd7b | 827 | vmstate_register_ram_global(&s->rom); |
da87dd7b MCA |
828 | fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, TCX_ROM_FILE); |
829 | if (fcode_filename) { | |
74976386 | 830 | ret = load_image_mr(fcode_filename, &s->rom); |
8684e85c | 831 | g_free(fcode_filename); |
da87dd7b | 832 | if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) { |
0765691e | 833 | warn_report("tcx: could not load prom '%s'", TCX_ROM_FILE); |
da87dd7b MCA |
834 | } |
835 | } | |
836 | ||
55d7bfe2 | 837 | /* 0/DFB8 : 8-bit plane */ |
eee0b836 | 838 | s->vram = vram_base; |
ee6847d1 | 839 | size = s->vram_size; |
3eadad55 | 840 | memory_region_init_alias(&s->vram_8bit, OBJECT(s), "tcx.vram.8bit", |
d08151bf | 841 | &s->vram_mem, vram_offset, size); |
d4ad9dec | 842 | sysbus_init_mmio(sbd, &s->vram_8bit); |
eee0b836 BS |
843 | vram_offset += size; |
844 | vram_base += size; | |
e80cfcfc | 845 | |
55d7bfe2 MCA |
846 | /* 1/DFB24 : 24bit plane */ |
847 | size = s->vram_size * 4; | |
848 | s->vram24 = (uint32_t *)vram_base; | |
849 | s->vram24_offset = vram_offset; | |
850 | memory_region_init_alias(&s->vram_24bit, OBJECT(s), "tcx.vram.24bit", | |
851 | &s->vram_mem, vram_offset, size); | |
852 | sysbus_init_mmio(sbd, &s->vram_24bit); | |
853 | vram_offset += size; | |
854 | vram_base += size; | |
855 | ||
856 | /* 4/RDFB32 : Raw Framebuffer */ | |
857 | size = s->vram_size * 4; | |
858 | s->cplane = (uint32_t *)vram_base; | |
859 | s->cplane_offset = vram_offset; | |
860 | memory_region_init_alias(&s->vram_cplane, OBJECT(s), "tcx.vram.cplane", | |
861 | &s->vram_mem, vram_offset, size); | |
862 | sysbus_init_mmio(sbd, &s->vram_cplane); | |
f40070c3 | 863 | |
55d7bfe2 MCA |
864 | /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ |
865 | if (s->depth == 8) { | |
866 | memory_region_init_io(&s->thc24, OBJECT(s), &tcx_dummy_ops, s, | |
867 | "tcx.thc24", TCX_THC_NREGS); | |
868 | sysbus_init_mmio(sbd, &s->thc24); | |
869 | } | |
870 | ||
871 | sysbus_init_irq(sbd, &s->irq); | |
f40070c3 | 872 | |
55d7bfe2 | 873 | if (s->depth == 8) { |
8e5c952b | 874 | s->con = graphic_console_init(dev, 0, &tcx_ops, s); |
55d7bfe2 | 875 | } else { |
8e5c952b | 876 | s->con = graphic_console_init(dev, 0, &tcx24_ops, s); |
eee0b836 | 877 | } |
55d7bfe2 | 878 | s->thcmisc = 0; |
e80cfcfc | 879 | |
c78f7137 | 880 | qemu_console_resize(s->con, s->width, s->height); |
420557e8 FB |
881 | } |
882 | ||
999e12bb | 883 | static Property tcx_properties[] = { |
c7bcc85d | 884 | DEFINE_PROP_UINT32("vram_size", TCXState, vram_size, -1), |
999e12bb AL |
885 | DEFINE_PROP_UINT16("width", TCXState, width, -1), |
886 | DEFINE_PROP_UINT16("height", TCXState, height, -1), | |
887 | DEFINE_PROP_UINT16("depth", TCXState, depth, -1), | |
888 | DEFINE_PROP_END_OF_LIST(), | |
889 | }; | |
890 | ||
891 | static void tcx_class_init(ObjectClass *klass, void *data) | |
892 | { | |
39bffca2 | 893 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 894 | |
d4ad9dec | 895 | dc->realize = tcx_realizefn; |
39bffca2 AL |
896 | dc->reset = tcx_reset; |
897 | dc->vmsd = &vmstate_tcx; | |
4f67d30b | 898 | device_class_set_props(dc, tcx_properties); |
999e12bb AL |
899 | } |
900 | ||
8c43a6f0 | 901 | static const TypeInfo tcx_info = { |
01774ddb | 902 | .name = TYPE_TCX, |
39bffca2 AL |
903 | .parent = TYPE_SYS_BUS_DEVICE, |
904 | .instance_size = sizeof(TCXState), | |
01b91ac2 | 905 | .instance_init = tcx_initfn, |
39bffca2 | 906 | .class_init = tcx_class_init, |
ee6847d1 GH |
907 | }; |
908 | ||
83f7d43a | 909 | static void tcx_register_types(void) |
f40070c3 | 910 | { |
39bffca2 | 911 | type_register_static(&tcx_info); |
f40070c3 BS |
912 | } |
913 | ||
83f7d43a | 914 | type_init(tcx_register_types) |