[mirror_qemu.git] / hw / display / vga-pci.c

/*
 * QEMU PCI VGA Emulator.
 *
 * see docs/specs/standard-vga.txt for virtual hardware specs.
 *
 * Copyright (c) 2003 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/pci/pci.h"
#include "vga_int.h"
#include "ui/pixel_ops.h"
#include "qemu/timer.h"
#include "hw/loader.h"
#include "hw/display/edid.h"

enum vga_pci_flags {
    PCI_VGA_FLAG_ENABLE_MMIO = 1,
    PCI_VGA_FLAG_ENABLE_QEXT = 2,
    PCI_VGA_FLAG_ENABLE_EDID = 3,
};

typedef struct PCIVGAState {
    PCIDevice dev;
    VGACommonState vga;
    uint32_t flags;
    qemu_edid_info edid_info;
    MemoryRegion mmio;
    MemoryRegion mrs[4];
    uint8_t edid[256];
} PCIVGAState;

#define TYPE_PCI_VGA "pci-vga"
#define PCI_VGA(obj) OBJECT_CHECK(PCIVGAState, (obj), TYPE_PCI_VGA)

static const VMStateDescription vmstate_vga_pci = {
    .name = "vga",
    .version_id = 2,
    .minimum_version_id = 2,
    .fields = (VMStateField[]) {
        VMSTATE_PCI_DEVICE(dev, PCIVGAState),
        VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState),
        VMSTATE_END_OF_LIST()
    }
};

static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr,
                                    unsigned size)
{
    VGACommonState *s = ptr;
    uint64_t ret = 0;

    switch (size) {
    case 1:
        ret = vga_ioport_read(s, addr + 0x3c0);
        break;
    case 2:
        ret  = vga_ioport_read(s, addr + 0x3c0);
        ret |= vga_ioport_read(s, addr + 0x3c1) << 8;
        break;
    }
    return ret;
}

static void pci_vga_ioport_write(void *ptr, hwaddr addr,
                                 uint64_t val, unsigned size)
{
    VGACommonState *s = ptr;

    switch (size) {
    case 1:
        vga_ioport_write(s, addr + 0x3c0, val);
        break;
    case 2:
        /*
         * Update bytes in little endian order.  Allows to update
         * indexed registers with a single word write because the
         * index byte is updated first.
         */
        vga_ioport_write(s, addr + 0x3c0, val & 0xff);
        vga_ioport_write(s, addr + 0x3c1, (val >> 8) & 0xff);
        break;
    }
}

static const MemoryRegionOps pci_vga_ioport_ops = {
    .read = pci_vga_ioport_read,
    .write = pci_vga_ioport_write,
    .valid.min_access_size = 1,
    .valid.max_access_size = 4,
    .impl.min_access_size = 1,
    .impl.max_access_size = 2,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr,
                                   unsigned size)
{
    VGACommonState *s = ptr;
    int index = addr >> 1;

    vbe_ioport_write_index(s, 0, index);
    return vbe_ioport_read_data(s, 0);
}

static void pci_vga_bochs_write(void *ptr, hwaddr addr,
                                uint64_t val, unsigned size)
{
    VGACommonState *s = ptr;
    int index = addr >> 1;

    vbe_ioport_write_index(s, 0, index);
    vbe_ioport_write_data(s, 0, val);
}

static const MemoryRegionOps pci_vga_bochs_ops = {
    .read = pci_vga_bochs_read,
    .write = pci_vga_bochs_write,
    .valid.min_access_size = 1,
    .valid.max_access_size = 4,
    .impl.min_access_size = 2,
    .impl.max_access_size = 2,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size)
{
    VGACommonState *s = ptr;

    switch (addr) {
    case PCI_VGA_QEXT_REG_SIZE:
        return PCI_VGA_QEXT_SIZE;
    case PCI_VGA_QEXT_REG_BYTEORDER:
        return s->big_endian_fb ?
            PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN;
    default:
        return 0;
    }
}

static void pci_vga_qext_write(void *ptr, hwaddr addr,
                               uint64_t val, unsigned size)
{
    VGACommonState *s = ptr;

    switch (addr) {
    case PCI_VGA_QEXT_REG_BYTEORDER:
        if (val == PCI_VGA_QEXT_BIG_ENDIAN) {
            s->big_endian_fb = true;
        }
        if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) {
            s->big_endian_fb = false;
        }
        break;
    }
}

static bool vga_get_big_endian_fb(Object *obj, Error **errp)
{
    PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));

    return d->vga.big_endian_fb;
}

static void vga_set_big_endian_fb(Object *obj, bool value, Error **errp)
{
    PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));

    d->vga.big_endian_fb = value;
}

static const MemoryRegionOps pci_vga_qext_ops = {
    .read = pci_vga_qext_read,
    .write = pci_vga_qext_write,
    .valid.min_access_size = 4,
    .valid.max_access_size = 4,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

void pci_std_vga_mmio_region_init(VGACommonState *s,
                                  Object *owner,
                                  MemoryRegion *parent,
                                  MemoryRegion *subs,
                                  bool qext, bool edid)
{
    PCIVGAState *d = container_of(s, PCIVGAState, vga);

    memory_region_init_io(&subs[0], owner, &pci_vga_ioport_ops, s,
                          "vga ioports remapped", PCI_VGA_IOPORT_SIZE);
    memory_region_add_subregion(parent, PCI_VGA_IOPORT_OFFSET,
                                &subs[0]);

    memory_region_init_io(&subs[1], owner, &pci_vga_bochs_ops, s,
                          "bochs dispi interface", PCI_VGA_BOCHS_SIZE);
    memory_region_add_subregion(parent, PCI_VGA_BOCHS_OFFSET,
                                &subs[1]);

    if (qext) {
        memory_region_init_io(&subs[2], owner, &pci_vga_qext_ops, s,
                              "qemu extended regs", PCI_VGA_QEXT_SIZE);
        memory_region_add_subregion(parent, PCI_VGA_QEXT_OFFSET,
                                    &subs[2]);
    }

    if (edid) {
        qemu_edid_generate(d->edid, sizeof(d->edid), &d->edid_info);
        qemu_edid_region_io(&subs[3], owner, d->edid, sizeof(d->edid));
        memory_region_add_subregion(parent, 0, &subs[3]);
    }
}

static void pci_std_vga_realize(PCIDevice *dev, Error **errp)
{
    PCIVGAState *d = PCI_VGA(dev);
    VGACommonState *s = &d->vga;
    bool qext = false;
    bool edid = false;

    /* vga + console init */
    vga_common_init(s, OBJECT(dev));
    vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev),
             true);

    s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);

    /* XXX: VGA_RAM_SIZE must be a power of two */
    pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);

    /* mmio bar for vga register access */
    if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) {
        memory_region_init(&d->mmio, NULL, "vga.mmio",
                           PCI_VGA_MMIO_SIZE);

        if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
            qext = true;
            pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
        }
        if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) {
            edid = true;
        }
        pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs,
                                     qext, edid);

        pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
    }

    if (!dev->rom_bar) {
        /* compatibility with pc-0.13 and older */
        vga_init_vbe(s, OBJECT(dev), pci_address_space(dev));
    }
}

static void pci_std_vga_init(Object *obj)
{
    /* Expose framebuffer byteorder via QOM */
    object_property_add_bool(obj, "big-endian-framebuffer",
                             vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
}

static void pci_secondary_vga_realize(PCIDevice *dev, Error **errp)
{
    PCIVGAState *d = PCI_VGA(dev);
    VGACommonState *s = &d->vga;
    bool qext = false;
    bool edid = false;

    /* vga + console init */
    vga_common_init(s, OBJECT(dev));
    s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);

    /* mmio bar */
    memory_region_init(&d->mmio, OBJECT(dev), "vga.mmio",
                       PCI_VGA_MMIO_SIZE);

    if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
        qext = true;
        pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
    }
    if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) {
        edid = true;
    }
    pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs, qext, edid);

    pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
    pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
}

static void pci_secondary_vga_exit(PCIDevice *dev)
{
    PCIVGAState *d = PCI_VGA(dev);
    VGACommonState *s = &d->vga;

    graphic_console_close(s->con);
    memory_region_del_subregion(&d->mmio, &d->mrs[0]);
    memory_region_del_subregion(&d->mmio, &d->mrs[1]);
    if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
        memory_region_del_subregion(&d->mmio, &d->mrs[2]);
    }
    if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) {
        memory_region_del_subregion(&d->mmio, &d->mrs[3]);
    }
}

static void pci_secondary_vga_init(Object *obj)
{
    /* Expose framebuffer byteorder via QOM */
    object_property_add_bool(obj, "big-endian-framebuffer",
                             vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
}

static void pci_secondary_vga_reset(DeviceState *dev)
{
    PCIVGAState *d = PCI_VGA(PCI_DEVICE(dev));
    vga_common_reset(&d->vga);
}

static Property vga_pci_properties[] = {
    DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
    DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true),
    DEFINE_PROP_BIT("qemu-extended-regs",
                    PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
    DEFINE_PROP_BIT("edid",
                    PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, false),
    DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info),
    DEFINE_PROP_BOOL("global-vmstate", PCIVGAState, vga.global_vmstate, false),
    DEFINE_PROP_END_OF_LIST(),
};

static Property secondary_pci_properties[] = {
    DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
    DEFINE_PROP_BIT("qemu-extended-regs",
                    PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
    DEFINE_PROP_BIT("edid",
                    PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, false),
    DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info),
    DEFINE_PROP_END_OF_LIST(),
};

static void vga_pci_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->vendor_id = PCI_VENDOR_ID_QEMU;
    k->device_id = PCI_DEVICE_ID_QEMU_VGA;
    dc->vmsd = &vmstate_vga_pci;
    set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
}

static const TypeInfo vga_pci_type_info = {
    .name = TYPE_PCI_VGA,
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIVGAState),
    .abstract = true,
    .class_init = vga_pci_class_init,
    .interfaces = (InterfaceInfo[]) {
        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
        { },
    },
};

static void vga_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->realize = pci_std_vga_realize;
    k->romfile = "vgabios-stdvga.bin";
    k->class_id = PCI_CLASS_DISPLAY_VGA;
    dc->props = vga_pci_properties;
    dc->hotpluggable = false;
}

static void secondary_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->realize = pci_secondary_vga_realize;
    k->exit = pci_secondary_vga_exit;
    k->class_id = PCI_CLASS_DISPLAY_OTHER;
    dc->props = secondary_pci_properties;
    dc->reset = pci_secondary_vga_reset;
}

static const TypeInfo vga_info = {
    .name          = "VGA",
    .parent        = TYPE_PCI_VGA,
    .instance_init = pci_std_vga_init,
    .class_init    = vga_class_init,
};

static const TypeInfo secondary_info = {
    .name          = "secondary-vga",
    .parent        = TYPE_PCI_VGA,
    .instance_init = pci_secondary_vga_init,
    .class_init    = secondary_class_init,
};

static void vga_register_types(void)
{
    type_register_static(&vga_pci_type_info);
    type_register_static(&vga_info);
    type_register_static(&secondary_info);
}

type_init(vga_register_types)
Commit	Line	Data
47d37dd9 JQ	1	/*
	2	* QEMU PCI VGA Emulator.
	3	*
cc228248 GH	4	* see docs/specs/standard-vga.txt for virtual hardware specs.
cc228248 GH	5	*
47d37dd9 JQ	6	* Copyright (c) 2003 Fabrice Bellard
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*/
47df5154	26	#include "qemu/osdep.h"
83c9f4ca	27	#include "hw/hw.h"
83c9f4ca	28	#include "hw/pci/pci.h"
47b43a1f	29	#include "vga_int.h"
28ecbaee	30	#include "ui/pixel_ops.h"
1de7afc9	31	#include "qemu/timer.h"
83c9f4ca	32	#include "hw/loader.h"
d46b40fc	33	#include "hw/display/edid.h"
47d37dd9	34
803ff052 GH	35	enum vga_pci_flags {
803ff052 GH	36	PCI_VGA_FLAG_ENABLE_MMIO = 1,
b5682aa4	37	PCI_VGA_FLAG_ENABLE_QEXT = 2,
d46b40fc	38	PCI_VGA_FLAG_ENABLE_EDID = 3,
803ff052 GH	39	};
803ff052 GH	40
47d37dd9 JQ	41	typedef struct PCIVGAState {
	42	PCIDevice dev;
	43	VGACommonState vga;
803ff052	44	uint32_t flags;
d46b40fc	45	qemu_edid_info edid_info;
803ff052	46	MemoryRegion mmio;
d46b40fc GH	47	MemoryRegion mrs[4];
d46b40fc GH	48	uint8_t edid[256];
47d37dd9 JQ	49	} PCIVGAState;
47d37dd9 JQ	50
176c324f GA	51	#define TYPE_PCI_VGA "pci-vga"
	52	#define PCI_VGA(obj) OBJECT_CHECK(PCIVGAState, (obj), TYPE_PCI_VGA)
	53
a4f9631c JQ	54	static const VMStateDescription vmstate_vga_pci = {
	55	.name = "vga",
	56	.version_id = 2,
	57	.minimum_version_id = 2,
d49805ae	58	.fields = (VMStateField[]) {
a4f9631c JQ	59	VMSTATE_PCI_DEVICE(dev, PCIVGAState),
	60	VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState),
	61	VMSTATE_END_OF_LIST()
47d37dd9	62	}
a4f9631c	63	};
47d37dd9	64
a8170e5e	65	static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr,
803ff052 GH	66	unsigned size)
803ff052 GH	67	{
cf45ec6a	68	VGACommonState *s = ptr;
803ff052 GH	69	uint64_t ret = 0;
	70
	71	switch (size) {
	72	case 1:
cf45ec6a	73	ret = vga_ioport_read(s, addr + 0x3c0);
803ff052 GH	74	break;
803ff052 GH	75	case 2:
cf45ec6a GH	76	ret = vga_ioport_read(s, addr + 0x3c0);
cf45ec6a GH	77	ret \|= vga_ioport_read(s, addr + 0x3c1) << 8;
803ff052 GH	78	break;
	79	}
	80	return ret;
	81	}
	82
a8170e5e	83	static void pci_vga_ioport_write(void *ptr, hwaddr addr,
803ff052 GH	84	uint64_t val, unsigned size)
803ff052 GH	85	{
cf45ec6a	86	VGACommonState *s = ptr;
c96c53b5	87
803ff052 GH	88	switch (size) {
803ff052 GH	89	case 1:
cf45ec6a	90	vga_ioport_write(s, addr + 0x3c0, val);
803ff052 GH	91	break;
	92	case 2:
	93	/*
	94	* Update bytes in little endian order. Allows to update
	95	* indexed registers with a single word write because the
	96	* index byte is updated first.
	97	*/
cf45ec6a GH	98	vga_ioport_write(s, addr + 0x3c0, val & 0xff);
cf45ec6a GH	99	vga_ioport_write(s, addr + 0x3c1, (val >> 8) & 0xff);
803ff052 GH	100	break;
	101	}
	102	}
	103
	104	static const MemoryRegionOps pci_vga_ioport_ops = {
	105	.read = pci_vga_ioport_read,
	106	.write = pci_vga_ioport_write,
	107	.valid.min_access_size = 1,
	108	.valid.max_access_size = 4,
	109	.impl.min_access_size = 1,
	110	.impl.max_access_size = 2,
	111	.endianness = DEVICE_LITTLE_ENDIAN,
	112	};
	113
a8170e5e	114	static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr,
803ff052 GH	115	unsigned size)
803ff052 GH	116	{
cf45ec6a	117	VGACommonState *s = ptr;
803ff052 GH	118	int index = addr >> 1;
803ff052 GH	119
cf45ec6a GH	120	vbe_ioport_write_index(s, 0, index);
cf45ec6a GH	121	return vbe_ioport_read_data(s, 0);
803ff052 GH	122	}
803ff052 GH	123
a8170e5e	124	static void pci_vga_bochs_write(void *ptr, hwaddr addr,
803ff052 GH	125	uint64_t val, unsigned size)
803ff052 GH	126	{
cf45ec6a	127	VGACommonState *s = ptr;
803ff052 GH	128	int index = addr >> 1;
803ff052 GH	129
cf45ec6a GH	130	vbe_ioport_write_index(s, 0, index);
cf45ec6a GH	131	vbe_ioport_write_data(s, 0, val);
803ff052 GH	132	}
	133
	134	static const MemoryRegionOps pci_vga_bochs_ops = {
	135	.read = pci_vga_bochs_read,
	136	.write = pci_vga_bochs_write,
	137	.valid.min_access_size = 1,
	138	.valid.max_access_size = 4,
	139	.impl.min_access_size = 2,
	140	.impl.max_access_size = 2,
	141	.endianness = DEVICE_LITTLE_ENDIAN,
	142	};
	143
b5682aa4 GH	144	static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size)
b5682aa4 GH	145	{
cf45ec6a	146	VGACommonState *s = ptr;
b5682aa4 GH	147
	148	switch (addr) {
	149	case PCI_VGA_QEXT_REG_SIZE:
	150	return PCI_VGA_QEXT_SIZE;
	151	case PCI_VGA_QEXT_REG_BYTEORDER:
cf45ec6a	152	return s->big_endian_fb ?
b5682aa4 GH	153	PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN;
	154	default:
	155	return 0;
	156	}
	157	}
	158
	159	static void pci_vga_qext_write(void *ptr, hwaddr addr,
	160	uint64_t val, unsigned size)
	161	{
cf45ec6a	162	VGACommonState *s = ptr;
b5682aa4 GH	163
	164	switch (addr) {
	165	case PCI_VGA_QEXT_REG_BYTEORDER:
	166	if (val == PCI_VGA_QEXT_BIG_ENDIAN) {
cf45ec6a	167	s->big_endian_fb = true;
b5682aa4 GH	168	}
b5682aa4 GH	169	if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) {
cf45ec6a	170	s->big_endian_fb = false;
b5682aa4 GH	171	}
	172	break;
	173	}
	174	}
	175
3c2784fc DG	176	static bool vga_get_big_endian_fb(Object obj, Error *errp)
3c2784fc DG	177	{
176c324f	178	PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
3c2784fc DG	179
	180	return d->vga.big_endian_fb;
	181	}
	182
	183	static void vga_set_big_endian_fb(Object obj, bool value, Error *errp)
	184	{
176c324f	185	PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
3c2784fc DG	186
	187	d->vga.big_endian_fb = value;
	188	}
	189
b5682aa4 GH	190	static const MemoryRegionOps pci_vga_qext_ops = {
	191	.read = pci_vga_qext_read,
	192	.write = pci_vga_qext_write,
	193	.valid.min_access_size = 4,
	194	.valid.max_access_size = 4,
	195	.endianness = DEVICE_LITTLE_ENDIAN,
	196	};
	197
c5d4dac8	198	void pci_std_vga_mmio_region_init(VGACommonState *s,
93abfc88	199	Object *owner,
c5d4dac8 GH	200	MemoryRegion *parent,
c5d4dac8 GH	201	MemoryRegion *subs,
d46b40fc	202	bool qext, bool edid)
220869e1	203	{
d46b40fc GH	204	PCIVGAState *d = container_of(s, PCIVGAState, vga);
d46b40fc GH	205
93abfc88	206	memory_region_init_io(&subs[0], owner, &pci_vga_ioport_ops, s,
220869e1 GH	207	"vga ioports remapped", PCI_VGA_IOPORT_SIZE);
	208	memory_region_add_subregion(parent, PCI_VGA_IOPORT_OFFSET,
	209	&subs[0]);
	210
93abfc88	211	memory_region_init_io(&subs[1], owner, &pci_vga_bochs_ops, s,
220869e1 GH	212	"bochs dispi interface", PCI_VGA_BOCHS_SIZE);
	213	memory_region_add_subregion(parent, PCI_VGA_BOCHS_OFFSET,
	214	&subs[1]);
	215
	216	if (qext) {
93abfc88	217	memory_region_init_io(&subs[2], owner, &pci_vga_qext_ops, s,
220869e1 GH	218	"qemu extended regs", PCI_VGA_QEXT_SIZE);
	219	memory_region_add_subregion(parent, PCI_VGA_QEXT_OFFSET,
	220	&subs[2]);
	221	}
d46b40fc GH	222
	223	if (edid) {
	224	qemu_edid_generate(d->edid, sizeof(d->edid), &d->edid_info);
	225	qemu_edid_region_io(&subs[3], owner, d->edid, sizeof(d->edid));
	226	memory_region_add_subregion(parent, 0, &subs[3]);
	227	}
220869e1 GH	228	}
220869e1 GH	229
9af21dbe	230	static void pci_std_vga_realize(PCIDevice dev, Error *errp)
47d37dd9	231	{
176c324f	232	PCIVGAState *d = PCI_VGA(dev);
0d0302e2	233	VGACommonState *s = &d->vga;
220869e1	234	bool qext = false;
d46b40fc	235	bool edid = false;
47d37dd9	236
0d0302e2	237	/* vga + console init */
1fcfdc43	238	vga_common_init(s, OBJECT(dev));
712f0cc7 PB	239	vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev),
712f0cc7 PB	240	true);
47d37dd9	241
5643706a	242	s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
47d37dd9	243
0d0302e2 GH	244	/* XXX: VGA_RAM_SIZE must be a power of two */
0d0302e2 GH	245	pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
47d37dd9	246
803ff052 GH	247	/* mmio bar for vga register access */
803ff052 GH	248	if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) {
83ff909f GH	249	memory_region_init(&d->mmio, NULL, "vga.mmio",
83ff909f GH	250	PCI_VGA_MMIO_SIZE);
b5682aa4 GH	251
b5682aa4 GH	252	if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
220869e1	253	qext = true;
b5682aa4 GH	254	pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
b5682aa4 GH	255	}
d46b40fc GH	256	if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) {
	257	edid = true;
	258	}
	259	pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs,
	260	qext, edid);
b5682aa4	261
803ff052 GH	262	pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
	263	}
	264
0d0302e2 GH	265	if (!dev->rom_bar) {
0d0302e2 GH	266	/* compatibility with pc-0.13 and older */
83118327	267	vga_init_vbe(s, OBJECT(dev), pci_address_space(dev));
0d0302e2	268	}
47d37dd9 JQ	269	}
47d37dd9 JQ	270
3c2784fc DG	271	static void pci_std_vga_init(Object *obj)
	272	{
	273	/* Expose framebuffer byteorder via QOM */
	274	object_property_add_bool(obj, "big-endian-framebuffer",
	275	vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
	276	}
	277
9af21dbe	278	static void pci_secondary_vga_realize(PCIDevice dev, Error *errp)
63e3e24d	279	{
176c324f	280	PCIVGAState *d = PCI_VGA(dev);
63e3e24d	281	VGACommonState *s = &d->vga;
220869e1	282	bool qext = false;
d46b40fc	283	bool edid = false;
63e3e24d GH	284
63e3e24d GH	285	/* vga + console init */
1fcfdc43	286	vga_common_init(s, OBJECT(dev));
63e3e24d GH	287	s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
	288
	289	/* mmio bar */
83ff909f GH	290	memory_region_init(&d->mmio, OBJECT(dev), "vga.mmio",
83ff909f GH	291	PCI_VGA_MMIO_SIZE);
63e3e24d	292
b5682aa4	293	if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
220869e1	294	qext = true;
b5682aa4 GH	295	pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
b5682aa4 GH	296	}
d46b40fc GH	297	if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) {
	298	edid = true;
	299	}
	300	pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs, qext, edid);
b5682aa4	301
63e3e24d GH	302	pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
63e3e24d GH	303	pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
3c2784fc	304	}
63e3e24d	305
fc70514c GH	306	static void pci_secondary_vga_exit(PCIDevice *dev)
	307	{
	308	PCIVGAState *d = PCI_VGA(dev);
	309	VGACommonState *s = &d->vga;
	310
	311	graphic_console_close(s->con);
0ab90e61 RN	312	memory_region_del_subregion(&d->mmio, &d->mrs[0]);
	313	memory_region_del_subregion(&d->mmio, &d->mrs[1]);
	314	if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
	315	memory_region_del_subregion(&d->mmio, &d->mrs[2]);
	316	}
	317	if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) {
	318	memory_region_del_subregion(&d->mmio, &d->mrs[3]);
	319	}
fc70514c GH	320	}
fc70514c GH	321
3c2784fc DG	322	static void pci_secondary_vga_init(Object *obj)
	323	{
	324	/* Expose framebuffer byteorder via QOM */
	325	object_property_add_bool(obj, "big-endian-framebuffer",
	326	vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
63e3e24d GH	327	}
	328
	329	static void pci_secondary_vga_reset(DeviceState *dev)
	330	{
176c324f	331	PCIVGAState *d = PCI_VGA(PCI_DEVICE(dev));
63e3e24d GH	332	vga_common_reset(&d->vga);
	333	}
	334
4a1e244e	335	static Property vga_pci_properties[] = {
9e56edcf	336	DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
803ff052	337	DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true),
b5682aa4 GH	338	DEFINE_PROP_BIT("qemu-extended-regs",
b5682aa4 GH	339	PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
d46b40fc GH	340	DEFINE_PROP_BIT("edid",
	341	PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, false),
	342	DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info),
1fcfdc43	343	DEFINE_PROP_BOOL("global-vmstate", PCIVGAState, vga.global_vmstate, false),
4a1e244e GH	344	DEFINE_PROP_END_OF_LIST(),
	345	};
	346
63e3e24d GH	347	static Property secondary_pci_properties[] = {
63e3e24d GH	348	DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
b5682aa4 GH	349	DEFINE_PROP_BIT("qemu-extended-regs",
b5682aa4 GH	350	PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
d46b40fc GH	351	DEFINE_PROP_BIT("edid",
	352	PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, false),
	353	DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info),
63e3e24d GH	354	DEFINE_PROP_END_OF_LIST(),
	355	};
	356
176c324f GA	357	static void vga_pci_class_init(ObjectClass klass, void data)
	358	{
	359	DeviceClass *dc = DEVICE_CLASS(klass);
	360	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	361
	362	k->vendor_id = PCI_VENDOR_ID_QEMU;
	363	k->device_id = PCI_DEVICE_ID_QEMU_VGA;
	364	dc->vmsd = &vmstate_vga_pci;
	365	set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
	366	}
	367
	368	static const TypeInfo vga_pci_type_info = {
	369	.name = TYPE_PCI_VGA,
	370	.parent = TYPE_PCI_DEVICE,
	371	.instance_size = sizeof(PCIVGAState),
	372	.abstract = true,
	373	.class_init = vga_pci_class_init,
fd3b02c8 EH	374	.interfaces = (InterfaceInfo[]) {
	375	{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
	376	{ },
	377	},
176c324f GA	378	};
176c324f GA	379
40021f08 AL	380	static void vga_class_init(ObjectClass klass, void data)
40021f08 AL	381	{
39bffca2	382	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	383	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
40021f08 AL	384
9af21dbe	385	k->realize = pci_std_vga_realize;
40021f08	386	k->romfile = "vgabios-stdvga.bin";
40021f08	387	k->class_id = PCI_CLASS_DISPLAY_VGA;
4a1e244e	388	dc->props = vga_pci_properties;
2897ae02	389	dc->hotpluggable = false;
40021f08	390	}
32902772	391
63e3e24d GH	392	static void secondary_class_init(ObjectClass klass, void data)
	393	{
	394	DeviceClass *dc = DEVICE_CLASS(klass);
	395	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	396
9af21dbe	397	k->realize = pci_secondary_vga_realize;
fc70514c	398	k->exit = pci_secondary_vga_exit;
63e3e24d	399	k->class_id = PCI_CLASS_DISPLAY_OTHER;
63e3e24d GH	400	dc->props = secondary_pci_properties;
	401	dc->reset = pci_secondary_vga_reset;
	402	}
	403
8c43a6f0	404	static const TypeInfo vga_info = {
39bffca2	405	.name = "VGA",
176c324f	406	.parent = TYPE_PCI_VGA,
3c2784fc	407	.instance_init = pci_std_vga_init,
39bffca2	408	.class_init = vga_class_init,
47d37dd9 JQ	409	};
47d37dd9 JQ	410
63e3e24d GH	411	static const TypeInfo secondary_info = {
63e3e24d GH	412	.name = "secondary-vga",
176c324f	413	.parent = TYPE_PCI_VGA,
3c2784fc	414	.instance_init = pci_secondary_vga_init,
63e3e24d GH	415	.class_init = secondary_class_init,
	416	};
	417
83f7d43a	418	static void vga_register_types(void)
47d37dd9	419	{
176c324f	420	type_register_static(&vga_pci_type_info);
39bffca2	421	type_register_static(&vga_info);
63e3e24d	422	type_register_static(&secondary_info);
47d37dd9	423	}
83f7d43a AF	424
83f7d43a AF	425	type_init(vga_register_types)