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Commit | Line | Data |
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47d37dd9 JQ |
1 | /* |
2 | * QEMU PCI VGA Emulator. | |
3 | * | |
cc228248 GH |
4 | * see docs/specs/standard-vga.txt for virtual hardware specs. |
5 | * | |
47d37dd9 JQ |
6 | * Copyright (c) 2003 Fabrice Bellard |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | */ | |
47df5154 | 26 | #include "qemu/osdep.h" |
83c9f4ca | 27 | #include "hw/hw.h" |
83c9f4ca | 28 | #include "hw/pci/pci.h" |
47b43a1f | 29 | #include "vga_int.h" |
28ecbaee | 30 | #include "ui/pixel_ops.h" |
1de7afc9 | 31 | #include "qemu/timer.h" |
83c9f4ca | 32 | #include "hw/loader.h" |
47d37dd9 | 33 | |
803ff052 GH |
34 | enum vga_pci_flags { |
35 | PCI_VGA_FLAG_ENABLE_MMIO = 1, | |
b5682aa4 | 36 | PCI_VGA_FLAG_ENABLE_QEXT = 2, |
803ff052 GH |
37 | }; |
38 | ||
47d37dd9 JQ |
39 | typedef struct PCIVGAState { |
40 | PCIDevice dev; | |
41 | VGACommonState vga; | |
803ff052 GH |
42 | uint32_t flags; |
43 | MemoryRegion mmio; | |
220869e1 | 44 | MemoryRegion mrs[3]; |
47d37dd9 JQ |
45 | } PCIVGAState; |
46 | ||
176c324f GA |
47 | #define TYPE_PCI_VGA "pci-vga" |
48 | #define PCI_VGA(obj) OBJECT_CHECK(PCIVGAState, (obj), TYPE_PCI_VGA) | |
49 | ||
a4f9631c JQ |
50 | static const VMStateDescription vmstate_vga_pci = { |
51 | .name = "vga", | |
52 | .version_id = 2, | |
53 | .minimum_version_id = 2, | |
d49805ae | 54 | .fields = (VMStateField[]) { |
a4f9631c JQ |
55 | VMSTATE_PCI_DEVICE(dev, PCIVGAState), |
56 | VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState), | |
57 | VMSTATE_END_OF_LIST() | |
47d37dd9 | 58 | } |
a4f9631c | 59 | }; |
47d37dd9 | 60 | |
a8170e5e | 61 | static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr, |
803ff052 GH |
62 | unsigned size) |
63 | { | |
cf45ec6a | 64 | VGACommonState *s = ptr; |
803ff052 GH |
65 | uint64_t ret = 0; |
66 | ||
67 | switch (size) { | |
68 | case 1: | |
cf45ec6a | 69 | ret = vga_ioport_read(s, addr + 0x3c0); |
803ff052 GH |
70 | break; |
71 | case 2: | |
cf45ec6a GH |
72 | ret = vga_ioport_read(s, addr + 0x3c0); |
73 | ret |= vga_ioport_read(s, addr + 0x3c1) << 8; | |
803ff052 GH |
74 | break; |
75 | } | |
76 | return ret; | |
77 | } | |
78 | ||
a8170e5e | 79 | static void pci_vga_ioport_write(void *ptr, hwaddr addr, |
803ff052 GH |
80 | uint64_t val, unsigned size) |
81 | { | |
cf45ec6a | 82 | VGACommonState *s = ptr; |
c96c53b5 | 83 | |
803ff052 GH |
84 | switch (size) { |
85 | case 1: | |
cf45ec6a | 86 | vga_ioport_write(s, addr + 0x3c0, val); |
803ff052 GH |
87 | break; |
88 | case 2: | |
89 | /* | |
90 | * Update bytes in little endian order. Allows to update | |
91 | * indexed registers with a single word write because the | |
92 | * index byte is updated first. | |
93 | */ | |
cf45ec6a GH |
94 | vga_ioport_write(s, addr + 0x3c0, val & 0xff); |
95 | vga_ioport_write(s, addr + 0x3c1, (val >> 8) & 0xff); | |
803ff052 GH |
96 | break; |
97 | } | |
98 | } | |
99 | ||
100 | static const MemoryRegionOps pci_vga_ioport_ops = { | |
101 | .read = pci_vga_ioport_read, | |
102 | .write = pci_vga_ioport_write, | |
103 | .valid.min_access_size = 1, | |
104 | .valid.max_access_size = 4, | |
105 | .impl.min_access_size = 1, | |
106 | .impl.max_access_size = 2, | |
107 | .endianness = DEVICE_LITTLE_ENDIAN, | |
108 | }; | |
109 | ||
a8170e5e | 110 | static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr, |
803ff052 GH |
111 | unsigned size) |
112 | { | |
cf45ec6a | 113 | VGACommonState *s = ptr; |
803ff052 GH |
114 | int index = addr >> 1; |
115 | ||
cf45ec6a GH |
116 | vbe_ioport_write_index(s, 0, index); |
117 | return vbe_ioport_read_data(s, 0); | |
803ff052 GH |
118 | } |
119 | ||
a8170e5e | 120 | static void pci_vga_bochs_write(void *ptr, hwaddr addr, |
803ff052 GH |
121 | uint64_t val, unsigned size) |
122 | { | |
cf45ec6a | 123 | VGACommonState *s = ptr; |
803ff052 GH |
124 | int index = addr >> 1; |
125 | ||
cf45ec6a GH |
126 | vbe_ioport_write_index(s, 0, index); |
127 | vbe_ioport_write_data(s, 0, val); | |
803ff052 GH |
128 | } |
129 | ||
130 | static const MemoryRegionOps pci_vga_bochs_ops = { | |
131 | .read = pci_vga_bochs_read, | |
132 | .write = pci_vga_bochs_write, | |
133 | .valid.min_access_size = 1, | |
134 | .valid.max_access_size = 4, | |
135 | .impl.min_access_size = 2, | |
136 | .impl.max_access_size = 2, | |
137 | .endianness = DEVICE_LITTLE_ENDIAN, | |
138 | }; | |
139 | ||
b5682aa4 GH |
140 | static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size) |
141 | { | |
cf45ec6a | 142 | VGACommonState *s = ptr; |
b5682aa4 GH |
143 | |
144 | switch (addr) { | |
145 | case PCI_VGA_QEXT_REG_SIZE: | |
146 | return PCI_VGA_QEXT_SIZE; | |
147 | case PCI_VGA_QEXT_REG_BYTEORDER: | |
cf45ec6a | 148 | return s->big_endian_fb ? |
b5682aa4 GH |
149 | PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN; |
150 | default: | |
151 | return 0; | |
152 | } | |
153 | } | |
154 | ||
155 | static void pci_vga_qext_write(void *ptr, hwaddr addr, | |
156 | uint64_t val, unsigned size) | |
157 | { | |
cf45ec6a | 158 | VGACommonState *s = ptr; |
b5682aa4 GH |
159 | |
160 | switch (addr) { | |
161 | case PCI_VGA_QEXT_REG_BYTEORDER: | |
162 | if (val == PCI_VGA_QEXT_BIG_ENDIAN) { | |
cf45ec6a | 163 | s->big_endian_fb = true; |
b5682aa4 GH |
164 | } |
165 | if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) { | |
cf45ec6a | 166 | s->big_endian_fb = false; |
b5682aa4 GH |
167 | } |
168 | break; | |
169 | } | |
170 | } | |
171 | ||
3c2784fc DG |
172 | static bool vga_get_big_endian_fb(Object *obj, Error **errp) |
173 | { | |
176c324f | 174 | PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj)); |
3c2784fc DG |
175 | |
176 | return d->vga.big_endian_fb; | |
177 | } | |
178 | ||
179 | static void vga_set_big_endian_fb(Object *obj, bool value, Error **errp) | |
180 | { | |
176c324f | 181 | PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj)); |
3c2784fc DG |
182 | |
183 | d->vga.big_endian_fb = value; | |
184 | } | |
185 | ||
b5682aa4 GH |
186 | static const MemoryRegionOps pci_vga_qext_ops = { |
187 | .read = pci_vga_qext_read, | |
188 | .write = pci_vga_qext_write, | |
189 | .valid.min_access_size = 4, | |
190 | .valid.max_access_size = 4, | |
191 | .endianness = DEVICE_LITTLE_ENDIAN, | |
192 | }; | |
193 | ||
c5d4dac8 | 194 | void pci_std_vga_mmio_region_init(VGACommonState *s, |
93abfc88 | 195 | Object *owner, |
c5d4dac8 GH |
196 | MemoryRegion *parent, |
197 | MemoryRegion *subs, | |
198 | bool qext) | |
220869e1 | 199 | { |
93abfc88 | 200 | memory_region_init_io(&subs[0], owner, &pci_vga_ioport_ops, s, |
220869e1 GH |
201 | "vga ioports remapped", PCI_VGA_IOPORT_SIZE); |
202 | memory_region_add_subregion(parent, PCI_VGA_IOPORT_OFFSET, | |
203 | &subs[0]); | |
204 | ||
93abfc88 | 205 | memory_region_init_io(&subs[1], owner, &pci_vga_bochs_ops, s, |
220869e1 GH |
206 | "bochs dispi interface", PCI_VGA_BOCHS_SIZE); |
207 | memory_region_add_subregion(parent, PCI_VGA_BOCHS_OFFSET, | |
208 | &subs[1]); | |
209 | ||
210 | if (qext) { | |
93abfc88 | 211 | memory_region_init_io(&subs[2], owner, &pci_vga_qext_ops, s, |
220869e1 GH |
212 | "qemu extended regs", PCI_VGA_QEXT_SIZE); |
213 | memory_region_add_subregion(parent, PCI_VGA_QEXT_OFFSET, | |
214 | &subs[2]); | |
215 | } | |
216 | } | |
217 | ||
9af21dbe | 218 | static void pci_std_vga_realize(PCIDevice *dev, Error **errp) |
47d37dd9 | 219 | { |
176c324f | 220 | PCIVGAState *d = PCI_VGA(dev); |
0d0302e2 | 221 | VGACommonState *s = &d->vga; |
220869e1 | 222 | bool qext = false; |
47d37dd9 | 223 | |
0d0302e2 | 224 | /* vga + console init */ |
e2bbfc8e | 225 | vga_common_init(s, OBJECT(dev), true); |
712f0cc7 PB |
226 | vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev), |
227 | true); | |
47d37dd9 | 228 | |
5643706a | 229 | s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s); |
47d37dd9 | 230 | |
0d0302e2 GH |
231 | /* XXX: VGA_RAM_SIZE must be a power of two */ |
232 | pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram); | |
47d37dd9 | 233 | |
803ff052 GH |
234 | /* mmio bar for vga register access */ |
235 | if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) { | |
83ff909f GH |
236 | memory_region_init(&d->mmio, NULL, "vga.mmio", |
237 | PCI_VGA_MMIO_SIZE); | |
b5682aa4 GH |
238 | |
239 | if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) { | |
220869e1 | 240 | qext = true; |
b5682aa4 GH |
241 | pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2); |
242 | } | |
93abfc88 | 243 | pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs, qext); |
b5682aa4 | 244 | |
803ff052 GH |
245 | pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); |
246 | } | |
247 | ||
0d0302e2 GH |
248 | if (!dev->rom_bar) { |
249 | /* compatibility with pc-0.13 and older */ | |
83118327 | 250 | vga_init_vbe(s, OBJECT(dev), pci_address_space(dev)); |
0d0302e2 | 251 | } |
47d37dd9 JQ |
252 | } |
253 | ||
3c2784fc DG |
254 | static void pci_std_vga_init(Object *obj) |
255 | { | |
256 | /* Expose framebuffer byteorder via QOM */ | |
257 | object_property_add_bool(obj, "big-endian-framebuffer", | |
258 | vga_get_big_endian_fb, vga_set_big_endian_fb, NULL); | |
259 | } | |
260 | ||
9af21dbe | 261 | static void pci_secondary_vga_realize(PCIDevice *dev, Error **errp) |
63e3e24d | 262 | { |
176c324f | 263 | PCIVGAState *d = PCI_VGA(dev); |
63e3e24d | 264 | VGACommonState *s = &d->vga; |
220869e1 | 265 | bool qext = false; |
63e3e24d GH |
266 | |
267 | /* vga + console init */ | |
268 | vga_common_init(s, OBJECT(dev), false); | |
269 | s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s); | |
270 | ||
271 | /* mmio bar */ | |
83ff909f GH |
272 | memory_region_init(&d->mmio, OBJECT(dev), "vga.mmio", |
273 | PCI_VGA_MMIO_SIZE); | |
63e3e24d | 274 | |
b5682aa4 | 275 | if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) { |
220869e1 | 276 | qext = true; |
b5682aa4 GH |
277 | pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2); |
278 | } | |
93abfc88 | 279 | pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs, qext); |
b5682aa4 | 280 | |
63e3e24d GH |
281 | pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram); |
282 | pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); | |
3c2784fc | 283 | } |
63e3e24d | 284 | |
fc70514c GH |
285 | static void pci_secondary_vga_exit(PCIDevice *dev) |
286 | { | |
287 | PCIVGAState *d = PCI_VGA(dev); | |
288 | VGACommonState *s = &d->vga; | |
289 | ||
290 | graphic_console_close(s->con); | |
291 | } | |
292 | ||
3c2784fc DG |
293 | static void pci_secondary_vga_init(Object *obj) |
294 | { | |
295 | /* Expose framebuffer byteorder via QOM */ | |
296 | object_property_add_bool(obj, "big-endian-framebuffer", | |
297 | vga_get_big_endian_fb, vga_set_big_endian_fb, NULL); | |
63e3e24d GH |
298 | } |
299 | ||
300 | static void pci_secondary_vga_reset(DeviceState *dev) | |
301 | { | |
176c324f | 302 | PCIVGAState *d = PCI_VGA(PCI_DEVICE(dev)); |
63e3e24d GH |
303 | vga_common_reset(&d->vga); |
304 | } | |
305 | ||
4a1e244e | 306 | static Property vga_pci_properties[] = { |
9e56edcf | 307 | DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16), |
803ff052 | 308 | DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true), |
b5682aa4 GH |
309 | DEFINE_PROP_BIT("qemu-extended-regs", |
310 | PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true), | |
4a1e244e GH |
311 | DEFINE_PROP_END_OF_LIST(), |
312 | }; | |
313 | ||
63e3e24d GH |
314 | static Property secondary_pci_properties[] = { |
315 | DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16), | |
b5682aa4 GH |
316 | DEFINE_PROP_BIT("qemu-extended-regs", |
317 | PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true), | |
63e3e24d GH |
318 | DEFINE_PROP_END_OF_LIST(), |
319 | }; | |
320 | ||
176c324f GA |
321 | static void vga_pci_class_init(ObjectClass *klass, void *data) |
322 | { | |
323 | DeviceClass *dc = DEVICE_CLASS(klass); | |
324 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
325 | ||
326 | k->vendor_id = PCI_VENDOR_ID_QEMU; | |
327 | k->device_id = PCI_DEVICE_ID_QEMU_VGA; | |
328 | dc->vmsd = &vmstate_vga_pci; | |
329 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); | |
330 | } | |
331 | ||
332 | static const TypeInfo vga_pci_type_info = { | |
333 | .name = TYPE_PCI_VGA, | |
334 | .parent = TYPE_PCI_DEVICE, | |
335 | .instance_size = sizeof(PCIVGAState), | |
336 | .abstract = true, | |
337 | .class_init = vga_pci_class_init, | |
fd3b02c8 EH |
338 | .interfaces = (InterfaceInfo[]) { |
339 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
340 | { }, | |
341 | }, | |
176c324f GA |
342 | }; |
343 | ||
40021f08 AL |
344 | static void vga_class_init(ObjectClass *klass, void *data) |
345 | { | |
39bffca2 | 346 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
347 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
348 | ||
9af21dbe | 349 | k->realize = pci_std_vga_realize; |
40021f08 | 350 | k->romfile = "vgabios-stdvga.bin"; |
40021f08 | 351 | k->class_id = PCI_CLASS_DISPLAY_VGA; |
4a1e244e | 352 | dc->props = vga_pci_properties; |
2897ae02 | 353 | dc->hotpluggable = false; |
40021f08 | 354 | } |
32902772 | 355 | |
63e3e24d GH |
356 | static void secondary_class_init(ObjectClass *klass, void *data) |
357 | { | |
358 | DeviceClass *dc = DEVICE_CLASS(klass); | |
359 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
360 | ||
9af21dbe | 361 | k->realize = pci_secondary_vga_realize; |
fc70514c | 362 | k->exit = pci_secondary_vga_exit; |
63e3e24d | 363 | k->class_id = PCI_CLASS_DISPLAY_OTHER; |
63e3e24d GH |
364 | dc->props = secondary_pci_properties; |
365 | dc->reset = pci_secondary_vga_reset; | |
366 | } | |
367 | ||
8c43a6f0 | 368 | static const TypeInfo vga_info = { |
39bffca2 | 369 | .name = "VGA", |
176c324f | 370 | .parent = TYPE_PCI_VGA, |
3c2784fc | 371 | .instance_init = pci_std_vga_init, |
39bffca2 | 372 | .class_init = vga_class_init, |
47d37dd9 JQ |
373 | }; |
374 | ||
63e3e24d GH |
375 | static const TypeInfo secondary_info = { |
376 | .name = "secondary-vga", | |
176c324f | 377 | .parent = TYPE_PCI_VGA, |
3c2784fc | 378 | .instance_init = pci_secondary_vga_init, |
63e3e24d GH |
379 | .class_init = secondary_class_init, |
380 | }; | |
381 | ||
83f7d43a | 382 | static void vga_register_types(void) |
47d37dd9 | 383 | { |
176c324f | 384 | type_register_static(&vga_pci_type_info); |
39bffca2 | 385 | type_register_static(&vga_info); |
63e3e24d | 386 | type_register_static(&secondary_info); |
47d37dd9 | 387 | } |
83f7d43a AF |
388 | |
389 | type_init(vga_register_types) |