[mirror_qemu.git] / hw / display / vga-pci.c

/*
 * QEMU PCI VGA Emulator.
 *
 * see docs/specs/standard-vga.txt for virtual hardware specs.
 *
 * Copyright (c) 2003 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw/hw.h"
#include "ui/console.h"
#include "hw/pci/pci.h"
#include "vga_int.h"
#include "ui/pixel_ops.h"
#include "qemu/timer.h"
#include "hw/loader.h"

#define PCI_VGA_IOPORT_OFFSET 0x400
#define PCI_VGA_IOPORT_SIZE   (0x3e0 - 0x3c0)
#define PCI_VGA_BOCHS_OFFSET  0x500
#define PCI_VGA_BOCHS_SIZE    (0x0b * 2)
#define PCI_VGA_QEXT_OFFSET   0x600
#define PCI_VGA_QEXT_SIZE     (2 * 4)
#define PCI_VGA_MMIO_SIZE     0x1000

#define PCI_VGA_QEXT_REG_SIZE         (0 * 4)
#define PCI_VGA_QEXT_REG_BYTEORDER    (1 * 4)
#define  PCI_VGA_QEXT_LITTLE_ENDIAN   0x1e1e1e1e
#define  PCI_VGA_QEXT_BIG_ENDIAN      0xbebebebe

enum vga_pci_flags {
    PCI_VGA_FLAG_ENABLE_MMIO = 1,
    PCI_VGA_FLAG_ENABLE_QEXT = 2,
};

typedef struct PCIVGAState {
    PCIDevice dev;
    VGACommonState vga;
    uint32_t flags;
    MemoryRegion mmio;
    MemoryRegion ioport;
    MemoryRegion bochs;
    MemoryRegion qext;
} PCIVGAState;

#define TYPE_PCI_VGA "pci-vga"
#define PCI_VGA(obj) OBJECT_CHECK(PCIVGAState, (obj), TYPE_PCI_VGA)

static const VMStateDescription vmstate_vga_pci = {
    .name = "vga",
    .version_id = 2,
    .minimum_version_id = 2,
    .fields = (VMStateField[]) {
        VMSTATE_PCI_DEVICE(dev, PCIVGAState),
        VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState),
        VMSTATE_END_OF_LIST()
    }
};

static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr,
                                    unsigned size)
{
    PCIVGAState *d = ptr;
    uint64_t ret = 0;

    switch (size) {
    case 1:
        ret = vga_ioport_read(&d->vga, addr + 0x3c0);
        break;
    case 2:
        ret  = vga_ioport_read(&d->vga, addr + 0x3c0);
        ret |= vga_ioport_read(&d->vga, addr + 0x3c1) << 8;
        break;
    }
    return ret;
}

static void pci_vga_ioport_write(void *ptr, hwaddr addr,
                                 uint64_t val, unsigned size)
{
    PCIVGAState *d = ptr;

    switch (size) {
    case 1:
        vga_ioport_write(&d->vga, addr + 0x3c0, val);
        break;
    case 2:
        /*
         * Update bytes in little endian order.  Allows to update
         * indexed registers with a single word write because the
         * index byte is updated first.
         */
        vga_ioport_write(&d->vga, addr + 0x3c0, val & 0xff);
        vga_ioport_write(&d->vga, addr + 0x3c1, (val >> 8) & 0xff);
        break;
    }
}

static const MemoryRegionOps pci_vga_ioport_ops = {
    .read = pci_vga_ioport_read,
    .write = pci_vga_ioport_write,
    .valid.min_access_size = 1,
    .valid.max_access_size = 4,
    .impl.min_access_size = 1,
    .impl.max_access_size = 2,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr,
                                   unsigned size)
{
    PCIVGAState *d = ptr;
    int index = addr >> 1;

    vbe_ioport_write_index(&d->vga, 0, index);
    return vbe_ioport_read_data(&d->vga, 0);
}

static void pci_vga_bochs_write(void *ptr, hwaddr addr,
                                uint64_t val, unsigned size)
{
    PCIVGAState *d = ptr;
    int index = addr >> 1;

    vbe_ioport_write_index(&d->vga, 0, index);
    vbe_ioport_write_data(&d->vga, 0, val);
}

static const MemoryRegionOps pci_vga_bochs_ops = {
    .read = pci_vga_bochs_read,
    .write = pci_vga_bochs_write,
    .valid.min_access_size = 1,
    .valid.max_access_size = 4,
    .impl.min_access_size = 2,
    .impl.max_access_size = 2,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size)
{
    PCIVGAState *d = ptr;

    switch (addr) {
    case PCI_VGA_QEXT_REG_SIZE:
        return PCI_VGA_QEXT_SIZE;
    case PCI_VGA_QEXT_REG_BYTEORDER:
        return d->vga.big_endian_fb ?
            PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN;
    default:
        return 0;
    }
}

static void pci_vga_qext_write(void *ptr, hwaddr addr,
                               uint64_t val, unsigned size)
{
    PCIVGAState *d = ptr;

    switch (addr) {
    case PCI_VGA_QEXT_REG_BYTEORDER:
        if (val == PCI_VGA_QEXT_BIG_ENDIAN) {
            d->vga.big_endian_fb = true;
        }
        if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) {
            d->vga.big_endian_fb = false;
        }
        break;
    }
}

static bool vga_get_big_endian_fb(Object *obj, Error **errp)
{
    PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));

    return d->vga.big_endian_fb;
}

static void vga_set_big_endian_fb(Object *obj, bool value, Error **errp)
{
    PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));

    d->vga.big_endian_fb = value;
}

static const MemoryRegionOps pci_vga_qext_ops = {
    .read = pci_vga_qext_read,
    .write = pci_vga_qext_write,
    .valid.min_access_size = 4,
    .valid.max_access_size = 4,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void pci_std_vga_realize(PCIDevice *dev, Error **errp)
{
    PCIVGAState *d = PCI_VGA(dev);
    VGACommonState *s = &d->vga;

    /* vga + console init */
    vga_common_init(s, OBJECT(dev), true);
    vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev),
             true);

    s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);

    /* XXX: VGA_RAM_SIZE must be a power of two */
    pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);

    /* mmio bar for vga register access */
    if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) {
        memory_region_init(&d->mmio, NULL, "vga.mmio", 4096);
        memory_region_init_io(&d->ioport, NULL, &pci_vga_ioport_ops, d,
                              "vga ioports remapped", PCI_VGA_IOPORT_SIZE);
        memory_region_init_io(&d->bochs, NULL, &pci_vga_bochs_ops, d,
                              "bochs dispi interface", PCI_VGA_BOCHS_SIZE);

        memory_region_add_subregion(&d->mmio, PCI_VGA_IOPORT_OFFSET,
                                    &d->ioport);
        memory_region_add_subregion(&d->mmio, PCI_VGA_BOCHS_OFFSET,
                                    &d->bochs);

        if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
            memory_region_init_io(&d->qext, NULL, &pci_vga_qext_ops, d,
                                  "qemu extended regs", PCI_VGA_QEXT_SIZE);
            memory_region_add_subregion(&d->mmio, PCI_VGA_QEXT_OFFSET,
                                        &d->qext);
            pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
        }

        pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
    }

    if (!dev->rom_bar) {
        /* compatibility with pc-0.13 and older */
        vga_init_vbe(s, OBJECT(dev), pci_address_space(dev));
    }
}

static void pci_std_vga_init(Object *obj)
{
    /* Expose framebuffer byteorder via QOM */
    object_property_add_bool(obj, "big-endian-framebuffer",
                             vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
}

static void pci_secondary_vga_realize(PCIDevice *dev, Error **errp)
{
    PCIVGAState *d = PCI_VGA(dev);
    VGACommonState *s = &d->vga;

    /* vga + console init */
    vga_common_init(s, OBJECT(dev), false);
    s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);

    /* mmio bar */
    memory_region_init(&d->mmio, OBJECT(dev), "vga.mmio", 4096);
    memory_region_init_io(&d->ioport, OBJECT(dev), &pci_vga_ioport_ops, d,
                          "vga ioports remapped", PCI_VGA_IOPORT_SIZE);
    memory_region_init_io(&d->bochs, OBJECT(dev), &pci_vga_bochs_ops, d,
                          "bochs dispi interface", PCI_VGA_BOCHS_SIZE);

    memory_region_add_subregion(&d->mmio, PCI_VGA_IOPORT_OFFSET,
                                &d->ioport);
    memory_region_add_subregion(&d->mmio, PCI_VGA_BOCHS_OFFSET,
                                &d->bochs);

    if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
        memory_region_init_io(&d->qext, NULL, &pci_vga_qext_ops, d,
                              "qemu extended regs", PCI_VGA_QEXT_SIZE);
        memory_region_add_subregion(&d->mmio, PCI_VGA_QEXT_OFFSET,
                                    &d->qext);
        pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
    }

    pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
    pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
}

static void pci_secondary_vga_init(Object *obj)
{
    /* Expose framebuffer byteorder via QOM */
    object_property_add_bool(obj, "big-endian-framebuffer",
                             vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
}

static void pci_secondary_vga_reset(DeviceState *dev)
{
    PCIVGAState *d = PCI_VGA(PCI_DEVICE(dev));
    vga_common_reset(&d->vga);
}

static Property vga_pci_properties[] = {
    DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
    DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true),
    DEFINE_PROP_BIT("qemu-extended-regs",
                    PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
    DEFINE_PROP_END_OF_LIST(),
};

static Property secondary_pci_properties[] = {
    DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
    DEFINE_PROP_BIT("qemu-extended-regs",
                    PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
    DEFINE_PROP_END_OF_LIST(),
};

static void vga_pci_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->vendor_id = PCI_VENDOR_ID_QEMU;
    k->device_id = PCI_DEVICE_ID_QEMU_VGA;
    dc->vmsd = &vmstate_vga_pci;
    set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
}

static const TypeInfo vga_pci_type_info = {
    .name = TYPE_PCI_VGA,
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIVGAState),
    .abstract = true,
    .class_init = vga_pci_class_init,
};

static void vga_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->realize = pci_std_vga_realize;
    k->romfile = "vgabios-stdvga.bin";
    k->class_id = PCI_CLASS_DISPLAY_VGA;
    dc->props = vga_pci_properties;
    dc->hotpluggable = false;
}

static void secondary_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->realize = pci_secondary_vga_realize;
    k->class_id = PCI_CLASS_DISPLAY_OTHER;
    dc->props = secondary_pci_properties;
    dc->reset = pci_secondary_vga_reset;
}

static const TypeInfo vga_info = {
    .name          = "VGA",
    .parent        = TYPE_PCI_VGA,
    .instance_init = pci_std_vga_init,
    .class_init    = vga_class_init,
};

static const TypeInfo secondary_info = {
    .name          = "secondary-vga",
    .parent        = TYPE_PCI_VGA,
    .instance_init = pci_secondary_vga_init,
    .class_init    = secondary_class_init,
};

static void vga_register_types(void)
{
    type_register_static(&vga_pci_type_info);
    type_register_static(&vga_info);
    type_register_static(&secondary_info);
}

type_init(vga_register_types)
Commit	Line	Data
47d37dd9 JQ	1	/*
	2	* QEMU PCI VGA Emulator.
	3	*
cc228248 GH	4	* see docs/specs/standard-vga.txt for virtual hardware specs.
cc228248 GH	5	*
47d37dd9 JQ	6	* Copyright (c) 2003 Fabrice Bellard
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*/
83c9f4ca	26	#include "hw/hw.h"
28ecbaee	27	#include "ui/console.h"
83c9f4ca	28	#include "hw/pci/pci.h"
47b43a1f	29	#include "vga_int.h"
28ecbaee	30	#include "ui/pixel_ops.h"
1de7afc9	31	#include "qemu/timer.h"
83c9f4ca	32	#include "hw/loader.h"
47d37dd9	33
803ff052 GH	34	#define PCI_VGA_IOPORT_OFFSET 0x400
	35	#define PCI_VGA_IOPORT_SIZE (0x3e0 - 0x3c0)
	36	#define PCI_VGA_BOCHS_OFFSET 0x500
	37	#define PCI_VGA_BOCHS_SIZE (0x0b * 2)
b5682aa4 GH	38	#define PCI_VGA_QEXT_OFFSET 0x600
b5682aa4 GH	39	#define PCI_VGA_QEXT_SIZE (2 * 4)
803ff052 GH	40	#define PCI_VGA_MMIO_SIZE 0x1000
803ff052 GH	41
b5682aa4 GH	42	#define PCI_VGA_QEXT_REG_SIZE (0 * 4)
	43	#define PCI_VGA_QEXT_REG_BYTEORDER (1 * 4)
	44	#define PCI_VGA_QEXT_LITTLE_ENDIAN 0x1e1e1e1e
	45	#define PCI_VGA_QEXT_BIG_ENDIAN 0xbebebebe
	46
803ff052 GH	47	enum vga_pci_flags {
803ff052 GH	48	PCI_VGA_FLAG_ENABLE_MMIO = 1,
b5682aa4	49	PCI_VGA_FLAG_ENABLE_QEXT = 2,
803ff052 GH	50	};
803ff052 GH	51
47d37dd9 JQ	52	typedef struct PCIVGAState {
	53	PCIDevice dev;
	54	VGACommonState vga;
803ff052 GH	55	uint32_t flags;
	56	MemoryRegion mmio;
	57	MemoryRegion ioport;
	58	MemoryRegion bochs;
b5682aa4	59	MemoryRegion qext;
47d37dd9 JQ	60	} PCIVGAState;
47d37dd9 JQ	61
176c324f GA	62	#define TYPE_PCI_VGA "pci-vga"
	63	#define PCI_VGA(obj) OBJECT_CHECK(PCIVGAState, (obj), TYPE_PCI_VGA)
	64
a4f9631c JQ	65	static const VMStateDescription vmstate_vga_pci = {
	66	.name = "vga",
	67	.version_id = 2,
	68	.minimum_version_id = 2,
d49805ae	69	.fields = (VMStateField[]) {
a4f9631c JQ	70	VMSTATE_PCI_DEVICE(dev, PCIVGAState),
	71	VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState),
	72	VMSTATE_END_OF_LIST()
47d37dd9	73	}
a4f9631c	74	};
47d37dd9	75
a8170e5e	76	static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr,
803ff052 GH	77	unsigned size)
	78	{
	79	PCIVGAState *d = ptr;
	80	uint64_t ret = 0;
	81
	82	switch (size) {
	83	case 1:
24cdff7c	84	ret = vga_ioport_read(&d->vga, addr + 0x3c0);
803ff052 GH	85	break;
803ff052 GH	86	case 2:
24cdff7c GH	87	ret = vga_ioport_read(&d->vga, addr + 0x3c0);
24cdff7c GH	88	ret \|= vga_ioport_read(&d->vga, addr + 0x3c1) << 8;
803ff052 GH	89	break;
	90	}
	91	return ret;
	92	}
	93
a8170e5e	94	static void pci_vga_ioport_write(void *ptr, hwaddr addr,
803ff052 GH	95	uint64_t val, unsigned size)
	96	{
	97	PCIVGAState *d = ptr;
c96c53b5	98
803ff052 GH	99	switch (size) {
803ff052 GH	100	case 1:
c96c53b5	101	vga_ioport_write(&d->vga, addr + 0x3c0, val);
803ff052 GH	102	break;
	103	case 2:
	104	/*
	105	* Update bytes in little endian order. Allows to update
	106	* indexed registers with a single word write because the
	107	* index byte is updated first.
	108	*/
c96c53b5 GH	109	vga_ioport_write(&d->vga, addr + 0x3c0, val & 0xff);
c96c53b5 GH	110	vga_ioport_write(&d->vga, addr + 0x3c1, (val >> 8) & 0xff);
803ff052 GH	111	break;
	112	}
	113	}
	114
	115	static const MemoryRegionOps pci_vga_ioport_ops = {
	116	.read = pci_vga_ioport_read,
	117	.write = pci_vga_ioport_write,
	118	.valid.min_access_size = 1,
	119	.valid.max_access_size = 4,
	120	.impl.min_access_size = 1,
	121	.impl.max_access_size = 2,
	122	.endianness = DEVICE_LITTLE_ENDIAN,
	123	};
	124
a8170e5e	125	static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr,
803ff052 GH	126	unsigned size)
	127	{
	128	PCIVGAState *d = ptr;
	129	int index = addr >> 1;
	130
	131	vbe_ioport_write_index(&d->vga, 0, index);
	132	return vbe_ioport_read_data(&d->vga, 0);
	133	}
	134
a8170e5e	135	static void pci_vga_bochs_write(void *ptr, hwaddr addr,
803ff052 GH	136	uint64_t val, unsigned size)
	137	{
	138	PCIVGAState *d = ptr;
	139	int index = addr >> 1;
	140
	141	vbe_ioport_write_index(&d->vga, 0, index);
	142	vbe_ioport_write_data(&d->vga, 0, val);
	143	}
	144
	145	static const MemoryRegionOps pci_vga_bochs_ops = {
	146	.read = pci_vga_bochs_read,
	147	.write = pci_vga_bochs_write,
	148	.valid.min_access_size = 1,
	149	.valid.max_access_size = 4,
	150	.impl.min_access_size = 2,
	151	.impl.max_access_size = 2,
	152	.endianness = DEVICE_LITTLE_ENDIAN,
	153	};
	154
b5682aa4 GH	155	static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size)
	156	{
	157	PCIVGAState *d = ptr;
	158
	159	switch (addr) {
	160	case PCI_VGA_QEXT_REG_SIZE:
	161	return PCI_VGA_QEXT_SIZE;
	162	case PCI_VGA_QEXT_REG_BYTEORDER:
	163	return d->vga.big_endian_fb ?
	164	PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN;
	165	default:
	166	return 0;
	167	}
	168	}
	169
	170	static void pci_vga_qext_write(void *ptr, hwaddr addr,
	171	uint64_t val, unsigned size)
	172	{
	173	PCIVGAState *d = ptr;
	174
	175	switch (addr) {
	176	case PCI_VGA_QEXT_REG_BYTEORDER:
	177	if (val == PCI_VGA_QEXT_BIG_ENDIAN) {
	178	d->vga.big_endian_fb = true;
	179	}
	180	if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) {
	181	d->vga.big_endian_fb = false;
	182	}
	183	break;
	184	}
	185	}
	186
3c2784fc DG	187	static bool vga_get_big_endian_fb(Object obj, Error *errp)
3c2784fc DG	188	{
176c324f	189	PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
3c2784fc DG	190
	191	return d->vga.big_endian_fb;
	192	}
	193
	194	static void vga_set_big_endian_fb(Object obj, bool value, Error *errp)
	195	{
176c324f	196	PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
3c2784fc DG	197
	198	d->vga.big_endian_fb = value;
	199	}
	200
b5682aa4 GH	201	static const MemoryRegionOps pci_vga_qext_ops = {
	202	.read = pci_vga_qext_read,
	203	.write = pci_vga_qext_write,
	204	.valid.min_access_size = 4,
	205	.valid.max_access_size = 4,
	206	.endianness = DEVICE_LITTLE_ENDIAN,
	207	};
	208
9af21dbe	209	static void pci_std_vga_realize(PCIDevice dev, Error *errp)
47d37dd9	210	{
176c324f	211	PCIVGAState *d = PCI_VGA(dev);
0d0302e2	212	VGACommonState *s = &d->vga;
47d37dd9	213
0d0302e2	214	/* vga + console init */
e2bbfc8e	215	vga_common_init(s, OBJECT(dev), true);
712f0cc7 PB	216	vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev),
712f0cc7 PB	217	true);
47d37dd9	218
5643706a	219	s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
47d37dd9	220
0d0302e2 GH	221	/* XXX: VGA_RAM_SIZE must be a power of two */
0d0302e2 GH	222	pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
47d37dd9	223
803ff052 GH	224	/* mmio bar for vga register access */
803ff052 GH	225	if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) {
2c9b15ca PB	226	memory_region_init(&d->mmio, NULL, "vga.mmio", 4096);
2c9b15ca PB	227	memory_region_init_io(&d->ioport, NULL, &pci_vga_ioport_ops, d,
803ff052	228	"vga ioports remapped", PCI_VGA_IOPORT_SIZE);
2c9b15ca	229	memory_region_init_io(&d->bochs, NULL, &pci_vga_bochs_ops, d,
803ff052 GH	230	"bochs dispi interface", PCI_VGA_BOCHS_SIZE);
	231
	232	memory_region_add_subregion(&d->mmio, PCI_VGA_IOPORT_OFFSET,
	233	&d->ioport);
	234	memory_region_add_subregion(&d->mmio, PCI_VGA_BOCHS_OFFSET,
	235	&d->bochs);
b5682aa4 GH	236
	237	if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
	238	memory_region_init_io(&d->qext, NULL, &pci_vga_qext_ops, d,
	239	"qemu extended regs", PCI_VGA_QEXT_SIZE);
	240	memory_region_add_subregion(&d->mmio, PCI_VGA_QEXT_OFFSET,
	241	&d->qext);
	242	pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
	243	}
	244
803ff052 GH	245	pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
	246	}
	247
0d0302e2 GH	248	if (!dev->rom_bar) {
0d0302e2 GH	249	/* compatibility with pc-0.13 and older */
83118327	250	vga_init_vbe(s, OBJECT(dev), pci_address_space(dev));
0d0302e2	251	}
47d37dd9 JQ	252	}
47d37dd9 JQ	253
3c2784fc DG	254	static void pci_std_vga_init(Object *obj)
	255	{
	256	/* Expose framebuffer byteorder via QOM */
	257	object_property_add_bool(obj, "big-endian-framebuffer",
	258	vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
	259	}
	260
9af21dbe	261	static void pci_secondary_vga_realize(PCIDevice dev, Error *errp)
63e3e24d	262	{
176c324f	263	PCIVGAState *d = PCI_VGA(dev);
63e3e24d GH	264	VGACommonState *s = &d->vga;
	265
	266	/* vga + console init */
	267	vga_common_init(s, OBJECT(dev), false);
	268	s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
	269
	270	/* mmio bar */
	271	memory_region_init(&d->mmio, OBJECT(dev), "vga.mmio", 4096);
	272	memory_region_init_io(&d->ioport, OBJECT(dev), &pci_vga_ioport_ops, d,
	273	"vga ioports remapped", PCI_VGA_IOPORT_SIZE);
	274	memory_region_init_io(&d->bochs, OBJECT(dev), &pci_vga_bochs_ops, d,
	275	"bochs dispi interface", PCI_VGA_BOCHS_SIZE);
	276
	277	memory_region_add_subregion(&d->mmio, PCI_VGA_IOPORT_OFFSET,
	278	&d->ioport);
	279	memory_region_add_subregion(&d->mmio, PCI_VGA_BOCHS_OFFSET,
	280	&d->bochs);
	281
b5682aa4 GH	282	if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
	283	memory_region_init_io(&d->qext, NULL, &pci_vga_qext_ops, d,
	284	"qemu extended regs", PCI_VGA_QEXT_SIZE);
	285	memory_region_add_subregion(&d->mmio, PCI_VGA_QEXT_OFFSET,
	286	&d->qext);
	287	pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
	288	}
	289
63e3e24d GH	290	pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
63e3e24d GH	291	pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
3c2784fc	292	}
63e3e24d	293
3c2784fc DG	294	static void pci_secondary_vga_init(Object *obj)
	295	{
	296	/* Expose framebuffer byteorder via QOM */
	297	object_property_add_bool(obj, "big-endian-framebuffer",
	298	vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
63e3e24d GH	299	}
	300
	301	static void pci_secondary_vga_reset(DeviceState *dev)
	302	{
176c324f	303	PCIVGAState *d = PCI_VGA(PCI_DEVICE(dev));
63e3e24d GH	304	vga_common_reset(&d->vga);
	305	}
	306
4a1e244e	307	static Property vga_pci_properties[] = {
9e56edcf	308	DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
803ff052	309	DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true),
b5682aa4 GH	310	DEFINE_PROP_BIT("qemu-extended-regs",
b5682aa4 GH	311	PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
4a1e244e GH	312	DEFINE_PROP_END_OF_LIST(),
	313	};
	314
63e3e24d GH	315	static Property secondary_pci_properties[] = {
63e3e24d GH	316	DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
b5682aa4 GH	317	DEFINE_PROP_BIT("qemu-extended-regs",
b5682aa4 GH	318	PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
63e3e24d GH	319	DEFINE_PROP_END_OF_LIST(),
	320	};
	321
176c324f GA	322	static void vga_pci_class_init(ObjectClass klass, void data)
	323	{
	324	DeviceClass *dc = DEVICE_CLASS(klass);
	325	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	326
	327	k->vendor_id = PCI_VENDOR_ID_QEMU;
	328	k->device_id = PCI_DEVICE_ID_QEMU_VGA;
	329	dc->vmsd = &vmstate_vga_pci;
	330	set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
	331	}
	332
	333	static const TypeInfo vga_pci_type_info = {
	334	.name = TYPE_PCI_VGA,
	335	.parent = TYPE_PCI_DEVICE,
	336	.instance_size = sizeof(PCIVGAState),
	337	.abstract = true,
	338	.class_init = vga_pci_class_init,
	339	};
	340
40021f08 AL	341	static void vga_class_init(ObjectClass klass, void data)
40021f08 AL	342	{
39bffca2	343	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	344	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
40021f08 AL	345
9af21dbe	346	k->realize = pci_std_vga_realize;
40021f08	347	k->romfile = "vgabios-stdvga.bin";
40021f08	348	k->class_id = PCI_CLASS_DISPLAY_VGA;
4a1e244e	349	dc->props = vga_pci_properties;
2897ae02	350	dc->hotpluggable = false;
40021f08	351	}
32902772	352
63e3e24d GH	353	static void secondary_class_init(ObjectClass klass, void data)
	354	{
	355	DeviceClass *dc = DEVICE_CLASS(klass);
	356	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	357
9af21dbe	358	k->realize = pci_secondary_vga_realize;
63e3e24d	359	k->class_id = PCI_CLASS_DISPLAY_OTHER;
63e3e24d GH	360	dc->props = secondary_pci_properties;
	361	dc->reset = pci_secondary_vga_reset;
	362	}
	363
8c43a6f0	364	static const TypeInfo vga_info = {
39bffca2	365	.name = "VGA",
176c324f	366	.parent = TYPE_PCI_VGA,
3c2784fc	367	.instance_init = pci_std_vga_init,
39bffca2	368	.class_init = vga_class_init,
47d37dd9 JQ	369	};
47d37dd9 JQ	370
63e3e24d GH	371	static const TypeInfo secondary_info = {
63e3e24d GH	372	.name = "secondary-vga",
176c324f	373	.parent = TYPE_PCI_VGA,
3c2784fc	374	.instance_init = pci_secondary_vga_init,
63e3e24d GH	375	.class_init = secondary_class_init,
	376	};
	377
83f7d43a	378	static void vga_register_types(void)
47d37dd9	379	{
176c324f	380	type_register_static(&vga_pci_type_info);
39bffca2	381	type_register_static(&vga_info);
63e3e24d	382	type_register_static(&secondary_info);
47d37dd9	383	}
83f7d43a AF	384
83f7d43a AF	385	type_init(vga_register_types)