[mirror_qemu.git] / hw / display / vga-pci.c

/*
 * QEMU PCI VGA Emulator.
 *
 * see docs/specs/standard-vga.txt for virtual hardware specs.
 *
 * Copyright (c) 2003 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw/hw.h"
#include "ui/console.h"
#include "hw/pci/pci.h"
#include "vga_int.h"
#include "ui/pixel_ops.h"
#include "qemu/timer.h"
#include "hw/loader.h"

#define PCI_VGA_IOPORT_OFFSET 0x400
#define PCI_VGA_IOPORT_SIZE   (0x3e0 - 0x3c0)
#define PCI_VGA_BOCHS_OFFSET  0x500
#define PCI_VGA_BOCHS_SIZE    (0x0b * 2)
#define PCI_VGA_QEXT_OFFSET   0x600
#define PCI_VGA_QEXT_SIZE     (2 * 4)
#define PCI_VGA_MMIO_SIZE     0x1000

#define PCI_VGA_QEXT_REG_SIZE         (0 * 4)
#define PCI_VGA_QEXT_REG_BYTEORDER    (1 * 4)
#define  PCI_VGA_QEXT_LITTLE_ENDIAN   0x1e1e1e1e
#define  PCI_VGA_QEXT_BIG_ENDIAN      0xbebebebe

enum vga_pci_flags {
    PCI_VGA_FLAG_ENABLE_MMIO = 1,
    PCI_VGA_FLAG_ENABLE_QEXT = 2,
};

typedef struct PCIVGAState {
    PCIDevice dev;
    VGACommonState vga;
    uint32_t flags;
    MemoryRegion mmio;
    MemoryRegion mrs[3];
} PCIVGAState;

#define TYPE_PCI_VGA "pci-vga"
#define PCI_VGA(obj) OBJECT_CHECK(PCIVGAState, (obj), TYPE_PCI_VGA)

static const VMStateDescription vmstate_vga_pci = {
    .name = "vga",
    .version_id = 2,
    .minimum_version_id = 2,
    .fields = (VMStateField[]) {
        VMSTATE_PCI_DEVICE(dev, PCIVGAState),
        VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState),
        VMSTATE_END_OF_LIST()
    }
};

static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr,
                                    unsigned size)
{
    VGACommonState *s = ptr;
    uint64_t ret = 0;

    switch (size) {
    case 1:
        ret = vga_ioport_read(s, addr + 0x3c0);
        break;
    case 2:
        ret  = vga_ioport_read(s, addr + 0x3c0);
        ret |= vga_ioport_read(s, addr + 0x3c1) << 8;
        break;
    }
    return ret;
}

static void pci_vga_ioport_write(void *ptr, hwaddr addr,
                                 uint64_t val, unsigned size)
{
    VGACommonState *s = ptr;

    switch (size) {
    case 1:
        vga_ioport_write(s, addr + 0x3c0, val);
        break;
    case 2:
        /*
         * Update bytes in little endian order.  Allows to update
         * indexed registers with a single word write because the
         * index byte is updated first.
         */
        vga_ioport_write(s, addr + 0x3c0, val & 0xff);
        vga_ioport_write(s, addr + 0x3c1, (val >> 8) & 0xff);
        break;
    }
}

static const MemoryRegionOps pci_vga_ioport_ops = {
    .read = pci_vga_ioport_read,
    .write = pci_vga_ioport_write,
    .valid.min_access_size = 1,
    .valid.max_access_size = 4,
    .impl.min_access_size = 1,
    .impl.max_access_size = 2,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr,
                                   unsigned size)
{
    VGACommonState *s = ptr;
    int index = addr >> 1;

    vbe_ioport_write_index(s, 0, index);
    return vbe_ioport_read_data(s, 0);
}

static void pci_vga_bochs_write(void *ptr, hwaddr addr,
                                uint64_t val, unsigned size)
{
    VGACommonState *s = ptr;
    int index = addr >> 1;

    vbe_ioport_write_index(s, 0, index);
    vbe_ioport_write_data(s, 0, val);
}

static const MemoryRegionOps pci_vga_bochs_ops = {
    .read = pci_vga_bochs_read,
    .write = pci_vga_bochs_write,
    .valid.min_access_size = 1,
    .valid.max_access_size = 4,
    .impl.min_access_size = 2,
    .impl.max_access_size = 2,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size)
{
    VGACommonState *s = ptr;

    switch (addr) {
    case PCI_VGA_QEXT_REG_SIZE:
        return PCI_VGA_QEXT_SIZE;
    case PCI_VGA_QEXT_REG_BYTEORDER:
        return s->big_endian_fb ?
            PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN;
    default:
        return 0;
    }
}

static void pci_vga_qext_write(void *ptr, hwaddr addr,
                               uint64_t val, unsigned size)
{
    VGACommonState *s = ptr;

    switch (addr) {
    case PCI_VGA_QEXT_REG_BYTEORDER:
        if (val == PCI_VGA_QEXT_BIG_ENDIAN) {
            s->big_endian_fb = true;
        }
        if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) {
            s->big_endian_fb = false;
        }
        break;
    }
}

static bool vga_get_big_endian_fb(Object *obj, Error **errp)
{
    PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));

    return d->vga.big_endian_fb;
}

static void vga_set_big_endian_fb(Object *obj, bool value, Error **errp)
{
    PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));

    d->vga.big_endian_fb = value;
}

static const MemoryRegionOps pci_vga_qext_ops = {
    .read = pci_vga_qext_read,
    .write = pci_vga_qext_write,
    .valid.min_access_size = 4,
    .valid.max_access_size = 4,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

void pci_std_vga_mmio_region_init(VGACommonState *s,
                                  MemoryRegion *parent,
                                  MemoryRegion *subs,
                                  bool qext)
{
    memory_region_init_io(&subs[0], NULL, &pci_vga_ioport_ops, s,
                          "vga ioports remapped", PCI_VGA_IOPORT_SIZE);
    memory_region_add_subregion(parent, PCI_VGA_IOPORT_OFFSET,
                                &subs[0]);

    memory_region_init_io(&subs[1], NULL, &pci_vga_bochs_ops, s,
                          "bochs dispi interface", PCI_VGA_BOCHS_SIZE);
    memory_region_add_subregion(parent, PCI_VGA_BOCHS_OFFSET,
                                &subs[1]);

    if (qext) {
        memory_region_init_io(&subs[2], NULL, &pci_vga_qext_ops, s,
                              "qemu extended regs", PCI_VGA_QEXT_SIZE);
        memory_region_add_subregion(parent, PCI_VGA_QEXT_OFFSET,
                                    &subs[2]);
    }
}

static void pci_std_vga_realize(PCIDevice *dev, Error **errp)
{
    PCIVGAState *d = PCI_VGA(dev);
    VGACommonState *s = &d->vga;
    bool qext = false;

    /* vga + console init */
    vga_common_init(s, OBJECT(dev), true);
    vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev),
             true);

    s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);

    /* XXX: VGA_RAM_SIZE must be a power of two */
    pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);

    /* mmio bar for vga register access */
    if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) {
        memory_region_init(&d->mmio, NULL, "vga.mmio", 4096);

        if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
            qext = true;
            pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
        }
        pci_std_vga_mmio_region_init(s, &d->mmio, d->mrs, qext);

        pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
    }

    if (!dev->rom_bar) {
        /* compatibility with pc-0.13 and older */
        vga_init_vbe(s, OBJECT(dev), pci_address_space(dev));
    }
}

static void pci_std_vga_init(Object *obj)
{
    /* Expose framebuffer byteorder via QOM */
    object_property_add_bool(obj, "big-endian-framebuffer",
                             vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
}

static void pci_secondary_vga_realize(PCIDevice *dev, Error **errp)
{
    PCIVGAState *d = PCI_VGA(dev);
    VGACommonState *s = &d->vga;
    bool qext = false;

    /* vga + console init */
    vga_common_init(s, OBJECT(dev), false);
    s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);

    /* mmio bar */
    memory_region_init(&d->mmio, OBJECT(dev), "vga.mmio", 4096);

    if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
        qext = true;
        pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
    }
    pci_std_vga_mmio_region_init(s, &d->mmio, d->mrs, qext);

    pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
    pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
}

static void pci_secondary_vga_init(Object *obj)
{
    /* Expose framebuffer byteorder via QOM */
    object_property_add_bool(obj, "big-endian-framebuffer",
                             vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
}

static void pci_secondary_vga_reset(DeviceState *dev)
{
    PCIVGAState *d = PCI_VGA(PCI_DEVICE(dev));
    vga_common_reset(&d->vga);
}

static Property vga_pci_properties[] = {
    DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
    DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true),
    DEFINE_PROP_BIT("qemu-extended-regs",
                    PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
    DEFINE_PROP_END_OF_LIST(),
};

static Property secondary_pci_properties[] = {
    DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
    DEFINE_PROP_BIT("qemu-extended-regs",
                    PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
    DEFINE_PROP_END_OF_LIST(),
};

static void vga_pci_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->vendor_id = PCI_VENDOR_ID_QEMU;
    k->device_id = PCI_DEVICE_ID_QEMU_VGA;
    dc->vmsd = &vmstate_vga_pci;
    set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
}

static const TypeInfo vga_pci_type_info = {
    .name = TYPE_PCI_VGA,
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIVGAState),
    .abstract = true,
    .class_init = vga_pci_class_init,
};

static void vga_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->realize = pci_std_vga_realize;
    k->romfile = "vgabios-stdvga.bin";
    k->class_id = PCI_CLASS_DISPLAY_VGA;
    dc->props = vga_pci_properties;
    dc->hotpluggable = false;
}

static void secondary_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->realize = pci_secondary_vga_realize;
    k->class_id = PCI_CLASS_DISPLAY_OTHER;
    dc->props = secondary_pci_properties;
    dc->reset = pci_secondary_vga_reset;
}

static const TypeInfo vga_info = {
    .name          = "VGA",
    .parent        = TYPE_PCI_VGA,
    .instance_init = pci_std_vga_init,
    .class_init    = vga_class_init,
};

static const TypeInfo secondary_info = {
    .name          = "secondary-vga",
    .parent        = TYPE_PCI_VGA,
    .instance_init = pci_secondary_vga_init,
    .class_init    = secondary_class_init,
};

static void vga_register_types(void)
{
    type_register_static(&vga_pci_type_info);
    type_register_static(&vga_info);
    type_register_static(&secondary_info);
}

type_init(vga_register_types)
Commit	Line	Data
47d37dd9 JQ	1	/*
	2	* QEMU PCI VGA Emulator.
	3	*
cc228248 GH	4	* see docs/specs/standard-vga.txt for virtual hardware specs.
cc228248 GH	5	*
47d37dd9 JQ	6	* Copyright (c) 2003 Fabrice Bellard
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*/
83c9f4ca	26	#include "hw/hw.h"
28ecbaee	27	#include "ui/console.h"
83c9f4ca	28	#include "hw/pci/pci.h"
47b43a1f	29	#include "vga_int.h"
28ecbaee	30	#include "ui/pixel_ops.h"
1de7afc9	31	#include "qemu/timer.h"
83c9f4ca	32	#include "hw/loader.h"
47d37dd9	33
803ff052 GH	34	#define PCI_VGA_IOPORT_OFFSET 0x400
	35	#define PCI_VGA_IOPORT_SIZE (0x3e0 - 0x3c0)
	36	#define PCI_VGA_BOCHS_OFFSET 0x500
	37	#define PCI_VGA_BOCHS_SIZE (0x0b * 2)
b5682aa4 GH	38	#define PCI_VGA_QEXT_OFFSET 0x600
b5682aa4 GH	39	#define PCI_VGA_QEXT_SIZE (2 * 4)
803ff052 GH	40	#define PCI_VGA_MMIO_SIZE 0x1000
803ff052 GH	41
b5682aa4 GH	42	#define PCI_VGA_QEXT_REG_SIZE (0 * 4)
	43	#define PCI_VGA_QEXT_REG_BYTEORDER (1 * 4)
	44	#define PCI_VGA_QEXT_LITTLE_ENDIAN 0x1e1e1e1e
	45	#define PCI_VGA_QEXT_BIG_ENDIAN 0xbebebebe
	46
803ff052 GH	47	enum vga_pci_flags {
803ff052 GH	48	PCI_VGA_FLAG_ENABLE_MMIO = 1,
b5682aa4	49	PCI_VGA_FLAG_ENABLE_QEXT = 2,
803ff052 GH	50	};
803ff052 GH	51
47d37dd9 JQ	52	typedef struct PCIVGAState {
	53	PCIDevice dev;
	54	VGACommonState vga;
803ff052 GH	55	uint32_t flags;
803ff052 GH	56	MemoryRegion mmio;
220869e1	57	MemoryRegion mrs[3];
47d37dd9 JQ	58	} PCIVGAState;
47d37dd9 JQ	59
176c324f GA	60	#define TYPE_PCI_VGA "pci-vga"
	61	#define PCI_VGA(obj) OBJECT_CHECK(PCIVGAState, (obj), TYPE_PCI_VGA)
	62
a4f9631c JQ	63	static const VMStateDescription vmstate_vga_pci = {
	64	.name = "vga",
	65	.version_id = 2,
	66	.minimum_version_id = 2,
d49805ae	67	.fields = (VMStateField[]) {
a4f9631c JQ	68	VMSTATE_PCI_DEVICE(dev, PCIVGAState),
	69	VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState),
	70	VMSTATE_END_OF_LIST()
47d37dd9	71	}
a4f9631c	72	};
47d37dd9	73
a8170e5e	74	static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr,
803ff052 GH	75	unsigned size)
803ff052 GH	76	{
cf45ec6a	77	VGACommonState *s = ptr;
803ff052 GH	78	uint64_t ret = 0;
	79
	80	switch (size) {
	81	case 1:
cf45ec6a	82	ret = vga_ioport_read(s, addr + 0x3c0);
803ff052 GH	83	break;
803ff052 GH	84	case 2:
cf45ec6a GH	85	ret = vga_ioport_read(s, addr + 0x3c0);
cf45ec6a GH	86	ret \|= vga_ioport_read(s, addr + 0x3c1) << 8;
803ff052 GH	87	break;
	88	}
	89	return ret;
	90	}
	91
a8170e5e	92	static void pci_vga_ioport_write(void *ptr, hwaddr addr,
803ff052 GH	93	uint64_t val, unsigned size)
803ff052 GH	94	{
cf45ec6a	95	VGACommonState *s = ptr;
c96c53b5	96
803ff052 GH	97	switch (size) {
803ff052 GH	98	case 1:
cf45ec6a	99	vga_ioport_write(s, addr + 0x3c0, val);
803ff052 GH	100	break;
	101	case 2:
	102	/*
	103	* Update bytes in little endian order. Allows to update
	104	* indexed registers with a single word write because the
	105	* index byte is updated first.
	106	*/
cf45ec6a GH	107	vga_ioport_write(s, addr + 0x3c0, val & 0xff);
cf45ec6a GH	108	vga_ioport_write(s, addr + 0x3c1, (val >> 8) & 0xff);
803ff052 GH	109	break;
	110	}
	111	}
	112
	113	static const MemoryRegionOps pci_vga_ioport_ops = {
	114	.read = pci_vga_ioport_read,
	115	.write = pci_vga_ioport_write,
	116	.valid.min_access_size = 1,
	117	.valid.max_access_size = 4,
	118	.impl.min_access_size = 1,
	119	.impl.max_access_size = 2,
	120	.endianness = DEVICE_LITTLE_ENDIAN,
	121	};
	122
a8170e5e	123	static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr,
803ff052 GH	124	unsigned size)
803ff052 GH	125	{
cf45ec6a	126	VGACommonState *s = ptr;
803ff052 GH	127	int index = addr >> 1;
803ff052 GH	128
cf45ec6a GH	129	vbe_ioport_write_index(s, 0, index);
cf45ec6a GH	130	return vbe_ioport_read_data(s, 0);
803ff052 GH	131	}
803ff052 GH	132
a8170e5e	133	static void pci_vga_bochs_write(void *ptr, hwaddr addr,
803ff052 GH	134	uint64_t val, unsigned size)
803ff052 GH	135	{
cf45ec6a	136	VGACommonState *s = ptr;
803ff052 GH	137	int index = addr >> 1;
803ff052 GH	138
cf45ec6a GH	139	vbe_ioport_write_index(s, 0, index);
cf45ec6a GH	140	vbe_ioport_write_data(s, 0, val);
803ff052 GH	141	}
	142
	143	static const MemoryRegionOps pci_vga_bochs_ops = {
	144	.read = pci_vga_bochs_read,
	145	.write = pci_vga_bochs_write,
	146	.valid.min_access_size = 1,
	147	.valid.max_access_size = 4,
	148	.impl.min_access_size = 2,
	149	.impl.max_access_size = 2,
	150	.endianness = DEVICE_LITTLE_ENDIAN,
	151	};
	152
b5682aa4 GH	153	static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size)
b5682aa4 GH	154	{
cf45ec6a	155	VGACommonState *s = ptr;
b5682aa4 GH	156
	157	switch (addr) {
	158	case PCI_VGA_QEXT_REG_SIZE:
	159	return PCI_VGA_QEXT_SIZE;
	160	case PCI_VGA_QEXT_REG_BYTEORDER:
cf45ec6a	161	return s->big_endian_fb ?
b5682aa4 GH	162	PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN;
	163	default:
	164	return 0;
	165	}
	166	}
	167
	168	static void pci_vga_qext_write(void *ptr, hwaddr addr,
	169	uint64_t val, unsigned size)
	170	{
cf45ec6a	171	VGACommonState *s = ptr;
b5682aa4 GH	172
	173	switch (addr) {
	174	case PCI_VGA_QEXT_REG_BYTEORDER:
	175	if (val == PCI_VGA_QEXT_BIG_ENDIAN) {
cf45ec6a	176	s->big_endian_fb = true;
b5682aa4 GH	177	}
b5682aa4 GH	178	if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) {
cf45ec6a	179	s->big_endian_fb = false;
b5682aa4 GH	180	}
	181	break;
	182	}
	183	}
	184
3c2784fc DG	185	static bool vga_get_big_endian_fb(Object obj, Error *errp)
3c2784fc DG	186	{
176c324f	187	PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
3c2784fc DG	188
	189	return d->vga.big_endian_fb;
	190	}
	191
	192	static void vga_set_big_endian_fb(Object obj, bool value, Error *errp)
	193	{
176c324f	194	PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
3c2784fc DG	195
	196	d->vga.big_endian_fb = value;
	197	}
	198
b5682aa4 GH	199	static const MemoryRegionOps pci_vga_qext_ops = {
	200	.read = pci_vga_qext_read,
	201	.write = pci_vga_qext_write,
	202	.valid.min_access_size = 4,
	203	.valid.max_access_size = 4,
	204	.endianness = DEVICE_LITTLE_ENDIAN,
	205	};
	206
c5d4dac8 GH	207	void pci_std_vga_mmio_region_init(VGACommonState *s,
	208	MemoryRegion *parent,
	209	MemoryRegion *subs,
	210	bool qext)
220869e1 GH	211	{
	212	memory_region_init_io(&subs[0], NULL, &pci_vga_ioport_ops, s,
	213	"vga ioports remapped", PCI_VGA_IOPORT_SIZE);
	214	memory_region_add_subregion(parent, PCI_VGA_IOPORT_OFFSET,
	215	&subs[0]);
	216
	217	memory_region_init_io(&subs[1], NULL, &pci_vga_bochs_ops, s,
	218	"bochs dispi interface", PCI_VGA_BOCHS_SIZE);
	219	memory_region_add_subregion(parent, PCI_VGA_BOCHS_OFFSET,
	220	&subs[1]);
	221
	222	if (qext) {
	223	memory_region_init_io(&subs[2], NULL, &pci_vga_qext_ops, s,
	224	"qemu extended regs", PCI_VGA_QEXT_SIZE);
	225	memory_region_add_subregion(parent, PCI_VGA_QEXT_OFFSET,
	226	&subs[2]);
	227	}
	228	}
	229
9af21dbe	230	static void pci_std_vga_realize(PCIDevice dev, Error *errp)
47d37dd9	231	{
176c324f	232	PCIVGAState *d = PCI_VGA(dev);
0d0302e2	233	VGACommonState *s = &d->vga;
220869e1	234	bool qext = false;
47d37dd9	235
0d0302e2	236	/* vga + console init */
e2bbfc8e	237	vga_common_init(s, OBJECT(dev), true);
712f0cc7 PB	238	vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev),
712f0cc7 PB	239	true);
47d37dd9	240
5643706a	241	s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
47d37dd9	242
0d0302e2 GH	243	/* XXX: VGA_RAM_SIZE must be a power of two */
0d0302e2 GH	244	pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
47d37dd9	245
803ff052 GH	246	/* mmio bar for vga register access */
803ff052 GH	247	if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) {
2c9b15ca	248	memory_region_init(&d->mmio, NULL, "vga.mmio", 4096);
b5682aa4 GH	249
b5682aa4 GH	250	if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
220869e1	251	qext = true;
b5682aa4 GH	252	pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
b5682aa4 GH	253	}
220869e1	254	pci_std_vga_mmio_region_init(s, &d->mmio, d->mrs, qext);
b5682aa4	255
803ff052 GH	256	pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
	257	}
	258
0d0302e2 GH	259	if (!dev->rom_bar) {
0d0302e2 GH	260	/* compatibility with pc-0.13 and older */
83118327	261	vga_init_vbe(s, OBJECT(dev), pci_address_space(dev));
0d0302e2	262	}
47d37dd9 JQ	263	}
47d37dd9 JQ	264
3c2784fc DG	265	static void pci_std_vga_init(Object *obj)
	266	{
	267	/* Expose framebuffer byteorder via QOM */
	268	object_property_add_bool(obj, "big-endian-framebuffer",
	269	vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
	270	}
	271
9af21dbe	272	static void pci_secondary_vga_realize(PCIDevice dev, Error *errp)
63e3e24d	273	{
176c324f	274	PCIVGAState *d = PCI_VGA(dev);
63e3e24d	275	VGACommonState *s = &d->vga;
220869e1	276	bool qext = false;
63e3e24d GH	277
	278	/* vga + console init */
	279	vga_common_init(s, OBJECT(dev), false);
	280	s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
	281
	282	/* mmio bar */
	283	memory_region_init(&d->mmio, OBJECT(dev), "vga.mmio", 4096);
63e3e24d	284
b5682aa4	285	if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
220869e1	286	qext = true;
b5682aa4 GH	287	pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
b5682aa4 GH	288	}
220869e1	289	pci_std_vga_mmio_region_init(s, &d->mmio, d->mrs, qext);
b5682aa4	290
63e3e24d GH	291	pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
63e3e24d GH	292	pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
3c2784fc	293	}
63e3e24d	294
3c2784fc DG	295	static void pci_secondary_vga_init(Object *obj)
	296	{
	297	/* Expose framebuffer byteorder via QOM */
	298	object_property_add_bool(obj, "big-endian-framebuffer",
	299	vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
63e3e24d GH	300	}
	301
	302	static void pci_secondary_vga_reset(DeviceState *dev)
	303	{
176c324f	304	PCIVGAState *d = PCI_VGA(PCI_DEVICE(dev));
63e3e24d GH	305	vga_common_reset(&d->vga);
	306	}
	307
4a1e244e	308	static Property vga_pci_properties[] = {
9e56edcf	309	DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
803ff052	310	DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true),
b5682aa4 GH	311	DEFINE_PROP_BIT("qemu-extended-regs",
b5682aa4 GH	312	PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
4a1e244e GH	313	DEFINE_PROP_END_OF_LIST(),
	314	};
	315
63e3e24d GH	316	static Property secondary_pci_properties[] = {
63e3e24d GH	317	DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
b5682aa4 GH	318	DEFINE_PROP_BIT("qemu-extended-regs",
b5682aa4 GH	319	PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
63e3e24d GH	320	DEFINE_PROP_END_OF_LIST(),
	321	};
	322
176c324f GA	323	static void vga_pci_class_init(ObjectClass klass, void data)
	324	{
	325	DeviceClass *dc = DEVICE_CLASS(klass);
	326	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	327
	328	k->vendor_id = PCI_VENDOR_ID_QEMU;
	329	k->device_id = PCI_DEVICE_ID_QEMU_VGA;
	330	dc->vmsd = &vmstate_vga_pci;
	331	set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
	332	}
	333
	334	static const TypeInfo vga_pci_type_info = {
	335	.name = TYPE_PCI_VGA,
	336	.parent = TYPE_PCI_DEVICE,
	337	.instance_size = sizeof(PCIVGAState),
	338	.abstract = true,
	339	.class_init = vga_pci_class_init,
	340	};
	341
40021f08 AL	342	static void vga_class_init(ObjectClass klass, void data)
40021f08 AL	343	{
39bffca2	344	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	345	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
40021f08 AL	346
9af21dbe	347	k->realize = pci_std_vga_realize;
40021f08	348	k->romfile = "vgabios-stdvga.bin";
40021f08	349	k->class_id = PCI_CLASS_DISPLAY_VGA;
4a1e244e	350	dc->props = vga_pci_properties;
2897ae02	351	dc->hotpluggable = false;
40021f08	352	}
32902772	353
63e3e24d GH	354	static void secondary_class_init(ObjectClass klass, void data)
	355	{
	356	DeviceClass *dc = DEVICE_CLASS(klass);
	357	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	358
9af21dbe	359	k->realize = pci_secondary_vga_realize;
63e3e24d	360	k->class_id = PCI_CLASS_DISPLAY_OTHER;
63e3e24d GH	361	dc->props = secondary_pci_properties;
	362	dc->reset = pci_secondary_vga_reset;
	363	}
	364
8c43a6f0	365	static const TypeInfo vga_info = {
39bffca2	366	.name = "VGA",
176c324f	367	.parent = TYPE_PCI_VGA,
3c2784fc	368	.instance_init = pci_std_vga_init,
39bffca2	369	.class_init = vga_class_init,
47d37dd9 JQ	370	};
47d37dd9 JQ	371
63e3e24d GH	372	static const TypeInfo secondary_info = {
63e3e24d GH	373	.name = "secondary-vga",
176c324f	374	.parent = TYPE_PCI_VGA,
3c2784fc	375	.instance_init = pci_secondary_vga_init,
63e3e24d GH	376	.class_init = secondary_class_init,
	377	};
	378
83f7d43a	379	static void vga_register_types(void)
47d37dd9	380	{
176c324f	381	type_register_static(&vga_pci_type_info);
39bffca2	382	type_register_static(&vga_info);
63e3e24d	383	type_register_static(&secondary_info);
47d37dd9	384	}
83f7d43a AF	385
83f7d43a AF	386	type_init(vga_register_types)