[mirror_qemu.git] / hw / display / vga_int.h

/*
 * QEMU internal VGA defines.
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#ifndef HW_VGA_INT_H
#define HW_VGA_INT_H 1

#include <hw/hw.h>
#include "qapi/error.h"
#include "exec/memory.h"

#define ST01_V_RETRACE      0x08
#define ST01_DISP_ENABLE    0x01

#define VBE_DISPI_MAX_XRES              16000
#define VBE_DISPI_MAX_YRES              12000
#define VBE_DISPI_MAX_BPP               32

#define VBE_DISPI_INDEX_ID              0x0
#define VBE_DISPI_INDEX_XRES            0x1
#define VBE_DISPI_INDEX_YRES            0x2
#define VBE_DISPI_INDEX_BPP             0x3
#define VBE_DISPI_INDEX_ENABLE          0x4
#define VBE_DISPI_INDEX_BANK            0x5
#define VBE_DISPI_INDEX_VIRT_WIDTH      0x6
#define VBE_DISPI_INDEX_VIRT_HEIGHT     0x7
#define VBE_DISPI_INDEX_X_OFFSET        0x8
#define VBE_DISPI_INDEX_Y_OFFSET        0x9
#define VBE_DISPI_INDEX_NB              0xa /* size of vbe_regs[] */
#define VBE_DISPI_INDEX_VIDEO_MEMORY_64K 0xa /* read-only, not in vbe_regs */

#define VBE_DISPI_ID0                   0xB0C0
#define VBE_DISPI_ID1                   0xB0C1
#define VBE_DISPI_ID2                   0xB0C2
#define VBE_DISPI_ID3                   0xB0C3
#define VBE_DISPI_ID4                   0xB0C4
#define VBE_DISPI_ID5                   0xB0C5

#define VBE_DISPI_DISABLED              0x00
#define VBE_DISPI_ENABLED               0x01
#define VBE_DISPI_GETCAPS               0x02
#define VBE_DISPI_8BIT_DAC              0x20
#define VBE_DISPI_LFB_ENABLED           0x40
#define VBE_DISPI_NOCLEARMEM            0x80

#define VBE_DISPI_LFB_PHYSICAL_ADDRESS  0xE0000000

#define CH_ATTR_SIZE (160 * 100)
#define VGA_MAX_HEIGHT 2048

struct vga_precise_retrace {
    int64_t ticks_per_char;
    int64_t total_chars;
    int htotal;
    int hstart;
    int hend;
    int vstart;
    int vend;
    int freq;
};

union vga_retrace {
    struct vga_precise_retrace precise;
};

struct VGACommonState;
typedef uint8_t (* vga_retrace_fn)(struct VGACommonState *s);
typedef void (* vga_update_retrace_info_fn)(struct VGACommonState *s);

typedef struct VGACommonState {
    MemoryRegion *legacy_address_space;
    uint8_t *vram_ptr;
    MemoryRegion vram;
    MemoryRegion vram_vbe;
    uint32_t vram_size;
    uint32_t vram_size_mb; /* property */
    uint32_t latch;
    bool has_chain4_alias;
    MemoryRegion chain4_alias;
    uint8_t sr_index;
    uint8_t sr[256];
    uint8_t gr_index;
    uint8_t gr[256];
    uint8_t ar_index;
    uint8_t ar[21];
    int ar_flip_flop;
    uint8_t cr_index;
    uint8_t cr[256]; /* CRT registers */
    uint8_t msr; /* Misc Output Register */
    uint8_t fcr; /* Feature Control Register */
    uint8_t st00; /* status 0 */
    uint8_t st01; /* status 1 */
    uint8_t dac_state;
    uint8_t dac_sub_index;
    uint8_t dac_read_index;
    uint8_t dac_write_index;
    uint8_t dac_cache[3]; /* used when writing */
    int dac_8bit;
    uint8_t palette[768];
    int32_t bank_offset;
    int (*get_bpp)(struct VGACommonState *s);
    void (*get_offsets)(struct VGACommonState *s,
                        uint32_t *pline_offset,
                        uint32_t *pstart_addr,
                        uint32_t *pline_compare);
    void (*get_resolution)(struct VGACommonState *s,
                        int *pwidth,
                        int *pheight);
    PortioList vga_port_list;
    PortioList vbe_port_list;
    /* bochs vbe state */
    uint16_t vbe_index;
    uint16_t vbe_regs[VBE_DISPI_INDEX_NB];
    uint32_t vbe_start_addr;
    uint32_t vbe_line_offset;
    uint32_t vbe_bank_mask;
    int vbe_mapped;
    /* display refresh support */
    QemuConsole *con;
    uint32_t font_offsets[2];
    int graphic_mode;
    uint8_t shift_control;
    uint8_t double_scan;
    uint32_t line_offset;
    uint32_t line_compare;
    uint32_t start_addr;
    uint32_t plane_updated;
    uint32_t last_line_offset;
    uint8_t last_cw, last_ch;
    uint32_t last_width, last_height; /* in chars or pixels */
    uint32_t last_scr_width, last_scr_height; /* in pixels */
    uint32_t last_depth; /* in bits */
    uint8_t cursor_start, cursor_end;
    bool cursor_visible_phase;
    int64_t cursor_blink_time;
    uint32_t cursor_offset;
    unsigned int (*rgb_to_pixel)(unsigned int r,
                                 unsigned int g, unsigned b);
    const GraphicHwOps *hw_ops;
    bool full_update_text;
    bool full_update_gfx;
    /* hardware mouse cursor support */
    uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32];
    void (*cursor_invalidate)(struct VGACommonState *s);
    void (*cursor_draw_line)(struct VGACommonState *s, uint8_t *d, int y);
    /* tell for each page if it has been updated since the last time */
    uint32_t last_palette[256];
    uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
    /* retrace */
    vga_retrace_fn retrace;
    vga_update_retrace_info_fn update_retrace_info;
    union vga_retrace retrace_info;
    uint8_t is_vbe_vmstate;
} VGACommonState;

static inline int c6_to_8(int v)
{
    int b;
    v &= 0x3f;
    b = v & 1;
    return (v << 2) | (b << 1) | b;
}

void vga_common_init(VGACommonState *s, Object *obj, bool global_vmstate);
void vga_init(VGACommonState *s, Object *obj, MemoryRegion *address_space,
              MemoryRegion *address_space_io, bool init_vga_ports);
MemoryRegion *vga_init_io(VGACommonState *s, Object *obj,
                          const MemoryRegionPortio **vga_ports,
                          const MemoryRegionPortio **vbe_ports);
void vga_common_reset(VGACommonState *s);

void vga_sync_dirty_bitmap(VGACommonState *s);
void vga_dirty_log_start(VGACommonState *s);
void vga_dirty_log_stop(VGACommonState *s);

extern const VMStateDescription vmstate_vga_common;
uint32_t vga_ioport_read(void *opaque, uint32_t addr);
void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val);
uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr);
void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val);
void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2);

int vga_ioport_invalid(VGACommonState *s, uint32_t addr);

void vga_init_vbe(VGACommonState *s, Object *obj, MemoryRegion *address_space);
uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr);
void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val);
void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val);

extern const uint8_t sr_mask[8];
extern const uint8_t gr_mask[16];

#define VGABIOS_FILENAME "vgabios.bin"
#define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"

extern const MemoryRegionOps vga_mem_ops;

#endif
Commit	Line	Data
798b0c25 FB	1	/*
798b0c25 FB	2	* QEMU internal VGA defines.
5fafdf24	3	*
798b0c25	4	* Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24	5	*
798b0c25 FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
cb9c377f PB	24	#ifndef HW_VGA_INT_H
cb9c377f PB	25	#define HW_VGA_INT_H 1
11b6b345 JQ	26
11b6b345 JQ	27	#include <hw/hw.h>
7b1b5d19	28	#include "qapi/error.h"
022c62cb	29	#include "exec/memory.h"
11b6b345	30
798b0c25 FB	31	#define ST01_V_RETRACE 0x08
	32	#define ST01_DISP_ENABLE 0x01
	33
e9c6149f GH	34	#define VBE_DISPI_MAX_XRES 16000
e9c6149f GH	35	#define VBE_DISPI_MAX_YRES 12000
8454df8b	36	#define VBE_DISPI_MAX_BPP 32
798b0c25 FB	37
	38	#define VBE_DISPI_INDEX_ID 0x0
	39	#define VBE_DISPI_INDEX_XRES 0x1
	40	#define VBE_DISPI_INDEX_YRES 0x2
	41	#define VBE_DISPI_INDEX_BPP 0x3
	42	#define VBE_DISPI_INDEX_ENABLE 0x4
	43	#define VBE_DISPI_INDEX_BANK 0x5
	44	#define VBE_DISPI_INDEX_VIRT_WIDTH 0x6
	45	#define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7
	46	#define VBE_DISPI_INDEX_X_OFFSET 0x8
	47	#define VBE_DISPI_INDEX_Y_OFFSET 0x9
af92284b GH	48	#define VBE_DISPI_INDEX_NB 0xa /* size of vbe_regs[] */
af92284b GH	49	#define VBE_DISPI_INDEX_VIDEO_MEMORY_64K 0xa /* read-only, not in vbe_regs */
3b46e624	50
798b0c25 FB	51	#define VBE_DISPI_ID0 0xB0C0
	52	#define VBE_DISPI_ID1 0xB0C1
	53	#define VBE_DISPI_ID2 0xB0C2
37dd208d FB	54	#define VBE_DISPI_ID3 0xB0C3
37dd208d FB	55	#define VBE_DISPI_ID4 0xB0C4
af92284b	56	#define VBE_DISPI_ID5 0xB0C5
3b46e624	57
798b0c25 FB	58	#define VBE_DISPI_DISABLED 0x00
798b0c25 FB	59	#define VBE_DISPI_ENABLED 0x01
8454df8b FB	60	#define VBE_DISPI_GETCAPS 0x02
8454df8b FB	61	#define VBE_DISPI_8BIT_DAC 0x20
798b0c25 FB	62	#define VBE_DISPI_LFB_ENABLED 0x40
798b0c25 FB	63	#define VBE_DISPI_NOCLEARMEM 0x80
3b46e624	64
798b0c25 FB	65	#define VBE_DISPI_LFB_PHYSICAL_ADDRESS 0xE0000000
798b0c25 FB	66
798b0c25	67	#define CH_ATTR_SIZE (160 * 100)
8454df8b	68	#define VGA_MAX_HEIGHT 2048
4e3e9d0b	69
cb5a7aa8	70	struct vga_precise_retrace {
	71	int64_t ticks_per_char;
	72	int64_t total_chars;
	73	int htotal;
	74	int hstart;
	75	int hend;
	76	int vstart;
	77	int vend;
	78	int freq;
	79	};
	80
	81	union vga_retrace {
	82	struct vga_precise_retrace precise;
	83	};
	84
4e12cd94 AK	85	struct VGACommonState;
	86	typedef uint8_t (* vga_retrace_fn)(struct VGACommonState *s);
	87	typedef void (* vga_update_retrace_info_fn)(struct VGACommonState *s);
	88
	89	typedef struct VGACommonState {
80763888	90	MemoryRegion *legacy_address_space;
4e12cd94	91	uint8_t *vram_ptr;
b1950430	92	MemoryRegion vram;
8294a64d	93	MemoryRegion vram_vbe;
a19cbfb3	94	uint32_t vram_size;
4a1e244e	95	uint32_t vram_size_mb; /* property */
4e12cd94	96	uint32_t latch;
ad37168c PB	97	bool has_chain4_alias;
ad37168c PB	98	MemoryRegion chain4_alias;
4e12cd94 AK	99	uint8_t sr_index;
	100	uint8_t sr[256];
	101	uint8_t gr_index;
	102	uint8_t gr[256];
	103	uint8_t ar_index;
	104	uint8_t ar[21];
	105	int ar_flip_flop;
	106	uint8_t cr_index;
	107	uint8_t cr[256]; /* CRT registers */
	108	uint8_t msr; /* Misc Output Register */
	109	uint8_t fcr; /* Feature Control Register */
	110	uint8_t st00; /* status 0 */
	111	uint8_t st01; /* status 1 */
	112	uint8_t dac_state;
	113	uint8_t dac_sub_index;
	114	uint8_t dac_read_index;
	115	uint8_t dac_write_index;
	116	uint8_t dac_cache[3]; /* used when writing */
	117	int dac_8bit;
	118	uint8_t palette[768];
	119	int32_t bank_offset;
4e12cd94 AK	120	int (get_bpp)(struct VGACommonState s);
	121	void (get_offsets)(struct VGACommonState s,
	122	uint32_t *pline_offset,
	123	uint32_t *pstart_addr,
	124	uint32_t *pline_compare);
	125	void (get_resolution)(struct VGACommonState s,
	126	int *pwidth,
	127	int *pheight);
848696bf KB	128	PortioList vga_port_list;
848696bf KB	129	PortioList vbe_port_list;
a96d8bea GH	130	/* bochs vbe state */
	131	uint16_t vbe_index;
	132	uint16_t vbe_regs[VBE_DISPI_INDEX_NB];
	133	uint32_t vbe_start_addr;
	134	uint32_t vbe_line_offset;
	135	uint32_t vbe_bank_mask;
	136	int vbe_mapped;
4e12cd94	137	/* display refresh support */
c78f7137	138	QemuConsole *con;
4e12cd94 AK	139	uint32_t font_offsets[2];
	140	int graphic_mode;
	141	uint8_t shift_control;
	142	uint8_t double_scan;
	143	uint32_t line_offset;
	144	uint32_t line_compare;
	145	uint32_t start_addr;
	146	uint32_t plane_updated;
	147	uint32_t last_line_offset;
	148	uint8_t last_cw, last_ch;
	149	uint32_t last_width, last_height; /* in chars or pixels */
	150	uint32_t last_scr_width, last_scr_height; /* in pixels */
	151	uint32_t last_depth; /* in bits */
	152	uint8_t cursor_start, cursor_end;
9aa0ff0b JK	153	bool cursor_visible_phase;
9aa0ff0b JK	154	int64_t cursor_blink_time;
4e12cd94 AK	155	uint32_t cursor_offset;
	156	unsigned int (*rgb_to_pixel)(unsigned int r,
	157	unsigned int g, unsigned b);
380cd056	158	const GraphicHwOps *hw_ops;
9678aedd GH	159	bool full_update_text;
9678aedd GH	160	bool full_update_gfx;
4e12cd94 AK	161	/* hardware mouse cursor support */
	162	uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32];
	163	void (cursor_invalidate)(struct VGACommonState s);
	164	void (cursor_draw_line)(struct VGACommonState s, uint8_t *d, int y);
	165	/* tell for each page if it has been updated since the last time */
	166	uint32_t last_palette[256];
	167	uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
	168	/* retrace */
	169	vga_retrace_fn retrace;
	170	vga_update_retrace_info_fn update_retrace_info;
cb5a7aa8	171	union vga_retrace retrace_info;
2a3138ab	172	uint8_t is_vbe_vmstate;
4e12cd94	173	} VGACommonState;
4e3e9d0b	174
a8aa669b FB	175	static inline int c6_to_8(int v)
	176	{
	177	int b;
	178	v &= 0x3f;
	179	b = v & 1;
	180	return (v << 2) \| (b << 1) \| b;
	181	}
	182
e2bbfc8e	183	void vga_common_init(VGACommonState s, Object obj, bool global_vmstate);
712f0cc7	184	void vga_init(VGACommonState s, Object obj, MemoryRegion *address_space,
0a039dc7	185	MemoryRegion *address_space_io, bool init_vga_ports);
c84b28ee	186	MemoryRegion vga_init_io(VGACommonState s, Object *obj,
0a039dc7 RH	187	const MemoryRegionPortio **vga_ports,
0a039dc7 RH	188	const MemoryRegionPortio **vbe_ports);
03a3e7ba	189	void vga_common_reset(VGACommonState *s);
2bec46dc	190
b51d7b2e	191	void vga_sync_dirty_bitmap(VGACommonState *s);
a4a2f59c	192	void vga_dirty_log_start(VGACommonState *s);
b5cc6e32	193	void vga_dirty_log_stop(VGACommonState *s);
2bec46dc	194
11b6b345	195	extern const VMStateDescription vmstate_vga_common;
43bf782b JQ	196	uint32_t vga_ioport_read(void *opaque, uint32_t addr);
43bf782b JQ	197	void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val);
a8170e5e AK	198	uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr);
a8170e5e AK	199	void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val);
a4a2f59c	200	void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2);
a8aa669b	201
25a18cbd	202	int vga_ioport_invalid(VGACommonState *s, uint32_t addr);
803ff052	203
83118327	204	void vga_init_vbe(VGACommonState s, Object obj, MemoryRegion *address_space);
803ff052 GH	205	uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr);
	206	void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val);
	207	void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val);
25a18cbd	208
798b0c25 FB	209	extern const uint8_t sr_mask[8];
798b0c25 FB	210	extern const uint8_t gr_mask[16];
fbe1b595	211
5245d57a GH	212	#define VGABIOS_FILENAME "vgabios.bin"
5245d57a GH	213	#define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"
fbe1b595	214
b1950430	215	extern const MemoryRegionOps vga_mem_ops;
cb9c377f PB	216
cb9c377f PB	217	#endif