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9d9e1521 GH |
1 | /* |
2 | * Virtio GPU Device | |
3 | * | |
4 | * Copyright Red Hat, Inc. 2013-2014 | |
5 | * | |
6 | * Authors: | |
7 | * Dave Airlie <airlied@redhat.com> | |
8 | * Gerd Hoffmann <kraxel@redhat.com> | |
9 | * | |
10 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
11 | * See the COPYING file in the top-level directory. | |
12 | */ | |
13 | ||
9b8bfe21 | 14 | #include "qemu/osdep.h" |
9d9e1521 GH |
15 | #include "qemu-common.h" |
16 | #include "qemu/iov.h" | |
17 | #include "trace.h" | |
18 | #include "hw/virtio/virtio.h" | |
19 | #include "hw/virtio/virtio-gpu.h" | |
20 | ||
21 | #ifdef CONFIG_VIRGL | |
22 | ||
23 | #include "virglrenderer.h" | |
24 | ||
25 | static struct virgl_renderer_callbacks virtio_gpu_3d_cbs; | |
26 | ||
27 | static void virgl_cmd_create_resource_2d(VirtIOGPU *g, | |
28 | struct virtio_gpu_ctrl_command *cmd) | |
29 | { | |
30 | struct virtio_gpu_resource_create_2d c2d; | |
31 | struct virgl_renderer_resource_create_args args; | |
32 | ||
33 | VIRTIO_GPU_FILL_CMD(c2d); | |
34 | trace_virtio_gpu_cmd_res_create_2d(c2d.resource_id, c2d.format, | |
35 | c2d.width, c2d.height); | |
36 | ||
37 | args.handle = c2d.resource_id; | |
38 | args.target = 2; | |
39 | args.format = c2d.format; | |
40 | args.bind = (1 << 1); | |
41 | args.width = c2d.width; | |
42 | args.height = c2d.height; | |
43 | args.depth = 1; | |
44 | args.array_size = 1; | |
45 | args.last_level = 0; | |
46 | args.nr_samples = 0; | |
47 | args.flags = VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP; | |
48 | virgl_renderer_resource_create(&args, NULL, 0); | |
49 | } | |
50 | ||
51 | static void virgl_cmd_create_resource_3d(VirtIOGPU *g, | |
52 | struct virtio_gpu_ctrl_command *cmd) | |
53 | { | |
54 | struct virtio_gpu_resource_create_3d c3d; | |
55 | struct virgl_renderer_resource_create_args args; | |
56 | ||
57 | VIRTIO_GPU_FILL_CMD(c3d); | |
58 | trace_virtio_gpu_cmd_res_create_3d(c3d.resource_id, c3d.format, | |
59 | c3d.width, c3d.height, c3d.depth); | |
60 | ||
61 | args.handle = c3d.resource_id; | |
62 | args.target = c3d.target; | |
63 | args.format = c3d.format; | |
64 | args.bind = c3d.bind; | |
65 | args.width = c3d.width; | |
66 | args.height = c3d.height; | |
67 | args.depth = c3d.depth; | |
68 | args.array_size = c3d.array_size; | |
69 | args.last_level = c3d.last_level; | |
70 | args.nr_samples = c3d.nr_samples; | |
71 | args.flags = c3d.flags; | |
72 | virgl_renderer_resource_create(&args, NULL, 0); | |
73 | } | |
74 | ||
75 | static void virgl_cmd_resource_unref(VirtIOGPU *g, | |
76 | struct virtio_gpu_ctrl_command *cmd) | |
77 | { | |
78 | struct virtio_gpu_resource_unref unref; | |
79 | ||
80 | VIRTIO_GPU_FILL_CMD(unref); | |
81 | trace_virtio_gpu_cmd_res_unref(unref.resource_id); | |
82 | ||
83 | virgl_renderer_resource_unref(unref.resource_id); | |
84 | } | |
85 | ||
86 | static void virgl_cmd_context_create(VirtIOGPU *g, | |
87 | struct virtio_gpu_ctrl_command *cmd) | |
88 | { | |
89 | struct virtio_gpu_ctx_create cc; | |
90 | ||
91 | VIRTIO_GPU_FILL_CMD(cc); | |
92 | trace_virtio_gpu_cmd_ctx_create(cc.hdr.ctx_id, | |
93 | cc.debug_name); | |
94 | ||
95 | virgl_renderer_context_create(cc.hdr.ctx_id, cc.nlen, | |
96 | cc.debug_name); | |
97 | } | |
98 | ||
99 | static void virgl_cmd_context_destroy(VirtIOGPU *g, | |
100 | struct virtio_gpu_ctrl_command *cmd) | |
101 | { | |
102 | struct virtio_gpu_ctx_destroy cd; | |
103 | ||
104 | VIRTIO_GPU_FILL_CMD(cd); | |
105 | trace_virtio_gpu_cmd_ctx_destroy(cd.hdr.ctx_id); | |
106 | ||
107 | virgl_renderer_context_destroy(cd.hdr.ctx_id); | |
108 | } | |
109 | ||
110 | static void virtio_gpu_rect_update(VirtIOGPU *g, int idx, int x, int y, | |
111 | int width, int height) | |
112 | { | |
113 | if (!g->scanout[idx].con) { | |
114 | return; | |
115 | } | |
116 | ||
117 | dpy_gl_update(g->scanout[idx].con, x, y, width, height); | |
118 | } | |
119 | ||
120 | static void virgl_cmd_resource_flush(VirtIOGPU *g, | |
121 | struct virtio_gpu_ctrl_command *cmd) | |
122 | { | |
123 | struct virtio_gpu_resource_flush rf; | |
124 | int i; | |
125 | ||
126 | VIRTIO_GPU_FILL_CMD(rf); | |
127 | trace_virtio_gpu_cmd_res_flush(rf.resource_id, | |
128 | rf.r.width, rf.r.height, rf.r.x, rf.r.y); | |
129 | ||
130 | for (i = 0; i < VIRTIO_GPU_MAX_SCANOUT; i++) { | |
131 | if (g->scanout[i].resource_id != rf.resource_id) { | |
132 | continue; | |
133 | } | |
134 | virtio_gpu_rect_update(g, i, rf.r.x, rf.r.y, rf.r.width, rf.r.height); | |
135 | } | |
136 | } | |
137 | ||
138 | static void virgl_cmd_set_scanout(VirtIOGPU *g, | |
139 | struct virtio_gpu_ctrl_command *cmd) | |
140 | { | |
141 | struct virtio_gpu_set_scanout ss; | |
142 | struct virgl_renderer_resource_info info; | |
143 | int ret; | |
144 | ||
145 | VIRTIO_GPU_FILL_CMD(ss); | |
146 | trace_virtio_gpu_cmd_set_scanout(ss.scanout_id, ss.resource_id, | |
147 | ss.r.width, ss.r.height, ss.r.x, ss.r.y); | |
148 | ||
149 | if (ss.scanout_id >= VIRTIO_GPU_MAX_SCANOUT) { | |
150 | qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal scanout id specified %d", | |
151 | __func__, ss.scanout_id); | |
152 | cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID; | |
153 | return; | |
154 | } | |
155 | g->enable = 1; | |
156 | ||
157 | memset(&info, 0, sizeof(info)); | |
158 | ||
159 | if (ss.resource_id && ss.r.width && ss.r.height) { | |
160 | ret = virgl_renderer_resource_get_info(ss.resource_id, &info); | |
161 | if (ret == -1) { | |
162 | qemu_log_mask(LOG_GUEST_ERROR, | |
163 | "%s: illegal resource specified %d\n", | |
164 | __func__, ss.resource_id); | |
165 | cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; | |
166 | return; | |
167 | } | |
168 | qemu_console_resize(g->scanout[ss.scanout_id].con, | |
169 | ss.r.width, ss.r.height); | |
170 | virgl_renderer_force_ctx_0(); | |
171 | dpy_gl_scanout(g->scanout[ss.scanout_id].con, info.tex_id, | |
172 | info.flags & 1 /* FIXME: Y_0_TOP */, | |
173 | ss.r.x, ss.r.y, ss.r.width, ss.r.height); | |
174 | } else { | |
175 | if (ss.scanout_id != 0) { | |
176 | dpy_gfx_replace_surface(g->scanout[ss.scanout_id].con, NULL); | |
177 | } | |
178 | dpy_gl_scanout(g->scanout[ss.scanout_id].con, 0, false, | |
179 | 0, 0, 0, 0); | |
180 | } | |
181 | g->scanout[ss.scanout_id].resource_id = ss.resource_id; | |
182 | } | |
183 | ||
184 | static void virgl_cmd_submit_3d(VirtIOGPU *g, | |
185 | struct virtio_gpu_ctrl_command *cmd) | |
186 | { | |
187 | struct virtio_gpu_cmd_submit cs; | |
188 | void *buf; | |
189 | size_t s; | |
190 | ||
191 | VIRTIO_GPU_FILL_CMD(cs); | |
192 | trace_virtio_gpu_cmd_ctx_submit(cs.hdr.ctx_id, cs.size); | |
193 | ||
194 | buf = g_malloc(cs.size); | |
195 | s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num, | |
196 | sizeof(cs), buf, cs.size); | |
197 | if (s != cs.size) { | |
198 | qemu_log_mask(LOG_GUEST_ERROR, "%s: size mismatch (%zd/%d)", | |
199 | __func__, s, cs.size); | |
200 | cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER; | |
201 | return; | |
202 | } | |
203 | ||
204 | if (virtio_gpu_stats_enabled(g->conf)) { | |
205 | g->stats.req_3d++; | |
206 | g->stats.bytes_3d += cs.size; | |
207 | } | |
208 | ||
209 | virgl_renderer_submit_cmd(buf, cs.hdr.ctx_id, cs.size / 4); | |
210 | ||
211 | g_free(buf); | |
212 | } | |
213 | ||
214 | static void virgl_cmd_transfer_to_host_2d(VirtIOGPU *g, | |
215 | struct virtio_gpu_ctrl_command *cmd) | |
216 | { | |
217 | struct virtio_gpu_transfer_to_host_2d t2d; | |
218 | struct virtio_gpu_box box; | |
219 | ||
220 | VIRTIO_GPU_FILL_CMD(t2d); | |
221 | trace_virtio_gpu_cmd_res_xfer_toh_2d(t2d.resource_id); | |
222 | ||
223 | box.x = t2d.r.x; | |
224 | box.y = t2d.r.y; | |
225 | box.z = 0; | |
226 | box.w = t2d.r.width; | |
227 | box.h = t2d.r.height; | |
228 | box.d = 1; | |
229 | ||
230 | virgl_renderer_transfer_write_iov(t2d.resource_id, | |
231 | 0, | |
232 | 0, | |
233 | 0, | |
234 | 0, | |
235 | (struct virgl_box *)&box, | |
236 | t2d.offset, NULL, 0); | |
237 | } | |
238 | ||
239 | static void virgl_cmd_transfer_to_host_3d(VirtIOGPU *g, | |
240 | struct virtio_gpu_ctrl_command *cmd) | |
241 | { | |
242 | struct virtio_gpu_transfer_host_3d t3d; | |
243 | ||
244 | VIRTIO_GPU_FILL_CMD(t3d); | |
245 | trace_virtio_gpu_cmd_res_xfer_toh_3d(t3d.resource_id); | |
246 | ||
247 | virgl_renderer_transfer_write_iov(t3d.resource_id, | |
248 | t3d.hdr.ctx_id, | |
249 | t3d.level, | |
250 | t3d.stride, | |
251 | t3d.layer_stride, | |
252 | (struct virgl_box *)&t3d.box, | |
253 | t3d.offset, NULL, 0); | |
254 | } | |
255 | ||
256 | static void | |
257 | virgl_cmd_transfer_from_host_3d(VirtIOGPU *g, | |
258 | struct virtio_gpu_ctrl_command *cmd) | |
259 | { | |
260 | struct virtio_gpu_transfer_host_3d tf3d; | |
261 | ||
262 | VIRTIO_GPU_FILL_CMD(tf3d); | |
263 | trace_virtio_gpu_cmd_res_xfer_fromh_3d(tf3d.resource_id); | |
264 | ||
265 | virgl_renderer_transfer_read_iov(tf3d.resource_id, | |
266 | tf3d.hdr.ctx_id, | |
267 | tf3d.level, | |
268 | tf3d.stride, | |
269 | tf3d.layer_stride, | |
270 | (struct virgl_box *)&tf3d.box, | |
271 | tf3d.offset, NULL, 0); | |
272 | } | |
273 | ||
274 | ||
275 | static void virgl_resource_attach_backing(VirtIOGPU *g, | |
276 | struct virtio_gpu_ctrl_command *cmd) | |
277 | { | |
278 | struct virtio_gpu_resource_attach_backing att_rb; | |
279 | struct iovec *res_iovs; | |
280 | int ret; | |
281 | ||
282 | VIRTIO_GPU_FILL_CMD(att_rb); | |
283 | trace_virtio_gpu_cmd_res_back_attach(att_rb.resource_id); | |
284 | ||
285 | ret = virtio_gpu_create_mapping_iov(&att_rb, cmd, &res_iovs); | |
286 | if (ret != 0) { | |
287 | cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC; | |
288 | return; | |
289 | } | |
290 | ||
291 | virgl_renderer_resource_attach_iov(att_rb.resource_id, | |
292 | res_iovs, att_rb.nr_entries); | |
293 | } | |
294 | ||
295 | static void virgl_resource_detach_backing(VirtIOGPU *g, | |
296 | struct virtio_gpu_ctrl_command *cmd) | |
297 | { | |
298 | struct virtio_gpu_resource_detach_backing detach_rb; | |
299 | struct iovec *res_iovs = NULL; | |
300 | int num_iovs = 0; | |
301 | ||
302 | VIRTIO_GPU_FILL_CMD(detach_rb); | |
303 | trace_virtio_gpu_cmd_res_back_detach(detach_rb.resource_id); | |
304 | ||
305 | virgl_renderer_resource_detach_iov(detach_rb.resource_id, | |
306 | &res_iovs, | |
307 | &num_iovs); | |
308 | if (res_iovs == NULL || num_iovs == 0) { | |
309 | return; | |
310 | } | |
311 | virtio_gpu_cleanup_mapping_iov(res_iovs, num_iovs); | |
312 | } | |
313 | ||
314 | ||
315 | static void virgl_cmd_ctx_attach_resource(VirtIOGPU *g, | |
316 | struct virtio_gpu_ctrl_command *cmd) | |
317 | { | |
318 | struct virtio_gpu_ctx_resource att_res; | |
319 | ||
320 | VIRTIO_GPU_FILL_CMD(att_res); | |
321 | trace_virtio_gpu_cmd_ctx_res_attach(att_res.hdr.ctx_id, | |
322 | att_res.resource_id); | |
323 | ||
324 | virgl_renderer_ctx_attach_resource(att_res.hdr.ctx_id, att_res.resource_id); | |
325 | } | |
326 | ||
327 | static void virgl_cmd_ctx_detach_resource(VirtIOGPU *g, | |
328 | struct virtio_gpu_ctrl_command *cmd) | |
329 | { | |
330 | struct virtio_gpu_ctx_resource det_res; | |
331 | ||
332 | VIRTIO_GPU_FILL_CMD(det_res); | |
333 | trace_virtio_gpu_cmd_ctx_res_detach(det_res.hdr.ctx_id, | |
334 | det_res.resource_id); | |
335 | ||
336 | virgl_renderer_ctx_detach_resource(det_res.hdr.ctx_id, det_res.resource_id); | |
337 | } | |
338 | ||
339 | static void virgl_cmd_get_capset_info(VirtIOGPU *g, | |
340 | struct virtio_gpu_ctrl_command *cmd) | |
341 | { | |
342 | struct virtio_gpu_get_capset_info info; | |
343 | struct virtio_gpu_resp_capset_info resp; | |
344 | ||
345 | VIRTIO_GPU_FILL_CMD(info); | |
346 | ||
347 | if (info.capset_index == 0) { | |
348 | resp.capset_id = VIRTIO_GPU_CAPSET_VIRGL; | |
349 | virgl_renderer_get_cap_set(resp.capset_id, | |
350 | &resp.capset_max_version, | |
351 | &resp.capset_max_size); | |
352 | } else { | |
353 | resp.capset_max_version = 0; | |
354 | resp.capset_max_size = 0; | |
355 | } | |
356 | resp.hdr.type = VIRTIO_GPU_RESP_OK_CAPSET_INFO; | |
357 | virtio_gpu_ctrl_response(g, cmd, &resp.hdr, sizeof(resp)); | |
358 | } | |
359 | ||
360 | static void virgl_cmd_get_capset(VirtIOGPU *g, | |
361 | struct virtio_gpu_ctrl_command *cmd) | |
362 | { | |
363 | struct virtio_gpu_get_capset gc; | |
364 | struct virtio_gpu_resp_capset *resp; | |
365 | uint32_t max_ver, max_size; | |
366 | VIRTIO_GPU_FILL_CMD(gc); | |
367 | ||
368 | virgl_renderer_get_cap_set(gc.capset_id, &max_ver, | |
369 | &max_size); | |
370 | resp = g_malloc(sizeof(*resp) + max_size); | |
371 | ||
372 | resp->hdr.type = VIRTIO_GPU_RESP_OK_CAPSET; | |
373 | virgl_renderer_fill_caps(gc.capset_id, | |
374 | gc.capset_version, | |
375 | (void *)resp->capset_data); | |
376 | virtio_gpu_ctrl_response(g, cmd, &resp->hdr, sizeof(*resp) + max_size); | |
377 | g_free(resp); | |
378 | } | |
379 | ||
380 | void virtio_gpu_virgl_process_cmd(VirtIOGPU *g, | |
381 | struct virtio_gpu_ctrl_command *cmd) | |
382 | { | |
383 | VIRTIO_GPU_FILL_CMD(cmd->cmd_hdr); | |
384 | ||
385 | virgl_renderer_force_ctx_0(); | |
386 | switch (cmd->cmd_hdr.type) { | |
387 | case VIRTIO_GPU_CMD_CTX_CREATE: | |
388 | virgl_cmd_context_create(g, cmd); | |
389 | break; | |
390 | case VIRTIO_GPU_CMD_CTX_DESTROY: | |
391 | virgl_cmd_context_destroy(g, cmd); | |
392 | break; | |
393 | case VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: | |
394 | virgl_cmd_create_resource_2d(g, cmd); | |
395 | break; | |
396 | case VIRTIO_GPU_CMD_RESOURCE_CREATE_3D: | |
397 | virgl_cmd_create_resource_3d(g, cmd); | |
398 | break; | |
399 | case VIRTIO_GPU_CMD_SUBMIT_3D: | |
400 | virgl_cmd_submit_3d(g, cmd); | |
401 | break; | |
402 | case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: | |
403 | virgl_cmd_transfer_to_host_2d(g, cmd); | |
404 | break; | |
405 | case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D: | |
406 | virgl_cmd_transfer_to_host_3d(g, cmd); | |
407 | break; | |
408 | case VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D: | |
409 | virgl_cmd_transfer_from_host_3d(g, cmd); | |
410 | break; | |
411 | case VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING: | |
412 | virgl_resource_attach_backing(g, cmd); | |
413 | break; | |
414 | case VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING: | |
415 | virgl_resource_detach_backing(g, cmd); | |
416 | break; | |
417 | case VIRTIO_GPU_CMD_SET_SCANOUT: | |
418 | virgl_cmd_set_scanout(g, cmd); | |
419 | break; | |
420 | case VIRTIO_GPU_CMD_RESOURCE_FLUSH: | |
421 | virgl_cmd_resource_flush(g, cmd); | |
422 | break; | |
423 | case VIRTIO_GPU_CMD_RESOURCE_UNREF: | |
424 | virgl_cmd_resource_unref(g, cmd); | |
425 | break; | |
426 | case VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE: | |
427 | /* TODO add security */ | |
428 | virgl_cmd_ctx_attach_resource(g, cmd); | |
429 | break; | |
430 | case VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE: | |
431 | /* TODO add security */ | |
432 | virgl_cmd_ctx_detach_resource(g, cmd); | |
433 | break; | |
434 | case VIRTIO_GPU_CMD_GET_CAPSET_INFO: | |
435 | virgl_cmd_get_capset_info(g, cmd); | |
436 | break; | |
437 | case VIRTIO_GPU_CMD_GET_CAPSET: | |
438 | virgl_cmd_get_capset(g, cmd); | |
439 | break; | |
440 | ||
441 | case VIRTIO_GPU_CMD_GET_DISPLAY_INFO: | |
442 | virtio_gpu_get_display_info(g, cmd); | |
443 | break; | |
444 | default: | |
445 | cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC; | |
446 | break; | |
447 | } | |
448 | ||
449 | if (cmd->finished) { | |
450 | return; | |
451 | } | |
452 | if (cmd->error) { | |
453 | fprintf(stderr, "%s: ctrl 0x%x, error 0x%x\n", __func__, | |
454 | cmd->cmd_hdr.type, cmd->error); | |
455 | virtio_gpu_ctrl_response_nodata(g, cmd, cmd->error); | |
456 | return; | |
457 | } | |
458 | if (!(cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_FENCE)) { | |
459 | virtio_gpu_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA); | |
460 | return; | |
461 | } | |
462 | ||
463 | trace_virtio_gpu_fence_ctrl(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type); | |
464 | virgl_renderer_create_fence(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type); | |
465 | } | |
466 | ||
467 | static void virgl_write_fence(void *opaque, uint32_t fence) | |
468 | { | |
469 | VirtIOGPU *g = opaque; | |
470 | struct virtio_gpu_ctrl_command *cmd, *tmp; | |
471 | ||
472 | QTAILQ_FOREACH_SAFE(cmd, &g->fenceq, next, tmp) { | |
473 | /* | |
474 | * the guest can end up emitting fences out of order | |
475 | * so we should check all fenced cmds not just the first one. | |
476 | */ | |
477 | if (cmd->cmd_hdr.fence_id > fence) { | |
478 | continue; | |
479 | } | |
480 | trace_virtio_gpu_fence_resp(cmd->cmd_hdr.fence_id); | |
481 | virtio_gpu_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA); | |
482 | QTAILQ_REMOVE(&g->fenceq, cmd, next); | |
483 | g_free(cmd); | |
484 | g->inflight--; | |
485 | if (virtio_gpu_stats_enabled(g->conf)) { | |
486 | fprintf(stderr, "inflight: %3d (-)\r", g->inflight); | |
487 | } | |
488 | } | |
489 | } | |
490 | ||
491 | static virgl_renderer_gl_context | |
492 | virgl_create_context(void *opaque, int scanout_idx, | |
493 | struct virgl_renderer_gl_ctx_param *params) | |
494 | { | |
495 | VirtIOGPU *g = opaque; | |
496 | QEMUGLContext ctx; | |
497 | QEMUGLParams qparams; | |
498 | ||
499 | qparams.major_ver = params->major_ver; | |
500 | qparams.minor_ver = params->minor_ver; | |
501 | ||
502 | ctx = dpy_gl_ctx_create(g->scanout[scanout_idx].con, &qparams); | |
503 | return (virgl_renderer_gl_context)ctx; | |
504 | } | |
505 | ||
506 | static void virgl_destroy_context(void *opaque, virgl_renderer_gl_context ctx) | |
507 | { | |
508 | VirtIOGPU *g = opaque; | |
509 | QEMUGLContext qctx = (QEMUGLContext)ctx; | |
510 | ||
511 | dpy_gl_ctx_destroy(g->scanout[0].con, qctx); | |
512 | } | |
513 | ||
514 | static int virgl_make_context_current(void *opaque, int scanout_idx, | |
515 | virgl_renderer_gl_context ctx) | |
516 | { | |
517 | VirtIOGPU *g = opaque; | |
518 | QEMUGLContext qctx = (QEMUGLContext)ctx; | |
519 | ||
520 | return dpy_gl_ctx_make_current(g->scanout[scanout_idx].con, qctx); | |
521 | } | |
522 | ||
523 | static struct virgl_renderer_callbacks virtio_gpu_3d_cbs = { | |
524 | .version = 1, | |
525 | .write_fence = virgl_write_fence, | |
526 | .create_gl_context = virgl_create_context, | |
527 | .destroy_gl_context = virgl_destroy_context, | |
528 | .make_current = virgl_make_context_current, | |
529 | }; | |
530 | ||
531 | static void virtio_gpu_print_stats(void *opaque) | |
532 | { | |
533 | VirtIOGPU *g = opaque; | |
534 | ||
535 | if (g->stats.requests) { | |
536 | fprintf(stderr, "stats: vq req %4d, %3d -- 3D %4d (%5d)\n", | |
537 | g->stats.requests, | |
538 | g->stats.max_inflight, | |
539 | g->stats.req_3d, | |
540 | g->stats.bytes_3d); | |
541 | g->stats.requests = 0; | |
542 | g->stats.max_inflight = 0; | |
543 | g->stats.req_3d = 0; | |
544 | g->stats.bytes_3d = 0; | |
545 | } else { | |
546 | fprintf(stderr, "stats: idle\r"); | |
547 | } | |
548 | timer_mod(g->print_stats, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000); | |
549 | } | |
550 | ||
551 | static void virtio_gpu_fence_poll(void *opaque) | |
552 | { | |
553 | VirtIOGPU *g = opaque; | |
554 | ||
555 | virgl_renderer_poll(); | |
556 | if (g->inflight) { | |
557 | timer_mod(g->fence_poll, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 10); | |
558 | } | |
559 | } | |
560 | ||
561 | void virtio_gpu_virgl_fence_poll(VirtIOGPU *g) | |
562 | { | |
563 | virtio_gpu_fence_poll(g); | |
564 | } | |
565 | ||
566 | void virtio_gpu_virgl_reset(VirtIOGPU *g) | |
567 | { | |
568 | int i; | |
569 | ||
570 | /* virgl_renderer_reset() ??? */ | |
571 | for (i = 0; i < g->conf.max_outputs; i++) { | |
572 | if (i != 0) { | |
573 | dpy_gfx_replace_surface(g->scanout[i].con, NULL); | |
574 | } | |
575 | dpy_gl_scanout(g->scanout[i].con, 0, false, 0, 0, 0, 0); | |
576 | } | |
577 | } | |
578 | ||
579 | int virtio_gpu_virgl_init(VirtIOGPU *g) | |
580 | { | |
581 | int ret; | |
582 | ||
583 | ret = virgl_renderer_init(g, 0, &virtio_gpu_3d_cbs); | |
584 | if (ret != 0) { | |
585 | return ret; | |
586 | } | |
587 | ||
588 | g->fence_poll = timer_new_ms(QEMU_CLOCK_VIRTUAL, | |
589 | virtio_gpu_fence_poll, g); | |
590 | ||
591 | if (virtio_gpu_stats_enabled(g->conf)) { | |
592 | g->print_stats = timer_new_ms(QEMU_CLOCK_VIRTUAL, | |
593 | virtio_gpu_print_stats, g); | |
594 | timer_mod(g->print_stats, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000); | |
595 | } | |
596 | return 0; | |
597 | } | |
598 | ||
599 | #endif /* CONFIG_VIRGL */ |