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[mirror_qemu.git] / hw / display / virtio-gpu.c
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62232bf4
GH		 1/*
2 * Virtio GPU Device
3 *
4 * Copyright Red Hat, Inc. 2013-2014
5 *
6 * Authors:
7 * Dave Airlie <airlied@redhat.com>
8 * Gerd Hoffmann <kraxel@redhat.com>
9 *
2e252145 10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
62232bf4
GH		 11 * See the COPYING file in the top-level directory.
12 */
13
9b8bfe21 14#include "qemu/osdep.h"
62232bf4
GH		 15#include "qemu-common.h"
16#include "qemu/iov.h"
17#include "ui/console.h"
18#include "trace.h"
19#include "hw/virtio/virtio.h"
20#include "hw/virtio/virtio-gpu.h"
21#include "hw/virtio/virtio-bus.h"
de889221 22#include "migration/migration.h"
03dd024f 23#include "qemu/log.h"
5e3d741c 24#include "qapi/error.h"
62232bf4 25
0c244e50
GH		 26#define VIRTIO_GPU_VM_VERSION 1
27
62232bf4
GH		 28static struct virtio_gpu_simple_resource*
29virtio_gpu_find_resource(VirtIOGPU *g, uint32_t resource_id);
30
b8e23926
LQ		 31static void virtio_gpu_cleanup_mapping(struct virtio_gpu_simple_resource *res);
32
9d9e1521 33#ifdef CONFIG_VIRGL
a9c94277 34#include <virglrenderer.h>
9d9e1521
GH		 35#define VIRGL(_g, _virgl, _simple, ...) \
36 do { \
37 if (_g->use_virgl_renderer) { \
38 _virgl(__VA_ARGS__); \
39 } else { \
40 _simple(__VA_ARGS__); \
41 } \
42 } while (0)
43#else
44#define VIRGL(_g, _virgl, _simple, ...) \
45 do { \
46 _simple(__VA_ARGS__); \
47 } while (0)
48#endif
49
62232bf4
GH		 50static void update_cursor_data_simple(VirtIOGPU *g,
51 struct virtio_gpu_scanout *s,
52 uint32_t resource_id)
53{
54 struct virtio_gpu_simple_resource *res;
55 uint32_t pixels;
56
57 res = virtio_gpu_find_resource(g, resource_id);
58 if (!res) {
59 return;
60 }
61
62 if (pixman_image_get_width(res->image) != s->current_cursor->width ||
63 pixman_image_get_height(res->image) != s->current_cursor->height) {
64 return;
65 }
66
67 pixels = s->current_cursor->width * s->current_cursor->height;
68 memcpy(s->current_cursor->data,
69 pixman_image_get_data(res->image),
70 pixels * sizeof(uint32_t));
71}
72
9d9e1521
GH		 73#ifdef CONFIG_VIRGL
74
75static void update_cursor_data_virgl(VirtIOGPU *g,
76 struct virtio_gpu_scanout *s,
77 uint32_t resource_id)
78{
79 uint32_t width, height;
80 uint32_t pixels, *data;
81
82 data = virgl_renderer_get_cursor_data(resource_id, &width, &height);
83 if (!data) {
84 return;
85 }
86
87 if (width != s->current_cursor->width ||
88 height != s->current_cursor->height) {
2d1cd6c7 89 free(data);
9d9e1521
GH		 90 return;
91 }
92
93 pixels = s->current_cursor->width * s->current_cursor->height;
94 memcpy(s->current_cursor->data, data, pixels * sizeof(uint32_t));
95 free(data);
96}
97
98#endif
99
62232bf4
GH		 100static void update_cursor(VirtIOGPU *g, struct virtio_gpu_update_cursor *cursor)
101{
102 struct virtio_gpu_scanout *s;
0c244e50 103 bool move = cursor->hdr.type == VIRTIO_GPU_CMD_MOVE_CURSOR;
62232bf4
GH		 104
105 if (cursor->pos.scanout_id >= g->conf.max_outputs) {
106 return;
107 }
108 s = &g->scanout[cursor->pos.scanout_id];
109
e9c1b459
GH		 110 trace_virtio_gpu_update_cursor(cursor->pos.scanout_id,
111 cursor->pos.x,
112 cursor->pos.y,
113 move ? "move" : "update",
114 cursor->resource_id);
115
0c244e50 116 if (!move) {
62232bf4
GH		 117 if (!s->current_cursor) {
118 s->current_cursor = cursor_alloc(64, 64);
119 }
120
121 s->current_cursor->hot_x = cursor->hot_x;
122 s->current_cursor->hot_y = cursor->hot_y;
123
124 if (cursor->resource_id > 0) {
9d9e1521
GH		 125 VIRGL(g, update_cursor_data_virgl, update_cursor_data_simple,
126 g, s, cursor->resource_id);
62232bf4
GH		 127 }
128 dpy_cursor_define(s->con, s->current_cursor);
0c244e50
GH		 129
130 s->cursor = *cursor;
131 } else {
132 s->cursor.pos.x = cursor->pos.x;
133 s->cursor.pos.y = cursor->pos.y;
62232bf4
GH		 134 }
135 dpy_mouse_set(s->con, cursor->pos.x, cursor->pos.y,
136 cursor->resource_id ? 1 : 0);
137}
138
139static void virtio_gpu_get_config(VirtIODevice *vdev, uint8_t *config)
140{
141 VirtIOGPU *g = VIRTIO_GPU(vdev);
142 memcpy(config, &g->virtio_config, sizeof(g->virtio_config));
143}
144
145static void virtio_gpu_set_config(VirtIODevice *vdev, const uint8_t *config)
146{
147 VirtIOGPU *g = VIRTIO_GPU(vdev);
148 struct virtio_gpu_config vgconfig;
149
150 memcpy(&vgconfig, config, sizeof(g->virtio_config));
151
152 if (vgconfig.events_clear) {
153 g->virtio_config.events_read &= ~vgconfig.events_clear;
154 }
155}
156
9d5b731d
JW		 157static uint64_t virtio_gpu_get_features(VirtIODevice *vdev, uint64_t features,
158 Error **errp)
62232bf4 159{
9d9e1521
GH		 160 VirtIOGPU *g = VIRTIO_GPU(vdev);
161
162 if (virtio_gpu_virgl_enabled(g->conf)) {
fff02bc0 163 features |= (1 << VIRTIO_GPU_F_VIRGL);
9d9e1521 164 }
62232bf4
GH		 165 return features;
166}
167
9d9e1521
GH		 168static void virtio_gpu_set_features(VirtIODevice *vdev, uint64_t features)
169{
fff02bc0 170 static const uint32_t virgl = (1 << VIRTIO_GPU_F_VIRGL);
9d9e1521
GH		 171 VirtIOGPU *g = VIRTIO_GPU(vdev);
172
173 g->use_virgl_renderer = ((features & virgl) == virgl);
174 trace_virtio_gpu_features(g->use_virgl_renderer);
175}
176
62232bf4
GH		 177static void virtio_gpu_notify_event(VirtIOGPU *g, uint32_t event_type)
178{
179 g->virtio_config.events_read |= event_type;
180 virtio_notify_config(&g->parent_obj);
181}
182
183static struct virtio_gpu_simple_resource *
184virtio_gpu_find_resource(VirtIOGPU *g, uint32_t resource_id)
185{
186 struct virtio_gpu_simple_resource *res;
187
188 QTAILQ_FOREACH(res, &g->reslist, next) {
189 if (res->resource_id == resource_id) {
190 return res;
191 }
192 }
193 return NULL;
194}
195
196void virtio_gpu_ctrl_response(VirtIOGPU *g,
197 struct virtio_gpu_ctrl_command *cmd,
198 struct virtio_gpu_ctrl_hdr *resp,
199 size_t resp_len)
200{
201 size_t s;
202
203 if (cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_FENCE) {
204 resp->flags |= VIRTIO_GPU_FLAG_FENCE;
205 resp->fence_id = cmd->cmd_hdr.fence_id;
206 resp->ctx_id = cmd->cmd_hdr.ctx_id;
207 }
208 s = iov_from_buf(cmd->elem.in_sg, cmd->elem.in_num, 0, resp, resp_len);
209 if (s != resp_len) {
210 qemu_log_mask(LOG_GUEST_ERROR,
211 "%s: response size incorrect %zu vs %zu\n",
212 __func__, s, resp_len);
213 }
214 virtqueue_push(cmd->vq, &cmd->elem, s);
215 virtio_notify(VIRTIO_DEVICE(g), cmd->vq);
216 cmd->finished = true;
217}
218
219void virtio_gpu_ctrl_response_nodata(VirtIOGPU *g,
220 struct virtio_gpu_ctrl_command *cmd,
221 enum virtio_gpu_ctrl_type type)
222{
223 struct virtio_gpu_ctrl_hdr resp;
224
225 memset(&resp, 0, sizeof(resp));
226 resp.type = type;
227 virtio_gpu_ctrl_response(g, cmd, &resp, sizeof(resp));
228}
229
230static void
231virtio_gpu_fill_display_info(VirtIOGPU *g,
232 struct virtio_gpu_resp_display_info *dpy_info)
233{
234 int i;
235
236 for (i = 0; i < g->conf.max_outputs; i++) {
237 if (g->enabled_output_bitmask & (1 << i)) {
238 dpy_info->pmodes[i].enabled = 1;
239 dpy_info->pmodes[i].r.width = g->req_state[i].width;
240 dpy_info->pmodes[i].r.height = g->req_state[i].height;
241 }
242 }
243}
244
245void virtio_gpu_get_display_info(VirtIOGPU *g,
246 struct virtio_gpu_ctrl_command *cmd)
247{
248 struct virtio_gpu_resp_display_info display_info;
249
250 trace_virtio_gpu_cmd_get_display_info();
251 memset(&display_info, 0, sizeof(display_info));
252 display_info.hdr.type = VIRTIO_GPU_RESP_OK_DISPLAY_INFO;
253 virtio_gpu_fill_display_info(g, &display_info);
254 virtio_gpu_ctrl_response(g, cmd, &display_info.hdr,
255 sizeof(display_info));
256}
257
258static pixman_format_code_t get_pixman_format(uint32_t virtio_gpu_format)
259{
260 switch (virtio_gpu_format) {
261#ifdef HOST_WORDS_BIGENDIAN
262 case VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM:
263 return PIXMAN_b8g8r8x8;
264 case VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM:
265 return PIXMAN_b8g8r8a8;
266 case VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM:
267 return PIXMAN_x8r8g8b8;
268 case VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM:
269 return PIXMAN_a8r8g8b8;
270 case VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM:
271 return PIXMAN_r8g8b8x8;
272 case VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM:
273 return PIXMAN_r8g8b8a8;
274 case VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM:
275 return PIXMAN_x8b8g8r8;
276 case VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM:
277 return PIXMAN_a8b8g8r8;
278#else
279 case VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM:
280 return PIXMAN_x8r8g8b8;
281 case VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM:
282 return PIXMAN_a8r8g8b8;
283 case VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM:
284 return PIXMAN_b8g8r8x8;
285 case VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM:
286 return PIXMAN_b8g8r8a8;
287 case VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM:
288 return PIXMAN_x8b8g8r8;
289 case VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM:
290 return PIXMAN_a8b8g8r8;
291 case VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM:
292 return PIXMAN_r8g8b8x8;
293 case VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM:
294 return PIXMAN_r8g8b8a8;
295#endif
296 default:
297 return 0;
298 }
299}
300
301static void virtio_gpu_resource_create_2d(VirtIOGPU *g,
302 struct virtio_gpu_ctrl_command *cmd)
303{
304 pixman_format_code_t pformat;
305 struct virtio_gpu_simple_resource *res;
306 struct virtio_gpu_resource_create_2d c2d;
307
308 VIRTIO_GPU_FILL_CMD(c2d);
309 trace_virtio_gpu_cmd_res_create_2d(c2d.resource_id, c2d.format,
310 c2d.width, c2d.height);
311
312 if (c2d.resource_id == 0) {
313 qemu_log_mask(LOG_GUEST_ERROR, "%s: resource id 0 is not allowed\n",
314 __func__);
315 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
316 return;
317 }
318
319 res = virtio_gpu_find_resource(g, c2d.resource_id);
320 if (res) {
321 qemu_log_mask(LOG_GUEST_ERROR, "%s: resource already exists %d\n",
322 __func__, c2d.resource_id);
323 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
324 return;
325 }
326
327 res = g_new0(struct virtio_gpu_simple_resource, 1);
328
329 res->width = c2d.width;
330 res->height = c2d.height;
331 res->format = c2d.format;
332 res->resource_id = c2d.resource_id;
333
334 pformat = get_pixman_format(c2d.format);
335 if (!pformat) {
336 qemu_log_mask(LOG_GUEST_ERROR,
337 "%s: host couldn't handle guest format %d\n",
338 __func__, c2d.format);
cb3a0522 339 g_free(res);
62232bf4
GH		 340 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
341 return;
342 }
9b7621bc
GH		 343
344 res->hostmem = PIXMAN_FORMAT_BPP(pformat) * c2d.width * c2d.height;
345 if (res->hostmem + g->hostmem < g->conf.max_hostmem) {
346 res->image = pixman_image_create_bits(pformat,
347 c2d.width,
348 c2d.height,
349 NULL, 0);
350 }
62232bf4
GH		 351
352 if (!res->image) {
353 qemu_log_mask(LOG_GUEST_ERROR,
354 "%s: resource creation failed %d %d %d\n",
355 __func__, c2d.resource_id, c2d.width, c2d.height);
356 g_free(res);
357 cmd->error = VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY;
358 return;
359 }
360
361 QTAILQ_INSERT_HEAD(&g->reslist, res, next);
9b7621bc 362 g->hostmem += res->hostmem;
62232bf4
GH		 363}
364
365static void virtio_gpu_resource_destroy(VirtIOGPU *g,
366 struct virtio_gpu_simple_resource *res)
367{
368 pixman_image_unref(res->image);
b8e23926 369 virtio_gpu_cleanup_mapping(res);
62232bf4 370 QTAILQ_REMOVE(&g->reslist, res, next);
9b7621bc 371 g->hostmem -= res->hostmem;
62232bf4
GH		 372 g_free(res);
373}
374
375static void virtio_gpu_resource_unref(VirtIOGPU *g,
376 struct virtio_gpu_ctrl_command *cmd)
377{
378 struct virtio_gpu_simple_resource *res;
379 struct virtio_gpu_resource_unref unref;
380
381 VIRTIO_GPU_FILL_CMD(unref);
382 trace_virtio_gpu_cmd_res_unref(unref.resource_id);
383
384 res = virtio_gpu_find_resource(g, unref.resource_id);
385 if (!res) {
386 qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal resource specified %d\n",
387 __func__, unref.resource_id);
388 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
389 return;
390 }
391 virtio_gpu_resource_destroy(g, res);
392}
393
394static void virtio_gpu_transfer_to_host_2d(VirtIOGPU *g,
395 struct virtio_gpu_ctrl_command *cmd)
396{
397 struct virtio_gpu_simple_resource *res;
398 int h;
399 uint32_t src_offset, dst_offset, stride;
400 int bpp;
401 pixman_format_code_t format;
402 struct virtio_gpu_transfer_to_host_2d t2d;
403
404 VIRTIO_GPU_FILL_CMD(t2d);
405 trace_virtio_gpu_cmd_res_xfer_toh_2d(t2d.resource_id);
406
407 res = virtio_gpu_find_resource(g, t2d.resource_id);
408 if (!res || !res->iov) {
409 qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal resource specified %d\n",
410 __func__, t2d.resource_id);
411 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
412 return;
413 }
414
415 if (t2d.r.x > res->width ||
416 t2d.r.y > res->height ||
417 t2d.r.width > res->width ||
418 t2d.r.height > res->height ||
419 t2d.r.x + t2d.r.width > res->width ||
420 t2d.r.y + t2d.r.height > res->height) {
421 qemu_log_mask(LOG_GUEST_ERROR, "%s: transfer bounds outside resource"
422 " bounds for resource %d: %d %d %d %d vs %d %d\n",
423 __func__, t2d.resource_id, t2d.r.x, t2d.r.y,
424 t2d.r.width, t2d.r.height, res->width, res->height);
425 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
426 return;
427 }
428
429 format = pixman_image_get_format(res->image);
430 bpp = (PIXMAN_FORMAT_BPP(format) + 7) / 8;
431 stride = pixman_image_get_stride(res->image);
432
433 if (t2d.offset || t2d.r.x || t2d.r.y ||
434 t2d.r.width != pixman_image_get_width(res->image)) {
435 void *img_data = pixman_image_get_data(res->image);
436 for (h = 0; h < t2d.r.height; h++) {
437 src_offset = t2d.offset + stride * h;
438 dst_offset = (t2d.r.y + h) * stride + (t2d.r.x * bpp);
439
440 iov_to_buf(res->iov, res->iov_cnt, src_offset,
441 (uint8_t *)img_data
442 + dst_offset, t2d.r.width * bpp);
443 }
444 } else {
445 iov_to_buf(res->iov, res->iov_cnt, 0,
446 pixman_image_get_data(res->image),
447 pixman_image_get_stride(res->image)
448 * pixman_image_get_height(res->image));
449 }
450}
451
452static void virtio_gpu_resource_flush(VirtIOGPU *g,
453 struct virtio_gpu_ctrl_command *cmd)
454{
455 struct virtio_gpu_simple_resource *res;
456 struct virtio_gpu_resource_flush rf;
457 pixman_region16_t flush_region;
458 int i;
459
460 VIRTIO_GPU_FILL_CMD(rf);
461 trace_virtio_gpu_cmd_res_flush(rf.resource_id,
462 rf.r.width, rf.r.height, rf.r.x, rf.r.y);
463
464 res = virtio_gpu_find_resource(g, rf.resource_id);
465 if (!res) {
466 qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal resource specified %d\n",
467 __func__, rf.resource_id);
468 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
469 return;
470 }
471
472 if (rf.r.x > res->width ||
473 rf.r.y > res->height ||
474 rf.r.width > res->width ||
475 rf.r.height > res->height ||
476 rf.r.x + rf.r.width > res->width ||
477 rf.r.y + rf.r.height > res->height) {
478 qemu_log_mask(LOG_GUEST_ERROR, "%s: flush bounds outside resource"
479 " bounds for resource %d: %d %d %d %d vs %d %d\n",
480 __func__, rf.resource_id, rf.r.x, rf.r.y,
481 rf.r.width, rf.r.height, res->width, res->height);
482 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
483 return;
484 }
485
486 pixman_region_init_rect(&flush_region,
487 rf.r.x, rf.r.y, rf.r.width, rf.r.height);
2fe76055 488 for (i = 0; i < g->conf.max_outputs; i++) {
62232bf4
GH		 489 struct virtio_gpu_scanout *scanout;
490 pixman_region16_t region, finalregion;
491 pixman_box16_t *extents;
492
493 if (!(res->scanout_bitmask & (1 << i))) {
494 continue;
495 }
496 scanout = &g->scanout[i];
497
498 pixman_region_init(&finalregion);
499 pixman_region_init_rect(&region, scanout->x, scanout->y,
500 scanout->width, scanout->height);
501
502 pixman_region_intersect(&finalregion, &flush_region, &region);
503 pixman_region_translate(&finalregion, -scanout->x, -scanout->y);
504 extents = pixman_region_extents(&finalregion);
505 /* work out the area we need to update for each console */
506 dpy_gfx_update(g->scanout[i].con,
507 extents->x1, extents->y1,
508 extents->x2 - extents->x1,
509 extents->y2 - extents->y1);
510
511 pixman_region_fini(&region);
512 pixman_region_fini(&finalregion);
513 }
514 pixman_region_fini(&flush_region);
515}
516
fa06e5cb
GH		 517static void virtio_unref_resource(pixman_image_t *image, void *data)
518{
519 pixman_image_unref(data);
520}
521
62232bf4
GH		 522static void virtio_gpu_set_scanout(VirtIOGPU *g,
523 struct virtio_gpu_ctrl_command *cmd)
524{
525 struct virtio_gpu_simple_resource *res;
526 struct virtio_gpu_scanout *scanout;
527 pixman_format_code_t format;
528 uint32_t offset;
529 int bpp;
530 struct virtio_gpu_set_scanout ss;
531
532 VIRTIO_GPU_FILL_CMD(ss);
533 trace_virtio_gpu_cmd_set_scanout(ss.scanout_id, ss.resource_id,
534 ss.r.width, ss.r.height, ss.r.x, ss.r.y);
535
2fe76055 536 if (ss.scanout_id >= g->conf.max_outputs) {
fe89fdeb
MAL		 537 qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal scanout id specified %d",
538 __func__, ss.scanout_id);
539 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID;
540 return;
541 }
542
62232bf4
GH		 543 g->enable = 1;
544 if (ss.resource_id == 0) {
545 scanout = &g->scanout[ss.scanout_id];
546 if (scanout->resource_id) {
547 res = virtio_gpu_find_resource(g, scanout->resource_id);
548 if (res) {
549 res->scanout_bitmask &= ~(1 << ss.scanout_id);
550 }
551 }
fe89fdeb 552 if (ss.scanout_id == 0) {
62232bf4
GH		 553 qemu_log_mask(LOG_GUEST_ERROR,
554 "%s: illegal scanout id specified %d",
555 __func__, ss.scanout_id);
556 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID;
557 return;
558 }
559 dpy_gfx_replace_surface(g->scanout[ss.scanout_id].con, NULL);
560 scanout->ds = NULL;
561 scanout->width = 0;
562 scanout->height = 0;
563 return;
564 }
565
566 /* create a surface for this scanout */
62232bf4
GH		 567 res = virtio_gpu_find_resource(g, ss.resource_id);
568 if (!res) {
569 qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal resource specified %d\n",
570 __func__, ss.resource_id);
571 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
572 return;
573 }
574
575 if (ss.r.x > res->width ||
576 ss.r.y > res->height ||
577 ss.r.width > res->width ||
578 ss.r.height > res->height ||
579 ss.r.x + ss.r.width > res->width ||
580 ss.r.y + ss.r.height > res->height) {
581 qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal scanout %d bounds for"
582 " resource %d, (%d,%d)+%d,%d vs %d %d\n",
583 __func__, ss.scanout_id, ss.resource_id, ss.r.x, ss.r.y,
584 ss.r.width, ss.r.height, res->width, res->height);
585 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
586 return;
587 }
588
589 scanout = &g->scanout[ss.scanout_id];
590
591 format = pixman_image_get_format(res->image);
592 bpp = (PIXMAN_FORMAT_BPP(format) + 7) / 8;
593 offset = (ss.r.x * bpp) + ss.r.y * pixman_image_get_stride(res->image);
594 if (!scanout->ds || surface_data(scanout->ds)
595 != ((uint8_t *)pixman_image_get_data(res->image) + offset) ||
596 scanout->width != ss.r.width ||
597 scanout->height != ss.r.height) {
fa06e5cb
GH		 598 pixman_image_t *rect;
599 void *ptr = (uint8_t *)pixman_image_get_data(res->image) + offset;
600 rect = pixman_image_create_bits(format, ss.r.width, ss.r.height, ptr,
601 pixman_image_get_stride(res->image));
602 pixman_image_ref(res->image);
603 pixman_image_set_destroy_function(rect, virtio_unref_resource,
604 res->image);
62232bf4 605 /* realloc the surface ptr */
fa06e5cb 606 scanout->ds = qemu_create_displaysurface_pixman(rect);
62232bf4
GH		 607 if (!scanout->ds) {
608 cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
609 return;
610 }
611 dpy_gfx_replace_surface(g->scanout[ss.scanout_id].con, scanout->ds);
612 }
613
614 res->scanout_bitmask |= (1 << ss.scanout_id);
615 scanout->resource_id = ss.resource_id;
616 scanout->x = ss.r.x;
617 scanout->y = ss.r.y;
618 scanout->width = ss.r.width;
619 scanout->height = ss.r.height;
620}
621
622int virtio_gpu_create_mapping_iov(struct virtio_gpu_resource_attach_backing *ab,
623 struct virtio_gpu_ctrl_command *cmd,
0c244e50 624 uint64_t **addr, struct iovec **iov)
62232bf4
GH		 625{
626 struct virtio_gpu_mem_entry *ents;
627 size_t esize, s;
628 int i;
629
630 if (ab->nr_entries > 16384) {
631 qemu_log_mask(LOG_GUEST_ERROR,
2c84167b 632 "%s: nr_entries is too big (%d > 16384)\n",
62232bf4
GH		 633 __func__, ab->nr_entries);
634 return -1;
635 }
636
637 esize = sizeof(*ents) * ab->nr_entries;
638 ents = g_malloc(esize);
639 s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num,
640 sizeof(*ab), ents, esize);
641 if (s != esize) {
642 qemu_log_mask(LOG_GUEST_ERROR,
643 "%s: command data size incorrect %zu vs %zu\n",
644 __func__, s, esize);
645 g_free(ents);
646 return -1;
647 }
648
649 *iov = g_malloc0(sizeof(struct iovec) * ab->nr_entries);
0c244e50
GH		 650 if (addr) {
651 *addr = g_malloc0(sizeof(uint64_t) * ab->nr_entries);
652 }
62232bf4
GH		 653 for (i = 0; i < ab->nr_entries; i++) {
654 hwaddr len = ents[i].length;
655 (*iov)[i].iov_len = ents[i].length;
656 (*iov)[i].iov_base = cpu_physical_memory_map(ents[i].addr, &len, 1);
0c244e50
GH		 657 if (addr) {
658 (*addr)[i] = ents[i].addr;
659 }
62232bf4
GH		 660 if (!(*iov)[i].iov_base || len != ents[i].length) {
661 qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to map MMIO memory for"
662 " resource %d element %d\n",
663 __func__, ab->resource_id, i);
664 virtio_gpu_cleanup_mapping_iov(*iov, i);
665 g_free(ents);
62232bf4 666 *iov = NULL;
0c244e50
GH		 667 if (addr) {
668 g_free(*addr);
669 *addr = NULL;
670 }
62232bf4
GH		 671 return -1;
672 }
673 }
674 g_free(ents);
675 return 0;
676}
677
678void virtio_gpu_cleanup_mapping_iov(struct iovec *iov, uint32_t count)
679{
680 int i;
681
682 for (i = 0; i < count; i++) {
683 cpu_physical_memory_unmap(iov[i].iov_base, iov[i].iov_len, 1,
684 iov[i].iov_len);
685 }
7f3be0f2 686 g_free(iov);
62232bf4
GH		 687}
688
689static void virtio_gpu_cleanup_mapping(struct virtio_gpu_simple_resource *res)
690{
691 virtio_gpu_cleanup_mapping_iov(res->iov, res->iov_cnt);
62232bf4
GH		 692 res->iov = NULL;
693 res->iov_cnt = 0;
0c244e50
GH		 694 g_free(res->addrs);
695 res->addrs = NULL;
62232bf4
GH		 696}
697
698static void
699virtio_gpu_resource_attach_backing(VirtIOGPU *g,
700 struct virtio_gpu_ctrl_command *cmd)
701{
702 struct virtio_gpu_simple_resource *res;
703 struct virtio_gpu_resource_attach_backing ab;
704 int ret;
705
706 VIRTIO_GPU_FILL_CMD(ab);
707 trace_virtio_gpu_cmd_res_back_attach(ab.resource_id);
708
709 res = virtio_gpu_find_resource(g, ab.resource_id);
710 if (!res) {
711 qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal resource specified %d\n",
712 __func__, ab.resource_id);
713 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
714 return;
715 }
716
204f01b3
LQ		 717 if (res->iov) {
718 cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
719 return;
720 }
721
0c244e50 722 ret = virtio_gpu_create_mapping_iov(&ab, cmd, &res->addrs, &res->iov);
62232bf4
GH		 723 if (ret != 0) {
724 cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
725 return;
726 }
727
728 res->iov_cnt = ab.nr_entries;
729}
730
731static void
732virtio_gpu_resource_detach_backing(VirtIOGPU *g,
733 struct virtio_gpu_ctrl_command *cmd)
734{
735 struct virtio_gpu_simple_resource *res;
736 struct virtio_gpu_resource_detach_backing detach;
737
738 VIRTIO_GPU_FILL_CMD(detach);
739 trace_virtio_gpu_cmd_res_back_detach(detach.resource_id);
740
741 res = virtio_gpu_find_resource(g, detach.resource_id);
742 if (!res || !res->iov) {
743 qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal resource specified %d\n",
744 __func__, detach.resource_id);
745 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
746 return;
747 }
748 virtio_gpu_cleanup_mapping(res);
749}
750
751static void virtio_gpu_simple_process_cmd(VirtIOGPU *g,
752 struct virtio_gpu_ctrl_command *cmd)
753{
754 VIRTIO_GPU_FILL_CMD(cmd->cmd_hdr);
755
756 switch (cmd->cmd_hdr.type) {
757 case VIRTIO_GPU_CMD_GET_DISPLAY_INFO:
758 virtio_gpu_get_display_info(g, cmd);
759 break;
760 case VIRTIO_GPU_CMD_RESOURCE_CREATE_2D:
761 virtio_gpu_resource_create_2d(g, cmd);
762 break;
763 case VIRTIO_GPU_CMD_RESOURCE_UNREF:
764 virtio_gpu_resource_unref(g, cmd);
765 break;
766 case VIRTIO_GPU_CMD_RESOURCE_FLUSH:
767 virtio_gpu_resource_flush(g, cmd);
768 break;
769 case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D:
770 virtio_gpu_transfer_to_host_2d(g, cmd);
771 break;
772 case VIRTIO_GPU_CMD_SET_SCANOUT:
773 virtio_gpu_set_scanout(g, cmd);
774 break;
775 case VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING:
776 virtio_gpu_resource_attach_backing(g, cmd);
777 break;
778 case VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING:
779 virtio_gpu_resource_detach_backing(g, cmd);
780 break;
781 default:
782 cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
783 break;
784 }
785 if (!cmd->finished) {
786 virtio_gpu_ctrl_response_nodata(g, cmd, cmd->error ? cmd->error :
787 VIRTIO_GPU_RESP_OK_NODATA);
788 }
789}
790
791static void virtio_gpu_handle_ctrl_cb(VirtIODevice *vdev, VirtQueue *vq)
792{
793 VirtIOGPU *g = VIRTIO_GPU(vdev);
794 qemu_bh_schedule(g->ctrl_bh);
795}
796
797static void virtio_gpu_handle_cursor_cb(VirtIODevice *vdev, VirtQueue *vq)
798{
799 VirtIOGPU *g = VIRTIO_GPU(vdev);
800 qemu_bh_schedule(g->cursor_bh);
801}
802
0c55a1cf 803void virtio_gpu_process_cmdq(VirtIOGPU *g)
3eb769fd
GH		 804{
805 struct virtio_gpu_ctrl_command *cmd;
806
807 while (!QTAILQ_EMPTY(&g->cmdq)) {
808 cmd = QTAILQ_FIRST(&g->cmdq);
809
810 /* process command */
811 VIRGL(g, virtio_gpu_virgl_process_cmd, virtio_gpu_simple_process_cmd,
812 g, cmd);
0c55a1cf
GH		 813 if (cmd->waiting) {
814 break;
815 }
3eb769fd
GH		 816 QTAILQ_REMOVE(&g->cmdq, cmd, next);
817 if (virtio_gpu_stats_enabled(g->conf)) {
818 g->stats.requests++;
819 }
820
821 if (!cmd->finished) {
822 QTAILQ_INSERT_TAIL(&g->fenceq, cmd, next);
823 g->inflight++;
824 if (virtio_gpu_stats_enabled(g->conf)) {
825 if (g->stats.max_inflight < g->inflight) {
826 g->stats.max_inflight = g->inflight;
827 }
828 fprintf(stderr, "inflight: %3d (+)\r", g->inflight);
829 }
830 } else {
831 g_free(cmd);
832 }
833 }
834}
835
62232bf4
GH		 836static void virtio_gpu_handle_ctrl(VirtIODevice *vdev, VirtQueue *vq)
837{
838 VirtIOGPU *g = VIRTIO_GPU(vdev);
839 struct virtio_gpu_ctrl_command *cmd;
840
841 if (!virtio_queue_ready(vq)) {
842 return;
843 }
844
9d9e1521
GH		 845#ifdef CONFIG_VIRGL
846 if (!g->renderer_inited && g->use_virgl_renderer) {
847 virtio_gpu_virgl_init(g);
848 g->renderer_inited = true;
849 }
850#endif
851
51b19ebe
PB		 852 cmd = virtqueue_pop(vq, sizeof(struct virtio_gpu_ctrl_command));
853 while (cmd) {
62232bf4
GH		 854 cmd->vq = vq;
855 cmd->error = 0;
856 cmd->finished = false;
3eb769fd
GH		 857 cmd->waiting = false;
858 QTAILQ_INSERT_TAIL(&g->cmdq, cmd, next);
51b19ebe 859 cmd = virtqueue_pop(vq, sizeof(struct virtio_gpu_ctrl_command));
62232bf4 860 }
9d9e1521 861
3eb769fd
GH		 862 virtio_gpu_process_cmdq(g);
863
9d9e1521
GH		 864#ifdef CONFIG_VIRGL
865 if (g->use_virgl_renderer) {
866 virtio_gpu_virgl_fence_poll(g);
867 }
868#endif
62232bf4
GH		 869}
870
871static void virtio_gpu_ctrl_bh(void *opaque)
872{
873 VirtIOGPU *g = opaque;
874 virtio_gpu_handle_ctrl(&g->parent_obj, g->ctrl_vq);
875}
876
877static void virtio_gpu_handle_cursor(VirtIODevice *vdev, VirtQueue *vq)
878{
879 VirtIOGPU *g = VIRTIO_GPU(vdev);
51b19ebe 880 VirtQueueElement *elem;
62232bf4
GH		 881 size_t s;
882 struct virtio_gpu_update_cursor cursor_info;
883
884 if (!virtio_queue_ready(vq)) {
885 return;
886 }
51b19ebe
PB		 887 for (;;) {
888 elem = virtqueue_pop(vq, sizeof(VirtQueueElement));
889 if (!elem) {
890 break;
891 }
892
893 s = iov_to_buf(elem->out_sg, elem->out_num, 0,
62232bf4
GH		 894 &cursor_info, sizeof(cursor_info));
895 if (s != sizeof(cursor_info)) {
896 qemu_log_mask(LOG_GUEST_ERROR,
897 "%s: cursor size incorrect %zu vs %zu\n",
898 __func__, s, sizeof(cursor_info));
899 } else {
900 update_cursor(g, &cursor_info);
901 }
51b19ebe 902 virtqueue_push(vq, elem, 0);
62232bf4 903 virtio_notify(vdev, vq);
51b19ebe 904 g_free(elem);
62232bf4
GH		 905 }
906}
907
908static void virtio_gpu_cursor_bh(void *opaque)
909{
910 VirtIOGPU *g = opaque;
911 virtio_gpu_handle_cursor(&g->parent_obj, g->cursor_vq);
912}
913
914static void virtio_gpu_invalidate_display(void *opaque)
915{
916}
917
918static void virtio_gpu_update_display(void *opaque)
919{
920}
921
922static void virtio_gpu_text_update(void *opaque, console_ch_t *chardata)
923{
924}
925
926static int virtio_gpu_ui_info(void *opaque, uint32_t idx, QemuUIInfo *info)
927{
928 VirtIOGPU *g = opaque;
929
6b860806 930 if (idx >= g->conf.max_outputs) {
62232bf4
GH		 931 return -1;
932 }
933
934 g->req_state[idx].x = info->xoff;
935 g->req_state[idx].y = info->yoff;
936 g->req_state[idx].width = info->width;
937 g->req_state[idx].height = info->height;
938
939 if (info->width && info->height) {
940 g->enabled_output_bitmask |= (1 << idx);
941 } else {
942 g->enabled_output_bitmask &= ~(1 << idx);
943 }
944
945 /* send event to guest */
946 virtio_gpu_notify_event(g, VIRTIO_GPU_EVENT_DISPLAY);
947 return 0;
948}
949
321c9adb
GH		 950static void virtio_gpu_gl_block(void *opaque, bool block)
951{
952 VirtIOGPU *g = opaque;
953
c540128f
MAL		 954 if (block) {
955 g->renderer_blocked++;
956 } else {
957 g->renderer_blocked--;
958 }
959 assert(g->renderer_blocked >= 0);
960
961 if (g->renderer_blocked == 0) {
321c9adb
GH		 962 virtio_gpu_process_cmdq(g);
963 }
964}
965
62232bf4
GH		 966const GraphicHwOps virtio_gpu_ops = {
967 .invalidate = virtio_gpu_invalidate_display,
968 .gfx_update = virtio_gpu_update_display,
969 .text_update = virtio_gpu_text_update,
970 .ui_info = virtio_gpu_ui_info,
321c9adb 971 .gl_block = virtio_gpu_gl_block,
62232bf4
GH		 972};
973
0c244e50
GH		 974static const VMStateDescription vmstate_virtio_gpu_scanout = {
975 .name = "virtio-gpu-one-scanout",
976 .version_id = 1,
977 .fields = (VMStateField[]) {
978 VMSTATE_UINT32(resource_id, struct virtio_gpu_scanout),
979 VMSTATE_UINT32(width, struct virtio_gpu_scanout),
980 VMSTATE_UINT32(height, struct virtio_gpu_scanout),
981 VMSTATE_INT32(x, struct virtio_gpu_scanout),
982 VMSTATE_INT32(y, struct virtio_gpu_scanout),
983 VMSTATE_UINT32(cursor.resource_id, struct virtio_gpu_scanout),
984 VMSTATE_UINT32(cursor.hot_x, struct virtio_gpu_scanout),
985 VMSTATE_UINT32(cursor.hot_y, struct virtio_gpu_scanout),
986 VMSTATE_UINT32(cursor.pos.x, struct virtio_gpu_scanout),
987 VMSTATE_UINT32(cursor.pos.y, struct virtio_gpu_scanout),
988 VMSTATE_END_OF_LIST()
989 },
990};
991
992static const VMStateDescription vmstate_virtio_gpu_scanouts = {
993 .name = "virtio-gpu-scanouts",
994 .version_id = 1,
995 .fields = (VMStateField[]) {
996 VMSTATE_INT32(enable, struct VirtIOGPU),
997 VMSTATE_UINT32_EQUAL(conf.max_outputs, struct VirtIOGPU),
998 VMSTATE_STRUCT_VARRAY_UINT32(scanout, struct VirtIOGPU,
999 conf.max_outputs, 1,
1000 vmstate_virtio_gpu_scanout,
1001 struct virtio_gpu_scanout),
1002 VMSTATE_END_OF_LIST()
1003 },
1004};
1005
0fc07498 1006static void virtio_gpu_save(QEMUFile *f, void *opaque, size_t size)
0c244e50
GH		 1007{
1008 VirtIOGPU *g = opaque;
0c244e50
GH		 1009 struct virtio_gpu_simple_resource *res;
1010 int i;
1011
0c244e50
GH		 1012 /* in 2d mode we should never find unprocessed commands here */
1013 assert(QTAILQ_EMPTY(&g->cmdq));
1014
1015 QTAILQ_FOREACH(res, &g->reslist, next) {
1016 qemu_put_be32(f, res->resource_id);
1017 qemu_put_be32(f, res->width);
1018 qemu_put_be32(f, res->height);
1019 qemu_put_be32(f, res->format);
1020 qemu_put_be32(f, res->iov_cnt);
1021 for (i = 0; i < res->iov_cnt; i++) {
1022 qemu_put_be64(f, res->addrs[i]);
1023 qemu_put_be32(f, res->iov[i].iov_len);
1024 }
1025 qemu_put_buffer(f, (void *)pixman_image_get_data(res->image),
1026 pixman_image_get_stride(res->image) * res->height);
1027 }
1028 qemu_put_be32(f, 0); /* end of list */
1029
1030 vmstate_save_state(f, &vmstate_virtio_gpu_scanouts, g, NULL);
1031}
1032
0fc07498 1033static int virtio_gpu_load(QEMUFile *f, void *opaque, size_t size)
0c244e50
GH		 1034{
1035 VirtIOGPU *g = opaque;
0c244e50
GH		 1036 struct virtio_gpu_simple_resource *res;
1037 struct virtio_gpu_scanout *scanout;
1038 uint32_t resource_id, pformat;
8a502efd 1039 int i;
0c244e50 1040
039aa5db
PM		 1041 g->hostmem = 0;
1042
0c244e50
GH		 1043 resource_id = qemu_get_be32(f);
1044 while (resource_id != 0) {
1045 res = g_new0(struct virtio_gpu_simple_resource, 1);
1046 res->resource_id = resource_id;
1047 res->width = qemu_get_be32(f);
1048 res->height = qemu_get_be32(f);
1049 res->format = qemu_get_be32(f);
1050 res->iov_cnt = qemu_get_be32(f);
1051
1052 /* allocate */
1053 pformat = get_pixman_format(res->format);
1054 if (!pformat) {
c84f0f25 1055 g_free(res);
0c244e50
GH		 1056 return -EINVAL;
1057 }
1058 res->image = pixman_image_create_bits(pformat,
1059 res->width, res->height,
1060 NULL, 0);
1061 if (!res->image) {
c84f0f25 1062 g_free(res);
0c244e50
GH		 1063 return -EINVAL;
1064 }
1065
039aa5db
PM		 1066 res->hostmem = PIXMAN_FORMAT_BPP(pformat) * res->width * res->height;
1067
0c244e50
GH		 1068 res->addrs = g_new(uint64_t, res->iov_cnt);
1069 res->iov = g_new(struct iovec, res->iov_cnt);
1070
1071 /* read data */
1072 for (i = 0; i < res->iov_cnt; i++) {
1073 res->addrs[i] = qemu_get_be64(f);
1074 res->iov[i].iov_len = qemu_get_be32(f);
1075 }
1076 qemu_get_buffer(f, (void *)pixman_image_get_data(res->image),
1077 pixman_image_get_stride(res->image) * res->height);
1078
1079 /* restore mapping */
1080 for (i = 0; i < res->iov_cnt; i++) {
1081 hwaddr len = res->iov[i].iov_len;
1082 res->iov[i].iov_base =
1083 cpu_physical_memory_map(res->addrs[i], &len, 1);
1084 if (!res->iov[i].iov_base || len != res->iov[i].iov_len) {
c84f0f25
PM		 1085 /* Clean up the half-a-mapping we just created... */
1086 if (res->iov[i].iov_base) {
1087 cpu_physical_memory_unmap(res->iov[i].iov_base,
1088 len, 0, 0);
1089 }
1090 /* ...and the mappings for previous loop iterations */
1091 res->iov_cnt = i;
1092 virtio_gpu_cleanup_mapping(res);
1093 pixman_image_unref(res->image);
1094 g_free(res);
0c244e50
GH		 1095 return -EINVAL;
1096 }
1097 }
1098
1099 QTAILQ_INSERT_HEAD(&g->reslist, res, next);
039aa5db 1100 g->hostmem += res->hostmem;
0c244e50
GH		 1101
1102 resource_id = qemu_get_be32(f);
1103 }
1104
1105 /* load & apply scanout state */
1106 vmstate_load_state(f, &vmstate_virtio_gpu_scanouts, g, 1);
1107 for (i = 0; i < g->conf.max_outputs; i++) {
1108 scanout = &g->scanout[i];
1109 if (!scanout->resource_id) {
1110 continue;
1111 }
1112 res = virtio_gpu_find_resource(g, scanout->resource_id);
1113 if (!res) {
1114 return -EINVAL;
1115 }
1116 scanout->ds = qemu_create_displaysurface_pixman(res->image);
1117 if (!scanout->ds) {
1118 return -EINVAL;
1119 }
1120
1121 dpy_gfx_replace_surface(scanout->con, scanout->ds);
1122 dpy_gfx_update(scanout->con, 0, 0, scanout->width, scanout->height);
1123 update_cursor(g, &scanout->cursor);
1124 res->scanout_bitmask |= (1 << i);
1125 }
1126
1127 return 0;
1128}
1129
62232bf4
GH		 1130static void virtio_gpu_device_realize(DeviceState *qdev, Error **errp)
1131{
1132 VirtIODevice *vdev = VIRTIO_DEVICE(qdev);
1133 VirtIOGPU *g = VIRTIO_GPU(qdev);
9d9e1521 1134 bool have_virgl;
62232bf4
GH		 1135 int i;
1136
acfc4846
MAL		 1137 if (g->conf.max_outputs > VIRTIO_GPU_MAX_SCANOUTS) {
1138 error_setg(errp, "invalid max_outputs > %d", VIRTIO_GPU_MAX_SCANOUTS);
5e3d741c
MAL		 1139 return;
1140 }
1141
62232bf4
GH		 1142 g->config_size = sizeof(struct virtio_gpu_config);
1143 g->virtio_config.num_scanouts = g->conf.max_outputs;
1144 virtio_init(VIRTIO_DEVICE(g), "virtio-gpu", VIRTIO_ID_GPU,
1145 g->config_size);
1146
1147 g->req_state[0].width = 1024;
1148 g->req_state[0].height = 768;
1149
9d9e1521
GH		 1150 g->use_virgl_renderer = false;
1151#if !defined(CONFIG_VIRGL) || defined(HOST_WORDS_BIGENDIAN)
1152 have_virgl = false;
1153#else
1154 have_virgl = display_opengl;
1155#endif
1156 if (!have_virgl) {
1157 g->conf.flags &= ~(1 << VIRTIO_GPU_FLAG_VIRGL_ENABLED);
1158 }
1159
1160 if (virtio_gpu_virgl_enabled(g->conf)) {
1161 /* use larger control queue in 3d mode */
1162 g->ctrl_vq = virtio_add_queue(vdev, 256, virtio_gpu_handle_ctrl_cb);
1163 g->cursor_vq = virtio_add_queue(vdev, 16, virtio_gpu_handle_cursor_cb);
1164 g->virtio_config.num_capsets = 1;
1165 } else {
1166 g->ctrl_vq = virtio_add_queue(vdev, 64, virtio_gpu_handle_ctrl_cb);
1167 g->cursor_vq = virtio_add_queue(vdev, 16, virtio_gpu_handle_cursor_cb);
1168 }
62232bf4
GH		 1169
1170 g->ctrl_bh = qemu_bh_new(virtio_gpu_ctrl_bh, g);
1171 g->cursor_bh = qemu_bh_new(virtio_gpu_cursor_bh, g);
1172 QTAILQ_INIT(&g->reslist);
3eb769fd 1173 QTAILQ_INIT(&g->cmdq);
62232bf4
GH		 1174 QTAILQ_INIT(&g->fenceq);
1175
1176 g->enabled_output_bitmask = 1;
1177 g->qdev = qdev;
1178
1179 for (i = 0; i < g->conf.max_outputs; i++) {
1180 g->scanout[i].con =
1181 graphic_console_init(DEVICE(g), i, &virtio_gpu_ops, g);
1182 if (i > 0) {
1183 dpy_gfx_replace_surface(g->scanout[i].con, NULL);
1184 }
1185 }
fa49e465 1186
0c244e50 1187 if (virtio_gpu_virgl_enabled(g->conf)) {
de889221
DDAG		 1188 error_setg(&g->migration_blocker, "virgl is not yet migratable");
1189 migrate_add_blocker(g->migration_blocker);
0c244e50 1190 }
62232bf4
GH		 1191}
1192
de889221
DDAG		 1193static void virtio_gpu_device_unrealize(DeviceState *qdev, Error **errp)
1194{
1195 VirtIOGPU *g = VIRTIO_GPU(qdev);
1196 if (g->migration_blocker) {
1197 migrate_del_blocker(g->migration_blocker);
1198 error_free(g->migration_blocker);
1199 }
1200}
1201
62232bf4
GH		 1202static void virtio_gpu_instance_init(Object *obj)
1203{
1204}
1205
1206static void virtio_gpu_reset(VirtIODevice *vdev)
1207{
1208 VirtIOGPU *g = VIRTIO_GPU(vdev);
1209 struct virtio_gpu_simple_resource *res, *tmp;
1210 int i;
1211
1212 g->enable = 0;
1213
1214 QTAILQ_FOREACH_SAFE(res, &g->reslist, next, tmp) {
1215 virtio_gpu_resource_destroy(g, res);
1216 }
1217 for (i = 0; i < g->conf.max_outputs; i++) {
1218#if 0
1219 g->req_state[i].x = 0;
1220 g->req_state[i].y = 0;
1221 if (i == 0) {
1222 g->req_state[0].width = 1024;
1223 g->req_state[0].height = 768;
1224 } else {
1225 g->req_state[i].width = 0;
1226 g->req_state[i].height = 0;
1227 }
1228#endif
1229 g->scanout[i].resource_id = 0;
1230 g->scanout[i].width = 0;
1231 g->scanout[i].height = 0;
1232 g->scanout[i].x = 0;
1233 g->scanout[i].y = 0;
1234 g->scanout[i].ds = NULL;
1235 }
1236 g->enabled_output_bitmask = 1;
9d9e1521
GH		 1237
1238#ifdef CONFIG_VIRGL
1239 if (g->use_virgl_renderer) {
1240 virtio_gpu_virgl_reset(g);
1241 g->use_virgl_renderer = 0;
1242 }
1243#endif
62232bf4
GH		 1244}
1245
8a502efd
HP		 1246/*
1247 * For historical reasons virtio_gpu does not adhere to virtio migration
1248 * scheme as described in doc/virtio-migration.txt, in a sense that no
1249 * save/load callback are provided to the core. Instead the device data
1250 * is saved/loaded after the core data.
1251 *
1252 * Because of this we need a special vmsd.
1253 */
1254static const VMStateDescription vmstate_virtio_gpu = {
1255 .name = "virtio-gpu",
1256 .minimum_version_id = VIRTIO_GPU_VM_VERSION,
1257 .version_id = VIRTIO_GPU_VM_VERSION,
1258 .fields = (VMStateField[]) {
1259 VMSTATE_VIRTIO_DEVICE /* core */,
1260 {
1261 .name = "virtio-gpu",
1262 .info = &(const VMStateInfo) {
1263 .name = "virtio-gpu",
1264 .get = virtio_gpu_load,
1265 .put = virtio_gpu_save,
1266 },
1267 .flags = VMS_SINGLE,
1268 } /* device */,
1269 VMSTATE_END_OF_LIST()
1270 },
1271};
0fc07498 1272
62232bf4 1273static Property virtio_gpu_properties[] = {
b3409a31 1274 DEFINE_PROP_UINT32("max_outputs", VirtIOGPU, conf.max_outputs, 1),
9b7621bc
GH		 1275 DEFINE_PROP_SIZE("max_hostmem", VirtIOGPU, conf.max_hostmem,
1276 256 * 1024 * 1024),
9d9e1521
GH		 1277#ifdef CONFIG_VIRGL
1278 DEFINE_PROP_BIT("virgl", VirtIOGPU, conf.flags,
1279 VIRTIO_GPU_FLAG_VIRGL_ENABLED, true),
1280 DEFINE_PROP_BIT("stats", VirtIOGPU, conf.flags,
1281 VIRTIO_GPU_FLAG_STATS_ENABLED, false),
1282#endif
62232bf4
GH		 1283 DEFINE_PROP_END_OF_LIST(),
1284};
1285
1286static void virtio_gpu_class_init(ObjectClass *klass, void *data)
1287{
1288 DeviceClass *dc = DEVICE_CLASS(klass);
1289 VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
1290
1291 vdc->realize = virtio_gpu_device_realize;
de889221 1292 vdc->unrealize = virtio_gpu_device_unrealize;
62232bf4
GH		 1293 vdc->get_config = virtio_gpu_get_config;
1294 vdc->set_config = virtio_gpu_set_config;
1295 vdc->get_features = virtio_gpu_get_features;
9d9e1521 1296 vdc->set_features = virtio_gpu_set_features;
62232bf4
GH		 1297
1298 vdc->reset = virtio_gpu_reset;
1299
1300 dc->props = virtio_gpu_properties;
0fc07498 1301 dc->vmsd = &vmstate_virtio_gpu;
a2056e09 1302 dc->hotpluggable = false;
62232bf4
GH		 1303}
1304
1305static const TypeInfo virtio_gpu_info = {
1306 .name = TYPE_VIRTIO_GPU,
1307 .parent = TYPE_VIRTIO_DEVICE,
1308 .instance_size = sizeof(VirtIOGPU),
1309 .instance_init = virtio_gpu_instance_init,
1310 .class_init = virtio_gpu_class_init,
1311};
1312
1313static void virtio_register_types(void)
1314{
1315 type_register_static(&virtio_gpu_info);
1316}
1317
1318type_init(virtio_register_types)
1319
1320QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_ctrl_hdr) != 24);
1321QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_update_cursor) != 56);
1322QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resource_unref) != 32);
1323QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resource_create_2d) != 40);
1324QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_set_scanout) != 48);
1325QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resource_flush) != 48);
1326QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_transfer_to_host_2d) != 56);
1327QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_mem_entry) != 16);
1328QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resource_attach_backing) != 32);
1329QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resource_detach_backing) != 32);
1330QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resp_display_info) != 408);
9d9e1521
GH		 1331
1332QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_transfer_host_3d) != 72);
1333QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resource_create_3d) != 72);
1334QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_ctx_create) != 96);
1335QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_ctx_destroy) != 24);
1336QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_ctx_resource) != 32);
1337QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_cmd_submit) != 32);
1338QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_get_capset_info) != 32);
1339QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resp_capset_info) != 40);
1340QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_get_capset) != 32);
1341QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resp_capset) != 24);
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