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Commit | Line | Data |
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9b8bfe21 | 1 | #include "qemu/osdep.h" |
c5d4dac8 | 2 | #include "hw/pci/pci.h" |
a27bd6c7 | 3 | #include "hw/qdev-properties.h" |
7ecb381f | 4 | #include "hw/virtio/virtio-gpu.h" |
d0f0c865 | 5 | #include "qapi/error.h" |
0b8fa32f | 6 | #include "qemu/module.h" |
c68082c4 | 7 | #include "virtio-vga.h" |
db1015e9 | 8 | #include "qom/object.h" |
c5d4dac8 | 9 | |
c68082c4 | 10 | static void virtio_vga_base_invalidate_display(void *opaque) |
c5d4dac8 | 11 | { |
c68082c4 MAL |
12 | VirtIOVGABase *vvga = opaque; |
13 | VirtIOGPUBase *g = vvga->vgpu; | |
c5d4dac8 | 14 | |
50d8e25e | 15 | if (g->enable) { |
3b593b3f | 16 | g->hw_ops->invalidate(g); |
c5d4dac8 GH |
17 | } else { |
18 | vvga->vga.hw_ops->invalidate(&vvga->vga); | |
19 | } | |
20 | } | |
21 | ||
c68082c4 | 22 | static void virtio_vga_base_update_display(void *opaque) |
c5d4dac8 | 23 | { |
c68082c4 MAL |
24 | VirtIOVGABase *vvga = opaque; |
25 | VirtIOGPUBase *g = vvga->vgpu; | |
c5d4dac8 | 26 | |
50d8e25e | 27 | if (g->enable) { |
3b593b3f | 28 | g->hw_ops->gfx_update(g); |
c5d4dac8 GH |
29 | } else { |
30 | vvga->vga.hw_ops->gfx_update(&vvga->vga); | |
31 | } | |
32 | } | |
33 | ||
c68082c4 | 34 | static void virtio_vga_base_text_update(void *opaque, console_ch_t *chardata) |
c5d4dac8 | 35 | { |
c68082c4 MAL |
36 | VirtIOVGABase *vvga = opaque; |
37 | VirtIOGPUBase *g = vvga->vgpu; | |
c5d4dac8 | 38 | |
50d8e25e | 39 | if (g->enable) { |
3b593b3f GH |
40 | if (g->hw_ops->text_update) { |
41 | g->hw_ops->text_update(g, chardata); | |
c5d4dac8 GH |
42 | } |
43 | } else { | |
44 | if (vvga->vga.hw_ops->text_update) { | |
45 | vvga->vga.hw_ops->text_update(&vvga->vga, chardata); | |
46 | } | |
47 | } | |
48 | } | |
49 | ||
c68082c4 | 50 | static int virtio_vga_base_ui_info(void *opaque, uint32_t idx, QemuUIInfo *info) |
c5d4dac8 | 51 | { |
c68082c4 MAL |
52 | VirtIOVGABase *vvga = opaque; |
53 | VirtIOGPUBase *g = vvga->vgpu; | |
c5d4dac8 | 54 | |
3b593b3f GH |
55 | if (g->hw_ops->ui_info) { |
56 | return g->hw_ops->ui_info(g, idx, info); | |
c5d4dac8 GH |
57 | } |
58 | return -1; | |
59 | } | |
60 | ||
c68082c4 | 61 | static void virtio_vga_base_gl_block(void *opaque, bool block) |
321c9adb | 62 | { |
c68082c4 MAL |
63 | VirtIOVGABase *vvga = opaque; |
64 | VirtIOGPUBase *g = vvga->vgpu; | |
321c9adb | 65 | |
3b593b3f GH |
66 | if (g->hw_ops->gl_block) { |
67 | g->hw_ops->gl_block(g, block); | |
321c9adb GH |
68 | } |
69 | } | |
70 | ||
3cddb8b9 MAL |
71 | static void virtio_vga_base_gl_flushed(void *opaque) |
72 | { | |
73 | VirtIOVGABase *vvga = opaque; | |
74 | VirtIOGPUBase *g = vvga->vgpu; | |
75 | ||
76 | if (g->hw_ops->gl_flushed) { | |
77 | g->hw_ops->gl_flushed(g); | |
78 | } | |
79 | } | |
80 | ||
a7dfbe28 MAL |
81 | static int virtio_vga_base_get_flags(void *opaque) |
82 | { | |
83 | VirtIOVGABase *vvga = opaque; | |
84 | VirtIOGPUBase *g = vvga->vgpu; | |
85 | ||
86 | return g->hw_ops->get_flags(g); | |
87 | } | |
88 | ||
c68082c4 | 89 | static const GraphicHwOps virtio_vga_base_ops = { |
a7dfbe28 | 90 | .get_flags = virtio_vga_base_get_flags, |
c68082c4 MAL |
91 | .invalidate = virtio_vga_base_invalidate_display, |
92 | .gfx_update = virtio_vga_base_update_display, | |
93 | .text_update = virtio_vga_base_text_update, | |
94 | .ui_info = virtio_vga_base_ui_info, | |
95 | .gl_block = virtio_vga_base_gl_block, | |
3cddb8b9 | 96 | .gl_flushed = virtio_vga_base_gl_flushed, |
c5d4dac8 GH |
97 | }; |
98 | ||
c68082c4 | 99 | static const VMStateDescription vmstate_virtio_vga_base = { |
0c244e50 GH |
100 | .name = "virtio-vga", |
101 | .version_id = 2, | |
102 | .minimum_version_id = 2, | |
103 | .fields = (VMStateField[]) { | |
104 | /* no pci stuff here, saving the virtio device will handle that */ | |
c68082c4 MAL |
105 | VMSTATE_STRUCT(vga, VirtIOVGABase, 0, |
106 | vmstate_vga_common, VGACommonState), | |
0c244e50 GH |
107 | VMSTATE_END_OF_LIST() |
108 | } | |
109 | }; | |
110 | ||
c5d4dac8 | 111 | /* VGA device wrapper around PCI device around virtio GPU */ |
c68082c4 | 112 | static void virtio_vga_base_realize(VirtIOPCIProxy *vpci_dev, Error **errp) |
c5d4dac8 | 113 | { |
c68082c4 MAL |
114 | VirtIOVGABase *vvga = VIRTIO_VGA_BASE(vpci_dev); |
115 | VirtIOGPUBase *g = vvga->vgpu; | |
c5d4dac8 GH |
116 | VGACommonState *vga = &vvga->vga; |
117 | uint32_t offset; | |
e1888295 | 118 | int i; |
c5d4dac8 GH |
119 | |
120 | /* init vga compat bits */ | |
121 | vga->vram_size_mb = 8; | |
1fcfdc43 | 122 | vga_common_init(vga, OBJECT(vpci_dev)); |
c5d4dac8 GH |
123 | vga_init(vga, OBJECT(vpci_dev), pci_address_space(&vpci_dev->pci_dev), |
124 | pci_address_space_io(&vpci_dev->pci_dev), true); | |
125 | pci_register_bar(&vpci_dev->pci_dev, 0, | |
126 | PCI_BASE_ADDRESS_MEM_PREFETCH, &vga->vram); | |
127 | ||
128 | /* | |
129 | * Configure virtio bar and regions | |
130 | * | |
131 | * We use bar #2 for the mmio regions, to be compatible with stdvga. | |
132 | * virtio regions are moved to the end of bar #2, to make room for | |
133 | * the stdvga mmio registers at the start of bar #2. | |
134 | */ | |
7a25126d CF |
135 | vpci_dev->modern_mem_bar_idx = 2; |
136 | vpci_dev->msix_bar_idx = 4; | |
15138b5e | 137 | vpci_dev->modern_io_bar_idx = 5; |
c2843e93 GH |
138 | |
139 | if (!(vpci_dev->flags & VIRTIO_PCI_FLAG_PAGE_PER_VQ)) { | |
140 | /* | |
141 | * with page-per-vq=off there is no padding space we can use | |
142 | * for the stdvga registers. Make the common and isr regions | |
143 | * smaller then. | |
144 | */ | |
145 | vpci_dev->common.size /= 2; | |
146 | vpci_dev->isr.size /= 2; | |
147 | } | |
148 | ||
c5d4dac8 GH |
149 | offset = memory_region_size(&vpci_dev->modern_bar); |
150 | offset -= vpci_dev->notify.size; | |
151 | vpci_dev->notify.offset = offset; | |
152 | offset -= vpci_dev->device.size; | |
153 | vpci_dev->device.offset = offset; | |
154 | offset -= vpci_dev->isr.size; | |
155 | vpci_dev->isr.offset = offset; | |
156 | offset -= vpci_dev->common.size; | |
157 | vpci_dev->common.offset = offset; | |
158 | ||
159 | /* init virtio bits */ | |
dd56040d | 160 | virtio_pci_force_virtio_1(vpci_dev); |
668f62ec | 161 | if (!qdev_realize(DEVICE(g), BUS(&vpci_dev->bus), errp)) { |
d0f0c865 MAL |
162 | return; |
163 | } | |
c5d4dac8 GH |
164 | |
165 | /* add stdvga mmio regions */ | |
93abfc88 | 166 | pci_std_vga_mmio_region_init(vga, OBJECT(vvga), &vpci_dev->modern_bar, |
d46b40fc | 167 | vvga->vga_mrs, true, false); |
c5d4dac8 GH |
168 | |
169 | vga->con = g->scanout[0].con; | |
c68082c4 | 170 | graphic_console_set_hwops(vga->con, &virtio_vga_base_ops, vvga); |
e1888295 GH |
171 | |
172 | for (i = 0; i < g->conf.max_outputs; i++) { | |
5325cc34 MA |
173 | object_property_set_link(OBJECT(g->scanout[i].con), "device", |
174 | OBJECT(vpci_dev), &error_abort); | |
e1888295 | 175 | } |
c5d4dac8 GH |
176 | } |
177 | ||
c68082c4 | 178 | static void virtio_vga_base_reset(DeviceState *dev) |
c5d4dac8 | 179 | { |
c68082c4 MAL |
180 | VirtIOVGABaseClass *klass = VIRTIO_VGA_BASE_GET_CLASS(dev); |
181 | VirtIOVGABase *vvga = VIRTIO_VGA_BASE(dev); | |
c5d4dac8 | 182 | |
43e4dbe2 | 183 | /* reset virtio-gpu */ |
3912e66a | 184 | klass->parent_reset(dev); |
43e4dbe2 GH |
185 | |
186 | /* reset vga */ | |
187 | vga_common_reset(&vvga->vga); | |
c5d4dac8 GH |
188 | vga_dirty_log_start(&vvga->vga); |
189 | } | |
190 | ||
8be61ce2 GH |
191 | static bool virtio_vga_get_big_endian_fb(Object *obj, Error **errp) |
192 | { | |
193 | VirtIOVGABase *d = VIRTIO_VGA_BASE(obj); | |
194 | ||
195 | return d->vga.big_endian_fb; | |
196 | } | |
197 | ||
198 | static void virtio_vga_set_big_endian_fb(Object *obj, bool value, Error **errp) | |
199 | { | |
200 | VirtIOVGABase *d = VIRTIO_VGA_BASE(obj); | |
201 | ||
202 | d->vga.big_endian_fb = value; | |
203 | } | |
204 | ||
c68082c4 | 205 | static Property virtio_vga_base_properties[] = { |
c5d4dac8 GH |
206 | DEFINE_VIRTIO_GPU_PCI_PROPERTIES(VirtIOPCIProxy), |
207 | DEFINE_PROP_END_OF_LIST(), | |
208 | }; | |
209 | ||
c68082c4 | 210 | static void virtio_vga_base_class_init(ObjectClass *klass, void *data) |
c5d4dac8 GH |
211 | { |
212 | DeviceClass *dc = DEVICE_CLASS(klass); | |
213 | VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass); | |
c68082c4 | 214 | VirtIOVGABaseClass *v = VIRTIO_VGA_BASE_CLASS(klass); |
c5d4dac8 GH |
215 | PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass); |
216 | ||
217 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); | |
4f67d30b | 218 | device_class_set_props(dc, virtio_vga_base_properties); |
c68082c4 | 219 | dc->vmsd = &vmstate_virtio_vga_base; |
c5d4dac8 | 220 | dc->hotpluggable = false; |
c68082c4 | 221 | device_class_set_parent_reset(dc, virtio_vga_base_reset, |
3912e66a | 222 | &v->parent_reset); |
c5d4dac8 | 223 | |
c68082c4 | 224 | k->realize = virtio_vga_base_realize; |
c5d4dac8 GH |
225 | pcidev_k->romfile = "vgabios-virtio.bin"; |
226 | pcidev_k->class_id = PCI_CLASS_DISPLAY_VGA; | |
8be61ce2 GH |
227 | |
228 | /* Expose framebuffer byteorder via QOM */ | |
229 | object_class_property_add_bool(klass, "big-endian-framebuffer", | |
230 | virtio_vga_get_big_endian_fb, | |
231 | virtio_vga_set_big_endian_fb); | |
c5d4dac8 GH |
232 | } |
233 | ||
c68082c4 MAL |
234 | static TypeInfo virtio_vga_base_info = { |
235 | .name = TYPE_VIRTIO_VGA_BASE, | |
236 | .parent = TYPE_VIRTIO_PCI, | |
b84bf23c EH |
237 | .instance_size = sizeof(VirtIOVGABase), |
238 | .class_size = sizeof(VirtIOVGABaseClass), | |
c68082c4 MAL |
239 | .class_init = virtio_vga_base_class_init, |
240 | .abstract = true, | |
241 | }; | |
561d0f45 | 242 | module_obj(TYPE_VIRTIO_VGA_BASE); |
c68082c4 MAL |
243 | |
244 | #define TYPE_VIRTIO_VGA "virtio-vga" | |
245 | ||
db1015e9 | 246 | typedef struct VirtIOVGA VirtIOVGA; |
8110fa1d EH |
247 | DECLARE_INSTANCE_CHECKER(VirtIOVGA, VIRTIO_VGA, |
248 | TYPE_VIRTIO_VGA) | |
c68082c4 | 249 | |
db1015e9 | 250 | struct VirtIOVGA { |
c68082c4 MAL |
251 | VirtIOVGABase parent_obj; |
252 | ||
253 | VirtIOGPU vdev; | |
db1015e9 | 254 | }; |
c68082c4 | 255 | |
c5d4dac8 GH |
256 | static void virtio_vga_inst_initfn(Object *obj) |
257 | { | |
258 | VirtIOVGA *dev = VIRTIO_VGA(obj); | |
b3409a31 GH |
259 | |
260 | virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev), | |
261 | TYPE_VIRTIO_GPU); | |
c68082c4 | 262 | VIRTIO_VGA_BASE(dev)->vgpu = VIRTIO_GPU_BASE(&dev->vdev); |
c5d4dac8 GH |
263 | } |
264 | ||
c68082c4 | 265 | |
a4ee4c8b EH |
266 | static VirtioPCIDeviceTypeInfo virtio_vga_info = { |
267 | .generic_name = TYPE_VIRTIO_VGA, | |
c68082c4 | 268 | .parent = TYPE_VIRTIO_VGA_BASE, |
b84bf23c | 269 | .instance_size = sizeof(VirtIOVGA), |
c5d4dac8 | 270 | .instance_init = virtio_vga_inst_initfn, |
c5d4dac8 | 271 | }; |
561d0f45 | 272 | module_obj(TYPE_VIRTIO_VGA); |
c5d4dac8 GH |
273 | |
274 | static void virtio_vga_register_types(void) | |
275 | { | |
c68082c4 | 276 | type_register_static(&virtio_vga_base_info); |
a4ee4c8b | 277 | virtio_pci_types_register(&virtio_vga_info); |
c5d4dac8 GH |
278 | } |
279 | ||
280 | type_init(virtio_vga_register_types) |