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d34cab9f TS |
1 | /* |
2 | * QEMU VMware-SVGA "chipset". | |
3 | * | |
4 | * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
47df5154 | 24 | #include "qemu/osdep.h" |
83c9f4ca PB |
25 | #include "hw/hw.h" |
26 | #include "hw/loader.h" | |
ac86048b | 27 | #include "trace.h" |
28ecbaee | 28 | #include "ui/console.h" |
2f487a3d | 29 | #include "ui/vnc.h" |
83c9f4ca | 30 | #include "hw/pci/pci.h" |
d34cab9f | 31 | |
ca0508df | 32 | #undef VERBOSE |
d34cab9f TS |
33 | #define HW_RECT_ACCEL |
34 | #define HW_FILL_ACCEL | |
35 | #define HW_MOUSE_ACCEL | |
36 | ||
47b43a1f | 37 | #include "vga_int.h" |
5b9575c8 BZ |
38 | |
39 | /* See http://vmware-svga.sf.net/ for some documentation on VMWare SVGA */ | |
d34cab9f TS |
40 | |
41 | struct vmsvga_state_s { | |
4e12cd94 | 42 | VGACommonState vga; |
d34cab9f | 43 | |
d34cab9f | 44 | int invalidated; |
d34cab9f TS |
45 | int enable; |
46 | int config; | |
47 | struct { | |
48 | int id; | |
49 | int x; | |
50 | int y; | |
51 | int on; | |
52 | } cursor; | |
53 | ||
d34cab9f TS |
54 | int index; |
55 | int scratch_size; | |
56 | uint32_t *scratch; | |
57 | int new_width; | |
58 | int new_height; | |
eb2f9b02 | 59 | int new_depth; |
d34cab9f TS |
60 | uint32_t guest; |
61 | uint32_t svgaid; | |
d34cab9f | 62 | int syncing; |
d34cab9f | 63 | |
b1950430 | 64 | MemoryRegion fifo_ram; |
f351d050 DA |
65 | uint8_t *fifo_ptr; |
66 | unsigned int fifo_size; | |
f351d050 | 67 | |
d34cab9f TS |
68 | union { |
69 | uint32_t *fifo; | |
541dc0d4 | 70 | struct QEMU_PACKED { |
d34cab9f TS |
71 | uint32_t min; |
72 | uint32_t max; | |
73 | uint32_t next_cmd; | |
74 | uint32_t stop; | |
75 | /* Add registers here when adding capabilities. */ | |
76 | uint32_t fifo[0]; | |
77 | } *cmd; | |
78 | }; | |
79 | ||
0d793797 | 80 | #define REDRAW_FIFO_LEN 512 |
d34cab9f TS |
81 | struct vmsvga_rect_s { |
82 | int x, y, w, h; | |
83 | } redraw_fifo[REDRAW_FIFO_LEN]; | |
84 | int redraw_fifo_first, redraw_fifo_last; | |
85 | }; | |
86 | ||
39d45987 PC |
87 | #define TYPE_VMWARE_SVGA "vmware-svga" |
88 | ||
89 | #define VMWARE_SVGA(obj) \ | |
90 | OBJECT_CHECK(struct pci_vmsvga_state_s, (obj), TYPE_VMWARE_SVGA) | |
91 | ||
d34cab9f | 92 | struct pci_vmsvga_state_s { |
af21c740 AF |
93 | /*< private >*/ |
94 | PCIDevice parent_obj; | |
95 | /*< public >*/ | |
96 | ||
d34cab9f | 97 | struct vmsvga_state_s chip; |
b1950430 | 98 | MemoryRegion io_bar; |
d34cab9f TS |
99 | }; |
100 | ||
0d793797 BZ |
101 | #define SVGA_MAGIC 0x900000UL |
102 | #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) | |
103 | #define SVGA_ID_0 SVGA_MAKE_ID(0) | |
104 | #define SVGA_ID_1 SVGA_MAKE_ID(1) | |
105 | #define SVGA_ID_2 SVGA_MAKE_ID(2) | |
d34cab9f | 106 | |
0d793797 BZ |
107 | #define SVGA_LEGACY_BASE_PORT 0x4560 |
108 | #define SVGA_INDEX_PORT 0x0 | |
109 | #define SVGA_VALUE_PORT 0x1 | |
110 | #define SVGA_BIOS_PORT 0x2 | |
d34cab9f TS |
111 | |
112 | #define SVGA_VERSION_2 | |
113 | ||
114 | #ifdef SVGA_VERSION_2 | |
0d793797 BZ |
115 | # define SVGA_ID SVGA_ID_2 |
116 | # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT | |
117 | # define SVGA_IO_MUL 1 | |
118 | # define SVGA_FIFO_SIZE 0x10000 | |
119 | # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2 | |
d34cab9f | 120 | #else |
0d793797 BZ |
121 | # define SVGA_ID SVGA_ID_1 |
122 | # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT | |
123 | # define SVGA_IO_MUL 4 | |
124 | # define SVGA_FIFO_SIZE 0x10000 | |
125 | # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA | |
d34cab9f TS |
126 | #endif |
127 | ||
128 | enum { | |
129 | /* ID 0, 1 and 2 registers */ | |
130 | SVGA_REG_ID = 0, | |
131 | SVGA_REG_ENABLE = 1, | |
132 | SVGA_REG_WIDTH = 2, | |
133 | SVGA_REG_HEIGHT = 3, | |
134 | SVGA_REG_MAX_WIDTH = 4, | |
135 | SVGA_REG_MAX_HEIGHT = 5, | |
136 | SVGA_REG_DEPTH = 6, | |
0d793797 | 137 | SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ |
d34cab9f TS |
138 | SVGA_REG_PSEUDOCOLOR = 8, |
139 | SVGA_REG_RED_MASK = 9, | |
140 | SVGA_REG_GREEN_MASK = 10, | |
141 | SVGA_REG_BLUE_MASK = 11, | |
142 | SVGA_REG_BYTES_PER_LINE = 12, | |
143 | SVGA_REG_FB_START = 13, | |
144 | SVGA_REG_FB_OFFSET = 14, | |
145 | SVGA_REG_VRAM_SIZE = 15, | |
146 | SVGA_REG_FB_SIZE = 16, | |
147 | ||
148 | /* ID 1 and 2 registers */ | |
149 | SVGA_REG_CAPABILITIES = 17, | |
0d793797 | 150 | SVGA_REG_MEM_START = 18, /* Memory for command FIFO */ |
d34cab9f | 151 | SVGA_REG_MEM_SIZE = 19, |
0d793797 BZ |
152 | SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ |
153 | SVGA_REG_SYNC = 21, /* Write to force synchronization */ | |
154 | SVGA_REG_BUSY = 22, /* Read to check if sync is done */ | |
155 | SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ | |
156 | SVGA_REG_CURSOR_ID = 24, /* ID of cursor */ | |
157 | SVGA_REG_CURSOR_X = 25, /* Set cursor X position */ | |
158 | SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */ | |
159 | SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */ | |
160 | SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */ | |
161 | SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ | |
162 | SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ | |
163 | SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */ | |
164 | SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ | |
165 | ||
166 | SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ | |
d34cab9f TS |
167 | SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767, |
168 | SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768, | |
169 | }; | |
170 | ||
0d793797 BZ |
171 | #define SVGA_CAP_NONE 0 |
172 | #define SVGA_CAP_RECT_FILL (1 << 0) | |
173 | #define SVGA_CAP_RECT_COPY (1 << 1) | |
174 | #define SVGA_CAP_RECT_PAT_FILL (1 << 2) | |
175 | #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3) | |
176 | #define SVGA_CAP_RASTER_OP (1 << 4) | |
177 | #define SVGA_CAP_CURSOR (1 << 5) | |
178 | #define SVGA_CAP_CURSOR_BYPASS (1 << 6) | |
179 | #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7) | |
180 | #define SVGA_CAP_8BIT_EMULATION (1 << 8) | |
181 | #define SVGA_CAP_ALPHA_CURSOR (1 << 9) | |
182 | #define SVGA_CAP_GLYPH (1 << 10) | |
183 | #define SVGA_CAP_GLYPH_CLIPPING (1 << 11) | |
184 | #define SVGA_CAP_OFFSCREEN_1 (1 << 12) | |
185 | #define SVGA_CAP_ALPHA_BLEND (1 << 13) | |
186 | #define SVGA_CAP_3D (1 << 14) | |
187 | #define SVGA_CAP_EXTENDED_FIFO (1 << 15) | |
188 | #define SVGA_CAP_MULTIMON (1 << 16) | |
189 | #define SVGA_CAP_PITCHLOCK (1 << 17) | |
d34cab9f TS |
190 | |
191 | /* | |
192 | * FIFO offsets (seen as an array of 32-bit words) | |
193 | */ | |
194 | enum { | |
195 | /* | |
196 | * The original defined FIFO offsets | |
197 | */ | |
198 | SVGA_FIFO_MIN = 0, | |
0d793797 | 199 | SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */ |
d34cab9f TS |
200 | SVGA_FIFO_NEXT_CMD, |
201 | SVGA_FIFO_STOP, | |
202 | ||
203 | /* | |
204 | * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO | |
205 | */ | |
206 | SVGA_FIFO_CAPABILITIES = 4, | |
207 | SVGA_FIFO_FLAGS, | |
208 | SVGA_FIFO_FENCE, | |
209 | SVGA_FIFO_3D_HWVERSION, | |
210 | SVGA_FIFO_PITCHLOCK, | |
211 | }; | |
212 | ||
0d793797 BZ |
213 | #define SVGA_FIFO_CAP_NONE 0 |
214 | #define SVGA_FIFO_CAP_FENCE (1 << 0) | |
215 | #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1) | |
216 | #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2) | |
d34cab9f | 217 | |
0d793797 BZ |
218 | #define SVGA_FIFO_FLAG_NONE 0 |
219 | #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0) | |
d34cab9f TS |
220 | |
221 | /* These values can probably be changed arbitrarily. */ | |
0d793797 | 222 | #define SVGA_SCRATCH_SIZE 0x8000 |
2f487a3d | 223 | #define SVGA_MAX_WIDTH ROUND_UP(2360, VNC_DIRTY_PIXELS_PER_BIT) |
0d793797 | 224 | #define SVGA_MAX_HEIGHT 1770 |
d34cab9f TS |
225 | |
226 | #ifdef VERBOSE | |
0d793797 | 227 | # define GUEST_OS_BASE 0x5001 |
d34cab9f | 228 | static const char *vmsvga_guest_id[] = { |
f707cfba AZ |
229 | [0x00] = "Dos", |
230 | [0x01] = "Windows 3.1", | |
231 | [0x02] = "Windows 95", | |
232 | [0x03] = "Windows 98", | |
233 | [0x04] = "Windows ME", | |
234 | [0x05] = "Windows NT", | |
235 | [0x06] = "Windows 2000", | |
236 | [0x07] = "Linux", | |
237 | [0x08] = "OS/2", | |
511d2b14 | 238 | [0x09] = "an unknown OS", |
f707cfba AZ |
239 | [0x0a] = "BSD", |
240 | [0x0b] = "Whistler", | |
511d2b14 BS |
241 | [0x0c] = "an unknown OS", |
242 | [0x0d] = "an unknown OS", | |
243 | [0x0e] = "an unknown OS", | |
244 | [0x0f] = "an unknown OS", | |
245 | [0x10] = "an unknown OS", | |
246 | [0x11] = "an unknown OS", | |
247 | [0x12] = "an unknown OS", | |
248 | [0x13] = "an unknown OS", | |
249 | [0x14] = "an unknown OS", | |
f707cfba | 250 | [0x15] = "Windows 2003", |
d34cab9f TS |
251 | }; |
252 | #endif | |
253 | ||
254 | enum { | |
255 | SVGA_CMD_INVALID_CMD = 0, | |
256 | SVGA_CMD_UPDATE = 1, | |
257 | SVGA_CMD_RECT_FILL = 2, | |
258 | SVGA_CMD_RECT_COPY = 3, | |
259 | SVGA_CMD_DEFINE_BITMAP = 4, | |
260 | SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5, | |
261 | SVGA_CMD_DEFINE_PIXMAP = 6, | |
262 | SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7, | |
263 | SVGA_CMD_RECT_BITMAP_FILL = 8, | |
264 | SVGA_CMD_RECT_PIXMAP_FILL = 9, | |
265 | SVGA_CMD_RECT_BITMAP_COPY = 10, | |
266 | SVGA_CMD_RECT_PIXMAP_COPY = 11, | |
267 | SVGA_CMD_FREE_OBJECT = 12, | |
268 | SVGA_CMD_RECT_ROP_FILL = 13, | |
269 | SVGA_CMD_RECT_ROP_COPY = 14, | |
270 | SVGA_CMD_RECT_ROP_BITMAP_FILL = 15, | |
271 | SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16, | |
272 | SVGA_CMD_RECT_ROP_BITMAP_COPY = 17, | |
273 | SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18, | |
274 | SVGA_CMD_DEFINE_CURSOR = 19, | |
275 | SVGA_CMD_DISPLAY_CURSOR = 20, | |
276 | SVGA_CMD_MOVE_CURSOR = 21, | |
277 | SVGA_CMD_DEFINE_ALPHA_CURSOR = 22, | |
278 | SVGA_CMD_DRAW_GLYPH = 23, | |
279 | SVGA_CMD_DRAW_GLYPH_CLIPPED = 24, | |
280 | SVGA_CMD_UPDATE_VERBOSE = 25, | |
281 | SVGA_CMD_SURFACE_FILL = 26, | |
282 | SVGA_CMD_SURFACE_COPY = 27, | |
283 | SVGA_CMD_SURFACE_ALPHA_BLEND = 28, | |
284 | SVGA_CMD_FRONT_ROP_FILL = 29, | |
285 | SVGA_CMD_FENCE = 30, | |
286 | }; | |
287 | ||
288 | /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */ | |
289 | enum { | |
290 | SVGA_CURSOR_ON_HIDE = 0, | |
291 | SVGA_CURSOR_ON_SHOW = 1, | |
292 | SVGA_CURSOR_ON_REMOVE_FROM_FB = 2, | |
293 | SVGA_CURSOR_ON_RESTORE_TO_FB = 3, | |
294 | }; | |
295 | ||
07258900 GH |
296 | static inline bool vmsvga_verify_rect(DisplaySurface *surface, |
297 | const char *name, | |
298 | int x, int y, int w, int h) | |
299 | { | |
300 | if (x < 0) { | |
301 | fprintf(stderr, "%s: x was < 0 (%d)\n", name, x); | |
302 | return false; | |
303 | } | |
304 | if (x > SVGA_MAX_WIDTH) { | |
305 | fprintf(stderr, "%s: x was > %d (%d)\n", name, SVGA_MAX_WIDTH, x); | |
306 | return false; | |
307 | } | |
308 | if (w < 0) { | |
309 | fprintf(stderr, "%s: w was < 0 (%d)\n", name, w); | |
310 | return false; | |
311 | } | |
312 | if (w > SVGA_MAX_WIDTH) { | |
313 | fprintf(stderr, "%s: w was > %d (%d)\n", name, SVGA_MAX_WIDTH, w); | |
314 | return false; | |
315 | } | |
316 | if (x + w > surface_width(surface)) { | |
317 | fprintf(stderr, "%s: width was > %d (x: %d, w: %d)\n", | |
318 | name, surface_width(surface), x, w); | |
319 | return false; | |
320 | } | |
321 | ||
322 | if (y < 0) { | |
323 | fprintf(stderr, "%s: y was < 0 (%d)\n", name, y); | |
324 | return false; | |
325 | } | |
326 | if (y > SVGA_MAX_HEIGHT) { | |
327 | fprintf(stderr, "%s: y was > %d (%d)\n", name, SVGA_MAX_HEIGHT, y); | |
328 | return false; | |
329 | } | |
330 | if (h < 0) { | |
331 | fprintf(stderr, "%s: h was < 0 (%d)\n", name, h); | |
332 | return false; | |
333 | } | |
334 | if (h > SVGA_MAX_HEIGHT) { | |
335 | fprintf(stderr, "%s: h was > %d (%d)\n", name, SVGA_MAX_HEIGHT, h); | |
336 | return false; | |
337 | } | |
338 | if (y + h > surface_height(surface)) { | |
339 | fprintf(stderr, "%s: update height > %d (y: %d, h: %d)\n", | |
340 | name, surface_height(surface), y, h); | |
341 | return false; | |
342 | } | |
343 | ||
344 | return true; | |
345 | } | |
346 | ||
d34cab9f | 347 | static inline void vmsvga_update_rect(struct vmsvga_state_s *s, |
07258900 | 348 | int x, int y, int w, int h) |
d34cab9f | 349 | { |
c78f7137 | 350 | DisplaySurface *surface = qemu_console_surface(s->vga.con); |
a8fbaf96 AZ |
351 | int line; |
352 | int bypl; | |
353 | int width; | |
354 | int start; | |
355 | uint8_t *src; | |
356 | uint8_t *dst; | |
357 | ||
1735fe1e GH |
358 | if (!vmsvga_verify_rect(surface, __func__, x, y, w, h)) { |
359 | /* go for a fullscreen update as fallback */ | |
8cb6bfb5 | 360 | x = 0; |
8cb6bfb5 | 361 | y = 0; |
1735fe1e GH |
362 | w = surface_width(surface); |
363 | h = surface_height(surface); | |
a8fbaf96 AZ |
364 | } |
365 | ||
c78f7137 GH |
366 | bypl = surface_stride(surface); |
367 | width = surface_bytes_per_pixel(surface) * w; | |
368 | start = surface_bytes_per_pixel(surface) * x + bypl * y; | |
4e12cd94 | 369 | src = s->vga.vram_ptr + start; |
c78f7137 | 370 | dst = surface_data(surface) + start; |
d34cab9f | 371 | |
0d793797 | 372 | for (line = h; line > 0; line--, src += bypl, dst += bypl) { |
d34cab9f | 373 | memcpy(dst, src, width); |
0d793797 | 374 | } |
c78f7137 | 375 | dpy_gfx_update(s->vga.con, x, y, w, h); |
d34cab9f TS |
376 | } |
377 | ||
d34cab9f TS |
378 | static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s, |
379 | int x, int y, int w, int h) | |
380 | { | |
0d793797 BZ |
381 | struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last++]; |
382 | ||
d34cab9f TS |
383 | s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1; |
384 | rect->x = x; | |
385 | rect->y = y; | |
386 | rect->w = w; | |
387 | rect->h = h; | |
388 | } | |
d34cab9f TS |
389 | |
390 | static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s) | |
391 | { | |
392 | struct vmsvga_rect_s *rect; | |
0d793797 | 393 | |
d34cab9f TS |
394 | if (s->invalidated) { |
395 | s->redraw_fifo_first = s->redraw_fifo_last; | |
396 | return; | |
397 | } | |
398 | /* Overlapping region updates can be optimised out here - if someone | |
399 | * knows a smart algorithm to do that, please share. */ | |
400 | while (s->redraw_fifo_first != s->redraw_fifo_last) { | |
0d793797 | 401 | rect = &s->redraw_fifo[s->redraw_fifo_first++]; |
d34cab9f TS |
402 | s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1; |
403 | vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h); | |
404 | } | |
405 | } | |
406 | ||
407 | #ifdef HW_RECT_ACCEL | |
61b41b4c | 408 | static inline int vmsvga_copy_rect(struct vmsvga_state_s *s, |
d34cab9f TS |
409 | int x0, int y0, int x1, int y1, int w, int h) |
410 | { | |
c78f7137 | 411 | DisplaySurface *surface = qemu_console_surface(s->vga.con); |
4e12cd94 | 412 | uint8_t *vram = s->vga.vram_ptr; |
c78f7137 GH |
413 | int bypl = surface_stride(surface); |
414 | int bypp = surface_bytes_per_pixel(surface); | |
aa32b38c | 415 | int width = bypp * w; |
d34cab9f TS |
416 | int line = h; |
417 | uint8_t *ptr[2]; | |
418 | ||
61b41b4c GH |
419 | if (!vmsvga_verify_rect(surface, "vmsvga_copy_rect/src", x0, y0, w, h)) { |
420 | return -1; | |
421 | } | |
422 | if (!vmsvga_verify_rect(surface, "vmsvga_copy_rect/dst", x1, y1, w, h)) { | |
423 | return -1; | |
424 | } | |
425 | ||
8d121d49 | 426 | if (y1 > y0) { |
aa32b38c BZ |
427 | ptr[0] = vram + bypp * x0 + bypl * (y0 + h - 1); |
428 | ptr[1] = vram + bypp * x1 + bypl * (y1 + h - 1); | |
8d121d49 JK |
429 | for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) { |
430 | memmove(ptr[1], ptr[0], width); | |
431 | } | |
432 | } else { | |
aa32b38c BZ |
433 | ptr[0] = vram + bypp * x0 + bypl * y0; |
434 | ptr[1] = vram + bypp * x1 + bypl * y1; | |
8d121d49 JK |
435 | for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) { |
436 | memmove(ptr[1], ptr[0], width); | |
d34cab9f TS |
437 | } |
438 | } | |
439 | ||
440 | vmsvga_update_rect_delayed(s, x1, y1, w, h); | |
61b41b4c | 441 | return 0; |
d34cab9f TS |
442 | } |
443 | #endif | |
444 | ||
445 | #ifdef HW_FILL_ACCEL | |
bd9ccd85 | 446 | static inline int vmsvga_fill_rect(struct vmsvga_state_s *s, |
d34cab9f TS |
447 | uint32_t c, int x, int y, int w, int h) |
448 | { | |
c78f7137 GH |
449 | DisplaySurface *surface = qemu_console_surface(s->vga.con); |
450 | int bypl = surface_stride(surface); | |
451 | int width = surface_bytes_per_pixel(surface) * w; | |
d34cab9f TS |
452 | int line = h; |
453 | int column; | |
aa32b38c | 454 | uint8_t *fst; |
d34cab9f TS |
455 | uint8_t *dst; |
456 | uint8_t *src; | |
457 | uint8_t col[4]; | |
458 | ||
bd9ccd85 GH |
459 | if (!vmsvga_verify_rect(surface, __func__, x, y, w, h)) { |
460 | return -1; | |
461 | } | |
462 | ||
8d121d49 JK |
463 | col[0] = c; |
464 | col[1] = c >> 8; | |
465 | col[2] = c >> 16; | |
466 | col[3] = c >> 24; | |
467 | ||
c78f7137 | 468 | fst = s->vga.vram_ptr + surface_bytes_per_pixel(surface) * x + bypl * y; |
aa32b38c | 469 | |
8d121d49 JK |
470 | if (line--) { |
471 | dst = fst; | |
472 | src = col; | |
473 | for (column = width; column > 0; column--) { | |
474 | *(dst++) = *(src++); | |
c78f7137 | 475 | if (src - col == surface_bytes_per_pixel(surface)) { |
8d121d49 | 476 | src = col; |
d34cab9f TS |
477 | } |
478 | } | |
8d121d49 JK |
479 | dst = fst; |
480 | for (; line > 0; line--) { | |
481 | dst += bypl; | |
482 | memcpy(dst, fst, width); | |
483 | } | |
d34cab9f TS |
484 | } |
485 | ||
486 | vmsvga_update_rect_delayed(s, x, y, w, h); | |
bd9ccd85 | 487 | return 0; |
d34cab9f TS |
488 | } |
489 | #endif | |
490 | ||
491 | struct vmsvga_cursor_definition_s { | |
5829b097 GH |
492 | uint32_t width; |
493 | uint32_t height; | |
d34cab9f | 494 | int id; |
5829b097 | 495 | uint32_t bpp; |
d34cab9f TS |
496 | int hot_x; |
497 | int hot_y; | |
498 | uint32_t mask[1024]; | |
8095cb3e | 499 | uint32_t image[4096]; |
d34cab9f TS |
500 | }; |
501 | ||
0d793797 BZ |
502 | #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h)) |
503 | #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h)) | |
d34cab9f TS |
504 | |
505 | #ifdef HW_MOUSE_ACCEL | |
506 | static inline void vmsvga_cursor_define(struct vmsvga_state_s *s, | |
507 | struct vmsvga_cursor_definition_s *c) | |
508 | { | |
fbe6d7a4 GH |
509 | QEMUCursor *qc; |
510 | int i, pixels; | |
511 | ||
512 | qc = cursor_alloc(c->width, c->height); | |
513 | qc->hot_x = c->hot_x; | |
514 | qc->hot_y = c->hot_y; | |
515 | switch (c->bpp) { | |
516 | case 1: | |
0d793797 BZ |
517 | cursor_set_mono(qc, 0xffffff, 0x000000, (void *)c->image, |
518 | 1, (void *)c->mask); | |
fbe6d7a4 GH |
519 | #ifdef DEBUG |
520 | cursor_print_ascii_art(qc, "vmware/mono"); | |
521 | #endif | |
522 | break; | |
523 | case 32: | |
524 | /* fill alpha channel from mask, set color to zero */ | |
0d793797 BZ |
525 | cursor_set_mono(qc, 0x000000, 0x000000, (void *)c->mask, |
526 | 1, (void *)c->mask); | |
fbe6d7a4 GH |
527 | /* add in rgb values */ |
528 | pixels = c->width * c->height; | |
529 | for (i = 0; i < pixels; i++) { | |
530 | qc->data[i] |= c->image[i] & 0xffffff; | |
531 | } | |
532 | #ifdef DEBUG | |
533 | cursor_print_ascii_art(qc, "vmware/32bit"); | |
534 | #endif | |
535 | break; | |
536 | default: | |
537 | fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n", | |
0d793797 | 538 | __func__, c->bpp); |
fbe6d7a4 GH |
539 | cursor_put(qc); |
540 | qc = cursor_builtin_left_ptr(); | |
541 | } | |
d34cab9f | 542 | |
c78f7137 | 543 | dpy_cursor_define(s->vga.con, qc); |
fbe6d7a4 | 544 | cursor_put(qc); |
d34cab9f TS |
545 | } |
546 | #endif | |
547 | ||
0d793797 | 548 | #define CMD(f) le32_to_cpu(s->cmd->f) |
ff9cf2cb | 549 | |
4dedc07f | 550 | static inline int vmsvga_fifo_length(struct vmsvga_state_s *s) |
d34cab9f | 551 | { |
4dedc07f | 552 | int num; |
0d793797 BZ |
553 | |
554 | if (!s->config || !s->enable) { | |
4dedc07f | 555 | return 0; |
0d793797 | 556 | } |
4dedc07f | 557 | num = CMD(next_cmd) - CMD(stop); |
0d793797 | 558 | if (num < 0) { |
4dedc07f | 559 | num += CMD(max) - CMD(min); |
0d793797 | 560 | } |
4dedc07f | 561 | return num >> 2; |
d34cab9f TS |
562 | } |
563 | ||
ff9cf2cb | 564 | static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s) |
d34cab9f | 565 | { |
ff9cf2cb | 566 | uint32_t cmd = s->fifo[CMD(stop) >> 2]; |
0d793797 | 567 | |
ff9cf2cb | 568 | s->cmd->stop = cpu_to_le32(CMD(stop) + 4); |
0d793797 | 569 | if (CMD(stop) >= CMD(max)) { |
d34cab9f | 570 | s->cmd->stop = s->cmd->min; |
0d793797 | 571 | } |
d34cab9f TS |
572 | return cmd; |
573 | } | |
574 | ||
ff9cf2cb AZ |
575 | static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s) |
576 | { | |
577 | return le32_to_cpu(vmsvga_fifo_read_raw(s)); | |
578 | } | |
579 | ||
d34cab9f TS |
580 | static void vmsvga_fifo_run(struct vmsvga_state_s *s) |
581 | { | |
582 | uint32_t cmd, colour; | |
4dedc07f | 583 | int args, len; |
d34cab9f TS |
584 | int x, y, dx, dy, width, height; |
585 | struct vmsvga_cursor_definition_s cursor; | |
4dedc07f AZ |
586 | uint32_t cmd_start; |
587 | ||
588 | len = vmsvga_fifo_length(s); | |
589 | while (len > 0) { | |
590 | /* May need to go back to the start of the command if incomplete */ | |
591 | cmd_start = s->cmd->stop; | |
592 | ||
d34cab9f TS |
593 | switch (cmd = vmsvga_fifo_read(s)) { |
594 | case SVGA_CMD_UPDATE: | |
595 | case SVGA_CMD_UPDATE_VERBOSE: | |
4dedc07f | 596 | len -= 5; |
0d793797 | 597 | if (len < 0) { |
4dedc07f | 598 | goto rewind; |
0d793797 | 599 | } |
4dedc07f | 600 | |
d34cab9f TS |
601 | x = vmsvga_fifo_read(s); |
602 | y = vmsvga_fifo_read(s); | |
603 | width = vmsvga_fifo_read(s); | |
604 | height = vmsvga_fifo_read(s); | |
605 | vmsvga_update_rect_delayed(s, x, y, width, height); | |
606 | break; | |
607 | ||
608 | case SVGA_CMD_RECT_FILL: | |
4dedc07f | 609 | len -= 6; |
0d793797 | 610 | if (len < 0) { |
4dedc07f | 611 | goto rewind; |
0d793797 | 612 | } |
4dedc07f | 613 | |
d34cab9f TS |
614 | colour = vmsvga_fifo_read(s); |
615 | x = vmsvga_fifo_read(s); | |
616 | y = vmsvga_fifo_read(s); | |
617 | width = vmsvga_fifo_read(s); | |
618 | height = vmsvga_fifo_read(s); | |
619 | #ifdef HW_FILL_ACCEL | |
bd9ccd85 GH |
620 | if (vmsvga_fill_rect(s, colour, x, y, width, height) == 0) { |
621 | break; | |
622 | } | |
623 | #endif | |
4dedc07f | 624 | args = 0; |
d34cab9f | 625 | goto badcmd; |
d34cab9f TS |
626 | |
627 | case SVGA_CMD_RECT_COPY: | |
4dedc07f | 628 | len -= 7; |
0d793797 | 629 | if (len < 0) { |
4dedc07f | 630 | goto rewind; |
0d793797 | 631 | } |
4dedc07f | 632 | |
d34cab9f TS |
633 | x = vmsvga_fifo_read(s); |
634 | y = vmsvga_fifo_read(s); | |
635 | dx = vmsvga_fifo_read(s); | |
636 | dy = vmsvga_fifo_read(s); | |
637 | width = vmsvga_fifo_read(s); | |
638 | height = vmsvga_fifo_read(s); | |
639 | #ifdef HW_RECT_ACCEL | |
61b41b4c GH |
640 | if (vmsvga_copy_rect(s, x, y, dx, dy, width, height) == 0) { |
641 | break; | |
642 | } | |
643 | #endif | |
4dedc07f | 644 | args = 0; |
d34cab9f | 645 | goto badcmd; |
d34cab9f TS |
646 | |
647 | case SVGA_CMD_DEFINE_CURSOR: | |
4dedc07f | 648 | len -= 8; |
0d793797 | 649 | if (len < 0) { |
4dedc07f | 650 | goto rewind; |
0d793797 | 651 | } |
4dedc07f | 652 | |
d34cab9f TS |
653 | cursor.id = vmsvga_fifo_read(s); |
654 | cursor.hot_x = vmsvga_fifo_read(s); | |
655 | cursor.hot_y = vmsvga_fifo_read(s); | |
656 | cursor.width = x = vmsvga_fifo_read(s); | |
657 | cursor.height = y = vmsvga_fifo_read(s); | |
658 | vmsvga_fifo_read(s); | |
659 | cursor.bpp = vmsvga_fifo_read(s); | |
f2d928d4 | 660 | |
4dedc07f | 661 | args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp); |
5829b097 GH |
662 | if (cursor.width > 256 || |
663 | cursor.height > 256 || | |
664 | cursor.bpp > 32 || | |
665 | SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask || | |
0d793797 | 666 | SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image) { |
9f810beb | 667 | goto badcmd; |
0d793797 | 668 | } |
4dedc07f AZ |
669 | |
670 | len -= args; | |
0d793797 | 671 | if (len < 0) { |
4dedc07f | 672 | goto rewind; |
0d793797 | 673 | } |
f2d928d4 | 674 | |
0d793797 | 675 | for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args++) { |
ff9cf2cb | 676 | cursor.mask[args] = vmsvga_fifo_read_raw(s); |
0d793797 BZ |
677 | } |
678 | for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args++) { | |
ff9cf2cb | 679 | cursor.image[args] = vmsvga_fifo_read_raw(s); |
0d793797 | 680 | } |
d34cab9f TS |
681 | #ifdef HW_MOUSE_ACCEL |
682 | vmsvga_cursor_define(s, &cursor); | |
683 | break; | |
684 | #else | |
685 | args = 0; | |
686 | goto badcmd; | |
687 | #endif | |
688 | ||
689 | /* | |
690 | * Other commands that we at least know the number of arguments | |
691 | * for so we can avoid FIFO desync if driver uses them illegally. | |
692 | */ | |
693 | case SVGA_CMD_DEFINE_ALPHA_CURSOR: | |
4dedc07f | 694 | len -= 6; |
0d793797 | 695 | if (len < 0) { |
4dedc07f | 696 | goto rewind; |
0d793797 | 697 | } |
d34cab9f TS |
698 | vmsvga_fifo_read(s); |
699 | vmsvga_fifo_read(s); | |
700 | vmsvga_fifo_read(s); | |
701 | x = vmsvga_fifo_read(s); | |
702 | y = vmsvga_fifo_read(s); | |
703 | args = x * y; | |
704 | goto badcmd; | |
705 | case SVGA_CMD_RECT_ROP_FILL: | |
706 | args = 6; | |
707 | goto badcmd; | |
708 | case SVGA_CMD_RECT_ROP_COPY: | |
709 | args = 7; | |
710 | goto badcmd; | |
711 | case SVGA_CMD_DRAW_GLYPH_CLIPPED: | |
4dedc07f | 712 | len -= 4; |
0d793797 | 713 | if (len < 0) { |
4dedc07f | 714 | goto rewind; |
0d793797 | 715 | } |
d34cab9f TS |
716 | vmsvga_fifo_read(s); |
717 | vmsvga_fifo_read(s); | |
718 | args = 7 + (vmsvga_fifo_read(s) >> 2); | |
719 | goto badcmd; | |
720 | case SVGA_CMD_SURFACE_ALPHA_BLEND: | |
721 | args = 12; | |
722 | goto badcmd; | |
723 | ||
724 | /* | |
725 | * Other commands that are not listed as depending on any | |
726 | * CAPABILITIES bits, but are not described in the README either. | |
727 | */ | |
728 | case SVGA_CMD_SURFACE_FILL: | |
729 | case SVGA_CMD_SURFACE_COPY: | |
730 | case SVGA_CMD_FRONT_ROP_FILL: | |
731 | case SVGA_CMD_FENCE: | |
732 | case SVGA_CMD_INVALID_CMD: | |
733 | break; /* Nop */ | |
734 | ||
735 | default: | |
4dedc07f | 736 | args = 0; |
d34cab9f | 737 | badcmd: |
4dedc07f | 738 | len -= args; |
0d793797 | 739 | if (len < 0) { |
4dedc07f | 740 | goto rewind; |
0d793797 BZ |
741 | } |
742 | while (args--) { | |
d34cab9f | 743 | vmsvga_fifo_read(s); |
0d793797 | 744 | } |
d34cab9f | 745 | printf("%s: Unknown command 0x%02x in SVGA command FIFO\n", |
0d793797 | 746 | __func__, cmd); |
d34cab9f | 747 | break; |
4dedc07f AZ |
748 | |
749 | rewind: | |
750 | s->cmd->stop = cmd_start; | |
751 | break; | |
d34cab9f | 752 | } |
4dedc07f | 753 | } |
d34cab9f TS |
754 | |
755 | s->syncing = 0; | |
756 | } | |
757 | ||
758 | static uint32_t vmsvga_index_read(void *opaque, uint32_t address) | |
759 | { | |
467d44b2 | 760 | struct vmsvga_state_s *s = opaque; |
0d793797 | 761 | |
d34cab9f TS |
762 | return s->index; |
763 | } | |
764 | ||
765 | static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index) | |
766 | { | |
467d44b2 | 767 | struct vmsvga_state_s *s = opaque; |
0d793797 | 768 | |
d34cab9f TS |
769 | s->index = index; |
770 | } | |
771 | ||
772 | static uint32_t vmsvga_value_read(void *opaque, uint32_t address) | |
773 | { | |
774 | uint32_t caps; | |
467d44b2 | 775 | struct vmsvga_state_s *s = opaque; |
c78f7137 | 776 | DisplaySurface *surface = qemu_console_surface(s->vga.con); |
eb2f9b02 | 777 | PixelFormat pf; |
7a6404cd | 778 | uint32_t ret; |
0d793797 | 779 | |
d34cab9f TS |
780 | switch (s->index) { |
781 | case SVGA_REG_ID: | |
7a6404cd GH |
782 | ret = s->svgaid; |
783 | break; | |
d34cab9f TS |
784 | |
785 | case SVGA_REG_ENABLE: | |
7a6404cd GH |
786 | ret = s->enable; |
787 | break; | |
d34cab9f TS |
788 | |
789 | case SVGA_REG_WIDTH: | |
eb2f9b02 | 790 | ret = s->new_width ? s->new_width : surface_width(surface); |
7a6404cd | 791 | break; |
d34cab9f TS |
792 | |
793 | case SVGA_REG_HEIGHT: | |
eb2f9b02 | 794 | ret = s->new_height ? s->new_height : surface_height(surface); |
7a6404cd | 795 | break; |
d34cab9f TS |
796 | |
797 | case SVGA_REG_MAX_WIDTH: | |
7a6404cd GH |
798 | ret = SVGA_MAX_WIDTH; |
799 | break; | |
d34cab9f TS |
800 | |
801 | case SVGA_REG_MAX_HEIGHT: | |
7a6404cd GH |
802 | ret = SVGA_MAX_HEIGHT; |
803 | break; | |
d34cab9f TS |
804 | |
805 | case SVGA_REG_DEPTH: | |
eb2f9b02 | 806 | ret = (s->new_depth == 32) ? 24 : s->new_depth; |
7a6404cd | 807 | break; |
d34cab9f TS |
808 | |
809 | case SVGA_REG_BITS_PER_PIXEL: | |
eb2f9b02 GH |
810 | case SVGA_REG_HOST_BITS_PER_PIXEL: |
811 | ret = s->new_depth; | |
7a6404cd | 812 | break; |
d34cab9f TS |
813 | |
814 | case SVGA_REG_PSEUDOCOLOR: | |
7a6404cd GH |
815 | ret = 0x0; |
816 | break; | |
d34cab9f TS |
817 | |
818 | case SVGA_REG_RED_MASK: | |
eb2f9b02 GH |
819 | pf = qemu_default_pixelformat(s->new_depth); |
820 | ret = pf.rmask; | |
7a6404cd | 821 | break; |
aa32b38c | 822 | |
d34cab9f | 823 | case SVGA_REG_GREEN_MASK: |
eb2f9b02 GH |
824 | pf = qemu_default_pixelformat(s->new_depth); |
825 | ret = pf.gmask; | |
7a6404cd | 826 | break; |
aa32b38c | 827 | |
d34cab9f | 828 | case SVGA_REG_BLUE_MASK: |
eb2f9b02 GH |
829 | pf = qemu_default_pixelformat(s->new_depth); |
830 | ret = pf.bmask; | |
7a6404cd | 831 | break; |
d34cab9f TS |
832 | |
833 | case SVGA_REG_BYTES_PER_LINE: | |
eb2f9b02 GH |
834 | if (s->new_width) { |
835 | ret = (s->new_depth * s->new_width) / 8; | |
836 | } else { | |
837 | ret = surface_stride(surface); | |
838 | } | |
7a6404cd | 839 | break; |
d34cab9f | 840 | |
7b619b9a AK |
841 | case SVGA_REG_FB_START: { |
842 | struct pci_vmsvga_state_s *pci_vmsvga | |
843 | = container_of(s, struct pci_vmsvga_state_s, chip); | |
af21c740 | 844 | ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 1); |
7a6404cd | 845 | break; |
7b619b9a | 846 | } |
d34cab9f TS |
847 | |
848 | case SVGA_REG_FB_OFFSET: | |
7a6404cd GH |
849 | ret = 0x0; |
850 | break; | |
d34cab9f TS |
851 | |
852 | case SVGA_REG_VRAM_SIZE: | |
7a6404cd GH |
853 | ret = s->vga.vram_size; /* No physical VRAM besides the framebuffer */ |
854 | break; | |
d34cab9f TS |
855 | |
856 | case SVGA_REG_FB_SIZE: | |
7a6404cd GH |
857 | ret = s->vga.vram_size; |
858 | break; | |
d34cab9f TS |
859 | |
860 | case SVGA_REG_CAPABILITIES: | |
861 | caps = SVGA_CAP_NONE; | |
862 | #ifdef HW_RECT_ACCEL | |
863 | caps |= SVGA_CAP_RECT_COPY; | |
864 | #endif | |
865 | #ifdef HW_FILL_ACCEL | |
866 | caps |= SVGA_CAP_RECT_FILL; | |
867 | #endif | |
868 | #ifdef HW_MOUSE_ACCEL | |
c78f7137 | 869 | if (dpy_cursor_define_supported(s->vga.con)) { |
d34cab9f TS |
870 | caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | |
871 | SVGA_CAP_CURSOR_BYPASS; | |
bf2fde70 | 872 | } |
d34cab9f | 873 | #endif |
7a6404cd GH |
874 | ret = caps; |
875 | break; | |
d34cab9f | 876 | |
b1950430 AK |
877 | case SVGA_REG_MEM_START: { |
878 | struct pci_vmsvga_state_s *pci_vmsvga | |
879 | = container_of(s, struct pci_vmsvga_state_s, chip); | |
af21c740 | 880 | ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 2); |
7a6404cd | 881 | break; |
b1950430 | 882 | } |
d34cab9f TS |
883 | |
884 | case SVGA_REG_MEM_SIZE: | |
7a6404cd GH |
885 | ret = s->fifo_size; |
886 | break; | |
d34cab9f TS |
887 | |
888 | case SVGA_REG_CONFIG_DONE: | |
7a6404cd GH |
889 | ret = s->config; |
890 | break; | |
d34cab9f TS |
891 | |
892 | case SVGA_REG_SYNC: | |
893 | case SVGA_REG_BUSY: | |
7a6404cd GH |
894 | ret = s->syncing; |
895 | break; | |
d34cab9f TS |
896 | |
897 | case SVGA_REG_GUEST_ID: | |
7a6404cd GH |
898 | ret = s->guest; |
899 | break; | |
d34cab9f TS |
900 | |
901 | case SVGA_REG_CURSOR_ID: | |
7a6404cd GH |
902 | ret = s->cursor.id; |
903 | break; | |
d34cab9f TS |
904 | |
905 | case SVGA_REG_CURSOR_X: | |
7a6404cd GH |
906 | ret = s->cursor.x; |
907 | break; | |
d34cab9f TS |
908 | |
909 | case SVGA_REG_CURSOR_Y: | |
e2bb4ae7 | 910 | ret = s->cursor.y; |
7a6404cd | 911 | break; |
d34cab9f TS |
912 | |
913 | case SVGA_REG_CURSOR_ON: | |
7a6404cd GH |
914 | ret = s->cursor.on; |
915 | break; | |
d34cab9f | 916 | |
d34cab9f | 917 | case SVGA_REG_SCRATCH_SIZE: |
7a6404cd GH |
918 | ret = s->scratch_size; |
919 | break; | |
d34cab9f TS |
920 | |
921 | case SVGA_REG_MEM_REGS: | |
922 | case SVGA_REG_NUM_DISPLAYS: | |
923 | case SVGA_REG_PITCHLOCK: | |
924 | case SVGA_PALETTE_BASE ... SVGA_PALETTE_END: | |
7a6404cd GH |
925 | ret = 0; |
926 | break; | |
d34cab9f TS |
927 | |
928 | default: | |
929 | if (s->index >= SVGA_SCRATCH_BASE && | |
0d793797 | 930 | s->index < SVGA_SCRATCH_BASE + s->scratch_size) { |
7a6404cd GH |
931 | ret = s->scratch[s->index - SVGA_SCRATCH_BASE]; |
932 | break; | |
0d793797 BZ |
933 | } |
934 | printf("%s: Bad register %02x\n", __func__, s->index); | |
7a6404cd GH |
935 | ret = 0; |
936 | break; | |
d34cab9f TS |
937 | } |
938 | ||
7a6404cd GH |
939 | if (s->index >= SVGA_SCRATCH_BASE) { |
940 | trace_vmware_scratch_read(s->index, ret); | |
941 | } else if (s->index >= SVGA_PALETTE_BASE) { | |
942 | trace_vmware_palette_read(s->index, ret); | |
943 | } else { | |
944 | trace_vmware_value_read(s->index, ret); | |
945 | } | |
946 | return ret; | |
d34cab9f TS |
947 | } |
948 | ||
949 | static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) | |
950 | { | |
467d44b2 | 951 | struct vmsvga_state_s *s = opaque; |
0d793797 | 952 | |
7a6404cd GH |
953 | if (s->index >= SVGA_SCRATCH_BASE) { |
954 | trace_vmware_scratch_write(s->index, value); | |
955 | } else if (s->index >= SVGA_PALETTE_BASE) { | |
956 | trace_vmware_palette_write(s->index, value); | |
957 | } else { | |
958 | trace_vmware_value_write(s->index, value); | |
959 | } | |
d34cab9f TS |
960 | switch (s->index) { |
961 | case SVGA_REG_ID: | |
0d793797 | 962 | if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0) { |
d34cab9f | 963 | s->svgaid = value; |
0d793797 | 964 | } |
d34cab9f TS |
965 | break; |
966 | ||
967 | case SVGA_REG_ENABLE: | |
b51d7b2e | 968 | s->enable = !!value; |
d34cab9f | 969 | s->invalidated = 1; |
380cd056 | 970 | s->vga.hw_ops->invalidate(&s->vga); |
b51d7b2e | 971 | if (s->enable && s->config) { |
9f810beb AZ |
972 | vga_dirty_log_stop(&s->vga); |
973 | } else { | |
974 | vga_dirty_log_start(&s->vga); | |
975 | } | |
d34cab9f TS |
976 | break; |
977 | ||
978 | case SVGA_REG_WIDTH: | |
aa32b38c BZ |
979 | if (value <= SVGA_MAX_WIDTH) { |
980 | s->new_width = value; | |
981 | s->invalidated = 1; | |
982 | } else { | |
983 | printf("%s: Bad width: %i\n", __func__, value); | |
984 | } | |
d34cab9f TS |
985 | break; |
986 | ||
987 | case SVGA_REG_HEIGHT: | |
aa32b38c BZ |
988 | if (value <= SVGA_MAX_HEIGHT) { |
989 | s->new_height = value; | |
990 | s->invalidated = 1; | |
991 | } else { | |
992 | printf("%s: Bad height: %i\n", __func__, value); | |
993 | } | |
d34cab9f TS |
994 | break; |
995 | ||
d34cab9f | 996 | case SVGA_REG_BITS_PER_PIXEL: |
eb2f9b02 | 997 | if (value != 32) { |
5b9575c8 | 998 | printf("%s: Bad bits per pixel: %i bits\n", __func__, value); |
d34cab9f | 999 | s->config = 0; |
eb2f9b02 | 1000 | s->invalidated = 1; |
d34cab9f TS |
1001 | } |
1002 | break; | |
1003 | ||
1004 | case SVGA_REG_CONFIG_DONE: | |
1005 | if (value) { | |
f351d050 | 1006 | s->fifo = (uint32_t *) s->fifo_ptr; |
d34cab9f | 1007 | /* Check range and alignment. */ |
0d793797 | 1008 | if ((CMD(min) | CMD(max) | CMD(next_cmd) | CMD(stop)) & 3) { |
d34cab9f | 1009 | break; |
0d793797 BZ |
1010 | } |
1011 | if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo) { | |
d34cab9f | 1012 | break; |
0d793797 BZ |
1013 | } |
1014 | if (CMD(max) > SVGA_FIFO_SIZE) { | |
d34cab9f | 1015 | break; |
0d793797 BZ |
1016 | } |
1017 | if (CMD(max) < CMD(min) + 10 * 1024) { | |
d34cab9f | 1018 | break; |
0d793797 | 1019 | } |
b51d7b2e | 1020 | vga_dirty_log_stop(&s->vga); |
d34cab9f | 1021 | } |
f707cfba | 1022 | s->config = !!value; |
d34cab9f TS |
1023 | break; |
1024 | ||
1025 | case SVGA_REG_SYNC: | |
1026 | s->syncing = 1; | |
1027 | vmsvga_fifo_run(s); /* Or should we just wait for update_display? */ | |
1028 | break; | |
1029 | ||
1030 | case SVGA_REG_GUEST_ID: | |
1031 | s->guest = value; | |
1032 | #ifdef VERBOSE | |
1033 | if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE + | |
0d793797 BZ |
1034 | ARRAY_SIZE(vmsvga_guest_id)) { |
1035 | printf("%s: guest runs %s.\n", __func__, | |
1036 | vmsvga_guest_id[value - GUEST_OS_BASE]); | |
1037 | } | |
d34cab9f TS |
1038 | #endif |
1039 | break; | |
1040 | ||
1041 | case SVGA_REG_CURSOR_ID: | |
1042 | s->cursor.id = value; | |
1043 | break; | |
1044 | ||
1045 | case SVGA_REG_CURSOR_X: | |
1046 | s->cursor.x = value; | |
1047 | break; | |
1048 | ||
1049 | case SVGA_REG_CURSOR_Y: | |
1050 | s->cursor.y = value; | |
1051 | break; | |
1052 | ||
1053 | case SVGA_REG_CURSOR_ON: | |
1054 | s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW); | |
1055 | s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE); | |
1056 | #ifdef HW_MOUSE_ACCEL | |
bf2fde70 | 1057 | if (value <= SVGA_CURSOR_ON_SHOW) { |
c78f7137 | 1058 | dpy_mouse_set(s->vga.con, s->cursor.x, s->cursor.y, s->cursor.on); |
bf2fde70 | 1059 | } |
d34cab9f TS |
1060 | #endif |
1061 | break; | |
1062 | ||
5b9575c8 | 1063 | case SVGA_REG_DEPTH: |
d34cab9f TS |
1064 | case SVGA_REG_MEM_REGS: |
1065 | case SVGA_REG_NUM_DISPLAYS: | |
1066 | case SVGA_REG_PITCHLOCK: | |
1067 | case SVGA_PALETTE_BASE ... SVGA_PALETTE_END: | |
1068 | break; | |
1069 | ||
1070 | default: | |
1071 | if (s->index >= SVGA_SCRATCH_BASE && | |
1072 | s->index < SVGA_SCRATCH_BASE + s->scratch_size) { | |
1073 | s->scratch[s->index - SVGA_SCRATCH_BASE] = value; | |
1074 | break; | |
1075 | } | |
0d793797 | 1076 | printf("%s: Bad register %02x\n", __func__, s->index); |
d34cab9f TS |
1077 | } |
1078 | } | |
1079 | ||
1080 | static uint32_t vmsvga_bios_read(void *opaque, uint32_t address) | |
1081 | { | |
0d793797 | 1082 | printf("%s: what are we supposed to return?\n", __func__); |
d34cab9f TS |
1083 | return 0xcafe; |
1084 | } | |
1085 | ||
1086 | static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data) | |
1087 | { | |
0d793797 | 1088 | printf("%s: what are we supposed to do with (%08x)?\n", __func__, data); |
d34cab9f TS |
1089 | } |
1090 | ||
aa32b38c | 1091 | static inline void vmsvga_check_size(struct vmsvga_state_s *s) |
d34cab9f | 1092 | { |
c78f7137 GH |
1093 | DisplaySurface *surface = qemu_console_surface(s->vga.con); |
1094 | ||
1095 | if (s->new_width != surface_width(surface) || | |
eb2f9b02 GH |
1096 | s->new_height != surface_height(surface) || |
1097 | s->new_depth != surface_bits_per_pixel(surface)) { | |
1098 | int stride = (s->new_depth * s->new_width) / 8; | |
30f1e661 GH |
1099 | pixman_format_code_t format = |
1100 | qemu_default_pixman_format(s->new_depth, true); | |
eb2f9b02 GH |
1101 | trace_vmware_setmode(s->new_width, s->new_height, s->new_depth); |
1102 | surface = qemu_create_displaysurface_from(s->new_width, s->new_height, | |
30f1e661 GH |
1103 | format, stride, |
1104 | s->vga.vram_ptr); | |
eb2f9b02 | 1105 | dpy_gfx_replace_surface(s->vga.con, surface); |
d34cab9f TS |
1106 | s->invalidated = 1; |
1107 | } | |
1108 | } | |
1109 | ||
1110 | static void vmsvga_update_display(void *opaque) | |
1111 | { | |
467d44b2 | 1112 | struct vmsvga_state_s *s = opaque; |
17866fc8 | 1113 | DisplaySurface *surface; |
b51d7b2e BZ |
1114 | bool dirty = false; |
1115 | ||
d34cab9f | 1116 | if (!s->enable) { |
380cd056 | 1117 | s->vga.hw_ops->gfx_update(&s->vga); |
d34cab9f TS |
1118 | return; |
1119 | } | |
1120 | ||
aa32b38c | 1121 | vmsvga_check_size(s); |
17866fc8 | 1122 | surface = qemu_console_surface(s->vga.con); |
d34cab9f TS |
1123 | |
1124 | vmsvga_fifo_run(s); | |
1125 | vmsvga_update_rect_flush(s); | |
1126 | ||
1127 | /* | |
1128 | * Is it more efficient to look at vram VGA-dirty bits or wait | |
1129 | * for the driver to issue SVGA_CMD_UPDATE? | |
1130 | */ | |
2d1a35be | 1131 | if (memory_region_is_logging(&s->vga.vram, DIRTY_MEMORY_VGA)) { |
b51d7b2e BZ |
1132 | vga_sync_dirty_bitmap(&s->vga); |
1133 | dirty = memory_region_get_dirty(&s->vga.vram, 0, | |
c78f7137 | 1134 | surface_stride(surface) * surface_height(surface), |
b51d7b2e BZ |
1135 | DIRTY_MEMORY_VGA); |
1136 | } | |
1137 | if (s->invalidated || dirty) { | |
d34cab9f | 1138 | s->invalidated = 0; |
c78f7137 GH |
1139 | dpy_gfx_update(s->vga.con, 0, 0, |
1140 | surface_width(surface), surface_height(surface)); | |
b51d7b2e BZ |
1141 | } |
1142 | if (dirty) { | |
1143 | memory_region_reset_dirty(&s->vga.vram, 0, | |
c78f7137 | 1144 | surface_stride(surface) * surface_height(surface), |
b51d7b2e | 1145 | DIRTY_MEMORY_VGA); |
d34cab9f TS |
1146 | } |
1147 | } | |
1148 | ||
8a9501ba | 1149 | static void vmsvga_reset(DeviceState *dev) |
d34cab9f | 1150 | { |
39d45987 | 1151 | struct pci_vmsvga_state_s *pci = VMWARE_SVGA(dev); |
8a9501ba JK |
1152 | struct vmsvga_state_s *s = &pci->chip; |
1153 | ||
d34cab9f TS |
1154 | s->index = 0; |
1155 | s->enable = 0; | |
1156 | s->config = 0; | |
d34cab9f | 1157 | s->svgaid = SVGA_ID; |
d34cab9f TS |
1158 | s->cursor.on = 0; |
1159 | s->redraw_fifo_first = 0; | |
1160 | s->redraw_fifo_last = 0; | |
d34cab9f | 1161 | s->syncing = 0; |
b5cc6e32 AL |
1162 | |
1163 | vga_dirty_log_start(&s->vga); | |
d34cab9f TS |
1164 | } |
1165 | ||
1166 | static void vmsvga_invalidate_display(void *opaque) | |
1167 | { | |
467d44b2 | 1168 | struct vmsvga_state_s *s = opaque; |
d34cab9f | 1169 | if (!s->enable) { |
380cd056 | 1170 | s->vga.hw_ops->invalidate(&s->vga); |
d34cab9f TS |
1171 | return; |
1172 | } | |
1173 | ||
1174 | s->invalidated = 1; | |
1175 | } | |
1176 | ||
c227f099 | 1177 | static void vmsvga_text_update(void *opaque, console_ch_t *chardata) |
4d3b6f6e | 1178 | { |
467d44b2 | 1179 | struct vmsvga_state_s *s = opaque; |
4d3b6f6e | 1180 | |
380cd056 GH |
1181 | if (s->vga.hw_ops->text_update) { |
1182 | s->vga.hw_ops->text_update(&s->vga, chardata); | |
0d793797 | 1183 | } |
4d3b6f6e AZ |
1184 | } |
1185 | ||
bacbe284 | 1186 | static int vmsvga_post_load(void *opaque, int version_id) |
d34cab9f | 1187 | { |
bacbe284 | 1188 | struct vmsvga_state_s *s = opaque; |
d34cab9f TS |
1189 | |
1190 | s->invalidated = 1; | |
0d793797 | 1191 | if (s->config) { |
f351d050 | 1192 | s->fifo = (uint32_t *) s->fifo_ptr; |
0d793797 | 1193 | } |
d34cab9f TS |
1194 | return 0; |
1195 | } | |
1196 | ||
d05ac8fa | 1197 | static const VMStateDescription vmstate_vmware_vga_internal = { |
bacbe284 JQ |
1198 | .name = "vmware_vga_internal", |
1199 | .version_id = 0, | |
1200 | .minimum_version_id = 0, | |
bacbe284 | 1201 | .post_load = vmsvga_post_load, |
d49805ae | 1202 | .fields = (VMStateField[]) { |
eb2f9b02 | 1203 | VMSTATE_INT32_EQUAL(new_depth, struct vmsvga_state_s), |
bacbe284 JQ |
1204 | VMSTATE_INT32(enable, struct vmsvga_state_s), |
1205 | VMSTATE_INT32(config, struct vmsvga_state_s), | |
1206 | VMSTATE_INT32(cursor.id, struct vmsvga_state_s), | |
1207 | VMSTATE_INT32(cursor.x, struct vmsvga_state_s), | |
1208 | VMSTATE_INT32(cursor.y, struct vmsvga_state_s), | |
1209 | VMSTATE_INT32(cursor.on, struct vmsvga_state_s), | |
1210 | VMSTATE_INT32(index, struct vmsvga_state_s), | |
1211 | VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s, | |
1212 | scratch_size, 0, vmstate_info_uint32, uint32_t), | |
1213 | VMSTATE_INT32(new_width, struct vmsvga_state_s), | |
1214 | VMSTATE_INT32(new_height, struct vmsvga_state_s), | |
1215 | VMSTATE_UINT32(guest, struct vmsvga_state_s), | |
1216 | VMSTATE_UINT32(svgaid, struct vmsvga_state_s), | |
1217 | VMSTATE_INT32(syncing, struct vmsvga_state_s), | |
5b9575c8 | 1218 | VMSTATE_UNUSED(4), /* was fb_size */ |
bacbe284 JQ |
1219 | VMSTATE_END_OF_LIST() |
1220 | } | |
1221 | }; | |
1222 | ||
d05ac8fa | 1223 | static const VMStateDescription vmstate_vmware_vga = { |
bacbe284 JQ |
1224 | .name = "vmware_vga", |
1225 | .version_id = 0, | |
1226 | .minimum_version_id = 0, | |
d49805ae | 1227 | .fields = (VMStateField[]) { |
af21c740 | 1228 | VMSTATE_PCI_DEVICE(parent_obj, struct pci_vmsvga_state_s), |
bacbe284 JQ |
1229 | VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0, |
1230 | vmstate_vmware_vga_internal, struct vmsvga_state_s), | |
1231 | VMSTATE_END_OF_LIST() | |
1232 | } | |
1233 | }; | |
1234 | ||
380cd056 GH |
1235 | static const GraphicHwOps vmsvga_ops = { |
1236 | .invalidate = vmsvga_invalidate_display, | |
1237 | .gfx_update = vmsvga_update_display, | |
1238 | .text_update = vmsvga_text_update, | |
1239 | }; | |
1240 | ||
aa2beaa1 | 1241 | static void vmsvga_init(DeviceState *dev, struct vmsvga_state_s *s, |
0a039dc7 | 1242 | MemoryRegion *address_space, MemoryRegion *io) |
d34cab9f | 1243 | { |
d34cab9f | 1244 | s->scratch_size = SVGA_SCRATCH_SIZE; |
7267c094 | 1245 | s->scratch = g_malloc(s->scratch_size * 4); |
d34cab9f | 1246 | |
5643706a | 1247 | s->vga.con = graphic_console_init(dev, 0, &vmsvga_ops, s); |
4445b0a6 | 1248 | |
f351d050 | 1249 | s->fifo_size = SVGA_FIFO_SIZE; |
49946538 | 1250 | memory_region_init_ram(&s->fifo_ram, NULL, "vmsvga.fifo", s->fifo_size, |
f8ed85ac | 1251 | &error_fatal); |
c5705a77 | 1252 | vmstate_register_ram_global(&s->fifo_ram); |
b1950430 | 1253 | s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram); |
f351d050 | 1254 | |
e2bbfc8e | 1255 | vga_common_init(&s->vga, OBJECT(dev), true); |
712f0cc7 | 1256 | vga_init(&s->vga, OBJECT(dev), address_space, io, true); |
0be71e32 | 1257 | vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga); |
eb2f9b02 | 1258 | s->new_depth = 32; |
d34cab9f TS |
1259 | } |
1260 | ||
aa32b38c | 1261 | static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, unsigned size) |
1492a3c4 | 1262 | { |
b1950430 AK |
1263 | struct vmsvga_state_s *s = opaque; |
1264 | ||
1265 | switch (addr) { | |
1266 | case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr); | |
1267 | case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr); | |
1268 | case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr); | |
1269 | default: return -1u; | |
1270 | } | |
1492a3c4 AZ |
1271 | } |
1272 | ||
a8170e5e | 1273 | static void vmsvga_io_write(void *opaque, hwaddr addr, |
b1950430 | 1274 | uint64_t data, unsigned size) |
3016d80b | 1275 | { |
b1950430 | 1276 | struct vmsvga_state_s *s = opaque; |
ee3e41a9 | 1277 | |
b1950430 AK |
1278 | switch (addr) { |
1279 | case SVGA_IO_MUL * SVGA_INDEX_PORT: | |
0ed8b6f6 BS |
1280 | vmsvga_index_write(s, addr, data); |
1281 | break; | |
b1950430 | 1282 | case SVGA_IO_MUL * SVGA_VALUE_PORT: |
0ed8b6f6 BS |
1283 | vmsvga_value_write(s, addr, data); |
1284 | break; | |
b1950430 | 1285 | case SVGA_IO_MUL * SVGA_BIOS_PORT: |
0ed8b6f6 BS |
1286 | vmsvga_bios_write(s, addr, data); |
1287 | break; | |
b1950430 | 1288 | } |
3016d80b AZ |
1289 | } |
1290 | ||
b1950430 AK |
1291 | static const MemoryRegionOps vmsvga_io_ops = { |
1292 | .read = vmsvga_io_read, | |
1293 | .write = vmsvga_io_write, | |
1294 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1295 | .valid = { | |
1296 | .min_access_size = 4, | |
1297 | .max_access_size = 4, | |
04e8cd50 JK |
1298 | .unaligned = true, |
1299 | }, | |
1300 | .impl = { | |
1301 | .unaligned = true, | |
b1950430 AK |
1302 | }, |
1303 | }; | |
f351d050 | 1304 | |
9af21dbe | 1305 | static void pci_vmsvga_realize(PCIDevice *dev, Error **errp) |
d34cab9f | 1306 | { |
39d45987 | 1307 | struct pci_vmsvga_state_s *s = VMWARE_SVGA(dev); |
b1950430 | 1308 | |
af21c740 AF |
1309 | dev->config[PCI_CACHE_LINE_SIZE] = 0x08; |
1310 | dev->config[PCI_LATENCY_TIMER] = 0x40; | |
1311 | dev->config[PCI_INTERRUPT_LINE] = 0xff; /* End */ | |
d34cab9f | 1312 | |
2c9b15ca | 1313 | memory_region_init_io(&s->io_bar, NULL, &vmsvga_io_ops, &s->chip, |
b1950430 | 1314 | "vmsvga-io", 0x10); |
bd8f2f5d | 1315 | memory_region_set_flush_coalesced(&s->io_bar); |
af21c740 | 1316 | pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); |
f351d050 | 1317 | |
aa2beaa1 GH |
1318 | vmsvga_init(DEVICE(dev), &s->chip, |
1319 | pci_address_space(dev), pci_address_space_io(dev)); | |
d34cab9f | 1320 | |
af21c740 | 1321 | pci_register_bar(dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, |
aa32b38c | 1322 | &s->chip.vga.vram); |
af21c740 | 1323 | pci_register_bar(dev, 2, PCI_BASE_ADDRESS_MEM_PREFETCH, |
e824b2cc | 1324 | &s->chip.fifo_ram); |
b1950430 | 1325 | |
281a26b1 GH |
1326 | if (!dev->rom_bar) { |
1327 | /* compatibility with pc-0.13 and older */ | |
83118327 | 1328 | vga_init_vbe(&s->chip.vga, OBJECT(dev), pci_address_space(dev)); |
281a26b1 | 1329 | } |
d34cab9f | 1330 | } |
a414c306 | 1331 | |
4a1e244e GH |
1332 | static Property vga_vmware_properties[] = { |
1333 | DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s, | |
9e56edcf | 1334 | chip.vga.vram_size_mb, 16), |
4a1e244e GH |
1335 | DEFINE_PROP_END_OF_LIST(), |
1336 | }; | |
1337 | ||
40021f08 AL |
1338 | static void vmsvga_class_init(ObjectClass *klass, void *data) |
1339 | { | |
39bffca2 | 1340 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
1341 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1342 | ||
9af21dbe | 1343 | k->realize = pci_vmsvga_realize; |
40021f08 AL |
1344 | k->romfile = "vgabios-vmware.bin"; |
1345 | k->vendor_id = PCI_VENDOR_ID_VMWARE; | |
1346 | k->device_id = SVGA_PCI_DEVICE_ID; | |
1347 | k->class_id = PCI_CLASS_DISPLAY_VGA; | |
1348 | k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE; | |
1349 | k->subsystem_id = SVGA_PCI_DEVICE_ID; | |
39bffca2 AL |
1350 | dc->reset = vmsvga_reset; |
1351 | dc->vmsd = &vmstate_vmware_vga; | |
4a1e244e | 1352 | dc->props = vga_vmware_properties; |
2897ae02 | 1353 | dc->hotpluggable = false; |
125ee0ed | 1354 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); |
40021f08 AL |
1355 | } |
1356 | ||
8c43a6f0 | 1357 | static const TypeInfo vmsvga_info = { |
39d45987 | 1358 | .name = TYPE_VMWARE_SVGA, |
39bffca2 AL |
1359 | .parent = TYPE_PCI_DEVICE, |
1360 | .instance_size = sizeof(struct pci_vmsvga_state_s), | |
1361 | .class_init = vmsvga_class_init, | |
a414c306 GH |
1362 | }; |
1363 | ||
83f7d43a | 1364 | static void vmsvga_register_types(void) |
a414c306 | 1365 | { |
39bffca2 | 1366 | type_register_static(&vmsvga_info); |
a414c306 | 1367 | } |
83f7d43a AF |
1368 | |
1369 | type_init(vmsvga_register_types) |