]>
Commit | Line | Data |
---|---|---|
27503323 FB |
1 | /* |
2 | * QEMU DMA emulation | |
85571bc7 FB |
3 | * |
4 | * Copyright (c) 2003-2004 Vassili Karpov (malc) | |
5 | * | |
27503323 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
83c9f4ca | 24 | #include "hw/hw.h" |
0d09e41a | 25 | #include "hw/isa/isa.h" |
1de7afc9 | 26 | #include "qemu/main-loop.h" |
7dbb4c49 | 27 | #include "trace.h" |
27503323 | 28 | |
85571bc7 | 29 | /* #define DEBUG_DMA */ |
7ebb5e41 | 30 | |
85571bc7 | 31 | #define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__) |
27503323 | 32 | #ifdef DEBUG_DMA |
27503323 FB |
33 | #define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__) |
34 | #define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__) | |
35 | #else | |
27503323 FB |
36 | #define linfo(...) |
37 | #define ldebug(...) | |
38 | #endif | |
39 | ||
27503323 FB |
40 | struct dma_regs { |
41 | int now[2]; | |
42 | uint16_t base[2]; | |
43 | uint8_t mode; | |
44 | uint8_t page; | |
b0bda528 | 45 | uint8_t pageh; |
27503323 FB |
46 | uint8_t dack; |
47 | uint8_t eop; | |
16f62432 FB |
48 | DMA_transfer_handler transfer_handler; |
49 | void *opaque; | |
27503323 FB |
50 | }; |
51 | ||
52 | #define ADDR 0 | |
53 | #define COUNT 1 | |
54 | ||
55 | static struct dma_cont { | |
56 | uint8_t status; | |
57 | uint8_t command; | |
58 | uint8_t mask; | |
59 | uint8_t flip_flop; | |
9eb153f1 | 60 | int dshift; |
27503323 | 61 | struct dma_regs regs[4]; |
58229933 JG |
62 | MemoryRegion channel_io; |
63 | MemoryRegion cont_io; | |
27503323 FB |
64 | } dma_controllers[2]; |
65 | ||
66 | enum { | |
e875c40a FB |
67 | CMD_MEMORY_TO_MEMORY = 0x01, |
68 | CMD_FIXED_ADDRESS = 0x02, | |
69 | CMD_BLOCK_CONTROLLER = 0x04, | |
70 | CMD_COMPRESSED_TIME = 0x08, | |
71 | CMD_CYCLIC_PRIORITY = 0x10, | |
72 | CMD_EXTENDED_WRITE = 0x20, | |
73 | CMD_LOW_DREQ = 0x40, | |
74 | CMD_LOW_DACK = 0x80, | |
75 | CMD_NOT_SUPPORTED = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS | |
76 | | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE | |
77 | | CMD_LOW_DREQ | CMD_LOW_DACK | |
27503323 FB |
78 | |
79 | }; | |
80 | ||
492c30af AL |
81 | static void DMA_run (void); |
82 | ||
9eb153f1 FB |
83 | static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0}; |
84 | ||
7d977de7 | 85 | static void write_page (void *opaque, uint32_t nport, uint32_t data) |
27503323 | 86 | { |
9eb153f1 | 87 | struct dma_cont *d = opaque; |
27503323 | 88 | int ichan; |
27503323 | 89 | |
9eb153f1 | 90 | ichan = channels[nport & 7]; |
27503323 | 91 | if (-1 == ichan) { |
85571bc7 | 92 | dolog ("invalid channel %#x %#x\n", nport, data); |
27503323 FB |
93 | return; |
94 | } | |
9eb153f1 FB |
95 | d->regs[ichan].page = data; |
96 | } | |
97 | ||
b0bda528 | 98 | static void write_pageh (void *opaque, uint32_t nport, uint32_t data) |
9eb153f1 FB |
99 | { |
100 | struct dma_cont *d = opaque; | |
101 | int ichan; | |
27503323 | 102 | |
9eb153f1 | 103 | ichan = channels[nport & 7]; |
b0bda528 | 104 | if (-1 == ichan) { |
85571bc7 | 105 | dolog ("invalid channel %#x %#x\n", nport, data); |
b0bda528 FB |
106 | return; |
107 | } | |
108 | d->regs[ichan].pageh = data; | |
109 | } | |
9eb153f1 | 110 | |
b0bda528 FB |
111 | static uint32_t read_page (void *opaque, uint32_t nport) |
112 | { | |
113 | struct dma_cont *d = opaque; | |
114 | int ichan; | |
115 | ||
116 | ichan = channels[nport & 7]; | |
9eb153f1 | 117 | if (-1 == ichan) { |
85571bc7 | 118 | dolog ("invalid channel read %#x\n", nport); |
9eb153f1 FB |
119 | return 0; |
120 | } | |
121 | return d->regs[ichan].page; | |
27503323 FB |
122 | } |
123 | ||
b0bda528 FB |
124 | static uint32_t read_pageh (void *opaque, uint32_t nport) |
125 | { | |
126 | struct dma_cont *d = opaque; | |
127 | int ichan; | |
128 | ||
129 | ichan = channels[nport & 7]; | |
130 | if (-1 == ichan) { | |
85571bc7 | 131 | dolog ("invalid channel read %#x\n", nport); |
b0bda528 FB |
132 | return 0; |
133 | } | |
134 | return d->regs[ichan].pageh; | |
135 | } | |
136 | ||
9eb153f1 | 137 | static inline void init_chan (struct dma_cont *d, int ichan) |
27503323 FB |
138 | { |
139 | struct dma_regs *r; | |
140 | ||
9eb153f1 | 141 | r = d->regs + ichan; |
85571bc7 | 142 | r->now[ADDR] = r->base[ADDR] << d->dshift; |
27503323 FB |
143 | r->now[COUNT] = 0; |
144 | } | |
145 | ||
9eb153f1 | 146 | static inline int getff (struct dma_cont *d) |
27503323 FB |
147 | { |
148 | int ff; | |
149 | ||
9eb153f1 FB |
150 | ff = d->flip_flop; |
151 | d->flip_flop = !ff; | |
27503323 FB |
152 | return ff; |
153 | } | |
154 | ||
58229933 | 155 | static uint64_t read_chan(void *opaque, hwaddr nport, unsigned size) |
27503323 | 156 | { |
9eb153f1 | 157 | struct dma_cont *d = opaque; |
85571bc7 | 158 | int ichan, nreg, iport, ff, val, dir; |
27503323 | 159 | struct dma_regs *r; |
27503323 | 160 | |
9eb153f1 FB |
161 | iport = (nport >> d->dshift) & 0x0f; |
162 | ichan = iport >> 1; | |
163 | nreg = iport & 1; | |
164 | r = d->regs + ichan; | |
27503323 | 165 | |
85571bc7 | 166 | dir = ((r->mode >> 5) & 1) ? -1 : 1; |
9eb153f1 | 167 | ff = getff (d); |
27503323 | 168 | if (nreg) |
9eb153f1 | 169 | val = (r->base[COUNT] << d->dshift) - r->now[COUNT]; |
27503323 | 170 | else |
85571bc7 | 171 | val = r->now[ADDR] + r->now[COUNT] * dir; |
27503323 | 172 | |
85571bc7 | 173 | ldebug ("read_chan %#x -> %d\n", iport, val); |
9eb153f1 | 174 | return (val >> (d->dshift + (ff << 3))) & 0xff; |
27503323 FB |
175 | } |
176 | ||
58229933 JG |
177 | static void write_chan(void *opaque, hwaddr nport, uint64_t data, |
178 | unsigned size) | |
27503323 | 179 | { |
9eb153f1 FB |
180 | struct dma_cont *d = opaque; |
181 | int iport, ichan, nreg; | |
27503323 FB |
182 | struct dma_regs *r; |
183 | ||
9eb153f1 FB |
184 | iport = (nport >> d->dshift) & 0x0f; |
185 | ichan = iport >> 1; | |
186 | nreg = iport & 1; | |
187 | r = d->regs + ichan; | |
188 | if (getff (d)) { | |
3504fe17 | 189 | r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00); |
9eb153f1 | 190 | init_chan (d, ichan); |
3504fe17 FB |
191 | } else { |
192 | r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff); | |
27503323 | 193 | } |
27503323 FB |
194 | } |
195 | ||
58229933 JG |
196 | static void write_cont(void *opaque, hwaddr nport, uint64_t data, |
197 | unsigned size) | |
27503323 | 198 | { |
9eb153f1 | 199 | struct dma_cont *d = opaque; |
85571bc7 | 200 | int iport, ichan = 0; |
27503323 | 201 | |
9eb153f1 | 202 | iport = (nport >> d->dshift) & 0x0f; |
27503323 | 203 | switch (iport) { |
ecd584b8 | 204 | case 0x00: /* command */ |
df475d18 | 205 | if ((data != 0) && (data & CMD_NOT_SUPPORTED)) { |
58229933 | 206 | dolog("command %"PRIx64" not supported\n", data); |
df475d18 | 207 | return; |
27503323 FB |
208 | } |
209 | d->command = data; | |
210 | break; | |
211 | ||
ecd584b8 | 212 | case 0x01: |
27503323 FB |
213 | ichan = data & 3; |
214 | if (data & 4) { | |
215 | d->status |= 1 << (ichan + 4); | |
216 | } | |
217 | else { | |
218 | d->status &= ~(1 << (ichan + 4)); | |
219 | } | |
220 | d->status &= ~(1 << ichan); | |
492c30af | 221 | DMA_run(); |
27503323 FB |
222 | break; |
223 | ||
ecd584b8 | 224 | case 0x02: /* single mask */ |
27503323 FB |
225 | if (data & 4) |
226 | d->mask |= 1 << (data & 3); | |
227 | else | |
228 | d->mask &= ~(1 << (data & 3)); | |
492c30af | 229 | DMA_run(); |
27503323 FB |
230 | break; |
231 | ||
ecd584b8 | 232 | case 0x03: /* mode */ |
27503323 | 233 | { |
16d17fdb FB |
234 | ichan = data & 3; |
235 | #ifdef DEBUG_DMA | |
85571bc7 FB |
236 | { |
237 | int op, ai, dir, opmode; | |
e875c40a FB |
238 | op = (data >> 2) & 3; |
239 | ai = (data >> 4) & 1; | |
240 | dir = (data >> 5) & 1; | |
241 | opmode = (data >> 6) & 3; | |
27503323 | 242 | |
e875c40a FB |
243 | linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n", |
244 | ichan, op, ai, dir, opmode); | |
85571bc7 | 245 | } |
27503323 | 246 | #endif |
27503323 FB |
247 | d->regs[ichan].mode = data; |
248 | break; | |
249 | } | |
250 | ||
ecd584b8 | 251 | case 0x04: /* clear flip flop */ |
27503323 FB |
252 | d->flip_flop = 0; |
253 | break; | |
254 | ||
ecd584b8 | 255 | case 0x05: /* reset */ |
27503323 FB |
256 | d->flip_flop = 0; |
257 | d->mask = ~0; | |
258 | d->status = 0; | |
259 | d->command = 0; | |
260 | break; | |
261 | ||
ecd584b8 | 262 | case 0x06: /* clear mask for all channels */ |
27503323 | 263 | d->mask = 0; |
492c30af | 264 | DMA_run(); |
27503323 FB |
265 | break; |
266 | ||
ecd584b8 | 267 | case 0x07: /* write mask for all channels */ |
27503323 | 268 | d->mask = data; |
492c30af | 269 | DMA_run(); |
27503323 FB |
270 | break; |
271 | ||
272 | default: | |
85571bc7 | 273 | dolog ("unknown iport %#x\n", iport); |
df475d18 | 274 | break; |
27503323 FB |
275 | } |
276 | ||
16d17fdb | 277 | #ifdef DEBUG_DMA |
27503323 | 278 | if (0xc != iport) { |
85571bc7 | 279 | linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n", |
9eb153f1 | 280 | nport, ichan, data); |
27503323 FB |
281 | } |
282 | #endif | |
27503323 FB |
283 | } |
284 | ||
58229933 | 285 | static uint64_t read_cont(void *opaque, hwaddr nport, unsigned size) |
9eb153f1 FB |
286 | { |
287 | struct dma_cont *d = opaque; | |
288 | int iport, val; | |
85571bc7 | 289 | |
9eb153f1 FB |
290 | iport = (nport >> d->dshift) & 0x0f; |
291 | switch (iport) { | |
ecd584b8 | 292 | case 0x00: /* status */ |
9eb153f1 FB |
293 | val = d->status; |
294 | d->status &= 0xf0; | |
295 | break; | |
ecd584b8 | 296 | case 0x01: /* mask */ |
9eb153f1 FB |
297 | val = d->mask; |
298 | break; | |
299 | default: | |
300 | val = 0; | |
301 | break; | |
302 | } | |
85571bc7 FB |
303 | |
304 | ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport, iport, val); | |
9eb153f1 FB |
305 | return val; |
306 | } | |
307 | ||
27503323 FB |
308 | int DMA_get_channel_mode (int nchan) |
309 | { | |
310 | return dma_controllers[nchan > 3].regs[nchan & 3].mode; | |
311 | } | |
312 | ||
313 | void DMA_hold_DREQ (int nchan) | |
314 | { | |
315 | int ncont, ichan; | |
316 | ||
317 | ncont = nchan > 3; | |
318 | ichan = nchan & 3; | |
319 | linfo ("held cont=%d chan=%d\n", ncont, ichan); | |
320 | dma_controllers[ncont].status |= 1 << (ichan + 4); | |
492c30af | 321 | DMA_run(); |
27503323 FB |
322 | } |
323 | ||
324 | void DMA_release_DREQ (int nchan) | |
325 | { | |
326 | int ncont, ichan; | |
327 | ||
328 | ncont = nchan > 3; | |
329 | ichan = nchan & 3; | |
330 | linfo ("released cont=%d chan=%d\n", ncont, ichan); | |
331 | dma_controllers[ncont].status &= ~(1 << (ichan + 4)); | |
492c30af | 332 | DMA_run(); |
27503323 FB |
333 | } |
334 | ||
335 | static void channel_run (int ncont, int ichan) | |
336 | { | |
27503323 | 337 | int n; |
85571bc7 FB |
338 | struct dma_regs *r = &dma_controllers[ncont].regs[ichan]; |
339 | #ifdef DEBUG_DMA | |
340 | int dir, opmode; | |
27503323 | 341 | |
85571bc7 FB |
342 | dir = (r->mode >> 5) & 1; |
343 | opmode = (r->mode >> 6) & 3; | |
27503323 | 344 | |
85571bc7 FB |
345 | if (dir) { |
346 | dolog ("DMA in address decrement mode\n"); | |
347 | } | |
348 | if (opmode != 1) { | |
349 | dolog ("DMA not in single mode select %#x\n", opmode); | |
350 | } | |
351 | #endif | |
27503323 | 352 | |
85571bc7 FB |
353 | n = r->transfer_handler (r->opaque, ichan + (ncont << 2), |
354 | r->now[COUNT], (r->base[COUNT] + 1) << ncont); | |
355 | r->now[COUNT] = n; | |
356 | ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont); | |
27503323 FB |
357 | } |
358 | ||
492c30af | 359 | static QEMUBH *dma_bh; |
19d2b5e6 | 360 | static bool dma_bh_scheduled; |
492c30af AL |
361 | |
362 | static void DMA_run (void) | |
27503323 | 363 | { |
27503323 FB |
364 | struct dma_cont *d; |
365 | int icont, ichan; | |
492c30af | 366 | int rearm = 0; |
acae6f1c KW |
367 | static int running = 0; |
368 | ||
369 | if (running) { | |
370 | rearm = 1; | |
371 | goto out; | |
372 | } else { | |
373 | running = 1; | |
374 | } | |
27503323 | 375 | |
27503323 FB |
376 | d = dma_controllers; |
377 | ||
378 | for (icont = 0; icont < 2; icont++, d++) { | |
379 | for (ichan = 0; ichan < 4; ichan++) { | |
380 | int mask; | |
381 | ||
382 | mask = 1 << ichan; | |
383 | ||
492c30af | 384 | if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) { |
27503323 | 385 | channel_run (icont, ichan); |
492c30af AL |
386 | rearm = 1; |
387 | } | |
27503323 FB |
388 | } |
389 | } | |
492c30af | 390 | |
acae6f1c KW |
391 | running = 0; |
392 | out: | |
19d2b5e6 | 393 | if (rearm) { |
492c30af | 394 | qemu_bh_schedule_idle(dma_bh); |
19d2b5e6 PB |
395 | dma_bh_scheduled = true; |
396 | } | |
492c30af AL |
397 | } |
398 | ||
399 | static void DMA_run_bh(void *unused) | |
400 | { | |
19d2b5e6 | 401 | dma_bh_scheduled = false; |
492c30af | 402 | DMA_run(); |
27503323 FB |
403 | } |
404 | ||
405 | void DMA_register_channel (int nchan, | |
85571bc7 | 406 | DMA_transfer_handler transfer_handler, |
16f62432 | 407 | void *opaque) |
27503323 FB |
408 | { |
409 | struct dma_regs *r; | |
410 | int ichan, ncont; | |
411 | ||
412 | ncont = nchan > 3; | |
413 | ichan = nchan & 3; | |
414 | ||
415 | r = dma_controllers[ncont].regs + ichan; | |
16f62432 FB |
416 | r->transfer_handler = transfer_handler; |
417 | r->opaque = opaque; | |
418 | } | |
419 | ||
85571bc7 FB |
420 | int DMA_read_memory (int nchan, void *buf, int pos, int len) |
421 | { | |
422 | struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; | |
a8170e5e | 423 | hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; |
85571bc7 FB |
424 | |
425 | if (r->mode & 0x20) { | |
426 | int i; | |
427 | uint8_t *p = buf; | |
428 | ||
429 | cpu_physical_memory_read (addr - pos - len, buf, len); | |
430 | /* What about 16bit transfers? */ | |
431 | for (i = 0; i < len >> 1; i++) { | |
432 | uint8_t b = p[len - i - 1]; | |
433 | p[i] = b; | |
434 | } | |
435 | } | |
436 | else | |
437 | cpu_physical_memory_read (addr + pos, buf, len); | |
438 | ||
439 | return len; | |
440 | } | |
441 | ||
442 | int DMA_write_memory (int nchan, void *buf, int pos, int len) | |
443 | { | |
444 | struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; | |
a8170e5e | 445 | hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; |
85571bc7 FB |
446 | |
447 | if (r->mode & 0x20) { | |
448 | int i; | |
449 | uint8_t *p = buf; | |
450 | ||
451 | cpu_physical_memory_write (addr - pos - len, buf, len); | |
452 | /* What about 16bit transfers? */ | |
453 | for (i = 0; i < len; i++) { | |
454 | uint8_t b = p[len - i - 1]; | |
455 | p[i] = b; | |
456 | } | |
457 | } | |
458 | else | |
459 | cpu_physical_memory_write (addr + pos, buf, len); | |
460 | ||
461 | return len; | |
462 | } | |
463 | ||
19d2b5e6 PB |
464 | /* request the emulator to transfer a new DMA memory block ASAP (even |
465 | * if the idle bottom half would not have exited the iothread yet). | |
466 | */ | |
467 | void DMA_schedule(void) | |
16f62432 | 468 | { |
19d2b5e6 PB |
469 | if (dma_bh_scheduled) { |
470 | qemu_notify_event(); | |
471 | } | |
27503323 FB |
472 | } |
473 | ||
d7d02e3c FB |
474 | static void dma_reset(void *opaque) |
475 | { | |
476 | struct dma_cont *d = opaque; | |
ecd584b8 | 477 | write_cont(d, (0x05 << d->dshift), 0, 1); |
d7d02e3c FB |
478 | } |
479 | ||
ca9cc28c AZ |
480 | static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int dma_len) |
481 | { | |
7dbb4c49 | 482 | trace_i8257_unregistered_dma(nchan, dma_pos, dma_len); |
ca9cc28c AZ |
483 | return dma_pos; |
484 | } | |
485 | ||
58229933 JG |
486 | |
487 | static const MemoryRegionOps channel_io_ops = { | |
488 | .read = read_chan, | |
489 | .write = write_chan, | |
490 | .endianness = DEVICE_NATIVE_ENDIAN, | |
491 | .impl = { | |
492 | .min_access_size = 1, | |
493 | .max_access_size = 1, | |
494 | }, | |
495 | }; | |
496 | ||
497 | /* IOport from page_base */ | |
498 | static const MemoryRegionPortio page_portio_list[] = { | |
499 | { 0x01, 3, 1, .write = write_page, .read = read_page, }, | |
500 | { 0x07, 1, 1, .write = write_page, .read = read_page, }, | |
501 | PORTIO_END_OF_LIST(), | |
502 | }; | |
503 | ||
504 | /* IOport from pageh_base */ | |
505 | static const MemoryRegionPortio pageh_portio_list[] = { | |
506 | { 0x01, 3, 1, .write = write_pageh, .read = read_pageh, }, | |
507 | { 0x07, 3, 1, .write = write_pageh, .read = read_pageh, }, | |
508 | PORTIO_END_OF_LIST(), | |
509 | }; | |
510 | ||
511 | static const MemoryRegionOps cont_io_ops = { | |
512 | .read = read_cont, | |
513 | .write = write_cont, | |
514 | .endianness = DEVICE_NATIVE_ENDIAN, | |
515 | .impl = { | |
516 | .min_access_size = 1, | |
517 | .max_access_size = 1, | |
518 | }, | |
519 | }; | |
520 | ||
9eb153f1 | 521 | /* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */ |
85571bc7 | 522 | static void dma_init2(struct dma_cont *d, int base, int dshift, |
5039d6e2 | 523 | int page_base, int pageh_base) |
27503323 FB |
524 | { |
525 | int i; | |
27503323 | 526 | |
9eb153f1 | 527 | d->dshift = dshift; |
58229933 | 528 | |
2c9b15ca | 529 | memory_region_init_io(&d->channel_io, NULL, &channel_io_ops, d, |
58229933 JG |
530 | "dma-chan", 8 << d->dshift); |
531 | memory_region_add_subregion(isa_address_space_io(NULL), | |
532 | base, &d->channel_io); | |
533 | ||
534 | isa_register_portio_list(NULL, page_base, page_portio_list, d, | |
535 | "dma-page"); | |
536 | if (pageh_base >= 0) { | |
537 | isa_register_portio_list(NULL, pageh_base, pageh_portio_list, d, | |
538 | "dma-pageh"); | |
27503323 | 539 | } |
58229933 | 540 | |
2c9b15ca | 541 | memory_region_init_io(&d->cont_io, NULL, &cont_io_ops, d, "dma-cont", |
58229933 JG |
542 | 8 << d->dshift); |
543 | memory_region_add_subregion(isa_address_space_io(NULL), | |
544 | base + (8 << d->dshift), &d->cont_io); | |
545 | ||
a08d4367 | 546 | qemu_register_reset(dma_reset, d); |
d7d02e3c | 547 | dma_reset(d); |
b1503cda | 548 | for (i = 0; i < ARRAY_SIZE (d->regs); ++i) { |
ca9cc28c AZ |
549 | d->regs[i].transfer_handler = dma_phony_handler; |
550 | } | |
9eb153f1 | 551 | } |
27503323 | 552 | |
7b5045c5 JQ |
553 | static const VMStateDescription vmstate_dma_regs = { |
554 | .name = "dma_regs", | |
555 | .version_id = 1, | |
556 | .minimum_version_id = 1, | |
d49805ae | 557 | .fields = (VMStateField[]) { |
7b5045c5 JQ |
558 | VMSTATE_INT32_ARRAY(now, struct dma_regs, 2), |
559 | VMSTATE_UINT16_ARRAY(base, struct dma_regs, 2), | |
560 | VMSTATE_UINT8(mode, struct dma_regs), | |
561 | VMSTATE_UINT8(page, struct dma_regs), | |
562 | VMSTATE_UINT8(pageh, struct dma_regs), | |
563 | VMSTATE_UINT8(dack, struct dma_regs), | |
564 | VMSTATE_UINT8(eop, struct dma_regs), | |
565 | VMSTATE_END_OF_LIST() | |
85571bc7 | 566 | } |
7b5045c5 | 567 | }; |
85571bc7 | 568 | |
e59fb374 | 569 | static int dma_post_load(void *opaque, int version_id) |
85571bc7 | 570 | { |
492c30af AL |
571 | DMA_run(); |
572 | ||
85571bc7 FB |
573 | return 0; |
574 | } | |
575 | ||
7b5045c5 JQ |
576 | static const VMStateDescription vmstate_dma = { |
577 | .name = "dma", | |
578 | .version_id = 1, | |
579 | .minimum_version_id = 1, | |
7b5045c5 | 580 | .post_load = dma_post_load, |
d49805ae | 581 | .fields = (VMStateField[]) { |
7b5045c5 JQ |
582 | VMSTATE_UINT8(command, struct dma_cont), |
583 | VMSTATE_UINT8(mask, struct dma_cont), | |
584 | VMSTATE_UINT8(flip_flop, struct dma_cont), | |
585 | VMSTATE_INT32(dshift, struct dma_cont), | |
586 | VMSTATE_STRUCT_ARRAY(regs, struct dma_cont, 4, 1, vmstate_dma_regs, struct dma_regs), | |
587 | VMSTATE_END_OF_LIST() | |
588 | } | |
589 | }; | |
590 | ||
5039d6e2 | 591 | void DMA_init(int high_page_enable) |
9eb153f1 | 592 | { |
5039d6e2 PB |
593 | dma_init2(&dma_controllers[0], 0x00, 0, 0x80, high_page_enable ? 0x480 : -1); |
594 | dma_init2(&dma_controllers[1], 0xc0, 1, 0x88, high_page_enable ? 0x488 : -1); | |
0be71e32 AW |
595 | vmstate_register (NULL, 0, &vmstate_dma, &dma_controllers[0]); |
596 | vmstate_register (NULL, 1, &vmstate_dma, &dma_controllers[1]); | |
492c30af AL |
597 | |
598 | dma_bh = qemu_bh_new(DMA_run_bh, NULL); | |
27503323 | 599 | } |