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Commit | Line | Data |
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27503323 FB |
1 | /* |
2 | * QEMU DMA emulation | |
85571bc7 FB |
3 | * |
4 | * Copyright (c) 2003-2004 Vassili Karpov (malc) | |
5 | * | |
27503323 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
83c9f4ca | 24 | #include "hw/hw.h" |
0d09e41a | 25 | #include "hw/isa/isa.h" |
1de7afc9 | 26 | #include "qemu/main-loop.h" |
7dbb4c49 | 27 | #include "trace.h" |
27503323 | 28 | |
85571bc7 | 29 | /* #define DEBUG_DMA */ |
7ebb5e41 | 30 | |
85571bc7 | 31 | #define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__) |
27503323 | 32 | #ifdef DEBUG_DMA |
27503323 FB |
33 | #define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__) |
34 | #define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__) | |
35 | #else | |
27503323 FB |
36 | #define linfo(...) |
37 | #define ldebug(...) | |
38 | #endif | |
39 | ||
27503323 FB |
40 | struct dma_regs { |
41 | int now[2]; | |
42 | uint16_t base[2]; | |
43 | uint8_t mode; | |
44 | uint8_t page; | |
b0bda528 | 45 | uint8_t pageh; |
27503323 FB |
46 | uint8_t dack; |
47 | uint8_t eop; | |
16f62432 FB |
48 | DMA_transfer_handler transfer_handler; |
49 | void *opaque; | |
27503323 FB |
50 | }; |
51 | ||
52 | #define ADDR 0 | |
53 | #define COUNT 1 | |
54 | ||
55 | static struct dma_cont { | |
56 | uint8_t status; | |
57 | uint8_t command; | |
58 | uint8_t mask; | |
59 | uint8_t flip_flop; | |
9eb153f1 | 60 | int dshift; |
27503323 | 61 | struct dma_regs regs[4]; |
4556bd8b | 62 | qemu_irq *cpu_request_exit; |
58229933 JG |
63 | MemoryRegion channel_io; |
64 | MemoryRegion cont_io; | |
27503323 FB |
65 | } dma_controllers[2]; |
66 | ||
67 | enum { | |
e875c40a FB |
68 | CMD_MEMORY_TO_MEMORY = 0x01, |
69 | CMD_FIXED_ADDRESS = 0x02, | |
70 | CMD_BLOCK_CONTROLLER = 0x04, | |
71 | CMD_COMPRESSED_TIME = 0x08, | |
72 | CMD_CYCLIC_PRIORITY = 0x10, | |
73 | CMD_EXTENDED_WRITE = 0x20, | |
74 | CMD_LOW_DREQ = 0x40, | |
75 | CMD_LOW_DACK = 0x80, | |
76 | CMD_NOT_SUPPORTED = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS | |
77 | | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE | |
78 | | CMD_LOW_DREQ | CMD_LOW_DACK | |
27503323 FB |
79 | |
80 | }; | |
81 | ||
492c30af AL |
82 | static void DMA_run (void); |
83 | ||
9eb153f1 FB |
84 | static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0}; |
85 | ||
7d977de7 | 86 | static void write_page (void *opaque, uint32_t nport, uint32_t data) |
27503323 | 87 | { |
9eb153f1 | 88 | struct dma_cont *d = opaque; |
27503323 | 89 | int ichan; |
27503323 | 90 | |
9eb153f1 | 91 | ichan = channels[nport & 7]; |
27503323 | 92 | if (-1 == ichan) { |
85571bc7 | 93 | dolog ("invalid channel %#x %#x\n", nport, data); |
27503323 FB |
94 | return; |
95 | } | |
9eb153f1 FB |
96 | d->regs[ichan].page = data; |
97 | } | |
98 | ||
b0bda528 | 99 | static void write_pageh (void *opaque, uint32_t nport, uint32_t data) |
9eb153f1 FB |
100 | { |
101 | struct dma_cont *d = opaque; | |
102 | int ichan; | |
27503323 | 103 | |
9eb153f1 | 104 | ichan = channels[nport & 7]; |
b0bda528 | 105 | if (-1 == ichan) { |
85571bc7 | 106 | dolog ("invalid channel %#x %#x\n", nport, data); |
b0bda528 FB |
107 | return; |
108 | } | |
109 | d->regs[ichan].pageh = data; | |
110 | } | |
9eb153f1 | 111 | |
b0bda528 FB |
112 | static uint32_t read_page (void *opaque, uint32_t nport) |
113 | { | |
114 | struct dma_cont *d = opaque; | |
115 | int ichan; | |
116 | ||
117 | ichan = channels[nport & 7]; | |
9eb153f1 | 118 | if (-1 == ichan) { |
85571bc7 | 119 | dolog ("invalid channel read %#x\n", nport); |
9eb153f1 FB |
120 | return 0; |
121 | } | |
122 | return d->regs[ichan].page; | |
27503323 FB |
123 | } |
124 | ||
b0bda528 FB |
125 | static uint32_t read_pageh (void *opaque, uint32_t nport) |
126 | { | |
127 | struct dma_cont *d = opaque; | |
128 | int ichan; | |
129 | ||
130 | ichan = channels[nport & 7]; | |
131 | if (-1 == ichan) { | |
85571bc7 | 132 | dolog ("invalid channel read %#x\n", nport); |
b0bda528 FB |
133 | return 0; |
134 | } | |
135 | return d->regs[ichan].pageh; | |
136 | } | |
137 | ||
9eb153f1 | 138 | static inline void init_chan (struct dma_cont *d, int ichan) |
27503323 FB |
139 | { |
140 | struct dma_regs *r; | |
141 | ||
9eb153f1 | 142 | r = d->regs + ichan; |
85571bc7 | 143 | r->now[ADDR] = r->base[ADDR] << d->dshift; |
27503323 FB |
144 | r->now[COUNT] = 0; |
145 | } | |
146 | ||
9eb153f1 | 147 | static inline int getff (struct dma_cont *d) |
27503323 FB |
148 | { |
149 | int ff; | |
150 | ||
9eb153f1 FB |
151 | ff = d->flip_flop; |
152 | d->flip_flop = !ff; | |
27503323 FB |
153 | return ff; |
154 | } | |
155 | ||
58229933 | 156 | static uint64_t read_chan(void *opaque, hwaddr nport, unsigned size) |
27503323 | 157 | { |
9eb153f1 | 158 | struct dma_cont *d = opaque; |
85571bc7 | 159 | int ichan, nreg, iport, ff, val, dir; |
27503323 | 160 | struct dma_regs *r; |
27503323 | 161 | |
9eb153f1 FB |
162 | iport = (nport >> d->dshift) & 0x0f; |
163 | ichan = iport >> 1; | |
164 | nreg = iport & 1; | |
165 | r = d->regs + ichan; | |
27503323 | 166 | |
85571bc7 | 167 | dir = ((r->mode >> 5) & 1) ? -1 : 1; |
9eb153f1 | 168 | ff = getff (d); |
27503323 | 169 | if (nreg) |
9eb153f1 | 170 | val = (r->base[COUNT] << d->dshift) - r->now[COUNT]; |
27503323 | 171 | else |
85571bc7 | 172 | val = r->now[ADDR] + r->now[COUNT] * dir; |
27503323 | 173 | |
85571bc7 | 174 | ldebug ("read_chan %#x -> %d\n", iport, val); |
9eb153f1 | 175 | return (val >> (d->dshift + (ff << 3))) & 0xff; |
27503323 FB |
176 | } |
177 | ||
58229933 JG |
178 | static void write_chan(void *opaque, hwaddr nport, uint64_t data, |
179 | unsigned size) | |
27503323 | 180 | { |
9eb153f1 FB |
181 | struct dma_cont *d = opaque; |
182 | int iport, ichan, nreg; | |
27503323 FB |
183 | struct dma_regs *r; |
184 | ||
9eb153f1 FB |
185 | iport = (nport >> d->dshift) & 0x0f; |
186 | ichan = iport >> 1; | |
187 | nreg = iport & 1; | |
188 | r = d->regs + ichan; | |
189 | if (getff (d)) { | |
3504fe17 | 190 | r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00); |
9eb153f1 | 191 | init_chan (d, ichan); |
3504fe17 FB |
192 | } else { |
193 | r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff); | |
27503323 | 194 | } |
27503323 FB |
195 | } |
196 | ||
58229933 JG |
197 | static void write_cont(void *opaque, hwaddr nport, uint64_t data, |
198 | unsigned size) | |
27503323 | 199 | { |
9eb153f1 | 200 | struct dma_cont *d = opaque; |
85571bc7 | 201 | int iport, ichan = 0; |
27503323 | 202 | |
9eb153f1 | 203 | iport = (nport >> d->dshift) & 0x0f; |
27503323 | 204 | switch (iport) { |
ecd584b8 | 205 | case 0x00: /* command */ |
df475d18 | 206 | if ((data != 0) && (data & CMD_NOT_SUPPORTED)) { |
58229933 | 207 | dolog("command %"PRIx64" not supported\n", data); |
df475d18 | 208 | return; |
27503323 FB |
209 | } |
210 | d->command = data; | |
211 | break; | |
212 | ||
ecd584b8 | 213 | case 0x01: |
27503323 FB |
214 | ichan = data & 3; |
215 | if (data & 4) { | |
216 | d->status |= 1 << (ichan + 4); | |
217 | } | |
218 | else { | |
219 | d->status &= ~(1 << (ichan + 4)); | |
220 | } | |
221 | d->status &= ~(1 << ichan); | |
492c30af | 222 | DMA_run(); |
27503323 FB |
223 | break; |
224 | ||
ecd584b8 | 225 | case 0x02: /* single mask */ |
27503323 FB |
226 | if (data & 4) |
227 | d->mask |= 1 << (data & 3); | |
228 | else | |
229 | d->mask &= ~(1 << (data & 3)); | |
492c30af | 230 | DMA_run(); |
27503323 FB |
231 | break; |
232 | ||
ecd584b8 | 233 | case 0x03: /* mode */ |
27503323 | 234 | { |
16d17fdb FB |
235 | ichan = data & 3; |
236 | #ifdef DEBUG_DMA | |
85571bc7 FB |
237 | { |
238 | int op, ai, dir, opmode; | |
e875c40a FB |
239 | op = (data >> 2) & 3; |
240 | ai = (data >> 4) & 1; | |
241 | dir = (data >> 5) & 1; | |
242 | opmode = (data >> 6) & 3; | |
27503323 | 243 | |
e875c40a FB |
244 | linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n", |
245 | ichan, op, ai, dir, opmode); | |
85571bc7 | 246 | } |
27503323 | 247 | #endif |
27503323 FB |
248 | d->regs[ichan].mode = data; |
249 | break; | |
250 | } | |
251 | ||
ecd584b8 | 252 | case 0x04: /* clear flip flop */ |
27503323 FB |
253 | d->flip_flop = 0; |
254 | break; | |
255 | ||
ecd584b8 | 256 | case 0x05: /* reset */ |
27503323 FB |
257 | d->flip_flop = 0; |
258 | d->mask = ~0; | |
259 | d->status = 0; | |
260 | d->command = 0; | |
261 | break; | |
262 | ||
ecd584b8 | 263 | case 0x06: /* clear mask for all channels */ |
27503323 | 264 | d->mask = 0; |
492c30af | 265 | DMA_run(); |
27503323 FB |
266 | break; |
267 | ||
ecd584b8 | 268 | case 0x07: /* write mask for all channels */ |
27503323 | 269 | d->mask = data; |
492c30af | 270 | DMA_run(); |
27503323 FB |
271 | break; |
272 | ||
273 | default: | |
85571bc7 | 274 | dolog ("unknown iport %#x\n", iport); |
df475d18 | 275 | break; |
27503323 FB |
276 | } |
277 | ||
16d17fdb | 278 | #ifdef DEBUG_DMA |
27503323 | 279 | if (0xc != iport) { |
85571bc7 | 280 | linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n", |
9eb153f1 | 281 | nport, ichan, data); |
27503323 FB |
282 | } |
283 | #endif | |
27503323 FB |
284 | } |
285 | ||
58229933 | 286 | static uint64_t read_cont(void *opaque, hwaddr nport, unsigned size) |
9eb153f1 FB |
287 | { |
288 | struct dma_cont *d = opaque; | |
289 | int iport, val; | |
85571bc7 | 290 | |
9eb153f1 FB |
291 | iport = (nport >> d->dshift) & 0x0f; |
292 | switch (iport) { | |
ecd584b8 | 293 | case 0x00: /* status */ |
9eb153f1 FB |
294 | val = d->status; |
295 | d->status &= 0xf0; | |
296 | break; | |
ecd584b8 | 297 | case 0x01: /* mask */ |
9eb153f1 FB |
298 | val = d->mask; |
299 | break; | |
300 | default: | |
301 | val = 0; | |
302 | break; | |
303 | } | |
85571bc7 FB |
304 | |
305 | ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport, iport, val); | |
9eb153f1 FB |
306 | return val; |
307 | } | |
308 | ||
27503323 FB |
309 | int DMA_get_channel_mode (int nchan) |
310 | { | |
311 | return dma_controllers[nchan > 3].regs[nchan & 3].mode; | |
312 | } | |
313 | ||
314 | void DMA_hold_DREQ (int nchan) | |
315 | { | |
316 | int ncont, ichan; | |
317 | ||
318 | ncont = nchan > 3; | |
319 | ichan = nchan & 3; | |
320 | linfo ("held cont=%d chan=%d\n", ncont, ichan); | |
321 | dma_controllers[ncont].status |= 1 << (ichan + 4); | |
492c30af | 322 | DMA_run(); |
27503323 FB |
323 | } |
324 | ||
325 | void DMA_release_DREQ (int nchan) | |
326 | { | |
327 | int ncont, ichan; | |
328 | ||
329 | ncont = nchan > 3; | |
330 | ichan = nchan & 3; | |
331 | linfo ("released cont=%d chan=%d\n", ncont, ichan); | |
332 | dma_controllers[ncont].status &= ~(1 << (ichan + 4)); | |
492c30af | 333 | DMA_run(); |
27503323 FB |
334 | } |
335 | ||
336 | static void channel_run (int ncont, int ichan) | |
337 | { | |
27503323 | 338 | int n; |
85571bc7 FB |
339 | struct dma_regs *r = &dma_controllers[ncont].regs[ichan]; |
340 | #ifdef DEBUG_DMA | |
341 | int dir, opmode; | |
27503323 | 342 | |
85571bc7 FB |
343 | dir = (r->mode >> 5) & 1; |
344 | opmode = (r->mode >> 6) & 3; | |
27503323 | 345 | |
85571bc7 FB |
346 | if (dir) { |
347 | dolog ("DMA in address decrement mode\n"); | |
348 | } | |
349 | if (opmode != 1) { | |
350 | dolog ("DMA not in single mode select %#x\n", opmode); | |
351 | } | |
352 | #endif | |
27503323 | 353 | |
85571bc7 FB |
354 | n = r->transfer_handler (r->opaque, ichan + (ncont << 2), |
355 | r->now[COUNT], (r->base[COUNT] + 1) << ncont); | |
356 | r->now[COUNT] = n; | |
357 | ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont); | |
27503323 FB |
358 | } |
359 | ||
492c30af AL |
360 | static QEMUBH *dma_bh; |
361 | ||
362 | static void DMA_run (void) | |
27503323 | 363 | { |
27503323 FB |
364 | struct dma_cont *d; |
365 | int icont, ichan; | |
492c30af | 366 | int rearm = 0; |
acae6f1c KW |
367 | static int running = 0; |
368 | ||
369 | if (running) { | |
370 | rearm = 1; | |
371 | goto out; | |
372 | } else { | |
373 | running = 1; | |
374 | } | |
27503323 | 375 | |
27503323 FB |
376 | d = dma_controllers; |
377 | ||
378 | for (icont = 0; icont < 2; icont++, d++) { | |
379 | for (ichan = 0; ichan < 4; ichan++) { | |
380 | int mask; | |
381 | ||
382 | mask = 1 << ichan; | |
383 | ||
492c30af | 384 | if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) { |
27503323 | 385 | channel_run (icont, ichan); |
492c30af AL |
386 | rearm = 1; |
387 | } | |
27503323 FB |
388 | } |
389 | } | |
492c30af | 390 | |
acae6f1c KW |
391 | running = 0; |
392 | out: | |
492c30af AL |
393 | if (rearm) |
394 | qemu_bh_schedule_idle(dma_bh); | |
395 | } | |
396 | ||
397 | static void DMA_run_bh(void *unused) | |
398 | { | |
399 | DMA_run(); | |
27503323 FB |
400 | } |
401 | ||
402 | void DMA_register_channel (int nchan, | |
85571bc7 | 403 | DMA_transfer_handler transfer_handler, |
16f62432 | 404 | void *opaque) |
27503323 FB |
405 | { |
406 | struct dma_regs *r; | |
407 | int ichan, ncont; | |
408 | ||
409 | ncont = nchan > 3; | |
410 | ichan = nchan & 3; | |
411 | ||
412 | r = dma_controllers[ncont].regs + ichan; | |
16f62432 FB |
413 | r->transfer_handler = transfer_handler; |
414 | r->opaque = opaque; | |
415 | } | |
416 | ||
85571bc7 FB |
417 | int DMA_read_memory (int nchan, void *buf, int pos, int len) |
418 | { | |
419 | struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; | |
a8170e5e | 420 | hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; |
85571bc7 FB |
421 | |
422 | if (r->mode & 0x20) { | |
423 | int i; | |
424 | uint8_t *p = buf; | |
425 | ||
426 | cpu_physical_memory_read (addr - pos - len, buf, len); | |
427 | /* What about 16bit transfers? */ | |
428 | for (i = 0; i < len >> 1; i++) { | |
429 | uint8_t b = p[len - i - 1]; | |
430 | p[i] = b; | |
431 | } | |
432 | } | |
433 | else | |
434 | cpu_physical_memory_read (addr + pos, buf, len); | |
435 | ||
436 | return len; | |
437 | } | |
438 | ||
439 | int DMA_write_memory (int nchan, void *buf, int pos, int len) | |
440 | { | |
441 | struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; | |
a8170e5e | 442 | hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; |
85571bc7 FB |
443 | |
444 | if (r->mode & 0x20) { | |
445 | int i; | |
446 | uint8_t *p = buf; | |
447 | ||
448 | cpu_physical_memory_write (addr - pos - len, buf, len); | |
449 | /* What about 16bit transfers? */ | |
450 | for (i = 0; i < len; i++) { | |
451 | uint8_t b = p[len - i - 1]; | |
452 | p[i] = b; | |
453 | } | |
454 | } | |
455 | else | |
456 | cpu_physical_memory_write (addr + pos, buf, len); | |
457 | ||
458 | return len; | |
459 | } | |
460 | ||
16f62432 FB |
461 | /* request the emulator to transfer a new DMA memory block ASAP */ |
462 | void DMA_schedule(int nchan) | |
463 | { | |
4556bd8b BS |
464 | struct dma_cont *d = &dma_controllers[nchan > 3]; |
465 | ||
466 | qemu_irq_pulse(*d->cpu_request_exit); | |
27503323 FB |
467 | } |
468 | ||
d7d02e3c FB |
469 | static void dma_reset(void *opaque) |
470 | { | |
471 | struct dma_cont *d = opaque; | |
ecd584b8 | 472 | write_cont(d, (0x05 << d->dshift), 0, 1); |
d7d02e3c FB |
473 | } |
474 | ||
ca9cc28c AZ |
475 | static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int dma_len) |
476 | { | |
7dbb4c49 | 477 | trace_i8257_unregistered_dma(nchan, dma_pos, dma_len); |
ca9cc28c AZ |
478 | return dma_pos; |
479 | } | |
480 | ||
58229933 JG |
481 | |
482 | static const MemoryRegionOps channel_io_ops = { | |
483 | .read = read_chan, | |
484 | .write = write_chan, | |
485 | .endianness = DEVICE_NATIVE_ENDIAN, | |
486 | .impl = { | |
487 | .min_access_size = 1, | |
488 | .max_access_size = 1, | |
489 | }, | |
490 | }; | |
491 | ||
492 | /* IOport from page_base */ | |
493 | static const MemoryRegionPortio page_portio_list[] = { | |
494 | { 0x01, 3, 1, .write = write_page, .read = read_page, }, | |
495 | { 0x07, 1, 1, .write = write_page, .read = read_page, }, | |
496 | PORTIO_END_OF_LIST(), | |
497 | }; | |
498 | ||
499 | /* IOport from pageh_base */ | |
500 | static const MemoryRegionPortio pageh_portio_list[] = { | |
501 | { 0x01, 3, 1, .write = write_pageh, .read = read_pageh, }, | |
502 | { 0x07, 3, 1, .write = write_pageh, .read = read_pageh, }, | |
503 | PORTIO_END_OF_LIST(), | |
504 | }; | |
505 | ||
506 | static const MemoryRegionOps cont_io_ops = { | |
507 | .read = read_cont, | |
508 | .write = write_cont, | |
509 | .endianness = DEVICE_NATIVE_ENDIAN, | |
510 | .impl = { | |
511 | .min_access_size = 1, | |
512 | .max_access_size = 1, | |
513 | }, | |
514 | }; | |
515 | ||
9eb153f1 | 516 | /* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */ |
85571bc7 | 517 | static void dma_init2(struct dma_cont *d, int base, int dshift, |
4556bd8b BS |
518 | int page_base, int pageh_base, |
519 | qemu_irq *cpu_request_exit) | |
27503323 FB |
520 | { |
521 | int i; | |
27503323 | 522 | |
9eb153f1 | 523 | d->dshift = dshift; |
4556bd8b | 524 | d->cpu_request_exit = cpu_request_exit; |
58229933 | 525 | |
2c9b15ca | 526 | memory_region_init_io(&d->channel_io, NULL, &channel_io_ops, d, |
58229933 JG |
527 | "dma-chan", 8 << d->dshift); |
528 | memory_region_add_subregion(isa_address_space_io(NULL), | |
529 | base, &d->channel_io); | |
530 | ||
531 | isa_register_portio_list(NULL, page_base, page_portio_list, d, | |
532 | "dma-page"); | |
533 | if (pageh_base >= 0) { | |
534 | isa_register_portio_list(NULL, pageh_base, pageh_portio_list, d, | |
535 | "dma-pageh"); | |
27503323 | 536 | } |
58229933 | 537 | |
2c9b15ca | 538 | memory_region_init_io(&d->cont_io, NULL, &cont_io_ops, d, "dma-cont", |
58229933 JG |
539 | 8 << d->dshift); |
540 | memory_region_add_subregion(isa_address_space_io(NULL), | |
541 | base + (8 << d->dshift), &d->cont_io); | |
542 | ||
a08d4367 | 543 | qemu_register_reset(dma_reset, d); |
d7d02e3c | 544 | dma_reset(d); |
b1503cda | 545 | for (i = 0; i < ARRAY_SIZE (d->regs); ++i) { |
ca9cc28c AZ |
546 | d->regs[i].transfer_handler = dma_phony_handler; |
547 | } | |
9eb153f1 | 548 | } |
27503323 | 549 | |
7b5045c5 JQ |
550 | static const VMStateDescription vmstate_dma_regs = { |
551 | .name = "dma_regs", | |
552 | .version_id = 1, | |
553 | .minimum_version_id = 1, | |
d49805ae | 554 | .fields = (VMStateField[]) { |
7b5045c5 JQ |
555 | VMSTATE_INT32_ARRAY(now, struct dma_regs, 2), |
556 | VMSTATE_UINT16_ARRAY(base, struct dma_regs, 2), | |
557 | VMSTATE_UINT8(mode, struct dma_regs), | |
558 | VMSTATE_UINT8(page, struct dma_regs), | |
559 | VMSTATE_UINT8(pageh, struct dma_regs), | |
560 | VMSTATE_UINT8(dack, struct dma_regs), | |
561 | VMSTATE_UINT8(eop, struct dma_regs), | |
562 | VMSTATE_END_OF_LIST() | |
85571bc7 | 563 | } |
7b5045c5 | 564 | }; |
85571bc7 | 565 | |
e59fb374 | 566 | static int dma_post_load(void *opaque, int version_id) |
85571bc7 | 567 | { |
492c30af AL |
568 | DMA_run(); |
569 | ||
85571bc7 FB |
570 | return 0; |
571 | } | |
572 | ||
7b5045c5 JQ |
573 | static const VMStateDescription vmstate_dma = { |
574 | .name = "dma", | |
575 | .version_id = 1, | |
576 | .minimum_version_id = 1, | |
7b5045c5 | 577 | .post_load = dma_post_load, |
d49805ae | 578 | .fields = (VMStateField[]) { |
7b5045c5 JQ |
579 | VMSTATE_UINT8(command, struct dma_cont), |
580 | VMSTATE_UINT8(mask, struct dma_cont), | |
581 | VMSTATE_UINT8(flip_flop, struct dma_cont), | |
582 | VMSTATE_INT32(dshift, struct dma_cont), | |
583 | VMSTATE_STRUCT_ARRAY(regs, struct dma_cont, 4, 1, vmstate_dma_regs, struct dma_regs), | |
584 | VMSTATE_END_OF_LIST() | |
585 | } | |
586 | }; | |
587 | ||
4556bd8b | 588 | void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit) |
9eb153f1 | 589 | { |
85571bc7 | 590 | dma_init2(&dma_controllers[0], 0x00, 0, 0x80, |
4556bd8b | 591 | high_page_enable ? 0x480 : -1, cpu_request_exit); |
b0bda528 | 592 | dma_init2(&dma_controllers[1], 0xc0, 1, 0x88, |
4556bd8b | 593 | high_page_enable ? 0x488 : -1, cpu_request_exit); |
0be71e32 AW |
594 | vmstate_register (NULL, 0, &vmstate_dma, &dma_controllers[0]); |
595 | vmstate_register (NULL, 1, &vmstate_dma, &dma_controllers[1]); | |
492c30af AL |
596 | |
597 | dma_bh = qemu_bh_new(DMA_run_bh, NULL); | |
27503323 | 598 | } |