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Commit | Line | Data |
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27503323 FB |
1 | /* |
2 | * QEMU DMA emulation | |
85571bc7 FB |
3 | * |
4 | * Copyright (c) 2003-2004 Vassili Karpov (malc) | |
5 | * | |
27503323 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
b6a0aa05 | 24 | #include "qemu/osdep.h" |
83c9f4ca | 25 | #include "hw/hw.h" |
0d09e41a | 26 | #include "hw/isa/isa.h" |
1de7afc9 | 27 | #include "qemu/main-loop.h" |
7dbb4c49 | 28 | #include "trace.h" |
27503323 | 29 | |
85571bc7 | 30 | /* #define DEBUG_DMA */ |
7ebb5e41 | 31 | |
85571bc7 | 32 | #define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__) |
27503323 | 33 | #ifdef DEBUG_DMA |
27503323 FB |
34 | #define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__) |
35 | #define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__) | |
36 | #else | |
27503323 FB |
37 | #define linfo(...) |
38 | #define ldebug(...) | |
39 | #endif | |
40 | ||
0eee6d62 | 41 | typedef struct I8257Regs { |
27503323 FB |
42 | int now[2]; |
43 | uint16_t base[2]; | |
44 | uint8_t mode; | |
45 | uint8_t page; | |
b0bda528 | 46 | uint8_t pageh; |
27503323 FB |
47 | uint8_t dack; |
48 | uint8_t eop; | |
16f62432 FB |
49 | DMA_transfer_handler transfer_handler; |
50 | void *opaque; | |
0eee6d62 | 51 | } I8257Regs; |
27503323 FB |
52 | |
53 | #define ADDR 0 | |
54 | #define COUNT 1 | |
55 | ||
6a128b13 | 56 | typedef struct I8257State { |
27503323 FB |
57 | uint8_t status; |
58 | uint8_t command; | |
59 | uint8_t mask; | |
60 | uint8_t flip_flop; | |
9eb153f1 | 61 | int dshift; |
0eee6d62 | 62 | I8257Regs regs[4]; |
58229933 JG |
63 | MemoryRegion channel_io; |
64 | MemoryRegion cont_io; | |
6a128b13 HP |
65 | } I8257State; |
66 | ||
67 | static I8257State dma_controllers[2]; | |
27503323 FB |
68 | |
69 | enum { | |
e875c40a FB |
70 | CMD_MEMORY_TO_MEMORY = 0x01, |
71 | CMD_FIXED_ADDRESS = 0x02, | |
72 | CMD_BLOCK_CONTROLLER = 0x04, | |
73 | CMD_COMPRESSED_TIME = 0x08, | |
74 | CMD_CYCLIC_PRIORITY = 0x10, | |
75 | CMD_EXTENDED_WRITE = 0x20, | |
76 | CMD_LOW_DREQ = 0x40, | |
77 | CMD_LOW_DACK = 0x80, | |
78 | CMD_NOT_SUPPORTED = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS | |
79 | | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE | |
80 | | CMD_LOW_DREQ | CMD_LOW_DACK | |
27503323 FB |
81 | |
82 | }; | |
83 | ||
74c47de0 | 84 | static void i8257_dma_run(void); |
492c30af | 85 | |
9eb153f1 FB |
86 | static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0}; |
87 | ||
74c47de0 | 88 | static void i8257_write_page(void *opaque, uint32_t nport, uint32_t data) |
27503323 | 89 | { |
6a128b13 | 90 | I8257State *d = opaque; |
27503323 | 91 | int ichan; |
27503323 | 92 | |
9eb153f1 | 93 | ichan = channels[nport & 7]; |
27503323 | 94 | if (-1 == ichan) { |
85571bc7 | 95 | dolog ("invalid channel %#x %#x\n", nport, data); |
27503323 FB |
96 | return; |
97 | } | |
9eb153f1 FB |
98 | d->regs[ichan].page = data; |
99 | } | |
100 | ||
74c47de0 | 101 | static void i8257_write_pageh(void *opaque, uint32_t nport, uint32_t data) |
9eb153f1 | 102 | { |
6a128b13 | 103 | I8257State *d = opaque; |
9eb153f1 | 104 | int ichan; |
27503323 | 105 | |
9eb153f1 | 106 | ichan = channels[nport & 7]; |
b0bda528 | 107 | if (-1 == ichan) { |
85571bc7 | 108 | dolog ("invalid channel %#x %#x\n", nport, data); |
b0bda528 FB |
109 | return; |
110 | } | |
111 | d->regs[ichan].pageh = data; | |
112 | } | |
9eb153f1 | 113 | |
74c47de0 | 114 | static uint32_t i8257_read_page(void *opaque, uint32_t nport) |
b0bda528 | 115 | { |
6a128b13 | 116 | I8257State *d = opaque; |
b0bda528 FB |
117 | int ichan; |
118 | ||
119 | ichan = channels[nport & 7]; | |
9eb153f1 | 120 | if (-1 == ichan) { |
85571bc7 | 121 | dolog ("invalid channel read %#x\n", nport); |
9eb153f1 FB |
122 | return 0; |
123 | } | |
124 | return d->regs[ichan].page; | |
27503323 FB |
125 | } |
126 | ||
74c47de0 | 127 | static uint32_t i8257_read_pageh(void *opaque, uint32_t nport) |
b0bda528 | 128 | { |
6a128b13 | 129 | I8257State *d = opaque; |
b0bda528 FB |
130 | int ichan; |
131 | ||
132 | ichan = channels[nport & 7]; | |
133 | if (-1 == ichan) { | |
85571bc7 | 134 | dolog ("invalid channel read %#x\n", nport); |
b0bda528 FB |
135 | return 0; |
136 | } | |
137 | return d->regs[ichan].pageh; | |
138 | } | |
139 | ||
74c47de0 | 140 | static inline void i8257_init_chan(I8257State *d, int ichan) |
27503323 | 141 | { |
0eee6d62 | 142 | I8257Regs *r; |
27503323 | 143 | |
9eb153f1 | 144 | r = d->regs + ichan; |
85571bc7 | 145 | r->now[ADDR] = r->base[ADDR] << d->dshift; |
27503323 FB |
146 | r->now[COUNT] = 0; |
147 | } | |
148 | ||
74c47de0 | 149 | static inline int i8257_getff(I8257State *d) |
27503323 FB |
150 | { |
151 | int ff; | |
152 | ||
9eb153f1 FB |
153 | ff = d->flip_flop; |
154 | d->flip_flop = !ff; | |
27503323 FB |
155 | return ff; |
156 | } | |
157 | ||
74c47de0 | 158 | static uint64_t i8257_read_chan(void *opaque, hwaddr nport, unsigned size) |
27503323 | 159 | { |
6a128b13 | 160 | I8257State *d = opaque; |
85571bc7 | 161 | int ichan, nreg, iport, ff, val, dir; |
0eee6d62 | 162 | I8257Regs *r; |
27503323 | 163 | |
9eb153f1 FB |
164 | iport = (nport >> d->dshift) & 0x0f; |
165 | ichan = iport >> 1; | |
166 | nreg = iport & 1; | |
167 | r = d->regs + ichan; | |
27503323 | 168 | |
85571bc7 | 169 | dir = ((r->mode >> 5) & 1) ? -1 : 1; |
74c47de0 | 170 | ff = i8257_getff(d); |
27503323 | 171 | if (nreg) |
9eb153f1 | 172 | val = (r->base[COUNT] << d->dshift) - r->now[COUNT]; |
27503323 | 173 | else |
85571bc7 | 174 | val = r->now[ADDR] + r->now[COUNT] * dir; |
27503323 | 175 | |
85571bc7 | 176 | ldebug ("read_chan %#x -> %d\n", iport, val); |
9eb153f1 | 177 | return (val >> (d->dshift + (ff << 3))) & 0xff; |
27503323 FB |
178 | } |
179 | ||
74c47de0 HP |
180 | static void i8257_write_chan(void *opaque, hwaddr nport, uint64_t data, |
181 | unsigned int size) | |
27503323 | 182 | { |
6a128b13 | 183 | I8257State *d = opaque; |
9eb153f1 | 184 | int iport, ichan, nreg; |
0eee6d62 | 185 | I8257Regs *r; |
27503323 | 186 | |
9eb153f1 FB |
187 | iport = (nport >> d->dshift) & 0x0f; |
188 | ichan = iport >> 1; | |
189 | nreg = iport & 1; | |
190 | r = d->regs + ichan; | |
74c47de0 | 191 | if (i8257_getff(d)) { |
3504fe17 | 192 | r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00); |
74c47de0 | 193 | i8257_init_chan(d, ichan); |
3504fe17 FB |
194 | } else { |
195 | r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff); | |
27503323 | 196 | } |
27503323 FB |
197 | } |
198 | ||
74c47de0 HP |
199 | static void i8257_write_cont(void *opaque, hwaddr nport, uint64_t data, |
200 | unsigned int size) | |
27503323 | 201 | { |
6a128b13 | 202 | I8257State *d = opaque; |
85571bc7 | 203 | int iport, ichan = 0; |
27503323 | 204 | |
9eb153f1 | 205 | iport = (nport >> d->dshift) & 0x0f; |
27503323 | 206 | switch (iport) { |
ecd584b8 | 207 | case 0x00: /* command */ |
df475d18 | 208 | if ((data != 0) && (data & CMD_NOT_SUPPORTED)) { |
58229933 | 209 | dolog("command %"PRIx64" not supported\n", data); |
df475d18 | 210 | return; |
27503323 FB |
211 | } |
212 | d->command = data; | |
213 | break; | |
214 | ||
ecd584b8 | 215 | case 0x01: |
27503323 FB |
216 | ichan = data & 3; |
217 | if (data & 4) { | |
218 | d->status |= 1 << (ichan + 4); | |
219 | } | |
220 | else { | |
221 | d->status &= ~(1 << (ichan + 4)); | |
222 | } | |
223 | d->status &= ~(1 << ichan); | |
74c47de0 | 224 | i8257_dma_run(); |
27503323 FB |
225 | break; |
226 | ||
ecd584b8 | 227 | case 0x02: /* single mask */ |
27503323 FB |
228 | if (data & 4) |
229 | d->mask |= 1 << (data & 3); | |
230 | else | |
231 | d->mask &= ~(1 << (data & 3)); | |
74c47de0 | 232 | i8257_dma_run(); |
27503323 FB |
233 | break; |
234 | ||
ecd584b8 | 235 | case 0x03: /* mode */ |
27503323 | 236 | { |
16d17fdb FB |
237 | ichan = data & 3; |
238 | #ifdef DEBUG_DMA | |
85571bc7 FB |
239 | { |
240 | int op, ai, dir, opmode; | |
e875c40a FB |
241 | op = (data >> 2) & 3; |
242 | ai = (data >> 4) & 1; | |
243 | dir = (data >> 5) & 1; | |
244 | opmode = (data >> 6) & 3; | |
27503323 | 245 | |
e875c40a FB |
246 | linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n", |
247 | ichan, op, ai, dir, opmode); | |
85571bc7 | 248 | } |
27503323 | 249 | #endif |
27503323 FB |
250 | d->regs[ichan].mode = data; |
251 | break; | |
252 | } | |
253 | ||
ecd584b8 | 254 | case 0x04: /* clear flip flop */ |
27503323 FB |
255 | d->flip_flop = 0; |
256 | break; | |
257 | ||
ecd584b8 | 258 | case 0x05: /* reset */ |
27503323 FB |
259 | d->flip_flop = 0; |
260 | d->mask = ~0; | |
261 | d->status = 0; | |
262 | d->command = 0; | |
263 | break; | |
264 | ||
ecd584b8 | 265 | case 0x06: /* clear mask for all channels */ |
27503323 | 266 | d->mask = 0; |
74c47de0 | 267 | i8257_dma_run(); |
27503323 FB |
268 | break; |
269 | ||
ecd584b8 | 270 | case 0x07: /* write mask for all channels */ |
27503323 | 271 | d->mask = data; |
74c47de0 | 272 | i8257_dma_run(); |
27503323 FB |
273 | break; |
274 | ||
275 | default: | |
85571bc7 | 276 | dolog ("unknown iport %#x\n", iport); |
df475d18 | 277 | break; |
27503323 FB |
278 | } |
279 | ||
16d17fdb | 280 | #ifdef DEBUG_DMA |
27503323 | 281 | if (0xc != iport) { |
85571bc7 | 282 | linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n", |
9eb153f1 | 283 | nport, ichan, data); |
27503323 FB |
284 | } |
285 | #endif | |
27503323 FB |
286 | } |
287 | ||
74c47de0 | 288 | static uint64_t i8257_read_cont(void *opaque, hwaddr nport, unsigned size) |
9eb153f1 | 289 | { |
6a128b13 | 290 | I8257State *d = opaque; |
9eb153f1 | 291 | int iport, val; |
85571bc7 | 292 | |
9eb153f1 FB |
293 | iport = (nport >> d->dshift) & 0x0f; |
294 | switch (iport) { | |
ecd584b8 | 295 | case 0x00: /* status */ |
9eb153f1 FB |
296 | val = d->status; |
297 | d->status &= 0xf0; | |
298 | break; | |
ecd584b8 | 299 | case 0x01: /* mask */ |
9eb153f1 FB |
300 | val = d->mask; |
301 | break; | |
302 | default: | |
303 | val = 0; | |
304 | break; | |
305 | } | |
85571bc7 FB |
306 | |
307 | ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport, iport, val); | |
9eb153f1 FB |
308 | return val; |
309 | } | |
310 | ||
27503323 FB |
311 | int DMA_get_channel_mode (int nchan) |
312 | { | |
313 | return dma_controllers[nchan > 3].regs[nchan & 3].mode; | |
314 | } | |
315 | ||
316 | void DMA_hold_DREQ (int nchan) | |
317 | { | |
318 | int ncont, ichan; | |
319 | ||
320 | ncont = nchan > 3; | |
321 | ichan = nchan & 3; | |
322 | linfo ("held cont=%d chan=%d\n", ncont, ichan); | |
323 | dma_controllers[ncont].status |= 1 << (ichan + 4); | |
74c47de0 | 324 | i8257_dma_run(); |
27503323 FB |
325 | } |
326 | ||
327 | void DMA_release_DREQ (int nchan) | |
328 | { | |
329 | int ncont, ichan; | |
330 | ||
331 | ncont = nchan > 3; | |
332 | ichan = nchan & 3; | |
333 | linfo ("released cont=%d chan=%d\n", ncont, ichan); | |
334 | dma_controllers[ncont].status &= ~(1 << (ichan + 4)); | |
74c47de0 | 335 | i8257_dma_run(); |
27503323 FB |
336 | } |
337 | ||
74c47de0 | 338 | static void i8257_channel_run(int ncont, int ichan) |
27503323 | 339 | { |
27503323 | 340 | int n; |
0eee6d62 | 341 | I8257Regs *r = &dma_controllers[ncont].regs[ichan]; |
85571bc7 FB |
342 | #ifdef DEBUG_DMA |
343 | int dir, opmode; | |
27503323 | 344 | |
85571bc7 FB |
345 | dir = (r->mode >> 5) & 1; |
346 | opmode = (r->mode >> 6) & 3; | |
27503323 | 347 | |
85571bc7 FB |
348 | if (dir) { |
349 | dolog ("DMA in address decrement mode\n"); | |
350 | } | |
351 | if (opmode != 1) { | |
352 | dolog ("DMA not in single mode select %#x\n", opmode); | |
353 | } | |
354 | #endif | |
27503323 | 355 | |
85571bc7 FB |
356 | n = r->transfer_handler (r->opaque, ichan + (ncont << 2), |
357 | r->now[COUNT], (r->base[COUNT] + 1) << ncont); | |
358 | r->now[COUNT] = n; | |
359 | ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont); | |
27503323 FB |
360 | } |
361 | ||
492c30af | 362 | static QEMUBH *dma_bh; |
19d2b5e6 | 363 | static bool dma_bh_scheduled; |
492c30af | 364 | |
74c47de0 | 365 | static void i8257_dma_run(void) |
27503323 | 366 | { |
6a128b13 | 367 | I8257State *d; |
27503323 | 368 | int icont, ichan; |
492c30af | 369 | int rearm = 0; |
acae6f1c KW |
370 | static int running = 0; |
371 | ||
372 | if (running) { | |
373 | rearm = 1; | |
374 | goto out; | |
375 | } else { | |
376 | running = 1; | |
377 | } | |
27503323 | 378 | |
27503323 FB |
379 | d = dma_controllers; |
380 | ||
381 | for (icont = 0; icont < 2; icont++, d++) { | |
382 | for (ichan = 0; ichan < 4; ichan++) { | |
383 | int mask; | |
384 | ||
385 | mask = 1 << ichan; | |
386 | ||
492c30af | 387 | if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) { |
74c47de0 | 388 | i8257_channel_run(icont, ichan); |
492c30af AL |
389 | rearm = 1; |
390 | } | |
27503323 FB |
391 | } |
392 | } | |
492c30af | 393 | |
acae6f1c KW |
394 | running = 0; |
395 | out: | |
19d2b5e6 | 396 | if (rearm) { |
492c30af | 397 | qemu_bh_schedule_idle(dma_bh); |
19d2b5e6 PB |
398 | dma_bh_scheduled = true; |
399 | } | |
492c30af AL |
400 | } |
401 | ||
74c47de0 | 402 | static void i8257_dma_run_bh(void *unused) |
492c30af | 403 | { |
19d2b5e6 | 404 | dma_bh_scheduled = false; |
74c47de0 | 405 | i8257_dma_run(); |
27503323 FB |
406 | } |
407 | ||
408 | void DMA_register_channel (int nchan, | |
85571bc7 | 409 | DMA_transfer_handler transfer_handler, |
16f62432 | 410 | void *opaque) |
27503323 | 411 | { |
0eee6d62 | 412 | I8257Regs *r; |
27503323 FB |
413 | int ichan, ncont; |
414 | ||
415 | ncont = nchan > 3; | |
416 | ichan = nchan & 3; | |
417 | ||
418 | r = dma_controllers[ncont].regs + ichan; | |
16f62432 FB |
419 | r->transfer_handler = transfer_handler; |
420 | r->opaque = opaque; | |
421 | } | |
422 | ||
85571bc7 FB |
423 | int DMA_read_memory (int nchan, void *buf, int pos, int len) |
424 | { | |
0eee6d62 | 425 | I8257Regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; |
a8170e5e | 426 | hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; |
85571bc7 FB |
427 | |
428 | if (r->mode & 0x20) { | |
429 | int i; | |
430 | uint8_t *p = buf; | |
431 | ||
432 | cpu_physical_memory_read (addr - pos - len, buf, len); | |
433 | /* What about 16bit transfers? */ | |
434 | for (i = 0; i < len >> 1; i++) { | |
435 | uint8_t b = p[len - i - 1]; | |
436 | p[i] = b; | |
437 | } | |
438 | } | |
439 | else | |
440 | cpu_physical_memory_read (addr + pos, buf, len); | |
441 | ||
442 | return len; | |
443 | } | |
444 | ||
445 | int DMA_write_memory (int nchan, void *buf, int pos, int len) | |
446 | { | |
0eee6d62 | 447 | I8257Regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; |
a8170e5e | 448 | hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; |
85571bc7 FB |
449 | |
450 | if (r->mode & 0x20) { | |
451 | int i; | |
452 | uint8_t *p = buf; | |
453 | ||
454 | cpu_physical_memory_write (addr - pos - len, buf, len); | |
455 | /* What about 16bit transfers? */ | |
456 | for (i = 0; i < len; i++) { | |
457 | uint8_t b = p[len - i - 1]; | |
458 | p[i] = b; | |
459 | } | |
460 | } | |
461 | else | |
462 | cpu_physical_memory_write (addr + pos, buf, len); | |
463 | ||
464 | return len; | |
465 | } | |
466 | ||
19d2b5e6 PB |
467 | /* request the emulator to transfer a new DMA memory block ASAP (even |
468 | * if the idle bottom half would not have exited the iothread yet). | |
469 | */ | |
470 | void DMA_schedule(void) | |
16f62432 | 471 | { |
19d2b5e6 PB |
472 | if (dma_bh_scheduled) { |
473 | qemu_notify_event(); | |
474 | } | |
27503323 FB |
475 | } |
476 | ||
74c47de0 | 477 | static void i8257_reset(void *opaque) |
d7d02e3c | 478 | { |
6a128b13 | 479 | I8257State *d = opaque; |
74c47de0 | 480 | i8257_write_cont(d, (0x05 << d->dshift), 0, 1); |
d7d02e3c FB |
481 | } |
482 | ||
74c47de0 HP |
483 | static int i8257_phony_handler(void *opaque, int nchan, int dma_pos, |
484 | int dma_len) | |
ca9cc28c | 485 | { |
7dbb4c49 | 486 | trace_i8257_unregistered_dma(nchan, dma_pos, dma_len); |
ca9cc28c AZ |
487 | return dma_pos; |
488 | } | |
489 | ||
58229933 JG |
490 | |
491 | static const MemoryRegionOps channel_io_ops = { | |
74c47de0 HP |
492 | .read = i8257_read_chan, |
493 | .write = i8257_write_chan, | |
58229933 JG |
494 | .endianness = DEVICE_NATIVE_ENDIAN, |
495 | .impl = { | |
496 | .min_access_size = 1, | |
497 | .max_access_size = 1, | |
498 | }, | |
499 | }; | |
500 | ||
501 | /* IOport from page_base */ | |
502 | static const MemoryRegionPortio page_portio_list[] = { | |
74c47de0 HP |
503 | { 0x01, 3, 1, .write = i8257_write_page, .read = i8257_read_page, }, |
504 | { 0x07, 1, 1, .write = i8257_write_page, .read = i8257_read_page, }, | |
58229933 JG |
505 | PORTIO_END_OF_LIST(), |
506 | }; | |
507 | ||
508 | /* IOport from pageh_base */ | |
509 | static const MemoryRegionPortio pageh_portio_list[] = { | |
74c47de0 HP |
510 | { 0x01, 3, 1, .write = i8257_write_pageh, .read = i8257_read_pageh, }, |
511 | { 0x07, 3, 1, .write = i8257_write_pageh, .read = i8257_read_pageh, }, | |
58229933 JG |
512 | PORTIO_END_OF_LIST(), |
513 | }; | |
514 | ||
515 | static const MemoryRegionOps cont_io_ops = { | |
74c47de0 HP |
516 | .read = i8257_read_cont, |
517 | .write = i8257_write_cont, | |
58229933 JG |
518 | .endianness = DEVICE_NATIVE_ENDIAN, |
519 | .impl = { | |
520 | .min_access_size = 1, | |
521 | .max_access_size = 1, | |
522 | }, | |
523 | }; | |
524 | ||
9eb153f1 | 525 | /* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */ |
6a128b13 | 526 | static void dma_init2(I8257State *d, int base, int dshift, |
5039d6e2 | 527 | int page_base, int pageh_base) |
27503323 FB |
528 | { |
529 | int i; | |
27503323 | 530 | |
9eb153f1 | 531 | d->dshift = dshift; |
58229933 | 532 | |
2c9b15ca | 533 | memory_region_init_io(&d->channel_io, NULL, &channel_io_ops, d, |
58229933 JG |
534 | "dma-chan", 8 << d->dshift); |
535 | memory_region_add_subregion(isa_address_space_io(NULL), | |
536 | base, &d->channel_io); | |
537 | ||
538 | isa_register_portio_list(NULL, page_base, page_portio_list, d, | |
539 | "dma-page"); | |
540 | if (pageh_base >= 0) { | |
541 | isa_register_portio_list(NULL, pageh_base, pageh_portio_list, d, | |
542 | "dma-pageh"); | |
27503323 | 543 | } |
58229933 | 544 | |
2c9b15ca | 545 | memory_region_init_io(&d->cont_io, NULL, &cont_io_ops, d, "dma-cont", |
58229933 JG |
546 | 8 << d->dshift); |
547 | memory_region_add_subregion(isa_address_space_io(NULL), | |
548 | base + (8 << d->dshift), &d->cont_io); | |
549 | ||
74c47de0 HP |
550 | qemu_register_reset(i8257_reset, d); |
551 | i8257_reset(d); | |
b1503cda | 552 | for (i = 0; i < ARRAY_SIZE (d->regs); ++i) { |
74c47de0 | 553 | d->regs[i].transfer_handler = i8257_phony_handler; |
ca9cc28c | 554 | } |
9eb153f1 | 555 | } |
27503323 | 556 | |
0eee6d62 | 557 | static const VMStateDescription vmstate_i8257_regs = { |
7b5045c5 JQ |
558 | .name = "dma_regs", |
559 | .version_id = 1, | |
560 | .minimum_version_id = 1, | |
d49805ae | 561 | .fields = (VMStateField[]) { |
0eee6d62 HP |
562 | VMSTATE_INT32_ARRAY(now, I8257Regs, 2), |
563 | VMSTATE_UINT16_ARRAY(base, I8257Regs, 2), | |
564 | VMSTATE_UINT8(mode, I8257Regs), | |
565 | VMSTATE_UINT8(page, I8257Regs), | |
566 | VMSTATE_UINT8(pageh, I8257Regs), | |
567 | VMSTATE_UINT8(dack, I8257Regs), | |
568 | VMSTATE_UINT8(eop, I8257Regs), | |
7b5045c5 | 569 | VMSTATE_END_OF_LIST() |
85571bc7 | 570 | } |
7b5045c5 | 571 | }; |
85571bc7 | 572 | |
74c47de0 | 573 | static int i8257_post_load(void *opaque, int version_id) |
85571bc7 | 574 | { |
74c47de0 | 575 | i8257_dma_run(); |
492c30af | 576 | |
85571bc7 FB |
577 | return 0; |
578 | } | |
579 | ||
7b5045c5 JQ |
580 | static const VMStateDescription vmstate_dma = { |
581 | .name = "dma", | |
582 | .version_id = 1, | |
583 | .minimum_version_id = 1, | |
74c47de0 | 584 | .post_load = i8257_post_load, |
d49805ae | 585 | .fields = (VMStateField[]) { |
6a128b13 HP |
586 | VMSTATE_UINT8(command, I8257State), |
587 | VMSTATE_UINT8(mask, I8257State), | |
588 | VMSTATE_UINT8(flip_flop, I8257State), | |
589 | VMSTATE_INT32(dshift, I8257State), | |
0eee6d62 HP |
590 | VMSTATE_STRUCT_ARRAY(regs, I8257State, 4, 1, vmstate_i8257_regs, |
591 | I8257Regs), | |
7b5045c5 JQ |
592 | VMSTATE_END_OF_LIST() |
593 | } | |
594 | }; | |
595 | ||
57146941 | 596 | void DMA_init(ISABus *bus, int high_page_enable) |
9eb153f1 | 597 | { |
5039d6e2 PB |
598 | dma_init2(&dma_controllers[0], 0x00, 0, 0x80, high_page_enable ? 0x480 : -1); |
599 | dma_init2(&dma_controllers[1], 0xc0, 1, 0x88, high_page_enable ? 0x488 : -1); | |
0be71e32 AW |
600 | vmstate_register (NULL, 0, &vmstate_dma, &dma_controllers[0]); |
601 | vmstate_register (NULL, 1, &vmstate_dma, &dma_controllers[1]); | |
492c30af | 602 | |
74c47de0 | 603 | dma_bh = qemu_bh_new(i8257_dma_run_bh, NULL); |
27503323 | 604 | } |