[mirror_qemu.git] / hw / dma / i8257.c

/*
 * QEMU DMA emulation
 *
 * Copyright (c) 2003-2004 Vassili Karpov (malc)
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/isa/isa.h"
#include "qemu/main-loop.h"
#include "trace.h"

/* #define DEBUG_DMA */

#define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__)
#ifdef DEBUG_DMA
#define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__)
#define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__)
#else
#define linfo(...)
#define ldebug(...)
#endif

typedef struct I8257Regs {
    int now[2];
    uint16_t base[2];
    uint8_t mode;
    uint8_t page;
    uint8_t pageh;
    uint8_t dack;
    uint8_t eop;
    DMA_transfer_handler transfer_handler;
    void *opaque;
} I8257Regs;

#define ADDR 0
#define COUNT 1

typedef struct I8257State {
    uint8_t status;
    uint8_t command;
    uint8_t mask;
    uint8_t flip_flop;
    int dshift;
    I8257Regs regs[4];
    MemoryRegion channel_io;
    MemoryRegion cont_io;

    QEMUBH *dma_bh;
    bool dma_bh_scheduled;
    int running;
} I8257State;

static I8257State dma_controllers[2];

enum {
    CMD_MEMORY_TO_MEMORY = 0x01,
    CMD_FIXED_ADDRESS    = 0x02,
    CMD_BLOCK_CONTROLLER = 0x04,
    CMD_COMPRESSED_TIME  = 0x08,
    CMD_CYCLIC_PRIORITY  = 0x10,
    CMD_EXTENDED_WRITE   = 0x20,
    CMD_LOW_DREQ         = 0x40,
    CMD_LOW_DACK         = 0x80,
    CMD_NOT_SUPPORTED    = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS
    | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE
    | CMD_LOW_DREQ | CMD_LOW_DACK

};

static void i8257_dma_run(void *opaque);

static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0};

static void i8257_write_page(void *opaque, uint32_t nport, uint32_t data)
{
    I8257State *d = opaque;
    int ichan;

    ichan = channels[nport & 7];
    if (-1 == ichan) {
        dolog ("invalid channel %#x %#x\n", nport, data);
        return;
    }
    d->regs[ichan].page = data;
}

static void i8257_write_pageh(void *opaque, uint32_t nport, uint32_t data)
{
    I8257State *d = opaque;
    int ichan;

    ichan = channels[nport & 7];
    if (-1 == ichan) {
        dolog ("invalid channel %#x %#x\n", nport, data);
        return;
    }
    d->regs[ichan].pageh = data;
}

static uint32_t i8257_read_page(void *opaque, uint32_t nport)
{
    I8257State *d = opaque;
    int ichan;

    ichan = channels[nport & 7];
    if (-1 == ichan) {
        dolog ("invalid channel read %#x\n", nport);
        return 0;
    }
    return d->regs[ichan].page;
}

static uint32_t i8257_read_pageh(void *opaque, uint32_t nport)
{
    I8257State *d = opaque;
    int ichan;

    ichan = channels[nport & 7];
    if (-1 == ichan) {
        dolog ("invalid channel read %#x\n", nport);
        return 0;
    }
    return d->regs[ichan].pageh;
}

static inline void i8257_init_chan(I8257State *d, int ichan)
{
    I8257Regs *r;

    r = d->regs + ichan;
    r->now[ADDR] = r->base[ADDR] << d->dshift;
    r->now[COUNT] = 0;
}

static inline int i8257_getff(I8257State *d)
{
    int ff;

    ff = d->flip_flop;
    d->flip_flop = !ff;
    return ff;
}

static uint64_t i8257_read_chan(void *opaque, hwaddr nport, unsigned size)
{
    I8257State *d = opaque;
    int ichan, nreg, iport, ff, val, dir;
    I8257Regs *r;

    iport = (nport >> d->dshift) & 0x0f;
    ichan = iport >> 1;
    nreg = iport & 1;
    r = d->regs + ichan;

    dir = ((r->mode >> 5) & 1) ? -1 : 1;
    ff = i8257_getff(d);
    if (nreg)
        val = (r->base[COUNT] << d->dshift) - r->now[COUNT];
    else
        val = r->now[ADDR] + r->now[COUNT] * dir;

    ldebug ("read_chan %#x -> %d\n", iport, val);
    return (val >> (d->dshift + (ff << 3))) & 0xff;
}

static void i8257_write_chan(void *opaque, hwaddr nport, uint64_t data,
                             unsigned int size)
{
    I8257State *d = opaque;
    int iport, ichan, nreg;
    I8257Regs *r;

    iport = (nport >> d->dshift) & 0x0f;
    ichan = iport >> 1;
    nreg = iport & 1;
    r = d->regs + ichan;
    if (i8257_getff(d)) {
        r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00);
        i8257_init_chan(d, ichan);
    } else {
        r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff);
    }
}

static void i8257_write_cont(void *opaque, hwaddr nport, uint64_t data,
                             unsigned int size)
{
    I8257State *d = opaque;
    int iport, ichan = 0;

    iport = (nport >> d->dshift) & 0x0f;
    switch (iport) {
    case 0x00:                  /* command */
        if ((data != 0) && (data & CMD_NOT_SUPPORTED)) {
            dolog("command %"PRIx64" not supported\n", data);
            return;
        }
        d->command = data;
        break;

    case 0x01:
        ichan = data & 3;
        if (data & 4) {
            d->status |= 1 << (ichan + 4);
        }
        else {
            d->status &= ~(1 << (ichan + 4));
        }
        d->status &= ~(1 << ichan);
        i8257_dma_run(d);
        break;

    case 0x02:                  /* single mask */
        if (data & 4)
            d->mask |= 1 << (data & 3);
        else
            d->mask &= ~(1 << (data & 3));
        i8257_dma_run(d);
        break;

    case 0x03:                  /* mode */
        {
            ichan = data & 3;
#ifdef DEBUG_DMA
            {
                int op, ai, dir, opmode;
                op = (data >> 2) & 3;
                ai = (data >> 4) & 1;
                dir = (data >> 5) & 1;
                opmode = (data >> 6) & 3;

                linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
                       ichan, op, ai, dir, opmode);
            }
#endif
            d->regs[ichan].mode = data;
            break;
        }

    case 0x04:                  /* clear flip flop */
        d->flip_flop = 0;
        break;

    case 0x05:                  /* reset */
        d->flip_flop = 0;
        d->mask = ~0;
        d->status = 0;
        d->command = 0;
        break;

    case 0x06:                  /* clear mask for all channels */
        d->mask = 0;
        i8257_dma_run(d);
        break;

    case 0x07:                  /* write mask for all channels */
        d->mask = data;
        i8257_dma_run(d);
        break;

    default:
        dolog ("unknown iport %#x\n", iport);
        break;
    }

#ifdef DEBUG_DMA
    if (0xc != iport) {
        linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n",
               nport, ichan, data);
    }
#endif
}

static uint64_t i8257_read_cont(void *opaque, hwaddr nport, unsigned size)
{
    I8257State *d = opaque;
    int iport, val;

    iport = (nport >> d->dshift) & 0x0f;
    switch (iport) {
    case 0x00:                  /* status */
        val = d->status;
        d->status &= 0xf0;
        break;
    case 0x01:                  /* mask */
        val = d->mask;
        break;
    default:
        val = 0;
        break;
    }

    ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport, iport, val);
    return val;
}

int DMA_get_channel_mode (int nchan)
{
    return dma_controllers[nchan > 3].regs[nchan & 3].mode;
}

void DMA_hold_DREQ (int nchan)
{
    int ncont, ichan;

    ncont = nchan > 3;
    ichan = nchan & 3;
    linfo ("held cont=%d chan=%d\n", ncont, ichan);
    dma_controllers[ncont].status |= 1 << (ichan + 4);
    i8257_dma_run(&dma_controllers[ncont]);
}

void DMA_release_DREQ (int nchan)
{
    int ncont, ichan;

    ncont = nchan > 3;
    ichan = nchan & 3;
    linfo ("released cont=%d chan=%d\n", ncont, ichan);
    dma_controllers[ncont].status &= ~(1 << (ichan + 4));
    i8257_dma_run(&dma_controllers[ncont]);
}

static void i8257_channel_run(I8257State *d, int ichan)
{
    int ncont = d->dshift;
    int n;
    I8257Regs *r = &d->regs[ichan];
#ifdef DEBUG_DMA
    int dir, opmode;

    dir = (r->mode >> 5) & 1;
    opmode = (r->mode >> 6) & 3;

    if (dir) {
        dolog ("DMA in address decrement mode\n");
    }
    if (opmode != 1) {
        dolog ("DMA not in single mode select %#x\n", opmode);
    }
#endif

    n = r->transfer_handler (r->opaque, ichan + (ncont << 2),
                             r->now[COUNT], (r->base[COUNT] + 1) << ncont);
    r->now[COUNT] = n;
    ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont);
}

static void i8257_dma_run(void *opaque)
{
    I8257State *d = opaque;
    int ichan;
    int rearm = 0;

    if (d->running) {
        rearm = 1;
        goto out;
    } else {
        d->running = 1;
    }

    for (ichan = 0; ichan < 4; ichan++) {
        int mask;

        mask = 1 << ichan;

        if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) {
            i8257_channel_run(d, ichan);
            rearm = 1;
        }
    }

    d->running = 0;
out:
    if (rearm) {
        qemu_bh_schedule_idle(d->dma_bh);
        d->dma_bh_scheduled = true;
    }
}

void DMA_register_channel (int nchan,
                           DMA_transfer_handler transfer_handler,
                           void *opaque)
{
    I8257Regs *r;
    int ichan, ncont;

    ncont = nchan > 3;
    ichan = nchan & 3;

    r = dma_controllers[ncont].regs + ichan;
    r->transfer_handler = transfer_handler;
    r->opaque = opaque;
}

int DMA_read_memory (int nchan, void *buf, int pos, int len)
{
    I8257Regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
    hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];

    if (r->mode & 0x20) {
        int i;
        uint8_t *p = buf;

        cpu_physical_memory_read (addr - pos - len, buf, len);
        /* What about 16bit transfers? */
        for (i = 0; i < len >> 1; i++) {
            uint8_t b = p[len - i - 1];
            p[i] = b;
        }
    }
    else
        cpu_physical_memory_read (addr + pos, buf, len);

    return len;
}

int DMA_write_memory (int nchan, void *buf, int pos, int len)
{
    I8257Regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
    hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];

    if (r->mode & 0x20) {
        int i;
        uint8_t *p = buf;

        cpu_physical_memory_write (addr - pos - len, buf, len);
        /* What about 16bit transfers? */
        for (i = 0; i < len; i++) {
            uint8_t b = p[len - i - 1];
            p[i] = b;
        }
    }
    else
        cpu_physical_memory_write (addr + pos, buf, len);

    return len;
}

/* request the emulator to transfer a new DMA memory block ASAP (even
 * if the idle bottom half would not have exited the iothread yet).
 */
void DMA_schedule(void)
{
    if (dma_controllers[0].dma_bh_scheduled ||
        dma_controllers[1].dma_bh_scheduled) {
        qemu_notify_event();
    }
}

static void i8257_reset(void *opaque)
{
    I8257State *d = opaque;
    i8257_write_cont(d, (0x05 << d->dshift), 0, 1);
}

static int i8257_phony_handler(void *opaque, int nchan, int dma_pos,
                               int dma_len)
{
    trace_i8257_unregistered_dma(nchan, dma_pos, dma_len);
    return dma_pos;
}


static const MemoryRegionOps channel_io_ops = {
    .read = i8257_read_chan,
    .write = i8257_write_chan,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .impl = {
        .min_access_size = 1,
        .max_access_size = 1,
    },
};

/* IOport from page_base */
static const MemoryRegionPortio page_portio_list[] = {
    { 0x01, 3, 1, .write = i8257_write_page, .read = i8257_read_page, },
    { 0x07, 1, 1, .write = i8257_write_page, .read = i8257_read_page, },
    PORTIO_END_OF_LIST(),
};

/* IOport from pageh_base */
static const MemoryRegionPortio pageh_portio_list[] = {
    { 0x01, 3, 1, .write = i8257_write_pageh, .read = i8257_read_pageh, },
    { 0x07, 3, 1, .write = i8257_write_pageh, .read = i8257_read_pageh, },
    PORTIO_END_OF_LIST(),
};

static const MemoryRegionOps cont_io_ops = {
    .read = i8257_read_cont,
    .write = i8257_write_cont,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .impl = {
        .min_access_size = 1,
        .max_access_size = 1,
    },
};

/* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
static void dma_init2(I8257State *d, int base, int dshift,
                      int page_base, int pageh_base)
{
    int i;

    d->dshift = dshift;

    memory_region_init_io(&d->channel_io, NULL, &channel_io_ops, d,
                          "dma-chan", 8 << d->dshift);
    memory_region_add_subregion(isa_address_space_io(NULL),
                                base, &d->channel_io);

    isa_register_portio_list(NULL, page_base, page_portio_list, d,
                             "dma-page");
    if (pageh_base >= 0) {
        isa_register_portio_list(NULL, pageh_base, pageh_portio_list, d,
                                 "dma-pageh");
    }

    memory_region_init_io(&d->cont_io, NULL, &cont_io_ops, d, "dma-cont",
                          8 << d->dshift);
    memory_region_add_subregion(isa_address_space_io(NULL),
                                base + (8 << d->dshift), &d->cont_io);

    qemu_register_reset(i8257_reset, d);
    i8257_reset(d);
    for (i = 0; i < ARRAY_SIZE (d->regs); ++i) {
        d->regs[i].transfer_handler = i8257_phony_handler;
    }

    d->dma_bh = qemu_bh_new(i8257_dma_run, d);
}

static const VMStateDescription vmstate_i8257_regs = {
    .name = "dma_regs",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_INT32_ARRAY(now, I8257Regs, 2),
        VMSTATE_UINT16_ARRAY(base, I8257Regs, 2),
        VMSTATE_UINT8(mode, I8257Regs),
        VMSTATE_UINT8(page, I8257Regs),
        VMSTATE_UINT8(pageh, I8257Regs),
        VMSTATE_UINT8(dack, I8257Regs),
        VMSTATE_UINT8(eop, I8257Regs),
        VMSTATE_END_OF_LIST()
    }
};

static int i8257_post_load(void *opaque, int version_id)
{
    I8257State *d = opaque;
    i8257_dma_run(d);

    return 0;
}

static const VMStateDescription vmstate_dma = {
    .name = "dma",
    .version_id = 1,
    .minimum_version_id = 1,
    .post_load = i8257_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT8(command, I8257State),
        VMSTATE_UINT8(mask, I8257State),
        VMSTATE_UINT8(flip_flop, I8257State),
        VMSTATE_INT32(dshift, I8257State),
        VMSTATE_STRUCT_ARRAY(regs, I8257State, 4, 1, vmstate_i8257_regs,
                             I8257Regs),
        VMSTATE_END_OF_LIST()
    }
};

void DMA_init(ISABus *bus, int high_page_enable)
{
    dma_init2(&dma_controllers[0], 0x00, 0, 0x80, high_page_enable ? 0x480 : -1);
    dma_init2(&dma_controllers[1], 0xc0, 1, 0x88, high_page_enable ? 0x488 : -1);
    vmstate_register (NULL, 0, &vmstate_dma, &dma_controllers[0]);
    vmstate_register (NULL, 1, &vmstate_dma, &dma_controllers[1]);
}
Commit	Line	Data
27503323 FB	1	/*
27503323 FB	2	* QEMU DMA emulation
85571bc7 FB	3	*
	4	* Copyright (c) 2003-2004 Vassili Karpov (malc)
	5	*
27503323 FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
b6a0aa05	24	#include "qemu/osdep.h"
83c9f4ca	25	#include "hw/hw.h"
0d09e41a	26	#include "hw/isa/isa.h"
1de7afc9	27	#include "qemu/main-loop.h"
7dbb4c49	28	#include "trace.h"
27503323	29
85571bc7	30	/* #define DEBUG_DMA */
7ebb5e41	31
85571bc7	32	#define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__)
27503323	33	#ifdef DEBUG_DMA
27503323 FB	34	#define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__)
	35	#define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__)
	36	#else
27503323 FB	37	#define linfo(...)
	38	#define ldebug(...)
	39	#endif
	40
0eee6d62	41	typedef struct I8257Regs {
27503323 FB	42	int now[2];
	43	uint16_t base[2];
	44	uint8_t mode;
	45	uint8_t page;
b0bda528	46	uint8_t pageh;
27503323 FB	47	uint8_t dack;
27503323 FB	48	uint8_t eop;
16f62432 FB	49	DMA_transfer_handler transfer_handler;
16f62432 FB	50	void *opaque;
0eee6d62	51	} I8257Regs;
27503323 FB	52
	53	#define ADDR 0
	54	#define COUNT 1
	55
6a128b13	56	typedef struct I8257State {
27503323 FB	57	uint8_t status;
	58	uint8_t command;
	59	uint8_t mask;
	60	uint8_t flip_flop;
9eb153f1	61	int dshift;
0eee6d62	62	I8257Regs regs[4];
58229933 JG	63	MemoryRegion channel_io;
58229933 JG	64	MemoryRegion cont_io;
b9ebd28c HP	65
	66	QEMUBH *dma_bh;
	67	bool dma_bh_scheduled;
	68	int running;
6a128b13 HP	69	} I8257State;
	70
	71	static I8257State dma_controllers[2];
27503323 FB	72
27503323 FB	73	enum {
e875c40a FB	74	CMD_MEMORY_TO_MEMORY = 0x01,
	75	CMD_FIXED_ADDRESS = 0x02,
	76	CMD_BLOCK_CONTROLLER = 0x04,
	77	CMD_COMPRESSED_TIME = 0x08,
	78	CMD_CYCLIC_PRIORITY = 0x10,
	79	CMD_EXTENDED_WRITE = 0x20,
	80	CMD_LOW_DREQ = 0x40,
	81	CMD_LOW_DACK = 0x80,
	82	CMD_NOT_SUPPORTED = CMD_MEMORY_TO_MEMORY \| CMD_FIXED_ADDRESS
	83	\| CMD_COMPRESSED_TIME \| CMD_CYCLIC_PRIORITY \| CMD_EXTENDED_WRITE
	84	\| CMD_LOW_DREQ \| CMD_LOW_DACK
27503323 FB	85
	86	};
	87
b9ebd28c	88	static void i8257_dma_run(void *opaque);
492c30af	89
9eb153f1 FB	90	static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
9eb153f1 FB	91
74c47de0	92	static void i8257_write_page(void *opaque, uint32_t nport, uint32_t data)
27503323	93	{
6a128b13	94	I8257State *d = opaque;
27503323	95	int ichan;
27503323	96
9eb153f1	97	ichan = channels[nport & 7];
27503323	98	if (-1 == ichan) {
85571bc7	99	dolog ("invalid channel %#x %#x\n", nport, data);
27503323 FB	100	return;
27503323 FB	101	}
9eb153f1 FB	102	d->regs[ichan].page = data;
	103	}
	104
74c47de0	105	static void i8257_write_pageh(void *opaque, uint32_t nport, uint32_t data)
9eb153f1	106	{
6a128b13	107	I8257State *d = opaque;
9eb153f1	108	int ichan;
27503323	109
9eb153f1	110	ichan = channels[nport & 7];
b0bda528	111	if (-1 == ichan) {
85571bc7	112	dolog ("invalid channel %#x %#x\n", nport, data);
b0bda528 FB	113	return;
	114	}
	115	d->regs[ichan].pageh = data;
	116	}
9eb153f1	117
74c47de0	118	static uint32_t i8257_read_page(void *opaque, uint32_t nport)
b0bda528	119	{
6a128b13	120	I8257State *d = opaque;
b0bda528 FB	121	int ichan;
	122
	123	ichan = channels[nport & 7];
9eb153f1	124	if (-1 == ichan) {
85571bc7	125	dolog ("invalid channel read %#x\n", nport);
9eb153f1 FB	126	return 0;
	127	}
	128	return d->regs[ichan].page;
27503323 FB	129	}
27503323 FB	130
74c47de0	131	static uint32_t i8257_read_pageh(void *opaque, uint32_t nport)
b0bda528	132	{
6a128b13	133	I8257State *d = opaque;
b0bda528 FB	134	int ichan;
	135
	136	ichan = channels[nport & 7];
	137	if (-1 == ichan) {
85571bc7	138	dolog ("invalid channel read %#x\n", nport);
b0bda528 FB	139	return 0;
	140	}
	141	return d->regs[ichan].pageh;
	142	}
	143
74c47de0	144	static inline void i8257_init_chan(I8257State *d, int ichan)
27503323	145	{
0eee6d62	146	I8257Regs *r;
27503323	147
9eb153f1	148	r = d->regs + ichan;
85571bc7	149	r->now[ADDR] = r->base[ADDR] << d->dshift;
27503323 FB	150	r->now[COUNT] = 0;
	151	}
	152
74c47de0	153	static inline int i8257_getff(I8257State *d)
27503323 FB	154	{
	155	int ff;
	156
9eb153f1 FB	157	ff = d->flip_flop;
9eb153f1 FB	158	d->flip_flop = !ff;
27503323 FB	159	return ff;
	160	}
	161
74c47de0	162	static uint64_t i8257_read_chan(void *opaque, hwaddr nport, unsigned size)
27503323	163	{
6a128b13	164	I8257State *d = opaque;
85571bc7	165	int ichan, nreg, iport, ff, val, dir;
0eee6d62	166	I8257Regs *r;
27503323	167
9eb153f1 FB	168	iport = (nport >> d->dshift) & 0x0f;
	169	ichan = iport >> 1;
	170	nreg = iport & 1;
	171	r = d->regs + ichan;
27503323	172
85571bc7	173	dir = ((r->mode >> 5) & 1) ? -1 : 1;
74c47de0	174	ff = i8257_getff(d);
27503323	175	if (nreg)
9eb153f1	176	val = (r->base[COUNT] << d->dshift) - r->now[COUNT];
27503323	177	else
85571bc7	178	val = r->now[ADDR] + r->now[COUNT] * dir;
27503323	179
85571bc7	180	ldebug ("read_chan %#x -> %d\n", iport, val);
9eb153f1	181	return (val >> (d->dshift + (ff << 3))) & 0xff;
27503323 FB	182	}
27503323 FB	183
74c47de0 HP	184	static void i8257_write_chan(void *opaque, hwaddr nport, uint64_t data,
74c47de0 HP	185	unsigned int size)
27503323	186	{
6a128b13	187	I8257State *d = opaque;
9eb153f1	188	int iport, ichan, nreg;
0eee6d62	189	I8257Regs *r;
27503323	190
9eb153f1 FB	191	iport = (nport >> d->dshift) & 0x0f;
	192	ichan = iport >> 1;
	193	nreg = iport & 1;
	194	r = d->regs + ichan;
74c47de0	195	if (i8257_getff(d)) {
3504fe17	196	r->base[nreg] = (r->base[nreg] & 0xff) \| ((data << 8) & 0xff00);
74c47de0	197	i8257_init_chan(d, ichan);
3504fe17 FB	198	} else {
3504fe17 FB	199	r->base[nreg] = (r->base[nreg] & 0xff00) \| (data & 0xff);
27503323	200	}
27503323 FB	201	}
27503323 FB	202
74c47de0 HP	203	static void i8257_write_cont(void *opaque, hwaddr nport, uint64_t data,
74c47de0 HP	204	unsigned int size)
27503323	205	{
6a128b13	206	I8257State *d = opaque;
85571bc7	207	int iport, ichan = 0;
27503323	208
9eb153f1	209	iport = (nport >> d->dshift) & 0x0f;
27503323	210	switch (iport) {
ecd584b8	211	case 0x00: /* command */
df475d18	212	if ((data != 0) && (data & CMD_NOT_SUPPORTED)) {
58229933	213	dolog("command %"PRIx64" not supported\n", data);
df475d18	214	return;
27503323 FB	215	}
	216	d->command = data;
	217	break;
	218
ecd584b8	219	case 0x01:
27503323 FB	220	ichan = data & 3;
	221	if (data & 4) {
	222	d->status \|= 1 << (ichan + 4);
	223	}
	224	else {
	225	d->status &= ~(1 << (ichan + 4));
	226	}
	227	d->status &= ~(1 << ichan);
b9ebd28c	228	i8257_dma_run(d);
27503323 FB	229	break;
27503323 FB	230
ecd584b8	231	case 0x02: /* single mask */
27503323 FB	232	if (data & 4)
	233	d->mask \|= 1 << (data & 3);
	234	else
	235	d->mask &= ~(1 << (data & 3));
b9ebd28c	236	i8257_dma_run(d);
27503323 FB	237	break;
27503323 FB	238
ecd584b8	239	case 0x03: /* mode */
27503323	240	{
16d17fdb FB	241	ichan = data & 3;
16d17fdb FB	242	#ifdef DEBUG_DMA
85571bc7 FB	243	{
85571bc7 FB	244	int op, ai, dir, opmode;
e875c40a FB	245	op = (data >> 2) & 3;
	246	ai = (data >> 4) & 1;
	247	dir = (data >> 5) & 1;
	248	opmode = (data >> 6) & 3;
27503323	249
e875c40a FB	250	linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
e875c40a FB	251	ichan, op, ai, dir, opmode);
85571bc7	252	}
27503323	253	#endif
27503323 FB	254	d->regs[ichan].mode = data;
	255	break;
	256	}
	257
ecd584b8	258	case 0x04: /* clear flip flop */
27503323 FB	259	d->flip_flop = 0;
	260	break;
	261
ecd584b8	262	case 0x05: /* reset */
27503323 FB	263	d->flip_flop = 0;
	264	d->mask = ~0;
	265	d->status = 0;
	266	d->command = 0;
	267	break;
	268
ecd584b8	269	case 0x06: /* clear mask for all channels */
27503323	270	d->mask = 0;
b9ebd28c	271	i8257_dma_run(d);
27503323 FB	272	break;
27503323 FB	273
ecd584b8	274	case 0x07: /* write mask for all channels */
27503323	275	d->mask = data;
b9ebd28c	276	i8257_dma_run(d);
27503323 FB	277	break;
	278
	279	default:
85571bc7	280	dolog ("unknown iport %#x\n", iport);
df475d18	281	break;
27503323 FB	282	}
27503323 FB	283
16d17fdb	284	#ifdef DEBUG_DMA
27503323	285	if (0xc != iport) {
85571bc7	286	linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n",
9eb153f1	287	nport, ichan, data);
27503323 FB	288	}
27503323 FB	289	#endif
27503323 FB	290	}
27503323 FB	291
74c47de0	292	static uint64_t i8257_read_cont(void *opaque, hwaddr nport, unsigned size)
9eb153f1	293	{
6a128b13	294	I8257State *d = opaque;
9eb153f1	295	int iport, val;
85571bc7	296
9eb153f1 FB	297	iport = (nport >> d->dshift) & 0x0f;
9eb153f1 FB	298	switch (iport) {
ecd584b8	299	case 0x00: /* status */
9eb153f1 FB	300	val = d->status;
	301	d->status &= 0xf0;
	302	break;
ecd584b8	303	case 0x01: /* mask */
9eb153f1 FB	304	val = d->mask;
	305	break;
	306	default:
	307	val = 0;
	308	break;
	309	}
85571bc7 FB	310
85571bc7 FB	311	ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport, iport, val);
9eb153f1 FB	312	return val;
	313	}
	314
27503323 FB	315	int DMA_get_channel_mode (int nchan)
	316	{
	317	return dma_controllers[nchan > 3].regs[nchan & 3].mode;
	318	}
	319
	320	void DMA_hold_DREQ (int nchan)
	321	{
	322	int ncont, ichan;
	323
	324	ncont = nchan > 3;
	325	ichan = nchan & 3;
	326	linfo ("held cont=%d chan=%d\n", ncont, ichan);
	327	dma_controllers[ncont].status \|= 1 << (ichan + 4);
b9ebd28c	328	i8257_dma_run(&dma_controllers[ncont]);
27503323 FB	329	}
	330
	331	void DMA_release_DREQ (int nchan)
	332	{
	333	int ncont, ichan;
	334
	335	ncont = nchan > 3;
	336	ichan = nchan & 3;
	337	linfo ("released cont=%d chan=%d\n", ncont, ichan);
	338	dma_controllers[ncont].status &= ~(1 << (ichan + 4));
b9ebd28c	339	i8257_dma_run(&dma_controllers[ncont]);
27503323 FB	340	}
27503323 FB	341
b9ebd28c	342	static void i8257_channel_run(I8257State *d, int ichan)
27503323	343	{
b9ebd28c	344	int ncont = d->dshift;
27503323	345	int n;
b9ebd28c	346	I8257Regs *r = &d->regs[ichan];
85571bc7 FB	347	#ifdef DEBUG_DMA
85571bc7 FB	348	int dir, opmode;
27503323	349
85571bc7 FB	350	dir = (r->mode >> 5) & 1;
85571bc7 FB	351	opmode = (r->mode >> 6) & 3;
27503323	352
85571bc7 FB	353	if (dir) {
	354	dolog ("DMA in address decrement mode\n");
	355	}
	356	if (opmode != 1) {
	357	dolog ("DMA not in single mode select %#x\n", opmode);
	358	}
	359	#endif
27503323	360
85571bc7 FB	361	n = r->transfer_handler (r->opaque, ichan + (ncont << 2),
	362	r->now[COUNT], (r->base[COUNT] + 1) << ncont);
	363	r->now[COUNT] = n;
	364	ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont);
27503323 FB	365	}
27503323 FB	366
b9ebd28c	367	static void i8257_dma_run(void *opaque)
27503323	368	{
b9ebd28c HP	369	I8257State *d = opaque;
b9ebd28c HP	370	int ichan;
492c30af	371	int rearm = 0;
acae6f1c	372
b9ebd28c	373	if (d->running) {
acae6f1c KW	374	rearm = 1;
	375	goto out;
	376	} else {
b9ebd28c	377	d->running = 1;
acae6f1c	378	}
27503323	379
b9ebd28c HP	380	for (ichan = 0; ichan < 4; ichan++) {
b9ebd28c HP	381	int mask;
27503323	382
b9ebd28c	383	mask = 1 << ichan;
27503323	384
b9ebd28c HP	385	if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) {
	386	i8257_channel_run(d, ichan);
	387	rearm = 1;
27503323 FB	388	}
27503323 FB	389	}
492c30af	390
b9ebd28c	391	d->running = 0;
acae6f1c	392	out:
19d2b5e6	393	if (rearm) {
b9ebd28c HP	394	qemu_bh_schedule_idle(d->dma_bh);
b9ebd28c HP	395	d->dma_bh_scheduled = true;
19d2b5e6	396	}
492c30af AL	397	}
492c30af AL	398
27503323	399	void DMA_register_channel (int nchan,
85571bc7	400	DMA_transfer_handler transfer_handler,
16f62432	401	void *opaque)
27503323	402	{
0eee6d62	403	I8257Regs *r;
27503323 FB	404	int ichan, ncont;
	405
	406	ncont = nchan > 3;
	407	ichan = nchan & 3;
	408
	409	r = dma_controllers[ncont].regs + ichan;
16f62432 FB	410	r->transfer_handler = transfer_handler;
	411	r->opaque = opaque;
	412	}
	413
85571bc7 FB	414	int DMA_read_memory (int nchan, void *buf, int pos, int len)
85571bc7 FB	415	{
0eee6d62	416	I8257Regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
a8170e5e	417	hwaddr addr = ((r->pageh & 0x7f) << 24) \| (r->page << 16) \| r->now[ADDR];
85571bc7 FB	418
	419	if (r->mode & 0x20) {
	420	int i;
	421	uint8_t *p = buf;
	422
	423	cpu_physical_memory_read (addr - pos - len, buf, len);
	424	/* What about 16bit transfers? */
	425	for (i = 0; i < len >> 1; i++) {
	426	uint8_t b = p[len - i - 1];
	427	p[i] = b;
	428	}
	429	}
	430	else
	431	cpu_physical_memory_read (addr + pos, buf, len);
	432
	433	return len;
	434	}
	435
	436	int DMA_write_memory (int nchan, void *buf, int pos, int len)
	437	{
0eee6d62	438	I8257Regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
a8170e5e	439	hwaddr addr = ((r->pageh & 0x7f) << 24) \| (r->page << 16) \| r->now[ADDR];
85571bc7 FB	440
	441	if (r->mode & 0x20) {
	442	int i;
	443	uint8_t *p = buf;
	444
	445	cpu_physical_memory_write (addr - pos - len, buf, len);
	446	/* What about 16bit transfers? */
	447	for (i = 0; i < len; i++) {
	448	uint8_t b = p[len - i - 1];
	449	p[i] = b;
	450	}
	451	}
	452	else
	453	cpu_physical_memory_write (addr + pos, buf, len);
	454
	455	return len;
	456	}
	457
19d2b5e6 PB	458	/* request the emulator to transfer a new DMA memory block ASAP (even
	459	* if the idle bottom half would not have exited the iothread yet).
	460	*/
	461	void DMA_schedule(void)
16f62432	462	{
b9ebd28c HP	463	if (dma_controllers[0].dma_bh_scheduled \|\|
b9ebd28c HP	464	dma_controllers[1].dma_bh_scheduled) {
19d2b5e6 PB	465	qemu_notify_event();
19d2b5e6 PB	466	}
27503323 FB	467	}
27503323 FB	468
74c47de0	469	static void i8257_reset(void *opaque)
d7d02e3c	470	{
6a128b13	471	I8257State *d = opaque;
74c47de0	472	i8257_write_cont(d, (0x05 << d->dshift), 0, 1);
d7d02e3c FB	473	}
d7d02e3c FB	474
74c47de0 HP	475	static int i8257_phony_handler(void *opaque, int nchan, int dma_pos,
74c47de0 HP	476	int dma_len)
ca9cc28c	477	{
7dbb4c49	478	trace_i8257_unregistered_dma(nchan, dma_pos, dma_len);
ca9cc28c AZ	479	return dma_pos;
	480	}
	481
58229933 JG	482
58229933 JG	483	static const MemoryRegionOps channel_io_ops = {
74c47de0 HP	484	.read = i8257_read_chan,
74c47de0 HP	485	.write = i8257_write_chan,
58229933 JG	486	.endianness = DEVICE_NATIVE_ENDIAN,
	487	.impl = {
	488	.min_access_size = 1,
	489	.max_access_size = 1,
	490	},
	491	};
	492
	493	/* IOport from page_base */
	494	static const MemoryRegionPortio page_portio_list[] = {
74c47de0 HP	495	{ 0x01, 3, 1, .write = i8257_write_page, .read = i8257_read_page, },
74c47de0 HP	496	{ 0x07, 1, 1, .write = i8257_write_page, .read = i8257_read_page, },
58229933 JG	497	PORTIO_END_OF_LIST(),
	498	};
	499
	500	/* IOport from pageh_base */
	501	static const MemoryRegionPortio pageh_portio_list[] = {
74c47de0 HP	502	{ 0x01, 3, 1, .write = i8257_write_pageh, .read = i8257_read_pageh, },
74c47de0 HP	503	{ 0x07, 3, 1, .write = i8257_write_pageh, .read = i8257_read_pageh, },
58229933 JG	504	PORTIO_END_OF_LIST(),
	505	};
	506
	507	static const MemoryRegionOps cont_io_ops = {
74c47de0 HP	508	.read = i8257_read_cont,
74c47de0 HP	509	.write = i8257_write_cont,
58229933 JG	510	.endianness = DEVICE_NATIVE_ENDIAN,
	511	.impl = {
	512	.min_access_size = 1,
	513	.max_access_size = 1,
	514	},
	515	};
	516
9eb153f1	517	/* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
6a128b13	518	static void dma_init2(I8257State *d, int base, int dshift,
5039d6e2	519	int page_base, int pageh_base)
27503323 FB	520	{
27503323 FB	521	int i;
27503323	522
9eb153f1	523	d->dshift = dshift;
58229933	524
2c9b15ca	525	memory_region_init_io(&d->channel_io, NULL, &channel_io_ops, d,
58229933 JG	526	"dma-chan", 8 << d->dshift);
	527	memory_region_add_subregion(isa_address_space_io(NULL),
	528	base, &d->channel_io);
	529
	530	isa_register_portio_list(NULL, page_base, page_portio_list, d,
	531	"dma-page");
	532	if (pageh_base >= 0) {
	533	isa_register_portio_list(NULL, pageh_base, pageh_portio_list, d,
	534	"dma-pageh");
27503323	535	}
58229933	536
2c9b15ca	537	memory_region_init_io(&d->cont_io, NULL, &cont_io_ops, d, "dma-cont",
58229933 JG	538	8 << d->dshift);
	539	memory_region_add_subregion(isa_address_space_io(NULL),
	540	base + (8 << d->dshift), &d->cont_io);
	541
74c47de0 HP	542	qemu_register_reset(i8257_reset, d);
74c47de0 HP	543	i8257_reset(d);
b1503cda	544	for (i = 0; i < ARRAY_SIZE (d->regs); ++i) {
74c47de0	545	d->regs[i].transfer_handler = i8257_phony_handler;
ca9cc28c	546	}
b9ebd28c HP	547
b9ebd28c HP	548	d->dma_bh = qemu_bh_new(i8257_dma_run, d);
9eb153f1	549	}
27503323	550
0eee6d62	551	static const VMStateDescription vmstate_i8257_regs = {
7b5045c5 JQ	552	.name = "dma_regs",
	553	.version_id = 1,
	554	.minimum_version_id = 1,
d49805ae	555	.fields = (VMStateField[]) {
0eee6d62 HP	556	VMSTATE_INT32_ARRAY(now, I8257Regs, 2),
	557	VMSTATE_UINT16_ARRAY(base, I8257Regs, 2),
	558	VMSTATE_UINT8(mode, I8257Regs),
	559	VMSTATE_UINT8(page, I8257Regs),
	560	VMSTATE_UINT8(pageh, I8257Regs),
	561	VMSTATE_UINT8(dack, I8257Regs),
	562	VMSTATE_UINT8(eop, I8257Regs),
7b5045c5	563	VMSTATE_END_OF_LIST()
85571bc7	564	}
7b5045c5	565	};
85571bc7	566
74c47de0	567	static int i8257_post_load(void *opaque, int version_id)
85571bc7	568	{
b9ebd28c HP	569	I8257State *d = opaque;
b9ebd28c HP	570	i8257_dma_run(d);
492c30af	571
85571bc7 FB	572	return 0;
	573	}
	574
7b5045c5 JQ	575	static const VMStateDescription vmstate_dma = {
	576	.name = "dma",
	577	.version_id = 1,
	578	.minimum_version_id = 1,
74c47de0	579	.post_load = i8257_post_load,
d49805ae	580	.fields = (VMStateField[]) {
6a128b13 HP	581	VMSTATE_UINT8(command, I8257State),
	582	VMSTATE_UINT8(mask, I8257State),
	583	VMSTATE_UINT8(flip_flop, I8257State),
	584	VMSTATE_INT32(dshift, I8257State),
0eee6d62 HP	585	VMSTATE_STRUCT_ARRAY(regs, I8257State, 4, 1, vmstate_i8257_regs,
0eee6d62 HP	586	I8257Regs),
7b5045c5 JQ	587	VMSTATE_END_OF_LIST()
	588	}
	589	};
	590
57146941	591	void DMA_init(ISABus *bus, int high_page_enable)
9eb153f1	592	{
5039d6e2 PB	593	dma_init2(&dma_controllers[0], 0x00, 0, 0x80, high_page_enable ? 0x480 : -1);
5039d6e2 PB	594	dma_init2(&dma_controllers[1], 0xc0, 1, 0x88, high_page_enable ? 0x488 : -1);
0be71e32 AW	595	vmstate_register (NULL, 0, &vmstate_dma, &dma_controllers[0]);
0be71e32 AW	596	vmstate_register (NULL, 1, &vmstate_dma, &dma_controllers[1]);
27503323	597	}