[mirror_qemu.git] / hw / dma / pl080.c

/*
 * Arm PrimeCell PL080/PL081 DMA controller
 *
 * Copyright (c) 2006 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "exec/address-spaces.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/dma/pl080.h"
#include "hw/hw.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "qapi/error.h"

#define PL080_CONF_E    0x1
#define PL080_CONF_M1   0x2
#define PL080_CONF_M2   0x4

#define PL080_CCONF_H   0x40000
#define PL080_CCONF_A   0x20000
#define PL080_CCONF_L   0x10000
#define PL080_CCONF_ITC 0x08000
#define PL080_CCONF_IE  0x04000
#define PL080_CCONF_E   0x00001

#define PL080_CCTRL_I   0x80000000
#define PL080_CCTRL_DI  0x08000000
#define PL080_CCTRL_SI  0x04000000
#define PL080_CCTRL_D   0x02000000
#define PL080_CCTRL_S   0x01000000

static const VMStateDescription vmstate_pl080_channel = {
    .name = "pl080_channel",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(src, pl080_channel),
        VMSTATE_UINT32(dest, pl080_channel),
        VMSTATE_UINT32(lli, pl080_channel),
        VMSTATE_UINT32(ctrl, pl080_channel),
        VMSTATE_UINT32(conf, pl080_channel),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pl080 = {
    .name = "pl080",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT8(tc_int, PL080State),
        VMSTATE_UINT8(tc_mask, PL080State),
        VMSTATE_UINT8(err_int, PL080State),
        VMSTATE_UINT8(err_mask, PL080State),
        VMSTATE_UINT32(conf, PL080State),
        VMSTATE_UINT32(sync, PL080State),
        VMSTATE_UINT32(req_single, PL080State),
        VMSTATE_UINT32(req_burst, PL080State),
        VMSTATE_UINT8(tc_int, PL080State),
        VMSTATE_UINT8(tc_int, PL080State),
        VMSTATE_UINT8(tc_int, PL080State),
        VMSTATE_STRUCT_ARRAY(chan, PL080State, PL080_MAX_CHANNELS,
                             1, vmstate_pl080_channel, pl080_channel),
        VMSTATE_INT32(running, PL080State),
        VMSTATE_END_OF_LIST()
    }
};

static const unsigned char pl080_id[] =
{ 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };

static const unsigned char pl081_id[] =
{ 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };

static void pl080_update(PL080State *s)
{
    bool tclevel = (s->tc_int & s->tc_mask);
    bool errlevel = (s->err_int & s->err_mask);

    qemu_set_irq(s->interr, errlevel);
    qemu_set_irq(s->inttc, tclevel);
    qemu_set_irq(s->irq, errlevel || tclevel);
}

static void pl080_run(PL080State *s)
{
    int c;
    int flow;
    pl080_channel *ch;
    int swidth;
    int dwidth;
    int xsize;
    int n;
    int src_id;
    int dest_id;
    int size;
    uint8_t buff[4];
    uint32_t req;

    s->tc_mask = 0;
    for (c = 0; c < s->nchannels; c++) {
        if (s->chan[c].conf & PL080_CCONF_ITC)
            s->tc_mask |= 1 << c;
        if (s->chan[c].conf & PL080_CCONF_IE)
            s->err_mask |= 1 << c;
    }

    if ((s->conf & PL080_CONF_E) == 0)
        return;

    /* If we are already in the middle of a DMA operation then indicate that
       there may be new DMA requests and return immediately.  */
    if (s->running) {
        s->running++;
        return;
    }
    s->running = 1;
    while (s->running) {
        for (c = 0; c < s->nchannels; c++) {
            ch = &s->chan[c];
again:
            /* Test if thiws channel has any pending DMA requests.  */
            if ((ch->conf & (PL080_CCONF_H | PL080_CCONF_E))
                    != PL080_CCONF_E)
                continue;
            flow = (ch->conf >> 11) & 7;
            if (flow >= 4) {
                hw_error(
                    "pl080_run: Peripheral flow control not implemented\n");
            }
            src_id = (ch->conf >> 1) & 0x1f;
            dest_id = (ch->conf >> 6) & 0x1f;
            size = ch->ctrl & 0xfff;
            req = s->req_single | s->req_burst;
            switch (flow) {
            case 0:
                break;
            case 1:
                if ((req & (1u << dest_id)) == 0)
                    size = 0;
                break;
            case 2:
                if ((req & (1u << src_id)) == 0)
                    size = 0;
                break;
            case 3:
                if ((req & (1u << src_id)) == 0
                        || (req & (1u << dest_id)) == 0)
                    size = 0;
                break;
            }
            if (!size)
                continue;

            /* Transfer one element.  */
            /* ??? Should transfer multiple elements for a burst request.  */
            /* ??? Unclear what the proper behavior is when source and
               destination widths are different.  */
            swidth = 1 << ((ch->ctrl >> 18) & 7);
            dwidth = 1 << ((ch->ctrl >> 21) & 7);
            for (n = 0; n < dwidth; n+= swidth) {
                address_space_read(&s->downstream_as, ch->src,
                                   MEMTXATTRS_UNSPECIFIED, buff + n, swidth);
                if (ch->ctrl & PL080_CCTRL_SI)
                    ch->src += swidth;
            }
            xsize = (dwidth < swidth) ? swidth : dwidth;
            /* ??? This may pad the value incorrectly for dwidth < 32.  */
            for (n = 0; n < xsize; n += dwidth) {
                address_space_write(&s->downstream_as, ch->dest + n,
                                    MEMTXATTRS_UNSPECIFIED, buff + n, dwidth);
                if (ch->ctrl & PL080_CCTRL_DI)
                    ch->dest += swidth;
            }

            size--;
            ch->ctrl = (ch->ctrl & 0xfffff000) | size;
            if (size == 0) {
                /* Transfer complete.  */
                if (ch->lli) {
                    ch->src = address_space_ldl_le(&s->downstream_as,
                                                   ch->lli,
                                                   MEMTXATTRS_UNSPECIFIED,
                                                   NULL);
                    ch->dest = address_space_ldl_le(&s->downstream_as,
                                                    ch->lli + 4,
                                                    MEMTXATTRS_UNSPECIFIED,
                                                    NULL);
                    ch->ctrl = address_space_ldl_le(&s->downstream_as,
                                                    ch->lli + 12,
                                                    MEMTXATTRS_UNSPECIFIED,
                                                    NULL);
                    ch->lli = address_space_ldl_le(&s->downstream_as,
                                                   ch->lli + 8,
                                                   MEMTXATTRS_UNSPECIFIED,
                                                   NULL);
                } else {
                    ch->conf &= ~PL080_CCONF_E;
                }
                if (ch->ctrl & PL080_CCTRL_I) {
                    s->tc_int |= 1 << c;
                }
            }
            goto again;
        }
        if (--s->running)
            s->running = 1;
    }
}

static uint64_t pl080_read(void *opaque, hwaddr offset,
                           unsigned size)
{
    PL080State *s = (PL080State *)opaque;
    uint32_t i;
    uint32_t mask;

    if (offset >= 0xfe0 && offset < 0x1000) {
        if (s->nchannels == 8) {
            return pl080_id[(offset - 0xfe0) >> 2];
        } else {
            return pl081_id[(offset - 0xfe0) >> 2];
        }
    }
    if (offset >= 0x100 && offset < 0x200) {
        i = (offset & 0xe0) >> 5;
        if (i >= s->nchannels)
            goto bad_offset;
        switch ((offset >> 2) & 7) {
        case 0: /* SrcAddr */
            return s->chan[i].src;
        case 1: /* DestAddr */
            return s->chan[i].dest;
        case 2: /* LLI */
            return s->chan[i].lli;
        case 3: /* Control */
            return s->chan[i].ctrl;
        case 4: /* Configuration */
            return s->chan[i].conf;
        default:
            goto bad_offset;
        }
    }
    switch (offset >> 2) {
    case 0: /* IntStatus */
        return (s->tc_int & s->tc_mask) | (s->err_int & s->err_mask);
    case 1: /* IntTCStatus */
        return (s->tc_int & s->tc_mask);
    case 3: /* IntErrorStatus */
        return (s->err_int & s->err_mask);
    case 5: /* RawIntTCStatus */
        return s->tc_int;
    case 6: /* RawIntErrorStatus */
        return s->err_int;
    case 7: /* EnbldChns */
        mask = 0;
        for (i = 0; i < s->nchannels; i++) {
            if (s->chan[i].conf & PL080_CCONF_E)
                mask |= 1 << i;
        }
        return mask;
    case 8: /* SoftBReq */
    case 9: /* SoftSReq */
    case 10: /* SoftLBReq */
    case 11: /* SoftLSReq */
        /* ??? Implement these. */
        return 0;
    case 12: /* Configuration */
        return s->conf;
    case 13: /* Sync */
        return s->sync;
    default:
    bad_offset:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl080_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

static void pl080_write(void *opaque, hwaddr offset,
                        uint64_t value, unsigned size)
{
    PL080State *s = (PL080State *)opaque;
    int i;

    if (offset >= 0x100 && offset < 0x200) {
        i = (offset & 0xe0) >> 5;
        if (i >= s->nchannels)
            goto bad_offset;
        switch ((offset >> 2) & 7) {
        case 0: /* SrcAddr */
            s->chan[i].src = value;
            break;
        case 1: /* DestAddr */
            s->chan[i].dest = value;
            break;
        case 2: /* LLI */
            s->chan[i].lli = value;
            break;
        case 3: /* Control */
            s->chan[i].ctrl = value;
            break;
        case 4: /* Configuration */
            s->chan[i].conf = value;
            pl080_run(s);
            break;
        }
        return;
    }
    switch (offset >> 2) {
    case 2: /* IntTCClear */
        s->tc_int &= ~value;
        break;
    case 4: /* IntErrorClear */
        s->err_int &= ~value;
        break;
    case 8: /* SoftBReq */
    case 9: /* SoftSReq */
    case 10: /* SoftLBReq */
    case 11: /* SoftLSReq */
        /* ??? Implement these.  */
        qemu_log_mask(LOG_UNIMP, "pl080_write: Soft DMA not implemented\n");
        break;
    case 12: /* Configuration */
        s->conf = value;
        if (s->conf & (PL080_CONF_M1 | PL080_CONF_M2)) {
            qemu_log_mask(LOG_UNIMP,
                          "pl080_write: Big-endian DMA not implemented\n");
        }
        pl080_run(s);
        break;
    case 13: /* Sync */
        s->sync = value;
        break;
    default:
    bad_offset:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl080_write: Bad offset %x\n", (int)offset);
    }
    pl080_update(s);
}

static const MemoryRegionOps pl080_ops = {
    .read = pl080_read,
    .write = pl080_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void pl080_reset(DeviceState *dev)
{
    PL080State *s = PL080(dev);
    int i;

    s->tc_int = 0;
    s->tc_mask = 0;
    s->err_int = 0;
    s->err_mask = 0;
    s->conf = 0;
    s->sync = 0;
    s->req_single = 0;
    s->req_burst = 0;
    s->running = 0;

    for (i = 0; i < s->nchannels; i++) {
        s->chan[i].src = 0;
        s->chan[i].dest = 0;
        s->chan[i].lli = 0;
        s->chan[i].ctrl = 0;
        s->chan[i].conf = 0;
    }
}

static void pl080_init(Object *obj)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    PL080State *s = PL080(obj);

    memory_region_init_io(&s->iomem, OBJECT(s), &pl080_ops, s, "pl080", 0x1000);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq);
    sysbus_init_irq(sbd, &s->interr);
    sysbus_init_irq(sbd, &s->inttc);
    s->nchannels = 8;
}

static void pl080_realize(DeviceState *dev, Error **errp)
{
    PL080State *s = PL080(dev);

    if (!s->downstream) {
        error_setg(errp, "PL080 'downstream' link not set");
        return;
    }

    address_space_init(&s->downstream_as, s->downstream, "pl080-downstream");
}

static void pl081_init(Object *obj)
{
    PL080State *s = PL080(obj);

    s->nchannels = 2;
}

static Property pl080_properties[] = {
    DEFINE_PROP_LINK("downstream", PL080State, downstream,
                     TYPE_MEMORY_REGION, MemoryRegion *),
    DEFINE_PROP_END_OF_LIST(),
};

static void pl080_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->vmsd = &vmstate_pl080;
    dc->realize = pl080_realize;
    device_class_set_props(dc, pl080_properties);
    dc->reset = pl080_reset;
}

static const TypeInfo pl080_info = {
    .name          = TYPE_PL080,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PL080State),
    .instance_init = pl080_init,
    .class_init    = pl080_class_init,
};

static const TypeInfo pl081_info = {
    .name          = TYPE_PL081,
    .parent        = TYPE_PL080,
    .instance_init = pl081_init,
};

/* The PL080 and PL081 are the same except for the number of channels
   they implement (8 and 2 respectively).  */
static void pl080_register_types(void)
{
    type_register_static(&pl080_info);
    type_register_static(&pl081_info);
}

type_init(pl080_register_types)
Commit	Line	Data
5fafdf24	1	/*
e69954b9	2	* Arm PrimeCell PL080/PL081 DMA controller
cdbdb648 PB	3	*
	4	* Copyright (c) 2006 CodeSourcery.
	5	* Written by Paul Brook
	6	*
8e31bf38	7	* This code is licensed under the GPL.
cdbdb648 PB	8	*/
cdbdb648 PB	9
8ef94f0b	10	#include "qemu/osdep.h"
83c9f4ca	11	#include "hw/sysbus.h"
d6454270	12	#include "migration/vmstate.h"
fdfba1a2	13	#include "exec/address-spaces.h"
03dd024f	14	#include "qemu/log.h"
0b8fa32f	15	#include "qemu/module.h"
aa74e355	16	#include "hw/dma/pl080.h"
650d103d	17	#include "hw/hw.h"
64552b6b	18	#include "hw/irq.h"
a27bd6c7	19	#include "hw/qdev-properties.h"
112a829f	20	#include "qapi/error.h"
cdbdb648	21
cdbdb648 PB	22	#define PL080_CONF_E 0x1
	23	#define PL080_CONF_M1 0x2
	24	#define PL080_CONF_M2 0x4
	25
	26	#define PL080_CCONF_H 0x40000
	27	#define PL080_CCONF_A 0x20000
	28	#define PL080_CCONF_L 0x10000
	29	#define PL080_CCONF_ITC 0x08000
	30	#define PL080_CCONF_IE 0x04000
	31	#define PL080_CCONF_E 0x00001
	32
	33	#define PL080_CCTRL_I 0x80000000
	34	#define PL080_CCTRL_DI 0x08000000
	35	#define PL080_CCTRL_SI 0x04000000
	36	#define PL080_CCTRL_D 0x02000000
	37	#define PL080_CCTRL_S 0x01000000
	38
ff175853 PM	39	static const VMStateDescription vmstate_pl080_channel = {
	40	.name = "pl080_channel",
	41	.version_id = 1,
	42	.minimum_version_id = 1,
	43	.fields = (VMStateField[]) {
	44	VMSTATE_UINT32(src, pl080_channel),
	45	VMSTATE_UINT32(dest, pl080_channel),
	46	VMSTATE_UINT32(lli, pl080_channel),
	47	VMSTATE_UINT32(ctrl, pl080_channel),
	48	VMSTATE_UINT32(conf, pl080_channel),
	49	VMSTATE_END_OF_LIST()
	50	}
	51	};
	52
	53	static const VMStateDescription vmstate_pl080 = {
	54	.name = "pl080",
	55	.version_id = 1,
	56	.minimum_version_id = 1,
	57	.fields = (VMStateField[]) {
d7ba0a62 AF	58	VMSTATE_UINT8(tc_int, PL080State),
	59	VMSTATE_UINT8(tc_mask, PL080State),
	60	VMSTATE_UINT8(err_int, PL080State),
	61	VMSTATE_UINT8(err_mask, PL080State),
	62	VMSTATE_UINT32(conf, PL080State),
	63	VMSTATE_UINT32(sync, PL080State),
	64	VMSTATE_UINT32(req_single, PL080State),
	65	VMSTATE_UINT32(req_burst, PL080State),
	66	VMSTATE_UINT8(tc_int, PL080State),
	67	VMSTATE_UINT8(tc_int, PL080State),
	68	VMSTATE_UINT8(tc_int, PL080State),
	69	VMSTATE_STRUCT_ARRAY(chan, PL080State, PL080_MAX_CHANNELS,
ff175853	70	1, vmstate_pl080_channel, pl080_channel),
d7ba0a62	71	VMSTATE_INT32(running, PL080State),
ff175853 PM	72	VMSTATE_END_OF_LIST()
	73	}
	74	};
	75
cdbdb648 PB	76	static const unsigned char pl080_id[] =
	77	{ 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
	78
e69954b9 PB	79	static const unsigned char pl081_id[] =
	80	{ 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
	81
d7ba0a62	82	static void pl080_update(PL080State *s)
cdbdb648	83	{
6d0ed6ba PM	84	bool tclevel = (s->tc_int & s->tc_mask);
	85	bool errlevel = (s->err_int & s->err_mask);
	86
	87	qemu_set_irq(s->interr, errlevel);
	88	qemu_set_irq(s->inttc, tclevel);
	89	qemu_set_irq(s->irq, errlevel \|\| tclevel);
cdbdb648 PB	90	}
cdbdb648 PB	91
d7ba0a62	92	static void pl080_run(PL080State *s)
cdbdb648 PB	93	{
	94	int c;
	95	int flow;
	96	pl080_channel *ch;
	97	int swidth;
	98	int dwidth;
	99	int xsize;
	100	int n;
	101	int src_id;
	102	int dest_id;
	103	int size;
b55266b5	104	uint8_t buff[4];
cdbdb648 PB	105	uint32_t req;
	106
	107	s->tc_mask = 0;
e69954b9	108	for (c = 0; c < s->nchannels; c++) {
cdbdb648 PB	109	if (s->chan[c].conf & PL080_CCONF_ITC)
	110	s->tc_mask \|= 1 << c;
	111	if (s->chan[c].conf & PL080_CCONF_IE)
	112	s->err_mask \|= 1 << c;
	113	}
	114
	115	if ((s->conf & PL080_CONF_E) == 0)
	116	return;
	117
cdbdb648 PB	118	/* If we are already in the middle of a DMA operation then indicate that
	119	there may be new DMA requests and return immediately. */
	120	if (s->running) {
	121	s->running++;
	122	return;
	123	}
	124	s->running = 1;
	125	while (s->running) {
e69954b9	126	for (c = 0; c < s->nchannels; c++) {
cdbdb648 PB	127	ch = &s->chan[c];
	128	again:
	129	/* Test if thiws channel has any pending DMA requests. */
	130	if ((ch->conf & (PL080_CCONF_H \| PL080_CCONF_E))
	131	!= PL080_CCONF_E)
	132	continue;
	133	flow = (ch->conf >> 11) & 7;
	134	if (flow >= 4) {
2ac71179	135	hw_error(
cdbdb648 PB	136	"pl080_run: Peripheral flow control not implemented\n");
	137	}
	138	src_id = (ch->conf >> 1) & 0x1f;
	139	dest_id = (ch->conf >> 6) & 0x1f;
	140	size = ch->ctrl & 0xfff;
	141	req = s->req_single \| s->req_burst;
	142	switch (flow) {
	143	case 0:
	144	break;
	145	case 1:
	146	if ((req & (1u << dest_id)) == 0)
	147	size = 0;
	148	break;
	149	case 2:
	150	if ((req & (1u << src_id)) == 0)
	151	size = 0;
	152	break;
	153	case 3:
	154	if ((req & (1u << src_id)) == 0
	155	\|\| (req & (1u << dest_id)) == 0)
	156	size = 0;
	157	break;
	158	}
	159	if (!size)
	160	continue;
	161
	162	/* Transfer one element. */
	163	/* ??? Should transfer multiple elements for a burst request. */
	164	/* ??? Unclear what the proper behavior is when source and
	165	destination widths are different. */
	166	swidth = 1 << ((ch->ctrl >> 18) & 7);
	167	dwidth = 1 << ((ch->ctrl >> 21) & 7);
	168	for (n = 0; n < dwidth; n+= swidth) {
112a829f PM	169	address_space_read(&s->downstream_as, ch->src,
112a829f PM	170	MEMTXATTRS_UNSPECIFIED, buff + n, swidth);
cdbdb648 PB	171	if (ch->ctrl & PL080_CCTRL_SI)
	172	ch->src += swidth;
	173	}
	174	xsize = (dwidth < swidth) ? swidth : dwidth;
	175	/* ??? This may pad the value incorrectly for dwidth < 32. */
	176	for (n = 0; n < xsize; n += dwidth) {
112a829f PM	177	address_space_write(&s->downstream_as, ch->dest + n,
112a829f PM	178	MEMTXATTRS_UNSPECIFIED, buff + n, dwidth);
cdbdb648 PB	179	if (ch->ctrl & PL080_CCTRL_DI)
	180	ch->dest += swidth;
	181	}
	182
	183	size--;
	184	ch->ctrl = (ch->ctrl & 0xfffff000) \| size;
	185	if (size == 0) {
	186	/* Transfer complete. */
	187	if (ch->lli) {
112a829f	188	ch->src = address_space_ldl_le(&s->downstream_as,
42874d3a PM	189	ch->lli,
	190	MEMTXATTRS_UNSPECIFIED,
	191	NULL);
112a829f	192	ch->dest = address_space_ldl_le(&s->downstream_as,
42874d3a PM	193	ch->lli + 4,
	194	MEMTXATTRS_UNSPECIFIED,
	195	NULL);
112a829f	196	ch->ctrl = address_space_ldl_le(&s->downstream_as,
42874d3a PM	197	ch->lli + 12,
	198	MEMTXATTRS_UNSPECIFIED,
	199	NULL);
112a829f	200	ch->lli = address_space_ldl_le(&s->downstream_as,
42874d3a PM	201	ch->lli + 8,
	202	MEMTXATTRS_UNSPECIFIED,
	203	NULL);
cdbdb648 PB	204	} else {
	205	ch->conf &= ~PL080_CCONF_E;
	206	}
	207	if (ch->ctrl & PL080_CCTRL_I) {
	208	s->tc_int \|= 1 << c;
	209	}
	210	}
	211	goto again;
	212	}
	213	if (--s->running)
	214	s->running = 1;
	215	}
	216	}
	217
a8170e5e	218	static uint64_t pl080_read(void *opaque, hwaddr offset,
63b02e04	219	unsigned size)
cdbdb648	220	{
d7ba0a62	221	PL080State s = (PL080State )opaque;
cdbdb648 PB	222	uint32_t i;
	223	uint32_t mask;
	224
cdbdb648	225	if (offset >= 0xfe0 && offset < 0x1000) {
e69954b9 PB	226	if (s->nchannels == 8) {
	227	return pl080_id[(offset - 0xfe0) >> 2];
	228	} else {
	229	return pl081_id[(offset - 0xfe0) >> 2];
	230	}
cdbdb648 PB	231	}
	232	if (offset >= 0x100 && offset < 0x200) {
	233	i = (offset & 0xe0) >> 5;
e69954b9 PB	234	if (i >= s->nchannels)
e69954b9 PB	235	goto bad_offset;
156448ab	236	switch ((offset >> 2) & 7) {
cdbdb648 PB	237	case 0: /* SrcAddr */
	238	return s->chan[i].src;
	239	case 1: /* DestAddr */
	240	return s->chan[i].dest;
	241	case 2: /* LLI */
	242	return s->chan[i].lli;
	243	case 3: /* Control */
	244	return s->chan[i].ctrl;
	245	case 4: /* Configuration */
	246	return s->chan[i].conf;
	247	default:
	248	goto bad_offset;
	249	}
	250	}
	251	switch (offset >> 2) {
	252	case 0: /* IntStatus */
	253	return (s->tc_int & s->tc_mask) \| (s->err_int & s->err_mask);
	254	case 1: /* IntTCStatus */
	255	return (s->tc_int & s->tc_mask);
	256	case 3: /* IntErrorStatus */
	257	return (s->err_int & s->err_mask);
	258	case 5: /* RawIntTCStatus */
	259	return s->tc_int;
	260	case 6: /* RawIntErrorStatus */
	261	return s->err_int;
	262	case 7: /* EnbldChns */
	263	mask = 0;
e69954b9	264	for (i = 0; i < s->nchannels; i++) {
cdbdb648 PB	265	if (s->chan[i].conf & PL080_CCONF_E)
	266	mask \|= 1 << i;
	267	}
	268	return mask;
	269	case 8: /* SoftBReq */
	270	case 9: /* SoftSReq */
	271	case 10: /* SoftLBReq */
	272	case 11: /* SoftLSReq */
	273	/* ??? Implement these. */
	274	return 0;
	275	case 12: /* Configuration */
	276	return s->conf;
	277	case 13: /* Sync */
	278	return s->sync;
	279	default:
	280	bad_offset:
df374162 PM	281	qemu_log_mask(LOG_GUEST_ERROR,
df374162 PM	282	"pl080_read: Bad offset %x\n", (int)offset);
cdbdb648 PB	283	return 0;
	284	}
	285	}
	286
a8170e5e	287	static void pl080_write(void *opaque, hwaddr offset,
63b02e04	288	uint64_t value, unsigned size)
cdbdb648	289	{
d7ba0a62	290	PL080State s = (PL080State )opaque;
cdbdb648 PB	291	int i;
cdbdb648 PB	292
cdbdb648 PB	293	if (offset >= 0x100 && offset < 0x200) {
cdbdb648 PB	294	i = (offset & 0xe0) >> 5;
e69954b9 PB	295	if (i >= s->nchannels)
e69954b9 PB	296	goto bad_offset;
156448ab	297	switch ((offset >> 2) & 7) {
cdbdb648 PB	298	case 0: /* SrcAddr */
	299	s->chan[i].src = value;
	300	break;
	301	case 1: /* DestAddr */
	302	s->chan[i].dest = value;
	303	break;
	304	case 2: /* LLI */
	305	s->chan[i].lli = value;
	306	break;
	307	case 3: /* Control */
	308	s->chan[i].ctrl = value;
	309	break;
	310	case 4: /* Configuration */
	311	s->chan[i].conf = value;
	312	pl080_run(s);
	313	break;
	314	}
156448ab	315	return;
cdbdb648 PB	316	}
	317	switch (offset >> 2) {
	318	case 2: /* IntTCClear */
	319	s->tc_int &= ~value;
	320	break;
	321	case 4: /* IntErrorClear */
	322	s->err_int &= ~value;
	323	break;
	324	case 8: /* SoftBReq */
	325	case 9: /* SoftSReq */
	326	case 10: /* SoftLBReq */
	327	case 11: /* SoftLSReq */
	328	/* ??? Implement these. */
df374162	329	qemu_log_mask(LOG_UNIMP, "pl080_write: Soft DMA not implemented\n");
cdbdb648 PB	330	break;
	331	case 12: /* Configuration */
	332	s->conf = value;
04bb79d1	333	if (s->conf & (PL080_CONF_M1 \| PL080_CONF_M2)) {
df374162 PM	334	qemu_log_mask(LOG_UNIMP,
df374162 PM	335	"pl080_write: Big-endian DMA not implemented\n");
cdbdb648 PB	336	}
	337	pl080_run(s);
	338	break;
	339	case 13: /* Sync */
	340	s->sync = value;
	341	break;
	342	default:
e69954b9	343	bad_offset:
df374162 PM	344	qemu_log_mask(LOG_GUEST_ERROR,
df374162 PM	345	"pl080_write: Bad offset %x\n", (int)offset);
cdbdb648 PB	346	}
	347	pl080_update(s);
	348	}
	349
63b02e04 AK	350	static const MemoryRegionOps pl080_ops = {
	351	.read = pl080_read,
	352	.write = pl080_write,
	353	.endianness = DEVICE_NATIVE_ENDIAN,
cdbdb648 PB	354	};
cdbdb648 PB	355
c193304d PM	356	static void pl080_reset(DeviceState *dev)
	357	{
	358	PL080State *s = PL080(dev);
	359	int i;
	360
	361	s->tc_int = 0;
	362	s->tc_mask = 0;
	363	s->err_int = 0;
	364	s->err_mask = 0;
	365	s->conf = 0;
	366	s->sync = 0;
	367	s->req_single = 0;
	368	s->req_burst = 0;
	369	s->running = 0;
	370
	371	for (i = 0; i < s->nchannels; i++) {
	372	s->chan[i].src = 0;
	373	s->chan[i].dest = 0;
	374	s->chan[i].lli = 0;
	375	s->chan[i].ctrl = 0;
	376	s->chan[i].conf = 0;
	377	}
	378	}
	379
4f800554	380	static void pl080_init(Object *obj)
cdbdb648	381	{
4f800554 AF	382	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
4f800554 AF	383	PL080State *s = PL080(obj);
cdbdb648	384
3eadad55	385	memory_region_init_io(&s->iomem, OBJECT(s), &pl080_ops, s, "pl080", 0x1000);
4f800554 AF	386	sysbus_init_mmio(sbd, &s->iomem);
4f800554 AF	387	sysbus_init_irq(sbd, &s->irq);
6d0ed6ba PM	388	sysbus_init_irq(sbd, &s->interr);
6d0ed6ba PM	389	sysbus_init_irq(sbd, &s->inttc);
4f800554	390	s->nchannels = 8;
cdbdb648	391	}
b4496b13	392
112a829f PM	393	static void pl080_realize(DeviceState dev, Error *errp)
	394	{
	395	PL080State *s = PL080(dev);
	396
	397	if (!s->downstream) {
	398	error_setg(errp, "PL080 'downstream' link not set");
	399	return;
	400	}
	401
	402	address_space_init(&s->downstream_as, s->downstream, "pl080-downstream");
	403	}
	404
4f800554	405	static void pl081_init(Object *obj)
b4496b13	406	{
4f800554	407	PL080State *s = PL080(obj);
b4496b13	408
4f800554	409	s->nchannels = 2;
b4496b13 PB	410	}
b4496b13 PB	411
112a829f PM	412	static Property pl080_properties[] = {
	413	DEFINE_PROP_LINK("downstream", PL080State, downstream,
	414	TYPE_MEMORY_REGION, MemoryRegion *),
	415	DEFINE_PROP_END_OF_LIST(),
	416	};
	417
4f800554	418	static void pl080_class_init(ObjectClass oc, void data)
999e12bb	419	{
4f800554	420	DeviceClass *dc = DEVICE_CLASS(oc);
999e12bb	421
39bffca2	422	dc->vmsd = &vmstate_pl080;
112a829f	423	dc->realize = pl080_realize;
4f67d30b	424	device_class_set_props(dc, pl080_properties);
c193304d	425	dc->reset = pl080_reset;
999e12bb AL	426	}
999e12bb AL	427
8c43a6f0	428	static const TypeInfo pl080_info = {
4f800554	429	.name = TYPE_PL080,
39bffca2	430	.parent = TYPE_SYS_BUS_DEVICE,
d7ba0a62	431	.instance_size = sizeof(PL080State),
4f800554	432	.instance_init = pl080_init,
39bffca2	433	.class_init = pl080_class_init,
ff175853 PM	434	};
ff175853 PM	435
8c43a6f0	436	static const TypeInfo pl081_info = {
aa74e355	437	.name = TYPE_PL081,
4f800554 AF	438	.parent = TYPE_PL080,
4f800554 AF	439	.instance_init = pl081_init,
ff175853 PM	440	};
ff175853 PM	441
b4496b13 PB	442	/* The PL080 and PL081 are the same except for the number of channels
b4496b13 PB	443	they implement (8 and 2 respectively). */
83f7d43a	444	static void pl080_register_types(void)
b4496b13	445	{
39bffca2 AL	446	type_register_static(&pl080_info);
39bffca2 AL	447	type_register_static(&pl081_info);
b4496b13 PB	448	}
b4496b13 PB	449
83f7d43a	450	type_init(pl080_register_types)