[mirror_qemu.git] / hw / dma / pl080.c

/*
 * Arm PrimeCell PL080/PL081 DMA controller
 *
 * Copyright (c) 2006 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "exec/address-spaces.h"

#define PL080_MAX_CHANNELS 8
#define PL080_CONF_E    0x1
#define PL080_CONF_M1   0x2
#define PL080_CONF_M2   0x4

#define PL080_CCONF_H   0x40000
#define PL080_CCONF_A   0x20000
#define PL080_CCONF_L   0x10000
#define PL080_CCONF_ITC 0x08000
#define PL080_CCONF_IE  0x04000
#define PL080_CCONF_E   0x00001

#define PL080_CCTRL_I   0x80000000
#define PL080_CCTRL_DI  0x08000000
#define PL080_CCTRL_SI  0x04000000
#define PL080_CCTRL_D   0x02000000
#define PL080_CCTRL_S   0x01000000

typedef struct {
    uint32_t src;
    uint32_t dest;
    uint32_t lli;
    uint32_t ctrl;
    uint32_t conf;
} pl080_channel;

#define TYPE_PL080 "pl080"
#define PL080(obj) OBJECT_CHECK(PL080State, (obj), TYPE_PL080)

typedef struct PL080State {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    uint8_t tc_int;
    uint8_t tc_mask;
    uint8_t err_int;
    uint8_t err_mask;
    uint32_t conf;
    uint32_t sync;
    uint32_t req_single;
    uint32_t req_burst;
    pl080_channel chan[PL080_MAX_CHANNELS];
    int nchannels;
    /* Flag to avoid recursive DMA invocations.  */
    int running;
    qemu_irq irq;
} PL080State;

static const VMStateDescription vmstate_pl080_channel = {
    .name = "pl080_channel",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(src, pl080_channel),
        VMSTATE_UINT32(dest, pl080_channel),
        VMSTATE_UINT32(lli, pl080_channel),
        VMSTATE_UINT32(ctrl, pl080_channel),
        VMSTATE_UINT32(conf, pl080_channel),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pl080 = {
    .name = "pl080",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT8(tc_int, PL080State),
        VMSTATE_UINT8(tc_mask, PL080State),
        VMSTATE_UINT8(err_int, PL080State),
        VMSTATE_UINT8(err_mask, PL080State),
        VMSTATE_UINT32(conf, PL080State),
        VMSTATE_UINT32(sync, PL080State),
        VMSTATE_UINT32(req_single, PL080State),
        VMSTATE_UINT32(req_burst, PL080State),
        VMSTATE_UINT8(tc_int, PL080State),
        VMSTATE_UINT8(tc_int, PL080State),
        VMSTATE_UINT8(tc_int, PL080State),
        VMSTATE_STRUCT_ARRAY(chan, PL080State, PL080_MAX_CHANNELS,
                             1, vmstate_pl080_channel, pl080_channel),
        VMSTATE_INT32(running, PL080State),
        VMSTATE_END_OF_LIST()
    }
};

static const unsigned char pl080_id[] =
{ 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };

static const unsigned char pl081_id[] =
{ 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };

static void pl080_update(PL080State *s)
{
    if ((s->tc_int & s->tc_mask)
            || (s->err_int & s->err_mask))
        qemu_irq_raise(s->irq);
    else
        qemu_irq_lower(s->irq);
}

static void pl080_run(PL080State *s)
{
    int c;
    int flow;
    pl080_channel *ch;
    int swidth;
    int dwidth;
    int xsize;
    int n;
    int src_id;
    int dest_id;
    int size;
    uint8_t buff[4];
    uint32_t req;

    s->tc_mask = 0;
    for (c = 0; c < s->nchannels; c++) {
        if (s->chan[c].conf & PL080_CCONF_ITC)
            s->tc_mask |= 1 << c;
        if (s->chan[c].conf & PL080_CCONF_IE)
            s->err_mask |= 1 << c;
    }

    if ((s->conf & PL080_CONF_E) == 0)
        return;

hw_error("DMA active\n");
    /* If we are already in the middle of a DMA operation then indicate that
       there may be new DMA requests and return immediately.  */
    if (s->running) {
        s->running++;
        return;
    }
    s->running = 1;
    while (s->running) {
        for (c = 0; c < s->nchannels; c++) {
            ch = &s->chan[c];
again:
            /* Test if thiws channel has any pending DMA requests.  */
            if ((ch->conf & (PL080_CCONF_H | PL080_CCONF_E))
                    != PL080_CCONF_E)
                continue;
            flow = (ch->conf >> 11) & 7;
            if (flow >= 4) {
                hw_error(
                    "pl080_run: Peripheral flow control not implemented\n");
            }
            src_id = (ch->conf >> 1) & 0x1f;
            dest_id = (ch->conf >> 6) & 0x1f;
            size = ch->ctrl & 0xfff;
            req = s->req_single | s->req_burst;
            switch (flow) {
            case 0:
                break;
            case 1:
                if ((req & (1u << dest_id)) == 0)
                    size = 0;
                break;
            case 2:
                if ((req & (1u << src_id)) == 0)
                    size = 0;
                break;
            case 3:
                if ((req & (1u << src_id)) == 0
                        || (req & (1u << dest_id)) == 0)
                    size = 0;
                break;
            }
            if (!size)
                continue;

            /* Transfer one element.  */
            /* ??? Should transfer multiple elements for a burst request.  */
            /* ??? Unclear what the proper behavior is when source and
               destination widths are different.  */
            swidth = 1 << ((ch->ctrl >> 18) & 7);
            dwidth = 1 << ((ch->ctrl >> 21) & 7);
            for (n = 0; n < dwidth; n+= swidth) {
                cpu_physical_memory_read(ch->src, buff + n, swidth);
                if (ch->ctrl & PL080_CCTRL_SI)
                    ch->src += swidth;
            }
            xsize = (dwidth < swidth) ? swidth : dwidth;
            /* ??? This may pad the value incorrectly for dwidth < 32.  */
            for (n = 0; n < xsize; n += dwidth) {
                cpu_physical_memory_write(ch->dest + n, buff + n, dwidth);
                if (ch->ctrl & PL080_CCTRL_DI)
                    ch->dest += swidth;
            }

            size--;
            ch->ctrl = (ch->ctrl & 0xfffff000) | size;
            if (size == 0) {
                /* Transfer complete.  */
                if (ch->lli) {
                    ch->src = address_space_ldl_le(&address_space_memory,
                                                   ch->lli,
                                                   MEMTXATTRS_UNSPECIFIED,
                                                   NULL);
                    ch->dest = address_space_ldl_le(&address_space_memory,
                                                    ch->lli + 4,
                                                    MEMTXATTRS_UNSPECIFIED,
                                                    NULL);
                    ch->ctrl = address_space_ldl_le(&address_space_memory,
                                                    ch->lli + 12,
                                                    MEMTXATTRS_UNSPECIFIED,
                                                    NULL);
                    ch->lli = address_space_ldl_le(&address_space_memory,
                                                   ch->lli + 8,
                                                   MEMTXATTRS_UNSPECIFIED,
                                                   NULL);
                } else {
                    ch->conf &= ~PL080_CCONF_E;
                }
                if (ch->ctrl & PL080_CCTRL_I) {
                    s->tc_int |= 1 << c;
                }
            }
            goto again;
        }
        if (--s->running)
            s->running = 1;
    }
}

static uint64_t pl080_read(void *opaque, hwaddr offset,
                           unsigned size)
{
    PL080State *s = (PL080State *)opaque;
    uint32_t i;
    uint32_t mask;

    if (offset >= 0xfe0 && offset < 0x1000) {
        if (s->nchannels == 8) {
            return pl080_id[(offset - 0xfe0) >> 2];
        } else {
            return pl081_id[(offset - 0xfe0) >> 2];
        }
    }
    if (offset >= 0x100 && offset < 0x200) {
        i = (offset & 0xe0) >> 5;
        if (i >= s->nchannels)
            goto bad_offset;
        switch (offset >> 2) {
        case 0: /* SrcAddr */
            return s->chan[i].src;
        case 1: /* DestAddr */
            return s->chan[i].dest;
        case 2: /* LLI */
            return s->chan[i].lli;
        case 3: /* Control */
            return s->chan[i].ctrl;
        case 4: /* Configuration */
            return s->chan[i].conf;
        default:
            goto bad_offset;
        }
    }
    switch (offset >> 2) {
    case 0: /* IntStatus */
        return (s->tc_int & s->tc_mask) | (s->err_int & s->err_mask);
    case 1: /* IntTCStatus */
        return (s->tc_int & s->tc_mask);
    case 3: /* IntErrorStatus */
        return (s->err_int & s->err_mask);
    case 5: /* RawIntTCStatus */
        return s->tc_int;
    case 6: /* RawIntErrorStatus */
        return s->err_int;
    case 7: /* EnbldChns */
        mask = 0;
        for (i = 0; i < s->nchannels; i++) {
            if (s->chan[i].conf & PL080_CCONF_E)
                mask |= 1 << i;
        }
        return mask;
    case 8: /* SoftBReq */
    case 9: /* SoftSReq */
    case 10: /* SoftLBReq */
    case 11: /* SoftLSReq */
        /* ??? Implement these. */
        return 0;
    case 12: /* Configuration */
        return s->conf;
    case 13: /* Sync */
        return s->sync;
    default:
    bad_offset:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl080_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

static void pl080_write(void *opaque, hwaddr offset,
                        uint64_t value, unsigned size)
{
    PL080State *s = (PL080State *)opaque;
    int i;

    if (offset >= 0x100 && offset < 0x200) {
        i = (offset & 0xe0) >> 5;
        if (i >= s->nchannels)
            goto bad_offset;
        switch (offset >> 2) {
        case 0: /* SrcAddr */
            s->chan[i].src = value;
            break;
        case 1: /* DestAddr */
            s->chan[i].dest = value;
            break;
        case 2: /* LLI */
            s->chan[i].lli = value;
            break;
        case 3: /* Control */
            s->chan[i].ctrl = value;
            break;
        case 4: /* Configuration */
            s->chan[i].conf = value;
            pl080_run(s);
            break;
        }
    }
    switch (offset >> 2) {
    case 2: /* IntTCClear */
        s->tc_int &= ~value;
        break;
    case 4: /* IntErrorClear */
        s->err_int &= ~value;
        break;
    case 8: /* SoftBReq */
    case 9: /* SoftSReq */
    case 10: /* SoftLBReq */
    case 11: /* SoftLSReq */
        /* ??? Implement these.  */
        qemu_log_mask(LOG_UNIMP, "pl080_write: Soft DMA not implemented\n");
        break;
    case 12: /* Configuration */
        s->conf = value;
        if (s->conf & (PL080_CONF_M1 | PL080_CONF_M1)) {
            qemu_log_mask(LOG_UNIMP,
                          "pl080_write: Big-endian DMA not implemented\n");
        }
        pl080_run(s);
        break;
    case 13: /* Sync */
        s->sync = value;
        break;
    default:
    bad_offset:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl080_write: Bad offset %x\n", (int)offset);
    }
    pl080_update(s);
}

static const MemoryRegionOps pl080_ops = {
    .read = pl080_read,
    .write = pl080_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void pl080_init(Object *obj)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    PL080State *s = PL080(obj);

    memory_region_init_io(&s->iomem, OBJECT(s), &pl080_ops, s, "pl080", 0x1000);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq);
    s->nchannels = 8;
}

static void pl081_init(Object *obj)
{
    PL080State *s = PL080(obj);

    s->nchannels = 2;
}

static void pl080_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->vmsd = &vmstate_pl080;
}

static const TypeInfo pl080_info = {
    .name          = TYPE_PL080,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PL080State),
    .instance_init = pl080_init,
    .class_init    = pl080_class_init,
};

static const TypeInfo pl081_info = {
    .name          = "pl081",
    .parent        = TYPE_PL080,
    .instance_init = pl081_init,
};

/* The PL080 and PL081 are the same except for the number of channels
   they implement (8 and 2 respectively).  */
static void pl080_register_types(void)
{
    type_register_static(&pl080_info);
    type_register_static(&pl081_info);
}

type_init(pl080_register_types)
Commit	Line	Data
5fafdf24	1	/*
e69954b9	2	* Arm PrimeCell PL080/PL081 DMA controller
cdbdb648 PB	3	*
	4	* Copyright (c) 2006 CodeSourcery.
	5	* Written by Paul Brook
	6	*
8e31bf38	7	* This code is licensed under the GPL.
cdbdb648 PB	8	*/
cdbdb648 PB	9
8ef94f0b	10	#include "qemu/osdep.h"
83c9f4ca	11	#include "hw/sysbus.h"
fdfba1a2	12	#include "exec/address-spaces.h"
cdbdb648	13
e69954b9	14	#define PL080_MAX_CHANNELS 8
cdbdb648 PB	15	#define PL080_CONF_E 0x1
	16	#define PL080_CONF_M1 0x2
	17	#define PL080_CONF_M2 0x4
	18
	19	#define PL080_CCONF_H 0x40000
	20	#define PL080_CCONF_A 0x20000
	21	#define PL080_CCONF_L 0x10000
	22	#define PL080_CCONF_ITC 0x08000
	23	#define PL080_CCONF_IE 0x04000
	24	#define PL080_CCONF_E 0x00001
	25
	26	#define PL080_CCTRL_I 0x80000000
	27	#define PL080_CCTRL_DI 0x08000000
	28	#define PL080_CCTRL_SI 0x04000000
	29	#define PL080_CCTRL_D 0x02000000
	30	#define PL080_CCTRL_S 0x01000000
	31
	32	typedef struct {
	33	uint32_t src;
	34	uint32_t dest;
	35	uint32_t lli;
	36	uint32_t ctrl;
	37	uint32_t conf;
	38	} pl080_channel;
	39
4f800554 AF	40	#define TYPE_PL080 "pl080"
	41	#define PL080(obj) OBJECT_CHECK(PL080State, (obj), TYPE_PL080)
	42
d7ba0a62	43	typedef struct PL080State {
4f800554 AF	44	SysBusDevice parent_obj;
4f800554 AF	45
63b02e04	46	MemoryRegion iomem;
cdbdb648 PB	47	uint8_t tc_int;
	48	uint8_t tc_mask;
	49	uint8_t err_int;
	50	uint8_t err_mask;
	51	uint32_t conf;
	52	uint32_t sync;
	53	uint32_t req_single;
	54	uint32_t req_burst;
e69954b9 PB	55	pl080_channel chan[PL080_MAX_CHANNELS];
e69954b9 PB	56	int nchannels;
cdbdb648 PB	57	/* Flag to avoid recursive DMA invocations. */
cdbdb648 PB	58	int running;
d537cf6c	59	qemu_irq irq;
d7ba0a62	60	} PL080State;
cdbdb648	61
ff175853 PM	62	static const VMStateDescription vmstate_pl080_channel = {
	63	.name = "pl080_channel",
	64	.version_id = 1,
	65	.minimum_version_id = 1,
	66	.fields = (VMStateField[]) {
	67	VMSTATE_UINT32(src, pl080_channel),
	68	VMSTATE_UINT32(dest, pl080_channel),
	69	VMSTATE_UINT32(lli, pl080_channel),
	70	VMSTATE_UINT32(ctrl, pl080_channel),
	71	VMSTATE_UINT32(conf, pl080_channel),
	72	VMSTATE_END_OF_LIST()
	73	}
	74	};
	75
	76	static const VMStateDescription vmstate_pl080 = {
	77	.name = "pl080",
	78	.version_id = 1,
	79	.minimum_version_id = 1,
	80	.fields = (VMStateField[]) {
d7ba0a62 AF	81	VMSTATE_UINT8(tc_int, PL080State),
	82	VMSTATE_UINT8(tc_mask, PL080State),
	83	VMSTATE_UINT8(err_int, PL080State),
	84	VMSTATE_UINT8(err_mask, PL080State),
	85	VMSTATE_UINT32(conf, PL080State),
	86	VMSTATE_UINT32(sync, PL080State),
	87	VMSTATE_UINT32(req_single, PL080State),
	88	VMSTATE_UINT32(req_burst, PL080State),
	89	VMSTATE_UINT8(tc_int, PL080State),
	90	VMSTATE_UINT8(tc_int, PL080State),
	91	VMSTATE_UINT8(tc_int, PL080State),
	92	VMSTATE_STRUCT_ARRAY(chan, PL080State, PL080_MAX_CHANNELS,
ff175853	93	1, vmstate_pl080_channel, pl080_channel),
d7ba0a62	94	VMSTATE_INT32(running, PL080State),
ff175853 PM	95	VMSTATE_END_OF_LIST()
	96	}
	97	};
	98
cdbdb648 PB	99	static const unsigned char pl080_id[] =
	100	{ 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
	101
e69954b9 PB	102	static const unsigned char pl081_id[] =
	103	{ 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
	104
d7ba0a62	105	static void pl080_update(PL080State *s)
cdbdb648 PB	106	{
	107	if ((s->tc_int & s->tc_mask)
	108	\|\| (s->err_int & s->err_mask))
d537cf6c	109	qemu_irq_raise(s->irq);
cdbdb648	110	else
d537cf6c	111	qemu_irq_lower(s->irq);
cdbdb648 PB	112	}
cdbdb648 PB	113
d7ba0a62	114	static void pl080_run(PL080State *s)
cdbdb648 PB	115	{
	116	int c;
	117	int flow;
	118	pl080_channel *ch;
	119	int swidth;
	120	int dwidth;
	121	int xsize;
	122	int n;
	123	int src_id;
	124	int dest_id;
	125	int size;
b55266b5	126	uint8_t buff[4];
cdbdb648 PB	127	uint32_t req;
	128
	129	s->tc_mask = 0;
e69954b9	130	for (c = 0; c < s->nchannels; c++) {
cdbdb648 PB	131	if (s->chan[c].conf & PL080_CCONF_ITC)
	132	s->tc_mask \|= 1 << c;
	133	if (s->chan[c].conf & PL080_CCONF_IE)
	134	s->err_mask \|= 1 << c;
	135	}
	136
	137	if ((s->conf & PL080_CONF_E) == 0)
	138	return;
	139
2ac71179	140	hw_error("DMA active\n");
cdbdb648 PB	141	/* If we are already in the middle of a DMA operation then indicate that
	142	there may be new DMA requests and return immediately. */
	143	if (s->running) {
	144	s->running++;
	145	return;
	146	}
	147	s->running = 1;
	148	while (s->running) {
e69954b9	149	for (c = 0; c < s->nchannels; c++) {
cdbdb648 PB	150	ch = &s->chan[c];
	151	again:
	152	/* Test if thiws channel has any pending DMA requests. */
	153	if ((ch->conf & (PL080_CCONF_H \| PL080_CCONF_E))
	154	!= PL080_CCONF_E)
	155	continue;
	156	flow = (ch->conf >> 11) & 7;
	157	if (flow >= 4) {
2ac71179	158	hw_error(
cdbdb648 PB	159	"pl080_run: Peripheral flow control not implemented\n");
	160	}
	161	src_id = (ch->conf >> 1) & 0x1f;
	162	dest_id = (ch->conf >> 6) & 0x1f;
	163	size = ch->ctrl & 0xfff;
	164	req = s->req_single \| s->req_burst;
	165	switch (flow) {
	166	case 0:
	167	break;
	168	case 1:
	169	if ((req & (1u << dest_id)) == 0)
	170	size = 0;
	171	break;
	172	case 2:
	173	if ((req & (1u << src_id)) == 0)
	174	size = 0;
	175	break;
	176	case 3:
	177	if ((req & (1u << src_id)) == 0
	178	\|\| (req & (1u << dest_id)) == 0)
	179	size = 0;
	180	break;
	181	}
	182	if (!size)
	183	continue;
	184
	185	/* Transfer one element. */
	186	/* ??? Should transfer multiple elements for a burst request. */
	187	/* ??? Unclear what the proper behavior is when source and
	188	destination widths are different. */
	189	swidth = 1 << ((ch->ctrl >> 18) & 7);
	190	dwidth = 1 << ((ch->ctrl >> 21) & 7);
	191	for (n = 0; n < dwidth; n+= swidth) {
	192	cpu_physical_memory_read(ch->src, buff + n, swidth);
	193	if (ch->ctrl & PL080_CCTRL_SI)
	194	ch->src += swidth;
	195	}
	196	xsize = (dwidth < swidth) ? swidth : dwidth;
	197	/* ??? This may pad the value incorrectly for dwidth < 32. */
	198	for (n = 0; n < xsize; n += dwidth) {
	199	cpu_physical_memory_write(ch->dest + n, buff + n, dwidth);
	200	if (ch->ctrl & PL080_CCTRL_DI)
	201	ch->dest += swidth;
	202	}
	203
	204	size--;
	205	ch->ctrl = (ch->ctrl & 0xfffff000) \| size;
	206	if (size == 0) {
	207	/* Transfer complete. */
	208	if (ch->lli) {
42874d3a PM	209	ch->src = address_space_ldl_le(&address_space_memory,
	210	ch->lli,
	211	MEMTXATTRS_UNSPECIFIED,
	212	NULL);
	213	ch->dest = address_space_ldl_le(&address_space_memory,
	214	ch->lli + 4,
	215	MEMTXATTRS_UNSPECIFIED,
	216	NULL);
	217	ch->ctrl = address_space_ldl_le(&address_space_memory,
	218	ch->lli + 12,
	219	MEMTXATTRS_UNSPECIFIED,
	220	NULL);
	221	ch->lli = address_space_ldl_le(&address_space_memory,
	222	ch->lli + 8,
	223	MEMTXATTRS_UNSPECIFIED,
	224	NULL);
cdbdb648 PB	225	} else {
	226	ch->conf &= ~PL080_CCONF_E;
	227	}
	228	if (ch->ctrl & PL080_CCTRL_I) {
	229	s->tc_int \|= 1 << c;
	230	}
	231	}
	232	goto again;
	233	}
	234	if (--s->running)
	235	s->running = 1;
	236	}
	237	}
	238
a8170e5e	239	static uint64_t pl080_read(void *opaque, hwaddr offset,
63b02e04	240	unsigned size)
cdbdb648	241	{
d7ba0a62	242	PL080State s = (PL080State )opaque;
cdbdb648 PB	243	uint32_t i;
	244	uint32_t mask;
	245
cdbdb648	246	if (offset >= 0xfe0 && offset < 0x1000) {
e69954b9 PB	247	if (s->nchannels == 8) {
	248	return pl080_id[(offset - 0xfe0) >> 2];
	249	} else {
	250	return pl081_id[(offset - 0xfe0) >> 2];
	251	}
cdbdb648 PB	252	}
	253	if (offset >= 0x100 && offset < 0x200) {
	254	i = (offset & 0xe0) >> 5;
e69954b9 PB	255	if (i >= s->nchannels)
e69954b9 PB	256	goto bad_offset;
cdbdb648 PB	257	switch (offset >> 2) {
	258	case 0: /* SrcAddr */
	259	return s->chan[i].src;
	260	case 1: /* DestAddr */
	261	return s->chan[i].dest;
	262	case 2: /* LLI */
	263	return s->chan[i].lli;
	264	case 3: /* Control */
	265	return s->chan[i].ctrl;
	266	case 4: /* Configuration */
	267	return s->chan[i].conf;
	268	default:
	269	goto bad_offset;
	270	}
	271	}
	272	switch (offset >> 2) {
	273	case 0: /* IntStatus */
	274	return (s->tc_int & s->tc_mask) \| (s->err_int & s->err_mask);
	275	case 1: /* IntTCStatus */
	276	return (s->tc_int & s->tc_mask);
	277	case 3: /* IntErrorStatus */
	278	return (s->err_int & s->err_mask);
	279	case 5: /* RawIntTCStatus */
	280	return s->tc_int;
	281	case 6: /* RawIntErrorStatus */
	282	return s->err_int;
	283	case 7: /* EnbldChns */
	284	mask = 0;
e69954b9	285	for (i = 0; i < s->nchannels; i++) {
cdbdb648 PB	286	if (s->chan[i].conf & PL080_CCONF_E)
	287	mask \|= 1 << i;
	288	}
	289	return mask;
	290	case 8: /* SoftBReq */
	291	case 9: /* SoftSReq */
	292	case 10: /* SoftLBReq */
	293	case 11: /* SoftLSReq */
	294	/* ??? Implement these. */
	295	return 0;
	296	case 12: /* Configuration */
	297	return s->conf;
	298	case 13: /* Sync */
	299	return s->sync;
	300	default:
	301	bad_offset:
df374162 PM	302	qemu_log_mask(LOG_GUEST_ERROR,
df374162 PM	303	"pl080_read: Bad offset %x\n", (int)offset);
cdbdb648 PB	304	return 0;
	305	}
	306	}
	307
a8170e5e	308	static void pl080_write(void *opaque, hwaddr offset,
63b02e04	309	uint64_t value, unsigned size)
cdbdb648	310	{
d7ba0a62	311	PL080State s = (PL080State )opaque;
cdbdb648 PB	312	int i;
cdbdb648 PB	313
cdbdb648 PB	314	if (offset >= 0x100 && offset < 0x200) {
cdbdb648 PB	315	i = (offset & 0xe0) >> 5;
e69954b9 PB	316	if (i >= s->nchannels)
e69954b9 PB	317	goto bad_offset;
cdbdb648 PB	318	switch (offset >> 2) {
	319	case 0: /* SrcAddr */
	320	s->chan[i].src = value;
	321	break;
	322	case 1: /* DestAddr */
	323	s->chan[i].dest = value;
	324	break;
	325	case 2: /* LLI */
	326	s->chan[i].lli = value;
	327	break;
	328	case 3: /* Control */
	329	s->chan[i].ctrl = value;
	330	break;
	331	case 4: /* Configuration */
	332	s->chan[i].conf = value;
	333	pl080_run(s);
	334	break;
	335	}
	336	}
	337	switch (offset >> 2) {
	338	case 2: /* IntTCClear */
	339	s->tc_int &= ~value;
	340	break;
	341	case 4: /* IntErrorClear */
	342	s->err_int &= ~value;
	343	break;
	344	case 8: /* SoftBReq */
	345	case 9: /* SoftSReq */
	346	case 10: /* SoftLBReq */
	347	case 11: /* SoftLSReq */
	348	/* ??? Implement these. */
df374162	349	qemu_log_mask(LOG_UNIMP, "pl080_write: Soft DMA not implemented\n");
cdbdb648 PB	350	break;
	351	case 12: /* Configuration */
	352	s->conf = value;
	353	if (s->conf & (PL080_CONF_M1 \| PL080_CONF_M1)) {
df374162 PM	354	qemu_log_mask(LOG_UNIMP,
df374162 PM	355	"pl080_write: Big-endian DMA not implemented\n");
cdbdb648 PB	356	}
	357	pl080_run(s);
	358	break;
	359	case 13: /* Sync */
	360	s->sync = value;
	361	break;
	362	default:
e69954b9	363	bad_offset:
df374162 PM	364	qemu_log_mask(LOG_GUEST_ERROR,
df374162 PM	365	"pl080_write: Bad offset %x\n", (int)offset);
cdbdb648 PB	366	}
	367	pl080_update(s);
	368	}
	369
63b02e04 AK	370	static const MemoryRegionOps pl080_ops = {
	371	.read = pl080_read,
	372	.write = pl080_write,
	373	.endianness = DEVICE_NATIVE_ENDIAN,
cdbdb648 PB	374	};
cdbdb648 PB	375
4f800554	376	static void pl080_init(Object *obj)
cdbdb648	377	{
4f800554 AF	378	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
4f800554 AF	379	PL080State *s = PL080(obj);
cdbdb648	380
3eadad55	381	memory_region_init_io(&s->iomem, OBJECT(s), &pl080_ops, s, "pl080", 0x1000);
4f800554 AF	382	sysbus_init_mmio(sbd, &s->iomem);
	383	sysbus_init_irq(sbd, &s->irq);
	384	s->nchannels = 8;
cdbdb648	385	}
b4496b13	386
4f800554	387	static void pl081_init(Object *obj)
b4496b13	388	{
4f800554	389	PL080State *s = PL080(obj);
b4496b13	390
4f800554	391	s->nchannels = 2;
b4496b13 PB	392	}
b4496b13 PB	393
4f800554	394	static void pl080_class_init(ObjectClass oc, void data)
999e12bb	395	{
4f800554	396	DeviceClass *dc = DEVICE_CLASS(oc);
999e12bb	397
39bffca2	398	dc->vmsd = &vmstate_pl080;
999e12bb AL	399	}
999e12bb AL	400
8c43a6f0	401	static const TypeInfo pl080_info = {
4f800554	402	.name = TYPE_PL080,
39bffca2	403	.parent = TYPE_SYS_BUS_DEVICE,
d7ba0a62	404	.instance_size = sizeof(PL080State),
4f800554	405	.instance_init = pl080_init,
39bffca2	406	.class_init = pl080_class_init,
ff175853 PM	407	};
ff175853 PM	408
8c43a6f0	409	static const TypeInfo pl081_info = {
39bffca2	410	.name = "pl081",
4f800554 AF	411	.parent = TYPE_PL080,
4f800554 AF	412	.instance_init = pl081_init,
ff175853 PM	413	};
ff175853 PM	414
b4496b13 PB	415	/* The PL080 and PL081 are the same except for the number of channels
b4496b13 PB	416	they implement (8 and 2 respectively). */
83f7d43a	417	static void pl080_register_types(void)
b4496b13	418	{
39bffca2 AL	419	type_register_static(&pl080_info);
39bffca2 AL	420	type_register_static(&pl081_info);
b4496b13 PB	421	}
b4496b13 PB	422
83f7d43a	423	type_init(pl080_register_types)