[mirror_qemu.git] / hw / dma / puv3_dma.c

/*
 * DMA device simulation in PKUnity SoC
 *
 * Copyright (C) 2010-2012 Guan Xuetao
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation, or any later version.
 * See the COPYING file in the top-level directory.
 */

#include "qemu/osdep.h"
#include "hw/sysbus.h"

#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
#include "qemu/module.h"

#define PUV3_DMA_CH_NR          (6)
#define PUV3_DMA_CH_MASK        (0xff)
#define PUV3_DMA_CH(offset)     ((offset) >> 8)

#define TYPE_PUV3_DMA "puv3_dma"
#define PUV3_DMA(obj) OBJECT_CHECK(PUV3DMAState, (obj), TYPE_PUV3_DMA)

typedef struct PUV3DMAState {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    uint32_t reg_CFG[PUV3_DMA_CH_NR];
} PUV3DMAState;

static uint64_t puv3_dma_read(void *opaque, hwaddr offset,
        unsigned size)
{
    PUV3DMAState *s = opaque;
    uint32_t ret = 0;

    assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR);

    switch (offset & PUV3_DMA_CH_MASK) {
    case 0x10:
        ret = s->reg_CFG[PUV3_DMA_CH(offset)];
        break;
    default:
        DPRINTF("Bad offset 0x%x\n", offset);
    }
    DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);

    return ret;
}

static void puv3_dma_write(void *opaque, hwaddr offset,
        uint64_t value, unsigned size)
{
    PUV3DMAState *s = opaque;

    assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR);

    switch (offset & PUV3_DMA_CH_MASK) {
    case 0x10:
        s->reg_CFG[PUV3_DMA_CH(offset)] = value;
        break;
    default:
        DPRINTF("Bad offset 0x%x\n", offset);
    }
    DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
}

static const MemoryRegionOps puv3_dma_ops = {
    .read = puv3_dma_read,
    .write = puv3_dma_write,
    .impl = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void puv3_dma_realize(DeviceState *dev, Error **errp)
{
    PUV3DMAState *s = PUV3_DMA(dev);
    int i;

    for (i = 0; i < PUV3_DMA_CH_NR; i++) {
        s->reg_CFG[i] = 0x0;
    }

    memory_region_init_io(&s->iomem, OBJECT(s), &puv3_dma_ops, s, "puv3_dma",
            PUV3_REGS_OFFSET);
    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
}

static void puv3_dma_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = puv3_dma_realize;
}

static const TypeInfo puv3_dma_info = {
    .name = TYPE_PUV3_DMA,
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PUV3DMAState),
    .class_init = puv3_dma_class_init,
};

static void puv3_dma_register_type(void)
{
    type_register_static(&puv3_dma_info);
}

type_init(puv3_dma_register_type)
Commit	Line	Data
1ea34899 GX	1	/*
	2	* DMA device simulation in PKUnity SoC
	3	*
	4	* Copyright (C) 2010-2012 Guan Xuetao
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation, or any later version.
	9	* See the COPYING file in the top-level directory.
	10	*/
0b8fa32f	11
5af98cc5	12	#include "qemu/osdep.h"
83c9f4ca	13	#include "hw/sysbus.h"
1ea34899 GX	14
1ea34899 GX	15	#undef DEBUG_PUV3
0d09e41a	16	#include "hw/unicore32/puv3.h"
0b8fa32f	17	#include "qemu/module.h"
1ea34899 GX	18
	19	#define PUV3_DMA_CH_NR (6)
	20	#define PUV3_DMA_CH_MASK (0xff)
	21	#define PUV3_DMA_CH(offset) ((offset) >> 8)
	22
6df7cdee AF	23	#define TYPE_PUV3_DMA "puv3_dma"
	24	#define PUV3_DMA(obj) OBJECT_CHECK(PUV3DMAState, (obj), TYPE_PUV3_DMA)
	25
	26	typedef struct PUV3DMAState {
	27	SysBusDevice parent_obj;
	28
1ea34899 GX	29	MemoryRegion iomem;
	30	uint32_t reg_CFG[PUV3_DMA_CH_NR];
	31	} PUV3DMAState;
	32
a8170e5e	33	static uint64_t puv3_dma_read(void *opaque, hwaddr offset,
1ea34899 GX	34	unsigned size)
	35	{
	36	PUV3DMAState *s = opaque;
	37	uint32_t ret = 0;
	38
	39	assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR);
	40
	41	switch (offset & PUV3_DMA_CH_MASK) {
	42	case 0x10:
	43	ret = s->reg_CFG[PUV3_DMA_CH(offset)];
	44	break;
	45	default:
	46	DPRINTF("Bad offset 0x%x\n", offset);
	47	}
	48	DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
	49
	50	return ret;
	51	}
	52
a8170e5e	53	static void puv3_dma_write(void *opaque, hwaddr offset,
1ea34899 GX	54	uint64_t value, unsigned size)
	55	{
	56	PUV3DMAState *s = opaque;
	57
	58	assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR);
	59
	60	switch (offset & PUV3_DMA_CH_MASK) {
	61	case 0x10:
	62	s->reg_CFG[PUV3_DMA_CH(offset)] = value;
	63	break;
	64	default:
	65	DPRINTF("Bad offset 0x%x\n", offset);
	66	}
	67	DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
	68	}
	69
	70	static const MemoryRegionOps puv3_dma_ops = {
	71	.read = puv3_dma_read,
	72	.write = puv3_dma_write,
	73	.impl = {
	74	.min_access_size = 4,
	75	.max_access_size = 4,
	76	},
	77	.endianness = DEVICE_NATIVE_ENDIAN,
	78	};
	79
8ba7f726	80	static void puv3_dma_realize(DeviceState dev, Error *errp)
1ea34899	81	{
6df7cdee	82	PUV3DMAState *s = PUV3_DMA(dev);
1ea34899 GX	83	int i;
	84
	85	for (i = 0; i < PUV3_DMA_CH_NR; i++) {
	86	s->reg_CFG[i] = 0x0;
	87	}
	88
3eadad55	89	memory_region_init_io(&s->iomem, OBJECT(s), &puv3_dma_ops, s, "puv3_dma",
1ea34899	90	PUV3_REGS_OFFSET);
8ba7f726	91	sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
1ea34899 GX	92	}
	93
	94	static void puv3_dma_class_init(ObjectClass klass, void data)
	95	{
8ba7f726	96	DeviceClass *dc = DEVICE_CLASS(klass);
1ea34899	97
8ba7f726	98	dc->realize = puv3_dma_realize;
1ea34899 GX	99	}
	100
	101	static const TypeInfo puv3_dma_info = {
6df7cdee	102	.name = TYPE_PUV3_DMA,
1ea34899 GX	103	.parent = TYPE_SYS_BUS_DEVICE,
	104	.instance_size = sizeof(PUV3DMAState),
	105	.class_init = puv3_dma_class_init,
	106	};
	107
	108	static void puv3_dma_register_type(void)
	109	{
	110	type_register_static(&puv3_dma_info);
	111	}
	112
	113	type_init(puv3_dma_register_type)