[mirror_qemu.git] / hw / dma / pxa2xx_dma.c

/*
 * Intel XScale PXA255/270 DMA controller.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Copyright (c) 2006 Thorsten Zitterell
 * Written by Andrzej Zaborowski <balrog@zabor.org>
 *
 * This code is licensed under the GPL.
 */

#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/arm/pxa.h"
#include "hw/sysbus.h"
#include "qapi/error.h"

#define PXA255_DMA_NUM_CHANNELS 16
#define PXA27X_DMA_NUM_CHANNELS 32

#define PXA2XX_DMA_NUM_REQUESTS 75

typedef struct {
    uint32_t descr;
    uint32_t src;
    uint32_t dest;
    uint32_t cmd;
    uint32_t state;
    int request;
} PXA2xxDMAChannel;

#define TYPE_PXA2XX_DMA "pxa2xx-dma"
#define PXA2XX_DMA(obj) OBJECT_CHECK(PXA2xxDMAState, (obj), TYPE_PXA2XX_DMA)

typedef struct PXA2xxDMAState {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    qemu_irq irq;

    uint32_t stopintr;
    uint32_t eorintr;
    uint32_t rasintr;
    uint32_t startintr;
    uint32_t endintr;

    uint32_t align;
    uint32_t pio;

    int channels;
    PXA2xxDMAChannel *chan;

    uint8_t req[PXA2XX_DMA_NUM_REQUESTS];

    /* Flag to avoid recursive DMA invocations.  */
    int running;
} PXA2xxDMAState;

#define DCSR0	0x0000	/* DMA Control / Status register for Channel 0 */
#define DCSR31	0x007c	/* DMA Control / Status register for Channel 31 */
#define DALGN	0x00a0	/* DMA Alignment register */
#define DPCSR	0x00a4	/* DMA Programmed I/O Control Status register */
#define DRQSR0	0x00e0	/* DMA DREQ<0> Status register */
#define DRQSR1	0x00e4	/* DMA DREQ<1> Status register */
#define DRQSR2	0x00e8	/* DMA DREQ<2> Status register */
#define DINT	0x00f0	/* DMA Interrupt register */
#define DRCMR0	0x0100	/* Request to Channel Map register 0 */
#define DRCMR63	0x01fc	/* Request to Channel Map register 63 */
#define D_CH0	0x0200	/* Channel 0 Descriptor start */
#define DRCMR64	0x1100	/* Request to Channel Map register 64 */
#define DRCMR74	0x1128	/* Request to Channel Map register 74 */

/* Per-channel register */
#define DDADR	0x00
#define DSADR	0x01
#define DTADR	0x02
#define DCMD	0x03

/* Bit-field masks */
#define DRCMR_CHLNUM		0x1f
#define DRCMR_MAPVLD		(1 << 7)
#define DDADR_STOP		(1 << 0)
#define DDADR_BREN		(1 << 1)
#define DCMD_LEN		0x1fff
#define DCMD_WIDTH(x)		(1 << ((((x) >> 14) & 3) - 1))
#define DCMD_SIZE(x)		(4 << (((x) >> 16) & 3))
#define DCMD_FLYBYT		(1 << 19)
#define DCMD_FLYBYS		(1 << 20)
#define DCMD_ENDIRQEN		(1 << 21)
#define DCMD_STARTIRQEN		(1 << 22)
#define DCMD_CMPEN		(1 << 25)
#define DCMD_FLOWTRG		(1 << 28)
#define DCMD_FLOWSRC		(1 << 29)
#define DCMD_INCTRGADDR		(1 << 30)
#define DCMD_INCSRCADDR		(1 << 31)
#define DCSR_BUSERRINTR		(1 << 0)
#define DCSR_STARTINTR		(1 << 1)
#define DCSR_ENDINTR		(1 << 2)
#define DCSR_STOPINTR		(1 << 3)
#define DCSR_RASINTR		(1 << 4)
#define DCSR_REQPEND		(1 << 8)
#define DCSR_EORINT		(1 << 9)
#define DCSR_CMPST		(1 << 10)
#define DCSR_MASKRUN		(1 << 22)
#define DCSR_RASIRQEN		(1 << 23)
#define DCSR_CLRCMPST		(1 << 24)
#define DCSR_SETCMPST		(1 << 25)
#define DCSR_EORSTOPEN		(1 << 26)
#define DCSR_EORJMPEN		(1 << 27)
#define DCSR_EORIRQEN		(1 << 28)
#define DCSR_STOPIRQEN		(1 << 29)
#define DCSR_NODESCFETCH	(1 << 30)
#define DCSR_RUN		(1 << 31)

static inline void pxa2xx_dma_update(PXA2xxDMAState *s, int ch)
{
    if (ch >= 0) {
        if ((s->chan[ch].state & DCSR_STOPIRQEN) &&
                (s->chan[ch].state & DCSR_STOPINTR))
            s->stopintr |= 1 << ch;
        else
            s->stopintr &= ~(1 << ch);

        if ((s->chan[ch].state & DCSR_EORIRQEN) &&
                (s->chan[ch].state & DCSR_EORINT))
            s->eorintr |= 1 << ch;
        else
            s->eorintr &= ~(1 << ch);

        if ((s->chan[ch].state & DCSR_RASIRQEN) &&
                (s->chan[ch].state & DCSR_RASINTR))
            s->rasintr |= 1 << ch;
        else
            s->rasintr &= ~(1 << ch);

        if (s->chan[ch].state & DCSR_STARTINTR)
            s->startintr |= 1 << ch;
        else
            s->startintr &= ~(1 << ch);

        if (s->chan[ch].state & DCSR_ENDINTR)
            s->endintr |= 1 << ch;
        else
            s->endintr &= ~(1 << ch);
    }

    if (s->stopintr | s->eorintr | s->rasintr | s->startintr | s->endintr)
        qemu_irq_raise(s->irq);
    else
        qemu_irq_lower(s->irq);
}

static inline void pxa2xx_dma_descriptor_fetch(
                PXA2xxDMAState *s, int ch)
{
    uint32_t desc[4];
    hwaddr daddr = s->chan[ch].descr & ~0xf;
    if ((s->chan[ch].descr & DDADR_BREN) && (s->chan[ch].state & DCSR_CMPST))
        daddr += 32;

    cpu_physical_memory_read(daddr, desc, 16);
    s->chan[ch].descr = desc[DDADR];
    s->chan[ch].src = desc[DSADR];
    s->chan[ch].dest = desc[DTADR];
    s->chan[ch].cmd = desc[DCMD];

    if (s->chan[ch].cmd & DCMD_FLOWSRC)
        s->chan[ch].src &= ~3;
    if (s->chan[ch].cmd & DCMD_FLOWTRG)
        s->chan[ch].dest &= ~3;

    if (s->chan[ch].cmd & (DCMD_CMPEN | DCMD_FLYBYS | DCMD_FLYBYT))
        printf("%s: unsupported mode in channel %i\n", __FUNCTION__, ch);

    if (s->chan[ch].cmd & DCMD_STARTIRQEN)
        s->chan[ch].state |= DCSR_STARTINTR;
}

static void pxa2xx_dma_run(PXA2xxDMAState *s)
{
    int c, srcinc, destinc;
    uint32_t n, size;
    uint32_t width;
    uint32_t length;
    uint8_t buffer[32];
    PXA2xxDMAChannel *ch;

    if (s->running ++)
        return;

    while (s->running) {
        s->running = 1;
        for (c = 0; c < s->channels; c ++) {
            ch = &s->chan[c];

            while ((ch->state & DCSR_RUN) && !(ch->state & DCSR_STOPINTR)) {
                /* Test for pending requests */
                if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && !ch->request)
                    break;

                length = ch->cmd & DCMD_LEN;
                size = DCMD_SIZE(ch->cmd);
                width = DCMD_WIDTH(ch->cmd);

                srcinc = (ch->cmd & DCMD_INCSRCADDR) ? width : 0;
                destinc = (ch->cmd & DCMD_INCTRGADDR) ? width : 0;

                while (length) {
                    size = MIN(length, size);

                    for (n = 0; n < size; n += width) {
                        cpu_physical_memory_read(ch->src, buffer + n, width);
                        ch->src += srcinc;
                    }

                    for (n = 0; n < size; n += width) {
                        cpu_physical_memory_write(ch->dest, buffer + n, width);
                        ch->dest += destinc;
                    }

                    length -= size;

                    if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) &&
                            !ch->request) {
                        ch->state |= DCSR_EORINT;
                        if (ch->state & DCSR_EORSTOPEN)
                            ch->state |= DCSR_STOPINTR;
                        if ((ch->state & DCSR_EORJMPEN) &&
                                        !(ch->state & DCSR_NODESCFETCH))
                            pxa2xx_dma_descriptor_fetch(s, c);
                        break;
		    }
                }

                ch->cmd = (ch->cmd & ~DCMD_LEN) | length;

                /* Is the transfer complete now? */
                if (!length) {
                    if (ch->cmd & DCMD_ENDIRQEN)
                        ch->state |= DCSR_ENDINTR;

                    if ((ch->state & DCSR_NODESCFETCH) ||
                                (ch->descr & DDADR_STOP) ||
                                (ch->state & DCSR_EORSTOPEN)) {
                        ch->state |= DCSR_STOPINTR;
                        ch->state &= ~DCSR_RUN;

                        break;
                    }

                    ch->state |= DCSR_STOPINTR;
                    break;
                }
            }
        }

        s->running --;
    }
}

static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
                                unsigned size)
{
    PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
    unsigned int channel;

    if (size != 4) {
        hw_error("%s: Bad access width\n", __FUNCTION__);
        return 5;
    }

    switch (offset) {
    case DRCMR64 ... DRCMR74:
        offset -= DRCMR64 - DRCMR0 - (64 << 2);
        /* Fall through */
    case DRCMR0 ... DRCMR63:
        channel = (offset - DRCMR0) >> 2;
        return s->req[channel];

    case DRQSR0:
    case DRQSR1:
    case DRQSR2:
        return 0;

    case DCSR0 ... DCSR31:
        channel = offset >> 2;
	if (s->chan[channel].request)
            return s->chan[channel].state | DCSR_REQPEND;
        return s->chan[channel].state;

    case DINT:
        return s->stopintr | s->eorintr | s->rasintr |
                s->startintr | s->endintr;

    case DALGN:
        return s->align;

    case DPCSR:
        return s->pio;
    }

    if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) {
        channel = (offset - D_CH0) >> 4;
        switch ((offset & 0x0f) >> 2) {
        case DDADR:
            return s->chan[channel].descr;
        case DSADR:
            return s->chan[channel].src;
        case DTADR:
            return s->chan[channel].dest;
        case DCMD:
            return s->chan[channel].cmd;
        }
    }

    hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __FUNCTION__, offset);
    return 7;
}

static void pxa2xx_dma_write(void *opaque, hwaddr offset,
                             uint64_t value, unsigned size)
{
    PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
    unsigned int channel;

    if (size != 4) {
        hw_error("%s: Bad access width\n", __FUNCTION__);
        return;
    }

    switch (offset) {
    case DRCMR64 ... DRCMR74:
        offset -= DRCMR64 - DRCMR0 - (64 << 2);
        /* Fall through */
    case DRCMR0 ... DRCMR63:
        channel = (offset - DRCMR0) >> 2;

        if (value & DRCMR_MAPVLD)
            if ((value & DRCMR_CHLNUM) > s->channels)
                hw_error("%s: Bad DMA channel %i\n",
                         __FUNCTION__, (unsigned)value & DRCMR_CHLNUM);

        s->req[channel] = value;
        break;

    case DRQSR0:
    case DRQSR1:
    case DRQSR2:
        /* Nothing to do */
        break;

    case DCSR0 ... DCSR31:
        channel = offset >> 2;
        s->chan[channel].state &= 0x0000071f & ~(value &
                        (DCSR_EORINT | DCSR_ENDINTR |
                         DCSR_STARTINTR | DCSR_BUSERRINTR));
        s->chan[channel].state |= value & 0xfc800000;

        if (s->chan[channel].state & DCSR_STOPIRQEN)
            s->chan[channel].state &= ~DCSR_STOPINTR;

        if (value & DCSR_NODESCFETCH) {
            /* No-descriptor-fetch mode */
            if (value & DCSR_RUN) {
                s->chan[channel].state &= ~DCSR_STOPINTR;
                pxa2xx_dma_run(s);
            }
        } else {
            /* Descriptor-fetch mode */
            if (value & DCSR_RUN) {
                s->chan[channel].state &= ~DCSR_STOPINTR;
                pxa2xx_dma_descriptor_fetch(s, channel);
                pxa2xx_dma_run(s);
            }
        }

        /* Shouldn't matter as our DMA is synchronous.  */
        if (!(value & (DCSR_RUN | DCSR_MASKRUN)))
            s->chan[channel].state |= DCSR_STOPINTR;

        if (value & DCSR_CLRCMPST)
            s->chan[channel].state &= ~DCSR_CMPST;
        if (value & DCSR_SETCMPST)
            s->chan[channel].state |= DCSR_CMPST;

        pxa2xx_dma_update(s, channel);
        break;

    case DALGN:
        s->align = value;
        break;

    case DPCSR:
        s->pio = value & 0x80000001;
        break;

    default:
        if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) {
            channel = (offset - D_CH0) >> 4;
            switch ((offset & 0x0f) >> 2) {
            case DDADR:
                s->chan[channel].descr = value;
                break;
            case DSADR:
                s->chan[channel].src = value;
                break;
            case DTADR:
                s->chan[channel].dest = value;
                break;
            case DCMD:
                s->chan[channel].cmd = value;
                break;
            default:
                goto fail;
            }

            break;
        }
    fail:
        hw_error("%s: Bad offset " TARGET_FMT_plx "\n", __FUNCTION__, offset);
    }
}

static const MemoryRegionOps pxa2xx_dma_ops = {
    .read = pxa2xx_dma_read,
    .write = pxa2xx_dma_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void pxa2xx_dma_request(void *opaque, int req_num, int on)
{
    PXA2xxDMAState *s = opaque;
    int ch;
    if (req_num < 0 || req_num >= PXA2XX_DMA_NUM_REQUESTS)
        hw_error("%s: Bad DMA request %i\n", __FUNCTION__, req_num);

    if (!(s->req[req_num] & DRCMR_MAPVLD))
        return;
    ch = s->req[req_num] & DRCMR_CHLNUM;

    if (!s->chan[ch].request && on)
        s->chan[ch].state |= DCSR_RASINTR;
    else
        s->chan[ch].state &= ~DCSR_RASINTR;
    if (s->chan[ch].request && !on)
        s->chan[ch].state |= DCSR_EORINT;

    s->chan[ch].request = on;
    if (on) {
        pxa2xx_dma_run(s);
        pxa2xx_dma_update(s, ch);
    }
}

static void pxa2xx_dma_init(Object *obj)
{
    DeviceState *dev = DEVICE(obj);
    PXA2xxDMAState *s = PXA2XX_DMA(obj);
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);

    memset(s->req, 0, sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS);

    qdev_init_gpio_in(dev, pxa2xx_dma_request, PXA2XX_DMA_NUM_REQUESTS);

    memory_region_init_io(&s->iomem, obj, &pxa2xx_dma_ops, s,
                          "pxa2xx.dma", 0x00010000);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq);
}

static void pxa2xx_dma_realize(DeviceState *dev, Error **errp)
{
    PXA2xxDMAState *s = PXA2XX_DMA(dev);
    int i;

    if (s->channels <= 0) {
        error_setg(errp, "channels value invalid");
        return;
    }

    s->chan = g_new0(PXA2xxDMAChannel, s->channels);

    for (i = 0; i < s->channels; i ++)
        s->chan[i].state = DCSR_STOPINTR;
}

DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq)
{
    DeviceState *dev;

    dev = qdev_create(NULL, "pxa2xx-dma");
    qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
    qdev_init_nofail(dev);

    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);

    return dev;
}

DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq)
{
    DeviceState *dev;

    dev = qdev_create(NULL, "pxa2xx-dma");
    qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
    qdev_init_nofail(dev);

    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);

    return dev;
}

static bool is_version_0(void *opaque, int version_id)
{
    return version_id == 0;
}

static VMStateDescription vmstate_pxa2xx_dma_chan = {
    .name = "pxa2xx_dma_chan",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(descr, PXA2xxDMAChannel),
        VMSTATE_UINT32(src, PXA2xxDMAChannel),
        VMSTATE_UINT32(dest, PXA2xxDMAChannel),
        VMSTATE_UINT32(cmd, PXA2xxDMAChannel),
        VMSTATE_UINT32(state, PXA2xxDMAChannel),
        VMSTATE_INT32(request, PXA2xxDMAChannel),
        VMSTATE_END_OF_LIST(),
    },
};

static VMStateDescription vmstate_pxa2xx_dma = {
    .name = "pxa2xx_dma",
    .version_id = 1,
    .minimum_version_id = 0,
    .fields = (VMStateField[]) {
        VMSTATE_UNUSED_TEST(is_version_0, 4),
        VMSTATE_UINT32(stopintr, PXA2xxDMAState),
        VMSTATE_UINT32(eorintr, PXA2xxDMAState),
        VMSTATE_UINT32(rasintr, PXA2xxDMAState),
        VMSTATE_UINT32(startintr, PXA2xxDMAState),
        VMSTATE_UINT32(endintr, PXA2xxDMAState),
        VMSTATE_UINT32(align, PXA2xxDMAState),
        VMSTATE_UINT32(pio, PXA2xxDMAState),
        VMSTATE_BUFFER(req, PXA2xxDMAState),
        VMSTATE_STRUCT_VARRAY_POINTER_INT32(chan, PXA2xxDMAState, channels,
                vmstate_pxa2xx_dma_chan, PXA2xxDMAChannel),
        VMSTATE_END_OF_LIST(),
    },
};

static Property pxa2xx_dma_properties[] = {
    DEFINE_PROP_INT32("channels", PXA2xxDMAState, channels, -1),
    DEFINE_PROP_END_OF_LIST(),
};

static void pxa2xx_dma_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->desc = "PXA2xx DMA controller";
    dc->vmsd = &vmstate_pxa2xx_dma;
    dc->props = pxa2xx_dma_properties;
    dc->realize = pxa2xx_dma_realize;
}

static const TypeInfo pxa2xx_dma_info = {
    .name          = TYPE_PXA2XX_DMA,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PXA2xxDMAState),
    .instance_init = pxa2xx_dma_init,
    .class_init    = pxa2xx_dma_class_init,
};

static void pxa2xx_dma_register_types(void)
{
    type_register_static(&pxa2xx_dma_info);
}

type_init(pxa2xx_dma_register_types)
Commit	Line	Data
c1713132 AZ	1	/*
	2	* Intel XScale PXA255/270 DMA controller.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Copyright (c) 2006 Thorsten Zitterell
	6	* Written by Andrzej Zaborowski <balrog@zabor.org>
	7	*
8e31bf38	8	* This code is licensed under the GPL.
c1713132 AZ	9	*/
c1713132 AZ	10
8ef94f0b	11	#include "qemu/osdep.h"
83c9f4ca	12	#include "hw/hw.h"
0d09e41a	13	#include "hw/arm/pxa.h"
83c9f4ca	14	#include "hw/sysbus.h"
c9796d71	15	#include "qapi/error.h"
2115c019 AZ	16
	17	#define PXA255_DMA_NUM_CHANNELS 16
	18	#define PXA27X_DMA_NUM_CHANNELS 32
	19
	20	#define PXA2XX_DMA_NUM_REQUESTS 75
c1713132	21
bc24a225	22	typedef struct {
a10394e1 MI	23	uint32_t descr;
	24	uint32_t src;
	25	uint32_t dest;
c1713132 AZ	26	uint32_t cmd;
	27	uint32_t state;
	28	int request;
bc24a225	29	} PXA2xxDMAChannel;
c1713132	30
358cd7ac AF	31	#define TYPE_PXA2XX_DMA "pxa2xx-dma"
	32	#define PXA2XX_DMA(obj) OBJECT_CHECK(PXA2xxDMAState, (obj), TYPE_PXA2XX_DMA)
	33
2115c019	34	typedef struct PXA2xxDMAState {
358cd7ac AF	35	SysBusDevice parent_obj;
358cd7ac AF	36
00049a12	37	MemoryRegion iomem;
c1713132 AZ	38	qemu_irq irq;
	39
	40	uint32_t stopintr;
	41	uint32_t eorintr;
	42	uint32_t rasintr;
	43	uint32_t startintr;
	44	uint32_t endintr;
	45
	46	uint32_t align;
	47	uint32_t pio;
	48
	49	int channels;
bc24a225	50	PXA2xxDMAChannel *chan;
c1713132	51
2115c019	52	uint8_t req[PXA2XX_DMA_NUM_REQUESTS];
c1713132 AZ	53
	54	/* Flag to avoid recursive DMA invocations. */
	55	int running;
2115c019	56	} PXA2xxDMAState;
c1713132 AZ	57
	58	#define DCSR0 0x0000 /* DMA Control / Status register for Channel 0 */
	59	#define DCSR31 0x007c /* DMA Control / Status register for Channel 31 */
	60	#define DALGN 0x00a0 /* DMA Alignment register */
	61	#define DPCSR 0x00a4 /* DMA Programmed I/O Control Status register */
	62	#define DRQSR0 0x00e0 /* DMA DREQ<0> Status register */
	63	#define DRQSR1 0x00e4 /* DMA DREQ<1> Status register */
	64	#define DRQSR2 0x00e8 /* DMA DREQ<2> Status register */
	65	#define DINT 0x00f0 /* DMA Interrupt register */
	66	#define DRCMR0 0x0100 /* Request to Channel Map register 0 */
	67	#define DRCMR63 0x01fc /* Request to Channel Map register 63 */
	68	#define D_CH0 0x0200 /* Channel 0 Descriptor start */
	69	#define DRCMR64 0x1100 /* Request to Channel Map register 64 */
	70	#define DRCMR74 0x1128 /* Request to Channel Map register 74 */
	71
	72	/* Per-channel register */
	73	#define DDADR 0x00
	74	#define DSADR 0x01
	75	#define DTADR 0x02
	76	#define DCMD 0x03
	77
	78	/* Bit-field masks */
	79	#define DRCMR_CHLNUM 0x1f
	80	#define DRCMR_MAPVLD (1 << 7)
	81	#define DDADR_STOP (1 << 0)
	82	#define DDADR_BREN (1 << 1)
	83	#define DCMD_LEN 0x1fff
	84	#define DCMD_WIDTH(x) (1 << ((((x) >> 14) & 3) - 1))
	85	#define DCMD_SIZE(x) (4 << (((x) >> 16) & 3))
	86	#define DCMD_FLYBYT (1 << 19)
	87	#define DCMD_FLYBYS (1 << 20)
	88	#define DCMD_ENDIRQEN (1 << 21)
	89	#define DCMD_STARTIRQEN (1 << 22)
	90	#define DCMD_CMPEN (1 << 25)
	91	#define DCMD_FLOWTRG (1 << 28)
	92	#define DCMD_FLOWSRC (1 << 29)
	93	#define DCMD_INCTRGADDR (1 << 30)
	94	#define DCMD_INCSRCADDR (1 << 31)
	95	#define DCSR_BUSERRINTR (1 << 0)
	96	#define DCSR_STARTINTR (1 << 1)
	97	#define DCSR_ENDINTR (1 << 2)
	98	#define DCSR_STOPINTR (1 << 3)
	99	#define DCSR_RASINTR (1 << 4)
	100	#define DCSR_REQPEND (1 << 8)
	101	#define DCSR_EORINT (1 << 9)
	102	#define DCSR_CMPST (1 << 10)
	103	#define DCSR_MASKRUN (1 << 22)
	104	#define DCSR_RASIRQEN (1 << 23)
	105	#define DCSR_CLRCMPST (1 << 24)
	106	#define DCSR_SETCMPST (1 << 25)
	107	#define DCSR_EORSTOPEN (1 << 26)
	108	#define DCSR_EORJMPEN (1 << 27)
	109	#define DCSR_EORIRQEN (1 << 28)
	110	#define DCSR_STOPIRQEN (1 << 29)
	111	#define DCSR_NODESCFETCH (1 << 30)
	112	#define DCSR_RUN (1 << 31)
	113
bc24a225	114	static inline void pxa2xx_dma_update(PXA2xxDMAState *s, int ch)
c1713132 AZ	115	{
	116	if (ch >= 0) {
	117	if ((s->chan[ch].state & DCSR_STOPIRQEN) &&
	118	(s->chan[ch].state & DCSR_STOPINTR))
	119	s->stopintr \|= 1 << ch;
	120	else
	121	s->stopintr &= ~(1 << ch);
	122
	123	if ((s->chan[ch].state & DCSR_EORIRQEN) &&
	124	(s->chan[ch].state & DCSR_EORINT))
	125	s->eorintr \|= 1 << ch;
	126	else
	127	s->eorintr &= ~(1 << ch);
	128
	129	if ((s->chan[ch].state & DCSR_RASIRQEN) &&
	130	(s->chan[ch].state & DCSR_RASINTR))
	131	s->rasintr \|= 1 << ch;
	132	else
	133	s->rasintr &= ~(1 << ch);
	134
	135	if (s->chan[ch].state & DCSR_STARTINTR)
	136	s->startintr \|= 1 << ch;
	137	else
	138	s->startintr &= ~(1 << ch);
	139
	140	if (s->chan[ch].state & DCSR_ENDINTR)
	141	s->endintr \|= 1 << ch;
	142	else
	143	s->endintr &= ~(1 << ch);
	144	}
	145
	146	if (s->stopintr \| s->eorintr \| s->rasintr \| s->startintr \| s->endintr)
	147	qemu_irq_raise(s->irq);
	148	else
	149	qemu_irq_lower(s->irq);
	150	}
	151
	152	static inline void pxa2xx_dma_descriptor_fetch(
bc24a225	153	PXA2xxDMAState *s, int ch)
c1713132 AZ	154	{
c1713132 AZ	155	uint32_t desc[4];
a8170e5e	156	hwaddr daddr = s->chan[ch].descr & ~0xf;
c1713132 AZ	157	if ((s->chan[ch].descr & DDADR_BREN) && (s->chan[ch].state & DCSR_CMPST))
	158	daddr += 32;
	159
e1fe50dc	160	cpu_physical_memory_read(daddr, desc, 16);
c1713132 AZ	161	s->chan[ch].descr = desc[DDADR];
	162	s->chan[ch].src = desc[DSADR];
	163	s->chan[ch].dest = desc[DTADR];
	164	s->chan[ch].cmd = desc[DCMD];
	165
	166	if (s->chan[ch].cmd & DCMD_FLOWSRC)
	167	s->chan[ch].src &= ~3;
	168	if (s->chan[ch].cmd & DCMD_FLOWTRG)
	169	s->chan[ch].dest &= ~3;
	170
	171	if (s->chan[ch].cmd & (DCMD_CMPEN \| DCMD_FLYBYS \| DCMD_FLYBYT))
	172	printf("%s: unsupported mode in channel %i\n", __FUNCTION__, ch);
	173
	174	if (s->chan[ch].cmd & DCMD_STARTIRQEN)
	175	s->chan[ch].state \|= DCSR_STARTINTR;
	176	}
	177
bc24a225	178	static void pxa2xx_dma_run(PXA2xxDMAState *s)
c1713132 AZ	179	{
	180	int c, srcinc, destinc;
	181	uint32_t n, size;
	182	uint32_t width;
	183	uint32_t length;
b55266b5	184	uint8_t buffer[32];
bc24a225	185	PXA2xxDMAChannel *ch;
c1713132 AZ	186
	187	if (s->running ++)
	188	return;
	189
	190	while (s->running) {
	191	s->running = 1;
	192	for (c = 0; c < s->channels; c ++) {
	193	ch = &s->chan[c];
	194
	195	while ((ch->state & DCSR_RUN) && !(ch->state & DCSR_STOPINTR)) {
	196	/* Test for pending requests */
	197	if ((ch->cmd & (DCMD_FLOWSRC \| DCMD_FLOWTRG)) && !ch->request)
	198	break;
	199
	200	length = ch->cmd & DCMD_LEN;
	201	size = DCMD_SIZE(ch->cmd);
	202	width = DCMD_WIDTH(ch->cmd);
	203
	204	srcinc = (ch->cmd & DCMD_INCSRCADDR) ? width : 0;
	205	destinc = (ch->cmd & DCMD_INCTRGADDR) ? width : 0;
	206
	207	while (length) {
	208	size = MIN(length, size);
	209
	210	for (n = 0; n < size; n += width) {
	211	cpu_physical_memory_read(ch->src, buffer + n, width);
	212	ch->src += srcinc;
	213	}
	214
	215	for (n = 0; n < size; n += width) {
	216	cpu_physical_memory_write(ch->dest, buffer + n, width);
	217	ch->dest += destinc;
	218	}
	219
	220	length -= size;
	221
	222	if ((ch->cmd & (DCMD_FLOWSRC \| DCMD_FLOWTRG)) &&
	223	!ch->request) {
	224	ch->state \|= DCSR_EORINT;
	225	if (ch->state & DCSR_EORSTOPEN)
	226	ch->state \|= DCSR_STOPINTR;
	227	if ((ch->state & DCSR_EORJMPEN) &&
	228	!(ch->state & DCSR_NODESCFETCH))
	229	pxa2xx_dma_descriptor_fetch(s, c);
	230	break;
	231	}
	232	}
	233
	234	ch->cmd = (ch->cmd & ~DCMD_LEN) \| length;
	235
	236	/* Is the transfer complete now? */
	237	if (!length) {
	238	if (ch->cmd & DCMD_ENDIRQEN)
	239	ch->state \|= DCSR_ENDINTR;
	240
	241	if ((ch->state & DCSR_NODESCFETCH) \|\|
	242	(ch->descr & DDADR_STOP) \|\|
	243	(ch->state & DCSR_EORSTOPEN)) {
	244	ch->state \|= DCSR_STOPINTR;
	245	ch->state &= ~DCSR_RUN;
	246
	247	break;
	248	}
	249
250	ch->state \|= DCSR_STOPINTR;
251	break;
252	}
253	}
254	}
255
256	s->running --;
257	}
258	}
259
a8170e5e	260	static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
00049a12	261	unsigned size)
c1713132	262	{
bc24a225	263	PXA2xxDMAState s = (PXA2xxDMAState ) opaque;
c1713132	264	unsigned int channel;
c1713132	265
00049a12 AK	266	if (size != 4) {
	267	hw_error("%s: Bad access width\n", __FUNCTION__);
	268	return 5;
	269	}
	270
c1713132 AZ	271	switch (offset) {
	272	case DRCMR64 ... DRCMR74:
	273	offset -= DRCMR64 - DRCMR0 - (64 << 2);
	274	/* Fall through */
	275	case DRCMR0 ... DRCMR63:
	276	channel = (offset - DRCMR0) >> 2;
	277	return s->req[channel];
	278
	279	case DRQSR0:
	280	case DRQSR1:
	281	case DRQSR2:
	282	return 0;
	283
	284	case DCSR0 ... DCSR31:
	285	channel = offset >> 2;
	286	if (s->chan[channel].request)
	287	return s->chan[channel].state \| DCSR_REQPEND;
	288	return s->chan[channel].state;
	289
	290	case DINT:
	291	return s->stopintr \| s->eorintr \| s->rasintr \|
	292	s->startintr \| s->endintr;
	293
	294	case DALGN:
	295	return s->align;
	296
	297	case DPCSR:
	298	return s->pio;
	299	}
	300
	301	if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) {
	302	channel = (offset - D_CH0) >> 4;
	303	switch ((offset & 0x0f) >> 2) {
	304	case DDADR:
	305	return s->chan[channel].descr;
	306	case DSADR:
	307	return s->chan[channel].src;
	308	case DTADR:
	309	return s->chan[channel].dest;
	310	case DCMD:
	311	return s->chan[channel].cmd;
	312	}
	313	}
	314
2ac71179	315	hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __FUNCTION__, offset);
c1713132 AZ	316	return 7;
	317	}
	318
a8170e5e	319	static void pxa2xx_dma_write(void *opaque, hwaddr offset,
00049a12	320	uint64_t value, unsigned size)
c1713132	321	{
bc24a225	322	PXA2xxDMAState s = (PXA2xxDMAState ) opaque;
c1713132	323	unsigned int channel;
c1713132	324
00049a12 AK	325	if (size != 4) {
	326	hw_error("%s: Bad access width\n", __FUNCTION__);
	327	return;
	328	}
	329
c1713132 AZ	330	switch (offset) {
	331	case DRCMR64 ... DRCMR74:
	332	offset -= DRCMR64 - DRCMR0 - (64 << 2);
	333	/* Fall through */
	334	case DRCMR0 ... DRCMR63:
	335	channel = (offset - DRCMR0) >> 2;
	336
	337	if (value & DRCMR_MAPVLD)
	338	if ((value & DRCMR_CHLNUM) > s->channels)
2ac71179	339	hw_error("%s: Bad DMA channel %i\n",
00049a12	340	__FUNCTION__, (unsigned)value & DRCMR_CHLNUM);
c1713132 AZ	341
	342	s->req[channel] = value;
	343	break;
	344
	345	case DRQSR0:
	346	case DRQSR1:
	347	case DRQSR2:
	348	/* Nothing to do */
	349	break;
	350
	351	case DCSR0 ... DCSR31:
	352	channel = offset >> 2;
	353	s->chan[channel].state &= 0x0000071f & ~(value &
	354	(DCSR_EORINT \| DCSR_ENDINTR \|
	355	DCSR_STARTINTR \| DCSR_BUSERRINTR));
	356	s->chan[channel].state \|= value & 0xfc800000;
	357
	358	if (s->chan[channel].state & DCSR_STOPIRQEN)
	359	s->chan[channel].state &= ~DCSR_STOPINTR;
	360
	361	if (value & DCSR_NODESCFETCH) {
	362	/* No-descriptor-fetch mode */
e1dad5a6 AZ	363	if (value & DCSR_RUN) {
e1dad5a6 AZ	364	s->chan[channel].state &= ~DCSR_STOPINTR;
c1713132	365	pxa2xx_dma_run(s);
e1dad5a6	366	}
c1713132 AZ	367	} else {
	368	/* Descriptor-fetch mode */
	369	if (value & DCSR_RUN) {
	370	s->chan[channel].state &= ~DCSR_STOPINTR;
	371	pxa2xx_dma_descriptor_fetch(s, channel);
	372	pxa2xx_dma_run(s);
	373	}
	374	}
	375
	376	/* Shouldn't matter as our DMA is synchronous. */
	377	if (!(value & (DCSR_RUN \| DCSR_MASKRUN)))
	378	s->chan[channel].state \|= DCSR_STOPINTR;
	379
	380	if (value & DCSR_CLRCMPST)
	381	s->chan[channel].state &= ~DCSR_CMPST;
	382	if (value & DCSR_SETCMPST)
	383	s->chan[channel].state \|= DCSR_CMPST;
	384
	385	pxa2xx_dma_update(s, channel);
	386	break;
	387
	388	case DALGN:
	389	s->align = value;
	390	break;
	391
	392	case DPCSR:
	393	s->pio = value & 0x80000001;
	394	break;
	395
	396	default:
	397	if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) {
	398	channel = (offset - D_CH0) >> 4;
	399	switch ((offset & 0x0f) >> 2) {
	400	case DDADR:
	401	s->chan[channel].descr = value;
	402	break;
	403	case DSADR:
	404	s->chan[channel].src = value;
	405	break;
	406	case DTADR:
	407	s->chan[channel].dest = value;
	408	break;
	409	case DCMD:
	410	s->chan[channel].cmd = value;
	411	break;
	412	default:
	413	goto fail;
	414	}
	415
	416	break;
	417	}
	418	fail:
2ac71179	419	hw_error("%s: Bad offset " TARGET_FMT_plx "\n", __FUNCTION__, offset);
c1713132 AZ	420	}
	421	}
	422
00049a12 AK	423	static const MemoryRegionOps pxa2xx_dma_ops = {
	424	.read = pxa2xx_dma_read,
	425	.write = pxa2xx_dma_write,
	426	.endianness = DEVICE_NATIVE_ENDIAN,
c1713132 AZ	427	};
c1713132 AZ	428
f114c826 AZ	429	static void pxa2xx_dma_request(void *opaque, int req_num, int on)
	430	{
	431	PXA2xxDMAState *s = opaque;
	432	int ch;
	433	if (req_num < 0 \|\| req_num >= PXA2XX_DMA_NUM_REQUESTS)
	434	hw_error("%s: Bad DMA request %i\n", __FUNCTION__, req_num);
	435
	436	if (!(s->req[req_num] & DRCMR_MAPVLD))
	437	return;
	438	ch = s->req[req_num] & DRCMR_CHLNUM;
	439
	440	if (!s->chan[ch].request && on)
	441	s->chan[ch].state \|= DCSR_RASINTR;
	442	else
	443	s->chan[ch].state &= ~DCSR_RASINTR;
	444	if (s->chan[ch].request && !on)
	445	s->chan[ch].state \|= DCSR_EORINT;
	446
	447	s->chan[ch].request = on;
	448	if (on) {
	449	pxa2xx_dma_run(s);
	450	pxa2xx_dma_update(s, ch);
	451	}
	452	}
aa941b94	453
c9796d71 XZ	454	static void pxa2xx_dma_init(Object *obj)
	455	{
	456	DeviceState *dev = DEVICE(obj);
	457	PXA2xxDMAState *s = PXA2XX_DMA(obj);
	458	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
	459
	460	memset(s->req, 0, sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS);
	461
	462	qdev_init_gpio_in(dev, pxa2xx_dma_request, PXA2XX_DMA_NUM_REQUESTS);
	463
	464	memory_region_init_io(&s->iomem, obj, &pxa2xx_dma_ops, s,
	465	"pxa2xx.dma", 0x00010000);
	466	sysbus_init_mmio(sbd, &s->iomem);
	467	sysbus_init_irq(sbd, &s->irq);
	468	}
	469
	470	static void pxa2xx_dma_realize(DeviceState dev, Error *errp)
c1713132	471	{
358cd7ac	472	PXA2xxDMAState *s = PXA2XX_DMA(dev);
00049a12	473	int i;
2115c019 AZ	474
2115c019 AZ	475	if (s->channels <= 0) {
c9796d71 XZ	476	error_setg(errp, "channels value invalid");
c9796d71 XZ	477	return;
2115c019	478	}
c1713132	479
1a13b272	480	s->chan = g_new0(PXA2xxDMAChannel, s->channels);
c1713132	481
c1713132 AZ	482	for (i = 0; i < s->channels; i ++)
c1713132 AZ	483	s->chan[i].state = DCSR_STOPINTR;
c1713132 AZ	484	}
c1713132 AZ	485
a8170e5e	486	DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq)
c1713132	487	{
2115c019 AZ	488	DeviceState *dev;
	489
	490	dev = qdev_create(NULL, "pxa2xx-dma");
	491	qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
	492	qdev_init_nofail(dev);
	493
1356b98d AF	494	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1356b98d AF	495	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
2115c019 AZ	496
2115c019 AZ	497	return dev;
c1713132 AZ	498	}
c1713132 AZ	499
a8170e5e	500	DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq)
c1713132	501	{
2115c019 AZ	502	DeviceState *dev;
	503
	504	dev = qdev_create(NULL, "pxa2xx-dma");
	505	qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
	506	qdev_init_nofail(dev);
	507
1356b98d AF	508	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1356b98d AF	509	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
2115c019 AZ	510
2115c019 AZ	511	return dev;
c1713132 AZ	512	}
c1713132 AZ	513
2115c019 AZ	514	static bool is_version_0(void *opaque, int version_id)
	515	{
	516	return version_id == 0;
	517	}
	518
	519	static VMStateDescription vmstate_pxa2xx_dma_chan = {
	520	.name = "pxa2xx_dma_chan",
	521	.version_id = 1,
	522	.minimum_version_id = 1,
2115c019	523	.fields = (VMStateField[]) {
a10394e1 MI	524	VMSTATE_UINT32(descr, PXA2xxDMAChannel),
	525	VMSTATE_UINT32(src, PXA2xxDMAChannel),
	526	VMSTATE_UINT32(dest, PXA2xxDMAChannel),
2115c019 AZ	527	VMSTATE_UINT32(cmd, PXA2xxDMAChannel),
	528	VMSTATE_UINT32(state, PXA2xxDMAChannel),
	529	VMSTATE_INT32(request, PXA2xxDMAChannel),
	530	VMSTATE_END_OF_LIST(),
	531	},
	532	};
	533
	534	static VMStateDescription vmstate_pxa2xx_dma = {
	535	.name = "pxa2xx_dma",
	536	.version_id = 1,
	537	.minimum_version_id = 0,
2115c019 AZ	538	.fields = (VMStateField[]) {
	539	VMSTATE_UNUSED_TEST(is_version_0, 4),
	540	VMSTATE_UINT32(stopintr, PXA2xxDMAState),
	541	VMSTATE_UINT32(eorintr, PXA2xxDMAState),
	542	VMSTATE_UINT32(rasintr, PXA2xxDMAState),
	543	VMSTATE_UINT32(startintr, PXA2xxDMAState),
	544	VMSTATE_UINT32(endintr, PXA2xxDMAState),
	545	VMSTATE_UINT32(align, PXA2xxDMAState),
	546	VMSTATE_UINT32(pio, PXA2xxDMAState),
	547	VMSTATE_BUFFER(req, PXA2xxDMAState),
	548	VMSTATE_STRUCT_VARRAY_POINTER_INT32(chan, PXA2xxDMAState, channels,
	549	vmstate_pxa2xx_dma_chan, PXA2xxDMAChannel),
	550	VMSTATE_END_OF_LIST(),
	551	},
	552	};
	553
999e12bb AL	554	static Property pxa2xx_dma_properties[] = {
	555	DEFINE_PROP_INT32("channels", PXA2xxDMAState, channels, -1),
	556	DEFINE_PROP_END_OF_LIST(),
	557	};
	558
	559	static void pxa2xx_dma_class_init(ObjectClass klass, void data)
	560	{
39bffca2	561	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	562
39bffca2 AL	563	dc->desc = "PXA2xx DMA controller";
	564	dc->vmsd = &vmstate_pxa2xx_dma;
	565	dc->props = pxa2xx_dma_properties;
c9796d71	566	dc->realize = pxa2xx_dma_realize;
999e12bb AL	567	}
999e12bb AL	568
8c43a6f0	569	static const TypeInfo pxa2xx_dma_info = {
358cd7ac	570	.name = TYPE_PXA2XX_DMA,
39bffca2 AL	571	.parent = TYPE_SYS_BUS_DEVICE,
39bffca2 AL	572	.instance_size = sizeof(PXA2xxDMAState),
c9796d71	573	.instance_init = pxa2xx_dma_init,
39bffca2	574	.class_init = pxa2xx_dma_class_init,
2115c019 AZ	575	};
2115c019 AZ	576
83f7d43a	577	static void pxa2xx_dma_register_types(void)
2115c019	578	{
39bffca2	579	type_register_static(&pxa2xx_dma_info);
2115c019	580	}
83f7d43a AF	581
83f7d43a AF	582	type_init(pxa2xx_dma_register_types)