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4ce7ff6e AJ |
1 | /* |
2 | * QEMU JAZZ RC4030 chipset | |
3 | * | |
d791d60f | 4 | * Copyright (c) 2007-2013 Hervé Poussineau |
4ce7ff6e AJ |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
0430891c | 25 | #include "qemu/osdep.h" |
d37eae6c | 26 | #include "qemu/units.h" |
64552b6b | 27 | #include "hw/irq.h" |
0d09e41a | 28 | #include "hw/mips/mips.h" |
d791d60f | 29 | #include "hw/sysbus.h" |
d6454270 | 30 | #include "migration/vmstate.h" |
3e80f690 | 31 | #include "qapi/error.h" |
1de7afc9 | 32 | #include "qemu/timer.h" |
03dd024f | 33 | #include "qemu/log.h" |
0b8fa32f | 34 | #include "qemu/module.h" |
a3d586f7 | 35 | #include "exec/address-spaces.h" |
95c357bc | 36 | #include "trace.h" |
db1015e9 | 37 | #include "qom/object.h" |
c6945b15 AJ |
38 | |
39 | /********************************************************/ | |
40 | /* rc4030 emulation */ | |
41 | ||
42 | typedef struct dma_pagetable_entry { | |
43 | int32_t frame; | |
44 | int32_t owner; | |
541dc0d4 | 45 | } QEMU_PACKED dma_pagetable_entry; |
c6945b15 AJ |
46 | |
47 | #define DMA_PAGESIZE 4096 | |
48 | #define DMA_REG_ENABLE 1 | |
49 | #define DMA_REG_COUNT 2 | |
50 | #define DMA_REG_ADDRESS 3 | |
51 | ||
52 | #define DMA_FLAG_ENABLE 0x0001 | |
53 | #define DMA_FLAG_MEM_TO_DEV 0x0002 | |
54 | #define DMA_FLAG_TC_INTR 0x0100 | |
55 | #define DMA_FLAG_MEM_INTR 0x0200 | |
56 | #define DMA_FLAG_ADDR_INTR 0x0400 | |
57 | ||
d791d60f | 58 | #define TYPE_RC4030 "rc4030" |
db1015e9 | 59 | typedef struct rc4030State rc4030State; |
8110fa1d EH |
60 | DECLARE_INSTANCE_CHECKER(rc4030State, RC4030, |
61 | TYPE_RC4030) | |
d791d60f | 62 | |
1221a474 AK |
63 | #define TYPE_RC4030_IOMMU_MEMORY_REGION "rc4030-iommu-memory-region" |
64 | ||
db1015e9 | 65 | struct rc4030State { |
a9e2d149 | 66 | |
d791d60f HP |
67 | SysBusDevice parent; |
68 | ||
4ce7ff6e | 69 | uint32_t config; /* 0x0000: RC4030 config register */ |
9ea0b7a1 | 70 | uint32_t revision; /* 0x0008: RC4030 Revision register */ |
4ce7ff6e AJ |
71 | uint32_t invalid_address_register; /* 0x0010: Invalid Address register */ |
72 | ||
73 | /* DMA */ | |
74 | uint32_t dma_regs[8][4]; | |
75 | uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */ | |
76 | uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */ | |
77 | ||
78 | /* cache */ | |
9ea0b7a1 | 79 | uint32_t cache_maint; /* 0x0030: Cache Maintenance */ |
4ce7ff6e AJ |
80 | uint32_t remote_failed_address; /* 0x0038: Remote Failed Address */ |
81 | uint32_t memory_failed_address; /* 0x0040: Memory Failed Address */ | |
82 | uint32_t cache_ptag; /* 0x0048: I/O Cache Physical Tag */ | |
83 | uint32_t cache_ltag; /* 0x0050: I/O Cache Logical Tag */ | |
84 | uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */ | |
4ce7ff6e | 85 | |
9ea0b7a1 | 86 | uint32_t nmi_interrupt; /* 0x0200: interrupt source */ |
dc6e3e1e | 87 | uint32_t memory_refresh_rate; /* 0x0210: memory refresh rate */ |
4ce7ff6e | 88 | uint32_t nvram_protect; /* 0x0220: NV ram protect register */ |
9ea0b7a1 | 89 | uint32_t rem_speed[16]; |
4ce7ff6e AJ |
90 | uint32_t imr_jazz; /* Local bus int enable mask */ |
91 | uint32_t isr_jazz; /* Local bus int source */ | |
92 | ||
93 | /* timer */ | |
94 | QEMUTimer *periodic_timer; | |
95 | uint32_t itr; /* Interval timer reload */ | |
96 | ||
4ce7ff6e AJ |
97 | qemu_irq timer_irq; |
98 | qemu_irq jazz_bus_irq; | |
3054434d | 99 | |
a3d586f7 | 100 | /* whole DMA memory region, root of DMA address space */ |
3df9d748 | 101 | IOMMUMemoryRegion dma_mr; |
a3d586f7 HP |
102 | AddressSpace dma_as; |
103 | ||
3054434d AK |
104 | MemoryRegion iomem_chipset; |
105 | MemoryRegion iomem_jazzio; | |
db1015e9 | 106 | }; |
4ce7ff6e AJ |
107 | |
108 | static void set_next_tick(rc4030State *s) | |
109 | { | |
b0f74c87 | 110 | uint32_t tm_hz; |
1b393b31 | 111 | qemu_irq_lower(s->timer_irq); |
4ce7ff6e | 112 | |
b0f74c87 | 113 | tm_hz = 1000 / (s->itr + 1); |
4ce7ff6e | 114 | |
bc72ad67 | 115 | timer_mod(s->periodic_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
73bcb24d | 116 | NANOSECONDS_PER_SECOND / tm_hz); |
4ce7ff6e AJ |
117 | } |
118 | ||
119 | /* called for accesses to rc4030 */ | |
b421f3f5 | 120 | static uint64_t rc4030_read(void *opaque, hwaddr addr, unsigned int size) |
4ce7ff6e AJ |
121 | { |
122 | rc4030State *s = opaque; | |
123 | uint32_t val; | |
124 | ||
125 | addr &= 0x3fff; | |
126 | switch (addr & ~0x3) { | |
127 | /* Global config register */ | |
128 | case 0x0000: | |
129 | val = s->config; | |
130 | break; | |
9ea0b7a1 AJ |
131 | /* Revision register */ |
132 | case 0x0008: | |
133 | val = s->revision; | |
134 | break; | |
4ce7ff6e AJ |
135 | /* Invalid Address register */ |
136 | case 0x0010: | |
137 | val = s->invalid_address_register; | |
138 | break; | |
139 | /* DMA transl. table base */ | |
140 | case 0x0018: | |
141 | val = s->dma_tl_base; | |
142 | break; | |
143 | /* DMA transl. table limit */ | |
144 | case 0x0020: | |
145 | val = s->dma_tl_limit; | |
146 | break; | |
147 | /* Remote Failed Address */ | |
148 | case 0x0038: | |
149 | val = s->remote_failed_address; | |
150 | break; | |
151 | /* Memory Failed Address */ | |
152 | case 0x0040: | |
153 | val = s->memory_failed_address; | |
154 | break; | |
155 | /* I/O Cache Byte Mask */ | |
156 | case 0x0058: | |
157 | val = s->cache_bmask; | |
158 | /* HACK */ | |
a9e2d149 | 159 | if (s->cache_bmask == (uint32_t)-1) { |
4ce7ff6e | 160 | s->cache_bmask = 0; |
a9e2d149 | 161 | } |
4ce7ff6e AJ |
162 | break; |
163 | /* Remote Speed Registers */ | |
164 | case 0x0070: | |
165 | case 0x0078: | |
166 | case 0x0080: | |
167 | case 0x0088: | |
168 | case 0x0090: | |
169 | case 0x0098: | |
170 | case 0x00a0: | |
171 | case 0x00a8: | |
172 | case 0x00b0: | |
173 | case 0x00b8: | |
174 | case 0x00c0: | |
175 | case 0x00c8: | |
176 | case 0x00d0: | |
177 | case 0x00d8: | |
178 | case 0x00e0: | |
9ea0b7a1 | 179 | case 0x00e8: |
4ce7ff6e AJ |
180 | val = s->rem_speed[(addr - 0x0070) >> 3]; |
181 | break; | |
182 | /* DMA channel base address */ | |
183 | case 0x0100: | |
184 | case 0x0108: | |
185 | case 0x0110: | |
186 | case 0x0118: | |
187 | case 0x0120: | |
188 | case 0x0128: | |
189 | case 0x0130: | |
190 | case 0x0138: | |
191 | case 0x0140: | |
192 | case 0x0148: | |
193 | case 0x0150: | |
194 | case 0x0158: | |
195 | case 0x0160: | |
196 | case 0x0168: | |
197 | case 0x0170: | |
198 | case 0x0178: | |
199 | case 0x0180: | |
200 | case 0x0188: | |
201 | case 0x0190: | |
202 | case 0x0198: | |
203 | case 0x01a0: | |
204 | case 0x01a8: | |
205 | case 0x01b0: | |
206 | case 0x01b8: | |
207 | case 0x01c0: | |
208 | case 0x01c8: | |
209 | case 0x01d0: | |
210 | case 0x01d8: | |
211 | case 0x01e0: | |
c6945b15 | 212 | case 0x01e8: |
4ce7ff6e AJ |
213 | case 0x01f0: |
214 | case 0x01f8: | |
215 | { | |
216 | int entry = (addr - 0x0100) >> 5; | |
217 | int idx = (addr & 0x1f) >> 3; | |
218 | val = s->dma_regs[entry][idx]; | |
219 | } | |
220 | break; | |
9ea0b7a1 AJ |
221 | /* Interrupt source */ |
222 | case 0x0200: | |
223 | val = s->nmi_interrupt; | |
224 | break; | |
225 | /* Error type */ | |
4ce7ff6e | 226 | case 0x0208: |
c6945b15 | 227 | val = 0; |
4ce7ff6e | 228 | break; |
dc6e3e1e | 229 | /* Memory refresh rate */ |
4ce7ff6e | 230 | case 0x0210: |
dc6e3e1e | 231 | val = s->memory_refresh_rate; |
4ce7ff6e AJ |
232 | break; |
233 | /* NV ram protect register */ | |
234 | case 0x0220: | |
235 | val = s->nvram_protect; | |
236 | break; | |
237 | /* Interval timer count */ | |
238 | case 0x0230: | |
c6945b15 | 239 | val = 0; |
4ce7ff6e AJ |
240 | qemu_irq_lower(s->timer_irq); |
241 | break; | |
9ea0b7a1 | 242 | /* EISA interrupt */ |
4ce7ff6e | 243 | case 0x0238: |
9ea0b7a1 | 244 | val = 7; /* FIXME: should be read from EISA controller */ |
4ce7ff6e AJ |
245 | break; |
246 | default: | |
95c357bc HP |
247 | qemu_log_mask(LOG_GUEST_ERROR, |
248 | "rc4030: invalid read at 0x%x", (int)addr); | |
4ce7ff6e AJ |
249 | val = 0; |
250 | break; | |
251 | } | |
252 | ||
4aa720f7 | 253 | if ((addr & ~3) != 0x230) { |
95c357bc | 254 | trace_rc4030_read(addr, val); |
4aa720f7 | 255 | } |
4ce7ff6e AJ |
256 | |
257 | return val; | |
258 | } | |
259 | ||
b421f3f5 HP |
260 | static void rc4030_write(void *opaque, hwaddr addr, uint64_t data, |
261 | unsigned int size) | |
4ce7ff6e AJ |
262 | { |
263 | rc4030State *s = opaque; | |
b421f3f5 | 264 | uint32_t val = data; |
4ce7ff6e AJ |
265 | addr &= 0x3fff; |
266 | ||
95c357bc | 267 | trace_rc4030_write(addr, val); |
4ce7ff6e AJ |
268 | |
269 | switch (addr & ~0x3) { | |
270 | /* Global config register */ | |
271 | case 0x0000: | |
272 | s->config = val; | |
273 | break; | |
274 | /* DMA transl. table base */ | |
275 | case 0x0018: | |
c627e752 | 276 | s->dma_tl_base = val; |
4ce7ff6e AJ |
277 | break; |
278 | /* DMA transl. table limit */ | |
279 | case 0x0020: | |
c627e752 | 280 | s->dma_tl_limit = val; |
4ce7ff6e | 281 | break; |
c6945b15 AJ |
282 | /* DMA transl. table invalidated */ |
283 | case 0x0028: | |
284 | break; | |
285 | /* Cache Maintenance */ | |
286 | case 0x0030: | |
9ea0b7a1 | 287 | s->cache_maint = val; |
c6945b15 | 288 | break; |
4ce7ff6e AJ |
289 | /* I/O Cache Physical Tag */ |
290 | case 0x0048: | |
291 | s->cache_ptag = val; | |
292 | break; | |
293 | /* I/O Cache Logical Tag */ | |
294 | case 0x0050: | |
295 | s->cache_ltag = val; | |
296 | break; | |
297 | /* I/O Cache Byte Mask */ | |
298 | case 0x0058: | |
299 | s->cache_bmask |= val; /* HACK */ | |
300 | break; | |
301 | /* I/O Cache Buffer Window */ | |
302 | case 0x0060: | |
4ce7ff6e AJ |
303 | /* HACK */ |
304 | if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) { | |
a8170e5e | 305 | hwaddr dest = s->cache_ptag & ~0x1; |
9ea0b7a1 | 306 | dest += (s->cache_maint & 0x3) << 3; |
54f7b4a3 | 307 | cpu_physical_memory_write(dest, &val, 4); |
4ce7ff6e AJ |
308 | } |
309 | break; | |
310 | /* Remote Speed Registers */ | |
311 | case 0x0070: | |
312 | case 0x0078: | |
313 | case 0x0080: | |
314 | case 0x0088: | |
315 | case 0x0090: | |
316 | case 0x0098: | |
317 | case 0x00a0: | |
318 | case 0x00a8: | |
319 | case 0x00b0: | |
320 | case 0x00b8: | |
321 | case 0x00c0: | |
322 | case 0x00c8: | |
323 | case 0x00d0: | |
324 | case 0x00d8: | |
325 | case 0x00e0: | |
9ea0b7a1 | 326 | case 0x00e8: |
4ce7ff6e AJ |
327 | s->rem_speed[(addr - 0x0070) >> 3] = val; |
328 | break; | |
329 | /* DMA channel base address */ | |
330 | case 0x0100: | |
331 | case 0x0108: | |
332 | case 0x0110: | |
333 | case 0x0118: | |
334 | case 0x0120: | |
335 | case 0x0128: | |
336 | case 0x0130: | |
337 | case 0x0138: | |
338 | case 0x0140: | |
339 | case 0x0148: | |
340 | case 0x0150: | |
341 | case 0x0158: | |
342 | case 0x0160: | |
343 | case 0x0168: | |
344 | case 0x0170: | |
345 | case 0x0178: | |
346 | case 0x0180: | |
347 | case 0x0188: | |
348 | case 0x0190: | |
349 | case 0x0198: | |
350 | case 0x01a0: | |
351 | case 0x01a8: | |
352 | case 0x01b0: | |
353 | case 0x01b8: | |
354 | case 0x01c0: | |
355 | case 0x01c8: | |
356 | case 0x01d0: | |
357 | case 0x01d8: | |
358 | case 0x01e0: | |
c6945b15 | 359 | case 0x01e8: |
4ce7ff6e AJ |
360 | case 0x01f0: |
361 | case 0x01f8: | |
362 | { | |
363 | int entry = (addr - 0x0100) >> 5; | |
364 | int idx = (addr & 0x1f) >> 3; | |
365 | s->dma_regs[entry][idx] = val; | |
366 | } | |
367 | break; | |
dc6e3e1e | 368 | /* Memory refresh rate */ |
4ce7ff6e | 369 | case 0x0210: |
dc6e3e1e | 370 | s->memory_refresh_rate = val; |
4ce7ff6e AJ |
371 | break; |
372 | /* Interval timer reload */ | |
373 | case 0x0228: | |
c0a3172f | 374 | s->itr = val & 0x01FF; |
4ce7ff6e AJ |
375 | qemu_irq_lower(s->timer_irq); |
376 | set_next_tick(s); | |
377 | break; | |
9ea0b7a1 AJ |
378 | /* EISA interrupt */ |
379 | case 0x0238: | |
380 | break; | |
4ce7ff6e | 381 | default: |
95c357bc HP |
382 | qemu_log_mask(LOG_GUEST_ERROR, |
383 | "rc4030: invalid write of 0x%02x at 0x%x", | |
384 | val, (int)addr); | |
4ce7ff6e AJ |
385 | break; |
386 | } | |
387 | } | |
388 | ||
3054434d | 389 | static const MemoryRegionOps rc4030_ops = { |
b421f3f5 HP |
390 | .read = rc4030_read, |
391 | .write = rc4030_write, | |
392 | .impl.min_access_size = 4, | |
393 | .impl.max_access_size = 4, | |
3054434d | 394 | .endianness = DEVICE_NATIVE_ENDIAN, |
4ce7ff6e AJ |
395 | }; |
396 | ||
397 | static void update_jazz_irq(rc4030State *s) | |
398 | { | |
399 | uint16_t pending; | |
400 | ||
401 | pending = s->isr_jazz & s->imr_jazz; | |
402 | ||
68fa5f55 | 403 | if (pending != 0) { |
4ce7ff6e | 404 | qemu_irq_raise(s->jazz_bus_irq); |
68fa5f55 | 405 | } else { |
4ce7ff6e | 406 | qemu_irq_lower(s->jazz_bus_irq); |
68fa5f55 | 407 | } |
4ce7ff6e AJ |
408 | } |
409 | ||
410 | static void rc4030_irq_jazz_request(void *opaque, int irq, int level) | |
411 | { | |
412 | rc4030State *s = opaque; | |
413 | ||
414 | if (level) { | |
415 | s->isr_jazz |= 1 << irq; | |
416 | } else { | |
417 | s->isr_jazz &= ~(1 << irq); | |
418 | } | |
419 | ||
420 | update_jazz_irq(s); | |
421 | } | |
422 | ||
423 | static void rc4030_periodic_timer(void *opaque) | |
424 | { | |
425 | rc4030State *s = opaque; | |
426 | ||
427 | set_next_tick(s); | |
428 | qemu_irq_raise(s->timer_irq); | |
429 | } | |
430 | ||
b421f3f5 | 431 | static uint64_t jazzio_read(void *opaque, hwaddr addr, unsigned int size) |
4ce7ff6e AJ |
432 | { |
433 | rc4030State *s = opaque; | |
434 | uint32_t val; | |
435 | uint32_t irq; | |
436 | addr &= 0xfff; | |
437 | ||
438 | switch (addr) { | |
c6945b15 | 439 | /* Local bus int source */ |
4ce7ff6e | 440 | case 0x00: { |
4ce7ff6e AJ |
441 | uint32_t pending = s->isr_jazz & s->imr_jazz; |
442 | val = 0; | |
443 | irq = 0; | |
444 | while (pending) { | |
445 | if (pending & 1) { | |
4ce7ff6e AJ |
446 | val = (irq + 1) << 2; |
447 | break; | |
448 | } | |
449 | irq++; | |
450 | pending >>= 1; | |
451 | } | |
452 | break; | |
453 | } | |
c6945b15 AJ |
454 | /* Local bus int enable mask */ |
455 | case 0x02: | |
456 | val = s->imr_jazz; | |
457 | break; | |
4ce7ff6e | 458 | default: |
95c357bc HP |
459 | qemu_log_mask(LOG_GUEST_ERROR, |
460 | "rc4030/jazzio: invalid read at 0x%x", (int)addr); | |
c6945b15 | 461 | val = 0; |
95c357bc | 462 | break; |
4ce7ff6e AJ |
463 | } |
464 | ||
95c357bc | 465 | trace_jazzio_read(addr, val); |
4ce7ff6e AJ |
466 | |
467 | return val; | |
468 | } | |
469 | ||
b421f3f5 HP |
470 | static void jazzio_write(void *opaque, hwaddr addr, uint64_t data, |
471 | unsigned int size) | |
4ce7ff6e AJ |
472 | { |
473 | rc4030State *s = opaque; | |
b421f3f5 | 474 | uint32_t val = data; |
4ce7ff6e AJ |
475 | addr &= 0xfff; |
476 | ||
95c357bc | 477 | trace_jazzio_write(addr, val); |
4ce7ff6e AJ |
478 | |
479 | switch (addr) { | |
480 | /* Local bus int enable mask */ | |
481 | case 0x02: | |
c6945b15 AJ |
482 | s->imr_jazz = val; |
483 | update_jazz_irq(s); | |
4ce7ff6e AJ |
484 | break; |
485 | default: | |
95c357bc HP |
486 | qemu_log_mask(LOG_GUEST_ERROR, |
487 | "rc4030/jazzio: invalid write of 0x%02x at 0x%x", | |
488 | val, (int)addr); | |
4ce7ff6e AJ |
489 | break; |
490 | } | |
491 | } | |
492 | ||
3054434d | 493 | static const MemoryRegionOps jazzio_ops = { |
b421f3f5 HP |
494 | .read = jazzio_read, |
495 | .write = jazzio_write, | |
496 | .impl.min_access_size = 2, | |
497 | .impl.max_access_size = 2, | |
3054434d | 498 | .endianness = DEVICE_NATIVE_ENDIAN, |
4ce7ff6e AJ |
499 | }; |
500 | ||
3df9d748 | 501 | static IOMMUTLBEntry rc4030_dma_translate(IOMMUMemoryRegion *iommu, hwaddr addr, |
2c91bcf2 | 502 | IOMMUAccessFlags flag, int iommu_idx) |
c627e752 HP |
503 | { |
504 | rc4030State *s = container_of(iommu, rc4030State, dma_mr); | |
505 | IOMMUTLBEntry ret = { | |
506 | .target_as = &address_space_memory, | |
507 | .iova = addr & ~(DMA_PAGESIZE - 1), | |
508 | .translated_addr = 0, | |
509 | .addr_mask = DMA_PAGESIZE - 1, | |
510 | .perm = IOMMU_NONE, | |
511 | }; | |
512 | uint64_t i, entry_address; | |
513 | dma_pagetable_entry entry; | |
514 | ||
515 | i = addr / DMA_PAGESIZE; | |
516 | if (i < s->dma_tl_limit / sizeof(entry)) { | |
517 | entry_address = (s->dma_tl_base & 0x7fffffff) + i * sizeof(entry); | |
518 | if (address_space_read(ret.target_as, entry_address, | |
b7cbebf2 PMD |
519 | MEMTXATTRS_UNSPECIFIED, &entry, sizeof(entry)) |
520 | == MEMTX_OK) { | |
c627e752 HP |
521 | ret.translated_addr = entry.frame & ~(DMA_PAGESIZE - 1); |
522 | ret.perm = IOMMU_RW; | |
523 | } | |
524 | } | |
525 | ||
526 | return ret; | |
527 | } | |
528 | ||
d791d60f | 529 | static void rc4030_reset(DeviceState *dev) |
4ce7ff6e | 530 | { |
d791d60f | 531 | rc4030State *s = RC4030(dev); |
4ce7ff6e AJ |
532 | int i; |
533 | ||
c6945b15 | 534 | s->config = 0x410; /* some boards seem to accept 0x104 too */ |
9ea0b7a1 | 535 | s->revision = 1; |
4ce7ff6e AJ |
536 | s->invalid_address_register = 0; |
537 | ||
538 | memset(s->dma_regs, 0, sizeof(s->dma_regs)); | |
4ce7ff6e AJ |
539 | |
540 | s->remote_failed_address = s->memory_failed_address = 0; | |
9ea0b7a1 | 541 | s->cache_maint = 0; |
4ce7ff6e | 542 | s->cache_ptag = s->cache_ltag = 0; |
9ea0b7a1 | 543 | s->cache_bmask = 0; |
4ce7ff6e | 544 | |
dc6e3e1e | 545 | s->memory_refresh_rate = 0x18186; |
4ce7ff6e | 546 | s->nvram_protect = 7; |
a9e2d149 | 547 | for (i = 0; i < 15; i++) { |
4ce7ff6e | 548 | s->rem_speed[i] = 7; |
a9e2d149 | 549 | } |
9ea0b7a1 AJ |
550 | s->imr_jazz = 0x10; /* XXX: required by firmware, but why? */ |
551 | s->isr_jazz = 0; | |
4ce7ff6e AJ |
552 | |
553 | s->itr = 0; | |
4ce7ff6e AJ |
554 | |
555 | qemu_irq_lower(s->timer_irq); | |
556 | qemu_irq_lower(s->jazz_bus_irq); | |
557 | } | |
558 | ||
73bfa8c0 | 559 | static int rc4030_post_load(void *opaque, int version_id) |
d5853c20 | 560 | { |
a9e2d149 | 561 | rc4030State *s = opaque; |
d5853c20 AJ |
562 | |
563 | set_next_tick(s); | |
564 | update_jazz_irq(s); | |
565 | ||
566 | return 0; | |
567 | } | |
568 | ||
73bfa8c0 DDAG |
569 | static const VMStateDescription vmstate_rc4030 = { |
570 | .name = "rc4030", | |
571 | .version_id = 3, | |
572 | .post_load = rc4030_post_load, | |
573 | .fields = (VMStateField []) { | |
574 | VMSTATE_UINT32(config, rc4030State), | |
575 | VMSTATE_UINT32(invalid_address_register, rc4030State), | |
576 | VMSTATE_UINT32_2DARRAY(dma_regs, rc4030State, 8, 4), | |
577 | VMSTATE_UINT32(dma_tl_base, rc4030State), | |
578 | VMSTATE_UINT32(dma_tl_limit, rc4030State), | |
579 | VMSTATE_UINT32(cache_maint, rc4030State), | |
580 | VMSTATE_UINT32(remote_failed_address, rc4030State), | |
581 | VMSTATE_UINT32(memory_failed_address, rc4030State), | |
582 | VMSTATE_UINT32(cache_ptag, rc4030State), | |
583 | VMSTATE_UINT32(cache_ltag, rc4030State), | |
584 | VMSTATE_UINT32(cache_bmask, rc4030State), | |
585 | VMSTATE_UINT32(memory_refresh_rate, rc4030State), | |
586 | VMSTATE_UINT32(nvram_protect, rc4030State), | |
587 | VMSTATE_UINT32_ARRAY(rem_speed, rc4030State, 16), | |
588 | VMSTATE_UINT32(imr_jazz, rc4030State), | |
589 | VMSTATE_UINT32(isr_jazz, rc4030State), | |
590 | VMSTATE_UINT32(itr, rc4030State), | |
591 | VMSTATE_END_OF_LIST() | |
592 | } | |
593 | }; | |
d5853c20 | 594 | |
68fa5f55 | 595 | static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, |
9842a9cf | 596 | int len, bool is_write) |
9ea0b7a1 AJ |
597 | { |
598 | rc4030State *s = opaque; | |
a8170e5e | 599 | hwaddr dma_addr; |
9ea0b7a1 AJ |
600 | int dev_to_mem; |
601 | ||
a9e2d149 AM |
602 | s->dma_regs[n][DMA_REG_ENABLE] &= |
603 | ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR); | |
9ea0b7a1 AJ |
604 | |
605 | /* Check DMA channel consistency */ | |
606 | dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1; | |
607 | if (!(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_ENABLE) || | |
608 | (is_write != dev_to_mem)) { | |
609 | s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR; | |
610 | s->nmi_interrupt |= 1 << n; | |
611 | return; | |
c6945b15 AJ |
612 | } |
613 | ||
9ea0b7a1 | 614 | /* Get start address and len */ |
a9e2d149 | 615 | if (len > s->dma_regs[n][DMA_REG_COUNT]) { |
9ea0b7a1 | 616 | len = s->dma_regs[n][DMA_REG_COUNT]; |
a9e2d149 | 617 | } |
9ea0b7a1 AJ |
618 | dma_addr = s->dma_regs[n][DMA_REG_ADDRESS]; |
619 | ||
620 | /* Read/write data at right place */ | |
a3d586f7 HP |
621 | address_space_rw(&s->dma_as, dma_addr, MEMTXATTRS_UNSPECIFIED, |
622 | buf, len, is_write); | |
9ea0b7a1 AJ |
623 | |
624 | s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_TC_INTR; | |
625 | s->dma_regs[n][DMA_REG_COUNT] -= len; | |
c6945b15 AJ |
626 | } |
627 | ||
628 | struct rc4030DMAState { | |
629 | void *opaque; | |
630 | int n; | |
631 | }; | |
632 | ||
68238a9e | 633 | void rc4030_dma_read(void *dma, uint8_t *buf, int len) |
c6945b15 AJ |
634 | { |
635 | rc4030_dma s = dma; | |
9842a9cf | 636 | rc4030_do_dma(s->opaque, s->n, buf, len, false); |
c6945b15 AJ |
637 | } |
638 | ||
68238a9e | 639 | void rc4030_dma_write(void *dma, uint8_t *buf, int len) |
c6945b15 AJ |
640 | { |
641 | rc4030_dma s = dma; | |
9842a9cf | 642 | rc4030_do_dma(s->opaque, s->n, buf, len, true); |
c6945b15 AJ |
643 | } |
644 | ||
645 | static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n) | |
646 | { | |
647 | rc4030_dma *s; | |
648 | struct rc4030DMAState *p; | |
649 | int i; | |
650 | ||
68fa5f55 FB |
651 | s = (rc4030_dma *)g_new0(rc4030_dma, n); |
652 | p = (struct rc4030DMAState *)g_new0(struct rc4030DMAState, n); | |
c6945b15 AJ |
653 | for (i = 0; i < n; i++) { |
654 | p->opaque = opaque; | |
655 | p->n = i; | |
656 | s[i] = p; | |
657 | p++; | |
658 | } | |
659 | return s; | |
660 | } | |
661 | ||
d791d60f | 662 | static void rc4030_initfn(Object *obj) |
4ce7ff6e | 663 | { |
d791d60f HP |
664 | DeviceState *dev = DEVICE(obj); |
665 | rc4030State *s = RC4030(obj); | |
666 | SysBusDevice *sysbus = SYS_BUS_DEVICE(obj); | |
4ce7ff6e | 667 | |
d791d60f | 668 | qdev_init_gpio_in(dev, rc4030_irq_jazz_request, 16); |
c6945b15 | 669 | |
d791d60f HP |
670 | sysbus_init_irq(sysbus, &s->timer_irq); |
671 | sysbus_init_irq(sysbus, &s->jazz_bus_irq); | |
4ce7ff6e | 672 | |
d791d60f HP |
673 | sysbus_init_mmio(sysbus, &s->iomem_chipset); |
674 | sysbus_init_mmio(sysbus, &s->iomem_jazzio); | |
675 | } | |
676 | ||
677 | static void rc4030_realize(DeviceState *dev, Error **errp) | |
678 | { | |
679 | rc4030State *s = RC4030(dev); | |
680 | Object *o = OBJECT(dev); | |
d791d60f HP |
681 | |
682 | s->periodic_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, | |
683 | rc4030_periodic_timer, s); | |
4ce7ff6e | 684 | |
a8457764 | 685 | memory_region_init_io(&s->iomem_chipset, o, &rc4030_ops, s, |
3054434d | 686 | "rc4030.chipset", 0x300); |
a8457764 | 687 | memory_region_init_io(&s->iomem_jazzio, o, &jazzio_ops, s, |
3054434d | 688 | "rc4030.jazzio", 0x00001000); |
4ce7ff6e | 689 | |
1221a474 AK |
690 | memory_region_init_iommu(&s->dma_mr, sizeof(s->dma_mr), |
691 | TYPE_RC4030_IOMMU_MEMORY_REGION, | |
d37eae6c | 692 | o, "rc4030.dma", 4 * GiB); |
3df9d748 | 693 | address_space_init(&s->dma_as, MEMORY_REGION(&s->dma_mr), "rc4030-dma"); |
d791d60f HP |
694 | } |
695 | ||
b69c3c21 | 696 | static void rc4030_unrealize(DeviceState *dev) |
d791d60f HP |
697 | { |
698 | rc4030State *s = RC4030(dev); | |
d791d60f HP |
699 | |
700 | timer_free(s->periodic_timer); | |
701 | ||
702 | address_space_destroy(&s->dma_as); | |
d791d60f | 703 | object_unparent(OBJECT(&s->dma_mr)); |
d791d60f HP |
704 | } |
705 | ||
706 | static void rc4030_class_init(ObjectClass *klass, void *class_data) | |
707 | { | |
708 | DeviceClass *dc = DEVICE_CLASS(klass); | |
709 | ||
710 | dc->realize = rc4030_realize; | |
711 | dc->unrealize = rc4030_unrealize; | |
712 | dc->reset = rc4030_reset; | |
73bfa8c0 | 713 | dc->vmsd = &vmstate_rc4030; |
d791d60f HP |
714 | } |
715 | ||
716 | static const TypeInfo rc4030_info = { | |
717 | .name = TYPE_RC4030, | |
718 | .parent = TYPE_SYS_BUS_DEVICE, | |
719 | .instance_size = sizeof(rc4030State), | |
720 | .instance_init = rc4030_initfn, | |
721 | .class_init = rc4030_class_init, | |
722 | }; | |
723 | ||
1221a474 AK |
724 | static void rc4030_iommu_memory_region_class_init(ObjectClass *klass, |
725 | void *data) | |
726 | { | |
727 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); | |
728 | ||
729 | imrc->translate = rc4030_dma_translate; | |
730 | } | |
731 | ||
732 | static const TypeInfo rc4030_iommu_memory_region_info = { | |
733 | .parent = TYPE_IOMMU_MEMORY_REGION, | |
734 | .name = TYPE_RC4030_IOMMU_MEMORY_REGION, | |
735 | .class_init = rc4030_iommu_memory_region_class_init, | |
736 | }; | |
737 | ||
d791d60f HP |
738 | static void rc4030_register_types(void) |
739 | { | |
740 | type_register_static(&rc4030_info); | |
1221a474 | 741 | type_register_static(&rc4030_iommu_memory_region_info); |
d791d60f HP |
742 | } |
743 | ||
744 | type_init(rc4030_register_types) | |
745 | ||
3df9d748 | 746 | DeviceState *rc4030_init(rc4030_dma **dmas, IOMMUMemoryRegion **dma_mr) |
d791d60f HP |
747 | { |
748 | DeviceState *dev; | |
749 | ||
3e80f690 | 750 | dev = qdev_new(TYPE_RC4030); |
3c6ef471 | 751 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
d791d60f HP |
752 | |
753 | *dmas = rc4030_allocate_dmas(dev, 4); | |
754 | *dma_mr = &RC4030(dev)->dma_mr; | |
755 | return dev; | |
4ce7ff6e | 756 | } |