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67e999be FB |
1 | /* |
2 | * QEMU Sparc32 DMA controller emulation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5 | * | |
6f57bbf4 AT |
6 | * Modifications: |
7 | * 2010-Feb-14 Artyom Tarasenko : reworked irq generation | |
8 | * | |
67e999be FB |
9 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
10 | * of this software and associated documentation files (the "Software"), to deal | |
11 | * in the Software without restriction, including without limitation the rights | |
12 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
13 | * copies of the Software, and to permit persons to whom the Software is | |
14 | * furnished to do so, subject to the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice shall be included in | |
17 | * all copies or substantial portions of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
23 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
24 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
25 | * THE SOFTWARE. | |
26 | */ | |
6f6260c7 | 27 | |
0430891c | 28 | #include "qemu/osdep.h" |
83c9f4ca | 29 | #include "hw/hw.h" |
0d09e41a PB |
30 | #include "hw/sparc/sparc32_dma.h" |
31 | #include "hw/sparc/sun4m.h" | |
83c9f4ca | 32 | #include "hw/sysbus.h" |
97bf4851 | 33 | #include "trace.h" |
67e999be FB |
34 | |
35 | /* | |
36 | * This is the DMA controller part of chip STP2000 (Master I/O), also | |
37 | * produced as NCR89C100. See | |
38 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt | |
39 | * and | |
40 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt | |
41 | */ | |
42 | ||
5aca8c3b BS |
43 | #define DMA_REGS 4 |
44 | #define DMA_SIZE (4 * sizeof(uint32_t)) | |
09723aa1 BS |
45 | /* We need the mask, because one instance of the device is not page |
46 | aligned (ledma, start address 0x0010) */ | |
47 | #define DMA_MASK (DMA_SIZE - 1) | |
e0087e61 | 48 | /* OBP says 0x20 bytes for ledma, the extras are aliased to espdma */ |
86d1c388 BB |
49 | #define DMA_ETH_SIZE (8 * sizeof(uint32_t)) |
50 | #define DMA_MAX_REG_OFFSET (2 * DMA_SIZE - 1) | |
67e999be FB |
51 | |
52 | #define DMA_VER 0xa0000000 | |
53 | #define DMA_INTR 1 | |
54 | #define DMA_INTREN 0x10 | |
55 | #define DMA_WRITE_MEM 0x100 | |
73d74342 | 56 | #define DMA_EN 0x200 |
67e999be | 57 | #define DMA_LOADED 0x04000000 |
5aca8c3b | 58 | #define DMA_DRAIN_FIFO 0x40 |
67e999be FB |
59 | #define DMA_RESET 0x80 |
60 | ||
65899fe3 AT |
61 | /* XXX SCSI and ethernet should have different read-only bit masks */ |
62 | #define DMA_CSR_RO_MASK 0xfe000007 | |
63 | ||
6a1f53f0 MCA |
64 | #define TYPE_SPARC32_DMA_DEVICE "sparc32-dma-device" |
65 | #define SPARC32_DMA_DEVICE(obj) OBJECT_CHECK(DMADeviceState, (obj), \ | |
66 | TYPE_SPARC32_DMA_DEVICE) | |
70cd8d4b | 67 | |
6a1f53f0 | 68 | typedef struct DMADeviceState DMADeviceState; |
67e999be | 69 | |
6a1f53f0 | 70 | struct DMADeviceState { |
70cd8d4b AF |
71 | SysBusDevice parent_obj; |
72 | ||
d6c5f066 | 73 | MemoryRegion iomem; |
67e999be | 74 | uint32_t dmaregs[DMA_REGS]; |
5aca8c3b | 75 | qemu_irq irq; |
2d069bab | 76 | void *iommu; |
73d74342 | 77 | qemu_irq gpio[2]; |
86d1c388 | 78 | uint32_t is_ledma; |
73d74342 BS |
79 | }; |
80 | ||
81 | enum { | |
82 | GPIO_RESET = 0, | |
83 | GPIO_DMA, | |
67e999be FB |
84 | }; |
85 | ||
9b94dc32 | 86 | /* Note: on sparc, the lance 16 bit bus is swapped */ |
a8170e5e | 87 | void ledma_memory_read(void *opaque, hwaddr addr, |
9b94dc32 | 88 | uint8_t *buf, int len, int do_bswap) |
67e999be | 89 | { |
6a1f53f0 | 90 | DMADeviceState *s = opaque; |
9b94dc32 | 91 | int i; |
67e999be | 92 | |
5aca8c3b | 93 | addr |= s->dmaregs[3]; |
97bf4851 | 94 | trace_ledma_memory_read(addr); |
9b94dc32 FB |
95 | if (do_bswap) { |
96 | sparc_iommu_memory_read(s->iommu, addr, buf, len); | |
97 | } else { | |
98 | addr &= ~1; | |
99 | len &= ~1; | |
100 | sparc_iommu_memory_read(s->iommu, addr, buf, len); | |
101 | for(i = 0; i < len; i += 2) { | |
102 | bswap16s((uint16_t *)(buf + i)); | |
103 | } | |
104 | } | |
67e999be FB |
105 | } |
106 | ||
a8170e5e | 107 | void ledma_memory_write(void *opaque, hwaddr addr, |
9b94dc32 | 108 | uint8_t *buf, int len, int do_bswap) |
67e999be | 109 | { |
6a1f53f0 | 110 | DMADeviceState *s = opaque; |
9b94dc32 FB |
111 | int l, i; |
112 | uint16_t tmp_buf[32]; | |
67e999be | 113 | |
5aca8c3b | 114 | addr |= s->dmaregs[3]; |
97bf4851 | 115 | trace_ledma_memory_write(addr); |
9b94dc32 FB |
116 | if (do_bswap) { |
117 | sparc_iommu_memory_write(s->iommu, addr, buf, len); | |
118 | } else { | |
119 | addr &= ~1; | |
120 | len &= ~1; | |
121 | while (len > 0) { | |
122 | l = len; | |
123 | if (l > sizeof(tmp_buf)) | |
124 | l = sizeof(tmp_buf); | |
125 | for(i = 0; i < l; i += 2) { | |
126 | tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i)); | |
127 | } | |
128 | sparc_iommu_memory_write(s->iommu, addr, (uint8_t *)tmp_buf, l); | |
129 | len -= l; | |
130 | buf += l; | |
131 | addr += l; | |
132 | } | |
133 | } | |
67e999be FB |
134 | } |
135 | ||
70c0de96 | 136 | static void dma_set_irq(void *opaque, int irq, int level) |
67e999be | 137 | { |
6a1f53f0 | 138 | DMADeviceState *s = opaque; |
70c0de96 | 139 | if (level) { |
70c0de96 | 140 | s->dmaregs[0] |= DMA_INTR; |
6f57bbf4 | 141 | if (s->dmaregs[0] & DMA_INTREN) { |
97bf4851 | 142 | trace_sparc32_dma_set_irq_raise(); |
6f57bbf4 AT |
143 | qemu_irq_raise(s->irq); |
144 | } | |
70c0de96 | 145 | } else { |
6f57bbf4 AT |
146 | if (s->dmaregs[0] & DMA_INTR) { |
147 | s->dmaregs[0] &= ~DMA_INTR; | |
148 | if (s->dmaregs[0] & DMA_INTREN) { | |
97bf4851 | 149 | trace_sparc32_dma_set_irq_lower(); |
6f57bbf4 AT |
150 | qemu_irq_lower(s->irq); |
151 | } | |
152 | } | |
70c0de96 | 153 | } |
67e999be FB |
154 | } |
155 | ||
156 | void espdma_memory_read(void *opaque, uint8_t *buf, int len) | |
157 | { | |
6a1f53f0 | 158 | DMADeviceState *s = opaque; |
67e999be | 159 | |
97bf4851 | 160 | trace_espdma_memory_read(s->dmaregs[1]); |
67e999be | 161 | sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len); |
67e999be FB |
162 | s->dmaregs[1] += len; |
163 | } | |
164 | ||
165 | void espdma_memory_write(void *opaque, uint8_t *buf, int len) | |
166 | { | |
6a1f53f0 | 167 | DMADeviceState *s = opaque; |
67e999be | 168 | |
97bf4851 | 169 | trace_espdma_memory_write(s->dmaregs[1]); |
67e999be | 170 | sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len); |
67e999be FB |
171 | s->dmaregs[1] += len; |
172 | } | |
173 | ||
a8170e5e | 174 | static uint64_t dma_mem_read(void *opaque, hwaddr addr, |
d6c5f066 | 175 | unsigned size) |
67e999be | 176 | { |
6a1f53f0 | 177 | DMADeviceState *s = opaque; |
67e999be FB |
178 | uint32_t saddr; |
179 | ||
86d1c388 | 180 | if (s->is_ledma && (addr > DMA_MAX_REG_OFFSET)) { |
e0087e61 BB |
181 | /* aliased to espdma, but we can't get there from here */ |
182 | /* buggy driver if using undocumented behavior, just return 0 */ | |
183 | trace_sparc32_dma_mem_readl(addr, 0); | |
184 | return 0; | |
86d1c388 | 185 | } |
09723aa1 | 186 | saddr = (addr & DMA_MASK) >> 2; |
97bf4851 | 187 | trace_sparc32_dma_mem_readl(addr, s->dmaregs[saddr]); |
67e999be FB |
188 | return s->dmaregs[saddr]; |
189 | } | |
190 | ||
a8170e5e | 191 | static void dma_mem_write(void *opaque, hwaddr addr, |
d6c5f066 | 192 | uint64_t val, unsigned size) |
67e999be | 193 | { |
6a1f53f0 | 194 | DMADeviceState *s = opaque; |
67e999be FB |
195 | uint32_t saddr; |
196 | ||
86d1c388 | 197 | if (s->is_ledma && (addr > DMA_MAX_REG_OFFSET)) { |
e0087e61 BB |
198 | /* aliased to espdma, but we can't get there from here */ |
199 | trace_sparc32_dma_mem_writel(addr, 0, val); | |
200 | return; | |
86d1c388 | 201 | } |
09723aa1 | 202 | saddr = (addr & DMA_MASK) >> 2; |
97bf4851 | 203 | trace_sparc32_dma_mem_writel(addr, s->dmaregs[saddr], val); |
67e999be FB |
204 | switch (saddr) { |
205 | case 0: | |
6f57bbf4 | 206 | if (val & DMA_INTREN) { |
65899fe3 | 207 | if (s->dmaregs[0] & DMA_INTR) { |
97bf4851 | 208 | trace_sparc32_dma_set_irq_raise(); |
6f57bbf4 AT |
209 | qemu_irq_raise(s->irq); |
210 | } | |
211 | } else { | |
212 | if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) { | |
97bf4851 | 213 | trace_sparc32_dma_set_irq_lower(); |
6f57bbf4 AT |
214 | qemu_irq_lower(s->irq); |
215 | } | |
d537cf6c | 216 | } |
67e999be | 217 | if (val & DMA_RESET) { |
73d74342 BS |
218 | qemu_irq_raise(s->gpio[GPIO_RESET]); |
219 | qemu_irq_lower(s->gpio[GPIO_RESET]); | |
5aca8c3b BS |
220 | } else if (val & DMA_DRAIN_FIFO) { |
221 | val &= ~DMA_DRAIN_FIFO; | |
67e999be | 222 | } else if (val == 0) |
5aca8c3b | 223 | val = DMA_DRAIN_FIFO; |
73d74342 BS |
224 | |
225 | if (val & DMA_EN && !(s->dmaregs[0] & DMA_EN)) { | |
97bf4851 | 226 | trace_sparc32_dma_enable_raise(); |
73d74342 BS |
227 | qemu_irq_raise(s->gpio[GPIO_DMA]); |
228 | } else if (!(val & DMA_EN) && !!(s->dmaregs[0] & DMA_EN)) { | |
97bf4851 | 229 | trace_sparc32_dma_enable_lower(); |
73d74342 BS |
230 | qemu_irq_lower(s->gpio[GPIO_DMA]); |
231 | } | |
232 | ||
65899fe3 | 233 | val &= ~DMA_CSR_RO_MASK; |
67e999be | 234 | val |= DMA_VER; |
65899fe3 | 235 | s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val; |
67e999be FB |
236 | break; |
237 | case 1: | |
238 | s->dmaregs[0] |= DMA_LOADED; | |
65899fe3 | 239 | /* fall through */ |
67e999be | 240 | default: |
65899fe3 | 241 | s->dmaregs[saddr] = val; |
67e999be FB |
242 | break; |
243 | } | |
67e999be FB |
244 | } |
245 | ||
d6c5f066 AK |
246 | static const MemoryRegionOps dma_mem_ops = { |
247 | .read = dma_mem_read, | |
248 | .write = dma_mem_write, | |
249 | .endianness = DEVICE_NATIVE_ENDIAN, | |
250 | .valid = { | |
251 | .min_access_size = 4, | |
252 | .max_access_size = 4, | |
253 | }, | |
67e999be FB |
254 | }; |
255 | ||
6a1f53f0 | 256 | static void sparc32_dma_device_reset(DeviceState *d) |
67e999be | 257 | { |
6a1f53f0 | 258 | DMADeviceState *s = SPARC32_DMA_DEVICE(d); |
67e999be | 259 | |
5aca8c3b | 260 | memset(s->dmaregs, 0, DMA_SIZE); |
67e999be | 261 | s->dmaregs[0] = DMA_VER; |
67e999be FB |
262 | } |
263 | ||
6a1f53f0 | 264 | static const VMStateDescription vmstate_sparc32_dma_device = { |
75c497dc BS |
265 | .name ="sparc32_dma", |
266 | .version_id = 2, | |
267 | .minimum_version_id = 2, | |
35d08458 | 268 | .fields = (VMStateField[]) { |
6a1f53f0 | 269 | VMSTATE_UINT32_ARRAY(dmaregs, DMADeviceState, DMA_REGS), |
75c497dc BS |
270 | VMSTATE_END_OF_LIST() |
271 | } | |
272 | }; | |
67e999be | 273 | |
6a1f53f0 | 274 | static void sparc32_dma_device_init(Object *obj) |
6f6260c7 | 275 | { |
8c612079 | 276 | DeviceState *dev = DEVICE(obj); |
6a1f53f0 | 277 | DMADeviceState *s = SPARC32_DMA_DEVICE(obj); |
8c612079 | 278 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
67e999be | 279 | |
70cd8d4b | 280 | sysbus_init_irq(sbd, &s->irq); |
67e999be | 281 | |
70cd8d4b | 282 | sysbus_init_mmio(sbd, &s->iomem); |
67e999be | 283 | |
70cd8d4b AF |
284 | qdev_init_gpio_in(dev, dma_set_irq, 1); |
285 | qdev_init_gpio_out(dev, s->gpio, 2); | |
8c612079 | 286 | } |
49ef6c90 | 287 | |
6a1f53f0 | 288 | static void sparc32_dma_device_realize(DeviceState *dev, Error **errp) |
8c612079 | 289 | { |
6a1f53f0 | 290 | DMADeviceState *s = SPARC32_DMA_DEVICE(dev); |
8c612079 XZ |
291 | int reg_size; |
292 | ||
293 | reg_size = s->is_ledma ? DMA_ETH_SIZE : DMA_SIZE; | |
294 | memory_region_init_io(&s->iomem, OBJECT(dev), &dma_mem_ops, s, | |
295 | "dma", reg_size); | |
6f6260c7 | 296 | } |
67e999be | 297 | |
6a1f53f0 MCA |
298 | static Property sparc32_dma_device_properties[] = { |
299 | DEFINE_PROP_PTR("iommu_opaque", DMADeviceState, iommu), | |
300 | DEFINE_PROP_UINT32("is_ledma", DMADeviceState, is_ledma, 0), | |
999e12bb AL |
301 | DEFINE_PROP_END_OF_LIST(), |
302 | }; | |
303 | ||
6a1f53f0 | 304 | static void sparc32_dma_device_class_init(ObjectClass *klass, void *data) |
999e12bb | 305 | { |
39bffca2 | 306 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 307 | |
6a1f53f0 MCA |
308 | dc->reset = sparc32_dma_device_reset; |
309 | dc->vmsd = &vmstate_sparc32_dma_device; | |
310 | dc->props = sparc32_dma_device_properties; | |
311 | dc->realize = sparc32_dma_device_realize; | |
1b111dc1 | 312 | /* Reason: pointer property "iommu_opaque" */ |
e90f2a8c | 313 | dc->user_creatable = false; |
999e12bb AL |
314 | } |
315 | ||
6a1f53f0 MCA |
316 | static const TypeInfo sparc32_dma_device_info = { |
317 | .name = TYPE_SPARC32_DMA_DEVICE, | |
39bffca2 | 318 | .parent = TYPE_SYS_BUS_DEVICE, |
6a1f53f0 MCA |
319 | .instance_size = sizeof(DMADeviceState), |
320 | .instance_init = sparc32_dma_device_init, | |
321 | .class_init = sparc32_dma_device_class_init, | |
6f6260c7 BS |
322 | }; |
323 | ||
83f7d43a | 324 | static void sparc32_dma_register_types(void) |
6f6260c7 | 325 | { |
6a1f53f0 | 326 | type_register_static(&sparc32_dma_device_info); |
67e999be | 327 | } |
6f6260c7 | 328 | |
83f7d43a | 329 | type_init(sparc32_dma_register_types) |