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Commit | Line | Data |
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67e999be FB |
1 | /* |
2 | * QEMU Sparc32 DMA controller emulation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5 | * | |
6f57bbf4 AT |
6 | * Modifications: |
7 | * 2010-Feb-14 Artyom Tarasenko : reworked irq generation | |
8 | * | |
67e999be FB |
9 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
10 | * of this software and associated documentation files (the "Software"), to deal | |
11 | * in the Software without restriction, including without limitation the rights | |
12 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
13 | * copies of the Software, and to permit persons to whom the Software is | |
14 | * furnished to do so, subject to the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice shall be included in | |
17 | * all copies or substantial portions of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
23 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
24 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
25 | * THE SOFTWARE. | |
26 | */ | |
6f6260c7 | 27 | |
0430891c | 28 | #include "qemu/osdep.h" |
64552b6b | 29 | #include "hw/irq.h" |
a27bd6c7 | 30 | #include "hw/qdev-properties.h" |
0d09e41a | 31 | #include "hw/sparc/sparc32_dma.h" |
1527f488 | 32 | #include "hw/sparc/sun4m_iommu.h" |
83c9f4ca | 33 | #include "hw/sysbus.h" |
d6454270 | 34 | #include "migration/vmstate.h" |
c413e9a4 | 35 | #include "sysemu/dma.h" |
6aa62ed6 | 36 | #include "qapi/error.h" |
0b8fa32f | 37 | #include "qemu/module.h" |
97bf4851 | 38 | #include "trace.h" |
67e999be FB |
39 | |
40 | /* | |
41 | * This is the DMA controller part of chip STP2000 (Master I/O), also | |
42 | * produced as NCR89C100. See | |
43 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt | |
44 | * and | |
45 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt | |
46 | */ | |
47 | ||
5aca8c3b | 48 | #define DMA_SIZE (4 * sizeof(uint32_t)) |
09723aa1 BS |
49 | /* We need the mask, because one instance of the device is not page |
50 | aligned (ledma, start address 0x0010) */ | |
51 | #define DMA_MASK (DMA_SIZE - 1) | |
e0087e61 | 52 | /* OBP says 0x20 bytes for ledma, the extras are aliased to espdma */ |
86d1c388 BB |
53 | #define DMA_ETH_SIZE (8 * sizeof(uint32_t)) |
54 | #define DMA_MAX_REG_OFFSET (2 * DMA_SIZE - 1) | |
67e999be FB |
55 | |
56 | #define DMA_VER 0xa0000000 | |
57 | #define DMA_INTR 1 | |
58 | #define DMA_INTREN 0x10 | |
59 | #define DMA_WRITE_MEM 0x100 | |
73d74342 | 60 | #define DMA_EN 0x200 |
67e999be | 61 | #define DMA_LOADED 0x04000000 |
5aca8c3b | 62 | #define DMA_DRAIN_FIFO 0x40 |
67e999be FB |
63 | #define DMA_RESET 0x80 |
64 | ||
65899fe3 AT |
65 | /* XXX SCSI and ethernet should have different read-only bit masks */ |
66 | #define DMA_CSR_RO_MASK 0xfe000007 | |
67 | ||
73d74342 BS |
68 | enum { |
69 | GPIO_RESET = 0, | |
70 | GPIO_DMA, | |
67e999be FB |
71 | }; |
72 | ||
9b94dc32 | 73 | /* Note: on sparc, the lance 16 bit bus is swapped */ |
a8170e5e | 74 | void ledma_memory_read(void *opaque, hwaddr addr, |
9b94dc32 | 75 | uint8_t *buf, int len, int do_bswap) |
67e999be | 76 | { |
6a1f53f0 | 77 | DMADeviceState *s = opaque; |
c413e9a4 | 78 | IOMMUState *is = (IOMMUState *)s->iommu; |
9b94dc32 | 79 | int i; |
67e999be | 80 | |
5aca8c3b | 81 | addr |= s->dmaregs[3]; |
331b7fc1 | 82 | trace_ledma_memory_read(addr, len); |
9b94dc32 | 83 | if (do_bswap) { |
ba06fe8a | 84 | dma_memory_read(&is->iommu_as, addr, buf, len, MEMTXATTRS_UNSPECIFIED); |
9b94dc32 FB |
85 | } else { |
86 | addr &= ~1; | |
87 | len &= ~1; | |
ba06fe8a | 88 | dma_memory_read(&is->iommu_as, addr, buf, len, MEMTXATTRS_UNSPECIFIED); |
9b94dc32 FB |
89 | for(i = 0; i < len; i += 2) { |
90 | bswap16s((uint16_t *)(buf + i)); | |
91 | } | |
92 | } | |
67e999be FB |
93 | } |
94 | ||
a8170e5e | 95 | void ledma_memory_write(void *opaque, hwaddr addr, |
9b94dc32 | 96 | uint8_t *buf, int len, int do_bswap) |
67e999be | 97 | { |
6a1f53f0 | 98 | DMADeviceState *s = opaque; |
c413e9a4 | 99 | IOMMUState *is = (IOMMUState *)s->iommu; |
9b94dc32 FB |
100 | int l, i; |
101 | uint16_t tmp_buf[32]; | |
67e999be | 102 | |
5aca8c3b | 103 | addr |= s->dmaregs[3]; |
331b7fc1 | 104 | trace_ledma_memory_write(addr, len); |
9b94dc32 | 105 | if (do_bswap) { |
ba06fe8a PMD |
106 | dma_memory_write(&is->iommu_as, addr, buf, len, |
107 | MEMTXATTRS_UNSPECIFIED); | |
9b94dc32 FB |
108 | } else { |
109 | addr &= ~1; | |
110 | len &= ~1; | |
111 | while (len > 0) { | |
112 | l = len; | |
113 | if (l > sizeof(tmp_buf)) | |
114 | l = sizeof(tmp_buf); | |
115 | for(i = 0; i < l; i += 2) { | |
116 | tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i)); | |
117 | } | |
ba06fe8a PMD |
118 | dma_memory_write(&is->iommu_as, addr, tmp_buf, l, |
119 | MEMTXATTRS_UNSPECIFIED); | |
9b94dc32 FB |
120 | len -= l; |
121 | buf += l; | |
122 | addr += l; | |
123 | } | |
124 | } | |
67e999be FB |
125 | } |
126 | ||
70c0de96 | 127 | static void dma_set_irq(void *opaque, int irq, int level) |
67e999be | 128 | { |
6a1f53f0 | 129 | DMADeviceState *s = opaque; |
70c0de96 | 130 | if (level) { |
70c0de96 | 131 | s->dmaregs[0] |= DMA_INTR; |
6f57bbf4 | 132 | if (s->dmaregs[0] & DMA_INTREN) { |
97bf4851 | 133 | trace_sparc32_dma_set_irq_raise(); |
6f57bbf4 AT |
134 | qemu_irq_raise(s->irq); |
135 | } | |
70c0de96 | 136 | } else { |
6f57bbf4 AT |
137 | if (s->dmaregs[0] & DMA_INTR) { |
138 | s->dmaregs[0] &= ~DMA_INTR; | |
139 | if (s->dmaregs[0] & DMA_INTREN) { | |
97bf4851 | 140 | trace_sparc32_dma_set_irq_lower(); |
6f57bbf4 AT |
141 | qemu_irq_lower(s->irq); |
142 | } | |
143 | } | |
70c0de96 | 144 | } |
67e999be FB |
145 | } |
146 | ||
147 | void espdma_memory_read(void *opaque, uint8_t *buf, int len) | |
148 | { | |
6a1f53f0 | 149 | DMADeviceState *s = opaque; |
c413e9a4 | 150 | IOMMUState *is = (IOMMUState *)s->iommu; |
67e999be | 151 | |
331b7fc1 | 152 | trace_espdma_memory_read(s->dmaregs[1], len); |
ba06fe8a PMD |
153 | dma_memory_read(&is->iommu_as, s->dmaregs[1], buf, len, |
154 | MEMTXATTRS_UNSPECIFIED); | |
67e999be FB |
155 | s->dmaregs[1] += len; |
156 | } | |
157 | ||
158 | void espdma_memory_write(void *opaque, uint8_t *buf, int len) | |
159 | { | |
6a1f53f0 | 160 | DMADeviceState *s = opaque; |
c413e9a4 | 161 | IOMMUState *is = (IOMMUState *)s->iommu; |
67e999be | 162 | |
331b7fc1 | 163 | trace_espdma_memory_write(s->dmaregs[1], len); |
ba06fe8a PMD |
164 | dma_memory_write(&is->iommu_as, s->dmaregs[1], buf, len, |
165 | MEMTXATTRS_UNSPECIFIED); | |
67e999be FB |
166 | s->dmaregs[1] += len; |
167 | } | |
168 | ||
a8170e5e | 169 | static uint64_t dma_mem_read(void *opaque, hwaddr addr, |
d6c5f066 | 170 | unsigned size) |
67e999be | 171 | { |
6a1f53f0 | 172 | DMADeviceState *s = opaque; |
67e999be FB |
173 | uint32_t saddr; |
174 | ||
09723aa1 | 175 | saddr = (addr & DMA_MASK) >> 2; |
97bf4851 | 176 | trace_sparc32_dma_mem_readl(addr, s->dmaregs[saddr]); |
67e999be FB |
177 | return s->dmaregs[saddr]; |
178 | } | |
179 | ||
a8170e5e | 180 | static void dma_mem_write(void *opaque, hwaddr addr, |
d6c5f066 | 181 | uint64_t val, unsigned size) |
67e999be | 182 | { |
6a1f53f0 | 183 | DMADeviceState *s = opaque; |
67e999be FB |
184 | uint32_t saddr; |
185 | ||
09723aa1 | 186 | saddr = (addr & DMA_MASK) >> 2; |
97bf4851 | 187 | trace_sparc32_dma_mem_writel(addr, s->dmaregs[saddr], val); |
67e999be FB |
188 | switch (saddr) { |
189 | case 0: | |
6f57bbf4 | 190 | if (val & DMA_INTREN) { |
65899fe3 | 191 | if (s->dmaregs[0] & DMA_INTR) { |
97bf4851 | 192 | trace_sparc32_dma_set_irq_raise(); |
6f57bbf4 AT |
193 | qemu_irq_raise(s->irq); |
194 | } | |
195 | } else { | |
196 | if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) { | |
97bf4851 | 197 | trace_sparc32_dma_set_irq_lower(); |
6f57bbf4 AT |
198 | qemu_irq_lower(s->irq); |
199 | } | |
d537cf6c | 200 | } |
67e999be | 201 | if (val & DMA_RESET) { |
73d74342 BS |
202 | qemu_irq_raise(s->gpio[GPIO_RESET]); |
203 | qemu_irq_lower(s->gpio[GPIO_RESET]); | |
5aca8c3b BS |
204 | } else if (val & DMA_DRAIN_FIFO) { |
205 | val &= ~DMA_DRAIN_FIFO; | |
67e999be | 206 | } else if (val == 0) |
5aca8c3b | 207 | val = DMA_DRAIN_FIFO; |
73d74342 BS |
208 | |
209 | if (val & DMA_EN && !(s->dmaregs[0] & DMA_EN)) { | |
97bf4851 | 210 | trace_sparc32_dma_enable_raise(); |
73d74342 BS |
211 | qemu_irq_raise(s->gpio[GPIO_DMA]); |
212 | } else if (!(val & DMA_EN) && !!(s->dmaregs[0] & DMA_EN)) { | |
97bf4851 | 213 | trace_sparc32_dma_enable_lower(); |
73d74342 BS |
214 | qemu_irq_lower(s->gpio[GPIO_DMA]); |
215 | } | |
216 | ||
65899fe3 | 217 | val &= ~DMA_CSR_RO_MASK; |
67e999be | 218 | val |= DMA_VER; |
65899fe3 | 219 | s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val; |
67e999be FB |
220 | break; |
221 | case 1: | |
222 | s->dmaregs[0] |= DMA_LOADED; | |
65899fe3 | 223 | /* fall through */ |
67e999be | 224 | default: |
65899fe3 | 225 | s->dmaregs[saddr] = val; |
67e999be FB |
226 | break; |
227 | } | |
67e999be FB |
228 | } |
229 | ||
d6c5f066 AK |
230 | static const MemoryRegionOps dma_mem_ops = { |
231 | .read = dma_mem_read, | |
232 | .write = dma_mem_write, | |
233 | .endianness = DEVICE_NATIVE_ENDIAN, | |
234 | .valid = { | |
235 | .min_access_size = 4, | |
236 | .max_access_size = 4, | |
237 | }, | |
67e999be FB |
238 | }; |
239 | ||
6a1f53f0 | 240 | static void sparc32_dma_device_reset(DeviceState *d) |
67e999be | 241 | { |
6a1f53f0 | 242 | DMADeviceState *s = SPARC32_DMA_DEVICE(d); |
67e999be | 243 | |
5aca8c3b | 244 | memset(s->dmaregs, 0, DMA_SIZE); |
67e999be | 245 | s->dmaregs[0] = DMA_VER; |
67e999be FB |
246 | } |
247 | ||
6a1f53f0 | 248 | static const VMStateDescription vmstate_sparc32_dma_device = { |
75c497dc BS |
249 | .name ="sparc32_dma", |
250 | .version_id = 2, | |
251 | .minimum_version_id = 2, | |
63e6b564 | 252 | .fields = (const VMStateField[]) { |
6a1f53f0 | 253 | VMSTATE_UINT32_ARRAY(dmaregs, DMADeviceState, DMA_REGS), |
75c497dc BS |
254 | VMSTATE_END_OF_LIST() |
255 | } | |
256 | }; | |
67e999be | 257 | |
6a1f53f0 | 258 | static void sparc32_dma_device_init(Object *obj) |
6f6260c7 | 259 | { |
8c612079 | 260 | DeviceState *dev = DEVICE(obj); |
6a1f53f0 | 261 | DMADeviceState *s = SPARC32_DMA_DEVICE(obj); |
8c612079 | 262 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
67e999be | 263 | |
70cd8d4b | 264 | sysbus_init_irq(sbd, &s->irq); |
67e999be | 265 | |
70cd8d4b | 266 | sysbus_init_mmio(sbd, &s->iomem); |
67e999be | 267 | |
f542ad03 MCA |
268 | object_property_add_link(OBJECT(dev), "iommu", TYPE_SUN4M_IOMMU, |
269 | (Object **) &s->iommu, | |
270 | qdev_prop_allow_set_link_before_realize, | |
d2623129 | 271 | 0); |
f542ad03 | 272 | |
70cd8d4b AF |
273 | qdev_init_gpio_in(dev, dma_set_irq, 1); |
274 | qdev_init_gpio_out(dev, s->gpio, 2); | |
8c612079 | 275 | } |
49ef6c90 | 276 | |
6a1f53f0 | 277 | static void sparc32_dma_device_class_init(ObjectClass *klass, void *data) |
999e12bb | 278 | { |
39bffca2 | 279 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 280 | |
6a1f53f0 MCA |
281 | dc->reset = sparc32_dma_device_reset; |
282 | dc->vmsd = &vmstate_sparc32_dma_device; | |
999e12bb AL |
283 | } |
284 | ||
6a1f53f0 MCA |
285 | static const TypeInfo sparc32_dma_device_info = { |
286 | .name = TYPE_SPARC32_DMA_DEVICE, | |
39bffca2 | 287 | .parent = TYPE_SYS_BUS_DEVICE, |
52d39e5b | 288 | .abstract = true, |
6a1f53f0 MCA |
289 | .instance_size = sizeof(DMADeviceState), |
290 | .instance_init = sparc32_dma_device_init, | |
291 | .class_init = sparc32_dma_device_class_init, | |
6f6260c7 BS |
292 | }; |
293 | ||
52d39e5b MCA |
294 | static void sparc32_espdma_device_init(Object *obj) |
295 | { | |
296 | DMADeviceState *s = SPARC32_DMA_DEVICE(obj); | |
d19265ea | 297 | ESPDMADeviceState *es = SPARC32_ESPDMA_DEVICE(obj); |
52d39e5b MCA |
298 | |
299 | memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s, | |
300 | "espdma-mmio", DMA_SIZE); | |
d19265ea | 301 | |
84fbefed | 302 | object_initialize_child(obj, "esp", &es->esp, TYPE_SYSBUS_ESP); |
52d39e5b MCA |
303 | } |
304 | ||
7f773ff5 MCA |
305 | static void sparc32_espdma_device_realize(DeviceState *dev, Error **errp) |
306 | { | |
d19265ea | 307 | ESPDMADeviceState *es = SPARC32_ESPDMA_DEVICE(dev); |
84fbefed | 308 | SysBusESPState *sysbus = SYSBUS_ESP(&es->esp); |
d19265ea MCA |
309 | ESPState *esp = &sysbus->esp; |
310 | ||
7f773ff5 MCA |
311 | esp->dma_memory_read = espdma_memory_read; |
312 | esp->dma_memory_write = espdma_memory_write; | |
313 | esp->dma_opaque = SPARC32_DMA_DEVICE(dev); | |
314 | sysbus->it_shift = 2; | |
315 | esp->dma_enabled = 1; | |
d19265ea | 316 | sysbus_realize(SYS_BUS_DEVICE(sysbus), &error_fatal); |
7f773ff5 MCA |
317 | } |
318 | ||
319 | static void sparc32_espdma_device_class_init(ObjectClass *klass, void *data) | |
320 | { | |
321 | DeviceClass *dc = DEVICE_CLASS(klass); | |
322 | ||
323 | dc->realize = sparc32_espdma_device_realize; | |
324 | } | |
325 | ||
52d39e5b MCA |
326 | static const TypeInfo sparc32_espdma_device_info = { |
327 | .name = TYPE_SPARC32_ESPDMA_DEVICE, | |
328 | .parent = TYPE_SPARC32_DMA_DEVICE, | |
329 | .instance_size = sizeof(ESPDMADeviceState), | |
330 | .instance_init = sparc32_espdma_device_init, | |
7f773ff5 | 331 | .class_init = sparc32_espdma_device_class_init, |
52d39e5b MCA |
332 | }; |
333 | ||
334 | static void sparc32_ledma_device_init(Object *obj) | |
335 | { | |
336 | DMADeviceState *s = SPARC32_DMA_DEVICE(obj); | |
bce83ed9 | 337 | LEDMADeviceState *ls = SPARC32_LEDMA_DEVICE(obj); |
52d39e5b MCA |
338 | |
339 | memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s, | |
4ca3d368 | 340 | "ledma-mmio", DMA_SIZE); |
bce83ed9 MCA |
341 | |
342 | object_initialize_child(obj, "lance", &ls->lance, TYPE_LANCE); | |
52d39e5b MCA |
343 | } |
344 | ||
e6ca02a4 MCA |
345 | static void sparc32_ledma_device_realize(DeviceState *dev, Error **errp) |
346 | { | |
bce83ed9 MCA |
347 | LEDMADeviceState *s = SPARC32_LEDMA_DEVICE(dev); |
348 | SysBusPCNetState *lance = SYSBUS_PCNET(&s->lance); | |
e6ca02a4 | 349 | |
bce83ed9 MCA |
350 | object_property_set_link(OBJECT(lance), "dma", OBJECT(dev), &error_abort); |
351 | sysbus_realize(SYS_BUS_DEVICE(lance), &error_fatal); | |
e6ca02a4 MCA |
352 | } |
353 | ||
354 | static void sparc32_ledma_device_class_init(ObjectClass *klass, void *data) | |
355 | { | |
356 | DeviceClass *dc = DEVICE_CLASS(klass); | |
357 | ||
358 | dc->realize = sparc32_ledma_device_realize; | |
359 | } | |
360 | ||
52d39e5b MCA |
361 | static const TypeInfo sparc32_ledma_device_info = { |
362 | .name = TYPE_SPARC32_LEDMA_DEVICE, | |
363 | .parent = TYPE_SPARC32_DMA_DEVICE, | |
364 | .instance_size = sizeof(LEDMADeviceState), | |
365 | .instance_init = sparc32_ledma_device_init, | |
e6ca02a4 | 366 | .class_init = sparc32_ledma_device_class_init, |
52d39e5b MCA |
367 | }; |
368 | ||
6aa62ed6 MCA |
369 | static void sparc32_dma_realize(DeviceState *dev, Error **errp) |
370 | { | |
371 | SPARC32DMAState *s = SPARC32_DMA(dev); | |
372 | DeviceState *espdma, *esp, *ledma, *lance; | |
373 | SysBusDevice *sbd; | |
374 | Object *iommu; | |
375 | ||
376 | iommu = object_resolve_path_type("", TYPE_SUN4M_IOMMU, NULL); | |
377 | if (!iommu) { | |
378 | error_setg(errp, "unable to locate sun4m IOMMU device"); | |
379 | return; | |
380 | } | |
381 | ||
1f10fd53 | 382 | espdma = DEVICE(&s->espdma); |
5325cc34 | 383 | object_property_set_link(OBJECT(espdma), "iommu", iommu, &error_abort); |
1f10fd53 | 384 | sysbus_realize(SYS_BUS_DEVICE(espdma), &error_fatal); |
6aa62ed6 MCA |
385 | |
386 | esp = DEVICE(object_resolve_path_component(OBJECT(espdma), "esp")); | |
387 | sbd = SYS_BUS_DEVICE(esp); | |
388 | sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(espdma, 0)); | |
389 | qdev_connect_gpio_out(espdma, 0, qdev_get_gpio_in(esp, 0)); | |
390 | qdev_connect_gpio_out(espdma, 1, qdev_get_gpio_in(esp, 1)); | |
391 | ||
392 | sbd = SYS_BUS_DEVICE(espdma); | |
393 | memory_region_add_subregion(&s->dmamem, 0x0, | |
394 | sysbus_mmio_get_region(sbd, 0)); | |
395 | ||
1f10fd53 | 396 | ledma = DEVICE(&s->ledma); |
5325cc34 | 397 | object_property_set_link(OBJECT(ledma), "iommu", iommu, &error_abort); |
1f10fd53 | 398 | sysbus_realize(SYS_BUS_DEVICE(ledma), &error_fatal); |
6aa62ed6 MCA |
399 | |
400 | lance = DEVICE(object_resolve_path_component(OBJECT(ledma), "lance")); | |
401 | sbd = SYS_BUS_DEVICE(lance); | |
402 | sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(ledma, 0)); | |
403 | qdev_connect_gpio_out(ledma, 0, qdev_get_gpio_in(lance, 0)); | |
404 | ||
405 | sbd = SYS_BUS_DEVICE(ledma); | |
406 | memory_region_add_subregion(&s->dmamem, 0x10, | |
407 | sysbus_mmio_get_region(sbd, 0)); | |
4ca3d368 MCA |
408 | |
409 | /* Add ledma alias to handle SunOS 5.7 - Solaris 9 invalid access bug */ | |
410 | memory_region_init_alias(&s->ledma_alias, OBJECT(dev), "ledma-alias", | |
411 | sysbus_mmio_get_region(sbd, 0), 0x4, 0x4); | |
412 | memory_region_add_subregion(&s->dmamem, 0x20, &s->ledma_alias); | |
6aa62ed6 MCA |
413 | } |
414 | ||
415 | static void sparc32_dma_init(Object *obj) | |
416 | { | |
417 | SPARC32DMAState *s = SPARC32_DMA(obj); | |
418 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
419 | ||
420 | memory_region_init(&s->dmamem, OBJECT(s), "dma", DMA_SIZE + DMA_ETH_SIZE); | |
421 | sysbus_init_mmio(sbd, &s->dmamem); | |
1f10fd53 MCA |
422 | |
423 | object_initialize_child(obj, "espdma", &s->espdma, | |
424 | TYPE_SPARC32_ESPDMA_DEVICE); | |
425 | object_initialize_child(obj, "ledma", &s->ledma, | |
426 | TYPE_SPARC32_LEDMA_DEVICE); | |
6aa62ed6 MCA |
427 | } |
428 | ||
429 | static void sparc32_dma_class_init(ObjectClass *klass, void *data) | |
430 | { | |
431 | DeviceClass *dc = DEVICE_CLASS(klass); | |
432 | ||
433 | dc->realize = sparc32_dma_realize; | |
434 | } | |
435 | ||
436 | static const TypeInfo sparc32_dma_info = { | |
437 | .name = TYPE_SPARC32_DMA, | |
438 | .parent = TYPE_SYS_BUS_DEVICE, | |
439 | .instance_size = sizeof(SPARC32DMAState), | |
440 | .instance_init = sparc32_dma_init, | |
441 | .class_init = sparc32_dma_class_init, | |
442 | }; | |
443 | ||
444 | ||
83f7d43a | 445 | static void sparc32_dma_register_types(void) |
6f6260c7 | 446 | { |
6a1f53f0 | 447 | type_register_static(&sparc32_dma_device_info); |
52d39e5b MCA |
448 | type_register_static(&sparc32_espdma_device_info); |
449 | type_register_static(&sparc32_ledma_device_info); | |
6aa62ed6 | 450 | type_register_static(&sparc32_dma_info); |
67e999be | 451 | } |
6f6260c7 | 452 | |
83f7d43a | 453 | type_init(sparc32_dma_register_types) |