[mirror_qemu.git] / hw / dma.c

/*
 * QEMU DMA emulation
 * 
 * Copyright (c) 2003 Vassili Karpov (malc)
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

#define log(...) fprintf (stderr, "dma: " __VA_ARGS__)
#ifdef DEBUG_DMA
#define lwarn(...) fprintf (stderr, "dma: " __VA_ARGS__)
#define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__)
#define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__)
#else
#define lwarn(...)
#define linfo(...)
#define ldebug(...)
#endif

#define LENOFA(a) ((int) (sizeof(a)/sizeof(a[0])))

struct dma_regs {
    int now[2];
    uint16_t base[2];
    uint8_t mode;
    uint8_t page;
    uint8_t dack;
    uint8_t eop;
    DMA_transfer_handler transfer_handler;
    void *opaque;
};

#define ADDR 0
#define COUNT 1

static struct dma_cont {
    uint8_t status;
    uint8_t command;
    uint8_t mask;
    uint8_t flip_flop;
    int dshift;
    struct dma_regs regs[4];
} dma_controllers[2];

enum {
  CMD_MEMORY_TO_MEMORY = 0x01,
  CMD_FIXED_ADDRESS    = 0x02,
  CMD_BLOCK_CONTROLLER = 0x04,
  CMD_COMPRESSED_TIME  = 0x08,
  CMD_CYCLIC_PRIORITY  = 0x10,
  CMD_EXTENDED_WRITE   = 0x20,
  CMD_LOW_DREQ         = 0x40,
  CMD_LOW_DACK         = 0x80,
  CMD_NOT_SUPPORTED    = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS
  | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE
  | CMD_LOW_DREQ | CMD_LOW_DACK

};

static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0};

static void write_page (void *opaque, uint32_t nport, uint32_t data)
{
    struct dma_cont *d = opaque;
    int ichan;

    ichan = channels[nport & 7];

    if (-1 == ichan) {
        log ("invalid channel %#x %#x\n", nport, data);
        return;
    }
    d->regs[ichan].page = data;
}

static uint32_t read_page (void *opaque, uint32_t nport)
{
    struct dma_cont *d = opaque;
    int ichan;

    ichan = channels[nport & 7];

    if (-1 == ichan) {
        log ("invalid channel read %#x\n", nport);
        return 0;
    }
    return d->regs[ichan].page;
}

static inline void init_chan (struct dma_cont *d, int ichan)
{
    struct dma_regs *r;

    r = d->regs + ichan;
    r->now[ADDR] = r->base[0] << d->dshift;
    r->now[COUNT] = 0;
}

static inline int getff (struct dma_cont *d)
{
    int ff;

    ff = d->flip_flop;
    d->flip_flop = !ff;
    return ff;
}

static uint32_t read_chan (void *opaque, uint32_t nport)
{
    struct dma_cont *d = opaque;
    int ichan, nreg, iport, ff, val;
    struct dma_regs *r;

    iport = (nport >> d->dshift) & 0x0f;
    ichan = iport >> 1;
    nreg = iport & 1;
    r = d->regs + ichan;

    ff = getff (d);
    if (nreg)
        val = (r->base[COUNT] << d->dshift) - r->now[COUNT];
    else
        val = r->now[ADDR] + r->now[COUNT];

    return (val >> (d->dshift + (ff << 3))) & 0xff;
}

static void write_chan (void *opaque, uint32_t nport, uint32_t data)
{
    struct dma_cont *d = opaque;
    int iport, ichan, nreg;
    struct dma_regs *r;

    iport = (nport >> d->dshift) & 0x0f;
    ichan = iport >> 1;
    nreg = iport & 1;
    r = d->regs + ichan;
    if (getff (d)) {
        r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00);
        init_chan (d, ichan);
    } else {
        r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff);
    }
}

static void write_cont (void *opaque, uint32_t nport, uint32_t data)
{
    struct dma_cont *d = opaque;
    int iport, ichan;

    iport = (nport >> d->dshift) & 0x0f;
    switch (iport) {
    case 8:                     /* command */
        if ((data != 0) && (data & CMD_NOT_SUPPORTED)) {
            log ("command %#x not supported\n", data);
            return;
        }
        d->command = data;
        break;

    case 9:
        ichan = data & 3;
        if (data & 4) {
            d->status |= 1 << (ichan + 4);
        }
        else {
            d->status &= ~(1 << (ichan + 4));
        }
        d->status &= ~(1 << ichan);
        break;

    case 0xa:                   /* single mask */
        if (data & 4)
            d->mask |= 1 << (data & 3);
        else
            d->mask &= ~(1 << (data & 3));
        break;

    case 0xb:                   /* mode */
        {
            ichan = data & 3;
#ifdef DEBUG_DMA
            int op;
            int ai;
            int dir;
            int opmode;

            op = (data >> 2) & 3;
            ai = (data >> 4) & 1;
            dir = (data >> 5) & 1;
            opmode = (data >> 6) & 3;

            linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
                   ichan, op, ai, dir, opmode);
#endif

            d->regs[ichan].mode = data;
            break;
        }

    case 0xc:                   /* clear flip flop */
        d->flip_flop = 0;
        break;

    case 0xd:                   /* reset */
        d->flip_flop = 0;
        d->mask = ~0;
        d->status = 0;
        d->command = 0;
        break;

    case 0xe:                   /* clear mask for all channels */
        d->mask = 0;
        break;

    case 0xf:                   /* write mask for all channels */
        d->mask = data;
        break;

    default:
        log ("dma: unknown iport %#x\n", iport);
        break;
    }

#ifdef DEBUG_DMA
    if (0xc != iport) {
        linfo ("nport %#06x, ichan % 2d, val %#06x\n",
               nport, ichan, data);
    }
#endif
}

static uint32_t read_cont (void *opaque, uint32_t nport)
{
    struct dma_cont *d = opaque;
    int iport, val;
    
    iport = (nport >> d->dshift) & 0x0f;
    switch (iport) {
    case 0x08: /* status */
        val = d->status;
        d->status &= 0xf0;
        break;
    case 0x0f: /* mask */
        val = d->mask;
        break;
    default:
        val = 0;
        break;
    }
    return val;
}

int DMA_get_channel_mode (int nchan)
{
    return dma_controllers[nchan > 3].regs[nchan & 3].mode;
}

void DMA_hold_DREQ (int nchan)
{
    int ncont, ichan;

    ncont = nchan > 3;
    ichan = nchan & 3;
    linfo ("held cont=%d chan=%d\n", ncont, ichan);
    dma_controllers[ncont].status |= 1 << (ichan + 4);
}

void DMA_release_DREQ (int nchan)
{
    int ncont, ichan;

    ncont = nchan > 3;
    ichan = nchan & 3;
    linfo ("released cont=%d chan=%d\n", ncont, ichan);
    dma_controllers[ncont].status &= ~(1 << (ichan + 4));
}

static void channel_run (int ncont, int ichan)
{
    struct dma_regs *r;
    int n;
    target_ulong addr;
/*     int ai, dir; */

    r = dma_controllers[ncont].regs + ichan;
/*   ai = r->mode & 16; */
/*   dir = r->mode & 32 ? -1 : 1; */

    addr = (r->page << 16) | r->now[ADDR];
    n = r->transfer_handler (r->opaque, addr, 
                             (r->base[COUNT] << ncont) + (1 << ncont));
    r->now[COUNT] = n;

    ldebug ("dma_pos %d size %d\n",
            n, (r->base[1] << ncont) + (1 << ncont));
}

void DMA_run (void)
{
    struct dma_cont *d;
    int icont, ichan;

    d = dma_controllers;

    for (icont = 0; icont < 2; icont++, d++) {
        for (ichan = 0; ichan < 4; ichan++) {
            int mask;

            mask = 1 << ichan;

            if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4))))
                channel_run (icont, ichan);
        }
    }
}

void DMA_register_channel (int nchan,
                           DMA_transfer_handler transfer_handler, 
                           void *opaque)
{
    struct dma_regs *r;
    int ichan, ncont;

    ncont = nchan > 3;
    ichan = nchan & 3;

    r = dma_controllers[ncont].regs + ichan;
    r->transfer_handler = transfer_handler;
    r->opaque = opaque;
}

/* request the emulator to transfer a new DMA memory block ASAP */
void DMA_schedule(int nchan)
{
    cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
}

/* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
static void dma_init2(struct dma_cont *d, int base, int dshift, int page_base)
{
    const static int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 };
    int i;

    d->dshift = dshift;
    for (i = 0; i < 8; i++) {
        register_ioport_write (base + (i << dshift), 1, 1, write_chan, d);
        register_ioport_read (base + (i << dshift), 1, 1, read_chan, d);
    }
    for (i = 0; i < LENOFA (page_port_list); i++) {
        register_ioport_write (page_base + page_port_list[i], 1, 1, 
                               write_page, d);
        register_ioport_read (page_base + page_port_list[i], 1, 1, 
                              read_page, d);
    }
    for (i = 0; i < 8; i++) {
        register_ioport_write (base + ((i + 8) << dshift), 1, 1, 
                               write_cont, d);
        register_ioport_read (base + ((i + 8) << dshift), 1, 1, 
                              read_cont, d);
    }
    write_cont (d, base + (0x0d << dshift), 0);
}

void DMA_init (void)
{
    dma_init2(&dma_controllers[0], 0x00, 0, 0x80);
    dma_init2(&dma_controllers[1], 0xc0, 1, 0x88);
}
Commit	Line	Data
27503323 FB	1	/*
	2	* QEMU DMA emulation
	3	*
	4	* Copyright (c) 2003 Vassili Karpov (malc)
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
16d17fdb	24	#include "vl.h"
27503323 FB	25
	26	#define log(...) fprintf (stderr, "dma: " __VA_ARGS__)
	27	#ifdef DEBUG_DMA
	28	#define lwarn(...) fprintf (stderr, "dma: " __VA_ARGS__)
	29	#define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__)
	30	#define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__)
	31	#else
	32	#define lwarn(...)
	33	#define linfo(...)
	34	#define ldebug(...)
	35	#endif
	36
27503323 FB	37	#define LENOFA(a) ((int) (sizeof(a)/sizeof(a[0])))
	38
	39	struct dma_regs {
	40	int now[2];
	41	uint16_t base[2];
	42	uint8_t mode;
	43	uint8_t page;
	44	uint8_t dack;
	45	uint8_t eop;
16f62432 FB	46	DMA_transfer_handler transfer_handler;
16f62432 FB	47	void *opaque;
27503323 FB	48	};
	49
	50	#define ADDR 0
	51	#define COUNT 1
	52
	53	static struct dma_cont {
	54	uint8_t status;
	55	uint8_t command;
	56	uint8_t mask;
	57	uint8_t flip_flop;
9eb153f1	58	int dshift;
27503323 FB	59	struct dma_regs regs[4];
	60	} dma_controllers[2];
	61
	62	enum {
	63	CMD_MEMORY_TO_MEMORY = 0x01,
	64	CMD_FIXED_ADDRESS = 0x02,
	65	CMD_BLOCK_CONTROLLER = 0x04,
	66	CMD_COMPRESSED_TIME = 0x08,
	67	CMD_CYCLIC_PRIORITY = 0x10,
	68	CMD_EXTENDED_WRITE = 0x20,
	69	CMD_LOW_DREQ = 0x40,
	70	CMD_LOW_DACK = 0x80,
	71	CMD_NOT_SUPPORTED = CMD_MEMORY_TO_MEMORY \| CMD_FIXED_ADDRESS
	72	\| CMD_COMPRESSED_TIME \| CMD_CYCLIC_PRIORITY \| CMD_EXTENDED_WRITE
	73	\| CMD_LOW_DREQ \| CMD_LOW_DACK
	74
	75	};
	76
9eb153f1 FB	77	static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
9eb153f1 FB	78
7d977de7	79	static void write_page (void *opaque, uint32_t nport, uint32_t data)
27503323	80	{
9eb153f1	81	struct dma_cont *d = opaque;
27503323	82	int ichan;
27503323	83
9eb153f1	84	ichan = channels[nport & 7];
27503323 FB	85
	86	if (-1 == ichan) {
	87	log ("invalid channel %#x %#x\n", nport, data);
	88	return;
	89	}
9eb153f1 FB	90	d->regs[ichan].page = data;
	91	}
	92
	93	static uint32_t read_page (void *opaque, uint32_t nport)
	94	{
	95	struct dma_cont *d = opaque;
	96	int ichan;
27503323	97
9eb153f1 FB	98	ichan = channels[nport & 7];
	99
	100	if (-1 == ichan) {
	101	log ("invalid channel read %#x\n", nport);
	102	return 0;
	103	}
	104	return d->regs[ichan].page;
27503323 FB	105	}
27503323 FB	106
9eb153f1	107	static inline void init_chan (struct dma_cont *d, int ichan)
27503323 FB	108	{
	109	struct dma_regs *r;
	110
9eb153f1 FB	111	r = d->regs + ichan;
9eb153f1 FB	112	r->now[ADDR] = r->base[0] << d->dshift;
27503323 FB	113	r->now[COUNT] = 0;
	114	}
	115
9eb153f1	116	static inline int getff (struct dma_cont *d)
27503323 FB	117	{
	118	int ff;
	119
9eb153f1 FB	120	ff = d->flip_flop;
9eb153f1 FB	121	d->flip_flop = !ff;
27503323 FB	122	return ff;
	123	}
	124
7d977de7	125	static uint32_t read_chan (void *opaque, uint32_t nport)
27503323	126	{
9eb153f1 FB	127	struct dma_cont *d = opaque;
9eb153f1 FB	128	int ichan, nreg, iport, ff, val;
27503323	129	struct dma_regs *r;
27503323	130
9eb153f1 FB	131	iport = (nport >> d->dshift) & 0x0f;
	132	ichan = iport >> 1;
	133	nreg = iport & 1;
	134	r = d->regs + ichan;
27503323	135
9eb153f1	136	ff = getff (d);
27503323	137	if (nreg)
9eb153f1	138	val = (r->base[COUNT] << d->dshift) - r->now[COUNT];
27503323 FB	139	else
	140	val = r->now[ADDR] + r->now[COUNT];
	141
9eb153f1	142	return (val >> (d->dshift + (ff << 3))) & 0xff;
27503323 FB	143	}
27503323 FB	144
7d977de7	145	static void write_chan (void *opaque, uint32_t nport, uint32_t data)
27503323	146	{
9eb153f1 FB	147	struct dma_cont *d = opaque;
9eb153f1 FB	148	int iport, ichan, nreg;
27503323 FB	149	struct dma_regs *r;
27503323 FB	150
9eb153f1 FB	151	iport = (nport >> d->dshift) & 0x0f;
	152	ichan = iport >> 1;
	153	nreg = iport & 1;
	154	r = d->regs + ichan;
	155	if (getff (d)) {
3504fe17	156	r->base[nreg] = (r->base[nreg] & 0xff) \| ((data << 8) & 0xff00);
9eb153f1	157	init_chan (d, ichan);
3504fe17 FB	158	} else {
3504fe17 FB	159	r->base[nreg] = (r->base[nreg] & 0xff00) \| (data & 0xff);
27503323	160	}
27503323 FB	161	}
27503323 FB	162
7d977de7	163	static void write_cont (void *opaque, uint32_t nport, uint32_t data)
27503323	164	{
9eb153f1 FB	165	struct dma_cont *d = opaque;
9eb153f1 FB	166	int iport, ichan;
27503323	167
9eb153f1	168	iport = (nport >> d->dshift) & 0x0f;
27503323 FB	169	switch (iport) {
27503323 FB	170	case 8: /* command */
df475d18	171	if ((data != 0) && (data & CMD_NOT_SUPPORTED)) {
27503323	172	log ("command %#x not supported\n", data);
df475d18	173	return;
27503323 FB	174	}
	175	d->command = data;
	176	break;
	177
	178	case 9:
	179	ichan = data & 3;
	180	if (data & 4) {
	181	d->status \|= 1 << (ichan + 4);
	182	}
	183	else {
	184	d->status &= ~(1 << (ichan + 4));
	185	}
	186	d->status &= ~(1 << ichan);
	187	break;
	188
	189	case 0xa: /* single mask */
	190	if (data & 4)
	191	d->mask \|= 1 << (data & 3);
	192	else
	193	d->mask &= ~(1 << (data & 3));
	194	break;
	195
	196	case 0xb: /* mode */
	197	{
16d17fdb FB	198	ichan = data & 3;
16d17fdb FB	199	#ifdef DEBUG_DMA
27503323 FB	200	int op;
	201	int ai;
	202	int dir;
	203	int opmode;
	204
16d17fdb FB	205	op = (data >> 2) & 3;
	206	ai = (data >> 4) & 1;
	207	dir = (data >> 5) & 1;
	208	opmode = (data >> 6) & 3;
27503323 FB	209
	210	linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
	211	ichan, op, ai, dir, opmode);
	212	#endif
	213
	214	d->regs[ichan].mode = data;
	215	break;
	216	}
	217
	218	case 0xc: /* clear flip flop */
	219	d->flip_flop = 0;
	220	break;
	221
	222	case 0xd: /* reset */
	223	d->flip_flop = 0;
	224	d->mask = ~0;
	225	d->status = 0;
	226	d->command = 0;
	227	break;
	228
	229	case 0xe: /* clear mask for all channels */
	230	d->mask = 0;
	231	break;
	232
	233	case 0xf: /* write mask for all channels */
	234	d->mask = data;
	235	break;
	236
	237	default:
	238	log ("dma: unknown iport %#x\n", iport);
df475d18	239	break;
27503323 FB	240	}
27503323 FB	241
16d17fdb	242	#ifdef DEBUG_DMA
27503323	243	if (0xc != iport) {
9eb153f1 FB	244	linfo ("nport %#06x, ichan % 2d, val %#06x\n",
9eb153f1 FB	245	nport, ichan, data);
27503323 FB	246	}
27503323 FB	247	#endif
27503323 FB	248	}
27503323 FB	249
9eb153f1 FB	250	static uint32_t read_cont (void *opaque, uint32_t nport)
	251	{
	252	struct dma_cont *d = opaque;
	253	int iport, val;
	254
	255	iport = (nport >> d->dshift) & 0x0f;
	256	switch (iport) {
	257	case 0x08: /* status */
	258	val = d->status;
	259	d->status &= 0xf0;
	260	break;
	261	case 0x0f: /* mask */
	262	val = d->mask;
	263	break;
	264	default:
	265	val = 0;
	266	break;
	267	}
	268	return val;
	269	}
	270
27503323 FB	271	int DMA_get_channel_mode (int nchan)
	272	{
	273	return dma_controllers[nchan > 3].regs[nchan & 3].mode;
	274	}
	275
	276	void DMA_hold_DREQ (int nchan)
	277	{
	278	int ncont, ichan;
	279
	280	ncont = nchan > 3;
	281	ichan = nchan & 3;
	282	linfo ("held cont=%d chan=%d\n", ncont, ichan);
	283	dma_controllers[ncont].status \|= 1 << (ichan + 4);
	284	}
	285
	286	void DMA_release_DREQ (int nchan)
	287	{
	288	int ncont, ichan;
	289
	290	ncont = nchan > 3;
	291	ichan = nchan & 3;
	292	linfo ("released cont=%d chan=%d\n", ncont, ichan);
	293	dma_controllers[ncont].status &= ~(1 << (ichan + 4));
	294	}
	295
	296	static void channel_run (int ncont, int ichan)
	297	{
	298	struct dma_regs *r;
	299	int n;
16f62432	300	target_ulong addr;
27503323 FB	301	/* int ai, dir; */
	302
	303	r = dma_controllers[ncont].regs + ichan;
	304	/* ai = r->mode & 16; */
	305	/* dir = r->mode & 32 ? -1 : 1; */
	306
16f62432 FB	307	addr = (r->page << 16) \| r->now[ADDR];
	308	n = r->transfer_handler (r->opaque, addr,
	309	(r->base[COUNT] << ncont) + (1 << ncont));
27503323 FB	310	r->now[COUNT] = n;
27503323 FB	311
16f62432 FB	312	ldebug ("dma_pos %d size %d\n",
16f62432 FB	313	n, (r->base[1] << ncont) + (1 << ncont));
27503323 FB	314	}
	315
	316	void DMA_run (void)
	317	{
27503323 FB	318	struct dma_cont *d;
	319	int icont, ichan;
	320
27503323 FB	321	d = dma_controllers;
	322
	323	for (icont = 0; icont < 2; icont++, d++) {
	324	for (ichan = 0; ichan < 4; ichan++) {
	325	int mask;
	326
	327	mask = 1 << ichan;
	328
	329	if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4))))
	330	channel_run (icont, ichan);
	331	}
	332	}
27503323 FB	333	}
	334
	335	void DMA_register_channel (int nchan,
16f62432 FB	336	DMA_transfer_handler transfer_handler,
16f62432 FB	337	void *opaque)
27503323 FB	338	{
	339	struct dma_regs *r;
	340	int ichan, ncont;
	341
	342	ncont = nchan > 3;
	343	ichan = nchan & 3;
	344
	345	r = dma_controllers[ncont].regs + ichan;
16f62432 FB	346	r->transfer_handler = transfer_handler;
	347	r->opaque = opaque;
	348	}
	349
	350	/* request the emulator to transfer a new DMA memory block ASAP */
	351	void DMA_schedule(int nchan)
	352	{
	353	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
27503323 FB	354	}
27503323 FB	355
9eb153f1 FB	356	/* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
9eb153f1 FB	357	static void dma_init2(struct dma_cont *d, int base, int dshift, int page_base)
27503323	358	{
9eb153f1	359	const static int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 };
27503323	360	int i;
27503323	361
9eb153f1	362	d->dshift = dshift;
27503323	363	for (i = 0; i < 8; i++) {
9eb153f1 FB	364	register_ioport_write (base + (i << dshift), 1, 1, write_chan, d);
9eb153f1 FB	365	register_ioport_read (base + (i << dshift), 1, 1, read_chan, d);
27503323	366	}
27503323	367	for (i = 0; i < LENOFA (page_port_list); i++) {
9eb153f1 FB	368	register_ioport_write (page_base + page_port_list[i], 1, 1,
	369	write_page, d);
	370	register_ioport_read (page_base + page_port_list[i], 1, 1,
	371	read_page, d);
27503323	372	}
27503323	373	for (i = 0; i < 8; i++) {
9eb153f1 FB	374	register_ioport_write (base + ((i + 8) << dshift), 1, 1,
	375	write_cont, d);
	376	register_ioport_read (base + ((i + 8) << dshift), 1, 1,
	377	read_cont, d);
27503323	378	}
9eb153f1 FB	379	write_cont (d, base + (0x0d << dshift), 0);
9eb153f1 FB	380	}
27503323	381
9eb153f1 FB	382	void DMA_init (void)
	383	{
	384	dma_init2(&dma_controllers[0], 0x00, 0, 0x80);
	385	dma_init2(&dma_controllers[1], 0xc0, 1, 0x88);
27503323	386	}