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7c23b892 AZ |
1 | /* |
2 | * QEMU e1000 emulation | |
3 | * | |
4 | * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. | |
5 | * Copyright (c) 2008 Qumranet | |
6 | * Based on work done by: | |
7 | * Copyright (c) 2007 Dan Aloni | |
8 | * Copyright (c) 2004 Antony T Curtis | |
9 | * | |
10 | * This library is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU Lesser General Public | |
12 | * License as published by the Free Software Foundation; either | |
13 | * version 2 of the License, or (at your option) any later version. | |
14 | * | |
15 | * This library is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * Lesser General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU Lesser General Public | |
21 | * License along with this library; if not, write to the Free Software | |
fad6cb1a | 22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA |
7c23b892 AZ |
23 | */ |
24 | ||
25 | ||
26 | #include "hw.h" | |
27 | #include "pci.h" | |
28 | #include "net.h" | |
29 | ||
7c23b892 AZ |
30 | #include "e1000_hw.h" |
31 | ||
32 | #define DEBUG | |
33 | ||
34 | #ifdef DEBUG | |
35 | enum { | |
36 | DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT, | |
37 | DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM, | |
38 | DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR, | |
39 | DEBUG_RXFILTER, DEBUG_NOTYET, | |
40 | }; | |
41 | #define DBGBIT(x) (1<<DEBUG_##x) | |
42 | static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL); | |
43 | ||
6c7f4b47 | 44 | #define DBGOUT(what, fmt, ...) do { \ |
7c23b892 | 45 | if (debugflags & DBGBIT(what)) \ |
6c7f4b47 | 46 | fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \ |
7c23b892 AZ |
47 | } while (0) |
48 | #else | |
6c7f4b47 | 49 | #define DBGOUT(what, fmt, ...) do {} while (0) |
7c23b892 AZ |
50 | #endif |
51 | ||
52 | #define IOPORT_SIZE 0x40 | |
e94bbefe | 53 | #define PNPMMIO_SIZE 0x20000 |
7c23b892 AZ |
54 | |
55 | /* | |
56 | * HW models: | |
57 | * E1000_DEV_ID_82540EM works with Windows and Linux | |
58 | * E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22, | |
59 | * appears to perform better than 82540EM, but breaks with Linux 2.6.18 | |
60 | * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested | |
61 | * Others never tested | |
62 | */ | |
63 | enum { E1000_DEVID = E1000_DEV_ID_82540EM }; | |
64 | ||
65 | /* | |
66 | * May need to specify additional MAC-to-PHY entries -- | |
67 | * Intel's Windows driver refuses to initialize unless they match | |
68 | */ | |
69 | enum { | |
70 | PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 : | |
71 | E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 : | |
72 | /* default to E1000_DEV_ID_82540EM */ 0xc20 | |
73 | }; | |
74 | ||
75 | typedef struct E1000State_st { | |
76 | PCIDevice dev; | |
77 | VLANClientState *vc; | |
7c23b892 AZ |
78 | int mmio_index; |
79 | ||
80 | uint32_t mac_reg[0x8000]; | |
81 | uint16_t phy_reg[0x20]; | |
82 | uint16_t eeprom_data[64]; | |
83 | ||
84 | uint32_t rxbuf_size; | |
85 | uint32_t rxbuf_min_shift; | |
86 | int check_rxov; | |
87 | struct e1000_tx { | |
88 | unsigned char header[256]; | |
8f2e8d1f AL |
89 | unsigned char vlan_header[4]; |
90 | unsigned char vlan[4]; | |
7c23b892 AZ |
91 | unsigned char data[0x10000]; |
92 | uint16_t size; | |
93 | unsigned char sum_needed; | |
8f2e8d1f | 94 | unsigned char vlan_needed; |
7c23b892 AZ |
95 | uint8_t ipcss; |
96 | uint8_t ipcso; | |
97 | uint16_t ipcse; | |
98 | uint8_t tucss; | |
99 | uint8_t tucso; | |
100 | uint16_t tucse; | |
101 | uint8_t hdr_len; | |
102 | uint16_t mss; | |
103 | uint32_t paylen; | |
104 | uint16_t tso_frames; | |
105 | char tse; | |
b6c4f71f BS |
106 | int8_t ip; |
107 | int8_t tcp; | |
1b0009db | 108 | char cptse; // current packet tse bit |
7c23b892 AZ |
109 | } tx; |
110 | ||
111 | struct { | |
112 | uint32_t val_in; // shifted in from guest driver | |
113 | uint16_t bitnum_in; | |
114 | uint16_t bitnum_out; | |
115 | uint16_t reading; | |
116 | uint32_t old_eecd; | |
117 | } eecd_state; | |
118 | } E1000State; | |
119 | ||
120 | #define defreg(x) x = (E1000_##x>>2) | |
121 | enum { | |
122 | defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC), | |
123 | defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC), | |
124 | defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC), | |
125 | defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH), | |
126 | defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT), | |
127 | defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH), | |
128 | defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT), | |
129 | defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL), | |
130 | defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC), | |
8f2e8d1f AL |
131 | defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA), |
132 | defreg(VET), | |
7c23b892 AZ |
133 | }; |
134 | ||
135 | enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W }; | |
88b4e9db | 136 | static const char phy_regcap[0x20] = { |
7c23b892 AZ |
137 | [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW, |
138 | [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW, | |
139 | [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW, | |
140 | [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R, | |
141 | [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R, | |
700f6e2c | 142 | [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R |
7c23b892 AZ |
143 | }; |
144 | ||
145 | static void | |
146 | ioport_map(PCIDevice *pci_dev, int region_num, uint32_t addr, | |
147 | uint32_t size, int type) | |
148 | { | |
149 | DBGOUT(IO, "e1000_ioport_map addr=0x%04x size=0x%08x\n", addr, size); | |
150 | } | |
151 | ||
3dcd219f BS |
152 | static void |
153 | update_irqs(E1000State *s) | |
154 | { | |
155 | qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0); | |
156 | } | |
157 | ||
7c23b892 AZ |
158 | static void |
159 | set_interrupt_cause(E1000State *s, int index, uint32_t val) | |
160 | { | |
161 | if (val) | |
162 | val |= E1000_ICR_INT_ASSERTED; | |
163 | s->mac_reg[ICR] = val; | |
3dcd219f | 164 | update_irqs(s); |
7c23b892 AZ |
165 | } |
166 | ||
167 | static void | |
168 | set_ics(E1000State *s, int index, uint32_t val) | |
169 | { | |
170 | DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR], | |
171 | s->mac_reg[IMS]); | |
172 | set_interrupt_cause(s, 0, val | s->mac_reg[ICR]); | |
173 | } | |
174 | ||
175 | static int | |
176 | rxbufsize(uint32_t v) | |
177 | { | |
178 | v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 | | |
179 | E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 | | |
180 | E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256; | |
181 | switch (v) { | |
182 | case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384: | |
183 | return 16384; | |
184 | case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192: | |
185 | return 8192; | |
186 | case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096: | |
187 | return 4096; | |
188 | case E1000_RCTL_SZ_1024: | |
189 | return 1024; | |
190 | case E1000_RCTL_SZ_512: | |
191 | return 512; | |
192 | case E1000_RCTL_SZ_256: | |
193 | return 256; | |
194 | } | |
195 | return 2048; | |
196 | } | |
197 | ||
cab3c825 KW |
198 | static void |
199 | set_ctrl(E1000State *s, int index, uint32_t val) | |
200 | { | |
201 | /* RST is self clearing */ | |
202 | s->mac_reg[CTRL] = val & ~E1000_CTRL_RST; | |
203 | } | |
204 | ||
7c23b892 AZ |
205 | static void |
206 | set_rx_control(E1000State *s, int index, uint32_t val) | |
207 | { | |
208 | s->mac_reg[RCTL] = val; | |
209 | s->rxbuf_size = rxbufsize(val); | |
210 | s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1; | |
211 | DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT], | |
212 | s->mac_reg[RCTL]); | |
213 | } | |
214 | ||
215 | static void | |
216 | set_mdic(E1000State *s, int index, uint32_t val) | |
217 | { | |
218 | uint32_t data = val & E1000_MDIC_DATA_MASK; | |
219 | uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); | |
220 | ||
221 | if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy # | |
222 | val = s->mac_reg[MDIC] | E1000_MDIC_ERROR; | |
223 | else if (val & E1000_MDIC_OP_READ) { | |
224 | DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr); | |
225 | if (!(phy_regcap[addr] & PHY_R)) { | |
226 | DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr); | |
227 | val |= E1000_MDIC_ERROR; | |
228 | } else | |
229 | val = (val ^ data) | s->phy_reg[addr]; | |
230 | } else if (val & E1000_MDIC_OP_WRITE) { | |
231 | DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data); | |
232 | if (!(phy_regcap[addr] & PHY_W)) { | |
233 | DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr); | |
234 | val |= E1000_MDIC_ERROR; | |
235 | } else | |
236 | s->phy_reg[addr] = data; | |
237 | } | |
238 | s->mac_reg[MDIC] = val | E1000_MDIC_READY; | |
239 | set_ics(s, 0, E1000_ICR_MDAC); | |
240 | } | |
241 | ||
242 | static uint32_t | |
243 | get_eecd(E1000State *s, int index) | |
244 | { | |
245 | uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd; | |
246 | ||
247 | DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n", | |
248 | s->eecd_state.bitnum_out, s->eecd_state.reading); | |
249 | if (!s->eecd_state.reading || | |
250 | ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >> | |
251 | ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1) | |
252 | ret |= E1000_EECD_DO; | |
253 | return ret; | |
254 | } | |
255 | ||
256 | static void | |
257 | set_eecd(E1000State *s, int index, uint32_t val) | |
258 | { | |
259 | uint32_t oldval = s->eecd_state.old_eecd; | |
260 | ||
261 | s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS | | |
262 | E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ); | |
263 | if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge | |
264 | return; | |
265 | if (!(E1000_EECD_SK & val)) { // falling edge | |
266 | s->eecd_state.bitnum_out++; | |
267 | return; | |
268 | } | |
269 | if (!(val & E1000_EECD_CS)) { // rising, no CS (EEPROM reset) | |
270 | memset(&s->eecd_state, 0, sizeof s->eecd_state); | |
271 | return; | |
272 | } | |
273 | s->eecd_state.val_in <<= 1; | |
274 | if (val & E1000_EECD_DI) | |
275 | s->eecd_state.val_in |= 1; | |
276 | if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) { | |
277 | s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1; | |
278 | s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) == | |
279 | EEPROM_READ_OPCODE_MICROWIRE); | |
280 | } | |
281 | DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n", | |
282 | s->eecd_state.bitnum_in, s->eecd_state.bitnum_out, | |
283 | s->eecd_state.reading); | |
284 | } | |
285 | ||
286 | static uint32_t | |
287 | flash_eerd_read(E1000State *s, int x) | |
288 | { | |
289 | unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START; | |
290 | ||
291 | if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG) | |
292 | return 0; | |
293 | return (s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) | | |
294 | E1000_EEPROM_RW_REG_DONE | r; | |
295 | } | |
296 | ||
7c23b892 AZ |
297 | static void |
298 | putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse) | |
299 | { | |
c6a6a5e3 AL |
300 | uint32_t sum; |
301 | ||
7c23b892 AZ |
302 | if (cse && cse < n) |
303 | n = cse + 1; | |
c6a6a5e3 AL |
304 | if (sloc < n-1) { |
305 | sum = net_checksum_add(n-css, data+css); | |
7c23b892 | 306 | cpu_to_be16wu((uint16_t *)(data + sloc), |
c6a6a5e3 AL |
307 | net_checksum_finish(sum)); |
308 | } | |
7c23b892 AZ |
309 | } |
310 | ||
8f2e8d1f AL |
311 | static inline int |
312 | vlan_enabled(E1000State *s) | |
313 | { | |
314 | return ((s->mac_reg[CTRL] & E1000_CTRL_VME) != 0); | |
315 | } | |
316 | ||
317 | static inline int | |
318 | vlan_rx_filter_enabled(E1000State *s) | |
319 | { | |
320 | return ((s->mac_reg[RCTL] & E1000_RCTL_VFE) != 0); | |
321 | } | |
322 | ||
323 | static inline int | |
324 | is_vlan_packet(E1000State *s, const uint8_t *buf) | |
325 | { | |
326 | return (be16_to_cpup((uint16_t *)(buf + 12)) == | |
327 | le16_to_cpup((uint16_t *)(s->mac_reg + VET))); | |
328 | } | |
329 | ||
330 | static inline int | |
331 | is_vlan_txd(uint32_t txd_lower) | |
332 | { | |
333 | return ((txd_lower & E1000_TXD_CMD_VLE) != 0); | |
334 | } | |
335 | ||
7c23b892 AZ |
336 | static void |
337 | xmit_seg(E1000State *s) | |
338 | { | |
339 | uint16_t len, *sp; | |
340 | unsigned int frames = s->tx.tso_frames, css, sofar, n; | |
341 | struct e1000_tx *tp = &s->tx; | |
342 | ||
1b0009db | 343 | if (tp->tse && tp->cptse) { |
7c23b892 AZ |
344 | css = tp->ipcss; |
345 | DBGOUT(TXSUM, "frames %d size %d ipcss %d\n", | |
346 | frames, tp->size, css); | |
347 | if (tp->ip) { // IPv4 | |
348 | cpu_to_be16wu((uint16_t *)(tp->data+css+2), | |
349 | tp->size - css); | |
350 | cpu_to_be16wu((uint16_t *)(tp->data+css+4), | |
351 | be16_to_cpup((uint16_t *)(tp->data+css+4))+frames); | |
352 | } else // IPv6 | |
353 | cpu_to_be16wu((uint16_t *)(tp->data+css+4), | |
354 | tp->size - css); | |
355 | css = tp->tucss; | |
356 | len = tp->size - css; | |
357 | DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len); | |
358 | if (tp->tcp) { | |
359 | sofar = frames * tp->mss; | |
360 | cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq | |
88738c09 | 361 | be32_to_cpupu((uint32_t *)(tp->data+css+4))+sofar); |
7c23b892 AZ |
362 | if (tp->paylen - sofar > tp->mss) |
363 | tp->data[css + 13] &= ~9; // PSH, FIN | |
364 | } else // UDP | |
365 | cpu_to_be16wu((uint16_t *)(tp->data+css+4), len); | |
366 | if (tp->sum_needed & E1000_TXD_POPTS_TXSM) { | |
367 | // add pseudo-header length before checksum calculation | |
368 | sp = (uint16_t *)(tp->data + tp->tucso); | |
369 | cpu_to_be16wu(sp, be16_to_cpup(sp) + len); | |
370 | } | |
371 | tp->tso_frames++; | |
372 | } | |
373 | ||
374 | if (tp->sum_needed & E1000_TXD_POPTS_TXSM) | |
375 | putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse); | |
376 | if (tp->sum_needed & E1000_TXD_POPTS_IXSM) | |
377 | putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse); | |
8f2e8d1f AL |
378 | if (tp->vlan_needed) { |
379 | memmove(tp->vlan, tp->data, 12); | |
380 | memcpy(tp->data + 8, tp->vlan_header, 4); | |
381 | qemu_send_packet(s->vc, tp->vlan, tp->size + 4); | |
382 | } else | |
383 | qemu_send_packet(s->vc, tp->data, tp->size); | |
7c23b892 AZ |
384 | s->mac_reg[TPT]++; |
385 | s->mac_reg[GPTC]++; | |
386 | n = s->mac_reg[TOTL]; | |
387 | if ((s->mac_reg[TOTL] += s->tx.size) < n) | |
388 | s->mac_reg[TOTH]++; | |
389 | } | |
390 | ||
391 | static void | |
392 | process_tx_desc(E1000State *s, struct e1000_tx_desc *dp) | |
393 | { | |
394 | uint32_t txd_lower = le32_to_cpu(dp->lower.data); | |
395 | uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D); | |
396 | unsigned int split_size = txd_lower & 0xffff, bytes, sz, op; | |
397 | unsigned int msh = 0xfffff, hdr = 0; | |
398 | uint64_t addr; | |
399 | struct e1000_context_desc *xp = (struct e1000_context_desc *)dp; | |
400 | struct e1000_tx *tp = &s->tx; | |
401 | ||
402 | if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor | |
403 | op = le32_to_cpu(xp->cmd_and_length); | |
404 | tp->ipcss = xp->lower_setup.ip_fields.ipcss; | |
405 | tp->ipcso = xp->lower_setup.ip_fields.ipcso; | |
406 | tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse); | |
407 | tp->tucss = xp->upper_setup.tcp_fields.tucss; | |
408 | tp->tucso = xp->upper_setup.tcp_fields.tucso; | |
409 | tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse); | |
410 | tp->paylen = op & 0xfffff; | |
411 | tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len; | |
412 | tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss); | |
413 | tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0; | |
414 | tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0; | |
415 | tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0; | |
416 | tp->tso_frames = 0; | |
417 | if (tp->tucso == 0) { // this is probably wrong | |
418 | DBGOUT(TXSUM, "TCP/UDP: cso 0!\n"); | |
419 | tp->tucso = tp->tucss + (tp->tcp ? 16 : 6); | |
420 | } | |
421 | return; | |
1b0009db AZ |
422 | } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) { |
423 | // data descriptor | |
7c23b892 | 424 | tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8; |
1b0009db AZ |
425 | tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0; |
426 | } else | |
427 | // legacy descriptor | |
428 | tp->cptse = 0; | |
7c23b892 | 429 | |
8f2e8d1f AL |
430 | if (vlan_enabled(s) && is_vlan_txd(txd_lower) && |
431 | (tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) { | |
432 | tp->vlan_needed = 1; | |
433 | cpu_to_be16wu((uint16_t *)(tp->vlan_header), | |
434 | le16_to_cpup((uint16_t *)(s->mac_reg + VET))); | |
435 | cpu_to_be16wu((uint16_t *)(tp->vlan_header + 2), | |
436 | le16_to_cpu(dp->upper.fields.special)); | |
437 | } | |
438 | ||
7c23b892 | 439 | addr = le64_to_cpu(dp->buffer_addr); |
1b0009db | 440 | if (tp->tse && tp->cptse) { |
7c23b892 AZ |
441 | hdr = tp->hdr_len; |
442 | msh = hdr + tp->mss; | |
1b0009db AZ |
443 | do { |
444 | bytes = split_size; | |
445 | if (tp->size + bytes > msh) | |
446 | bytes = msh - tp->size; | |
447 | cpu_physical_memory_read(addr, tp->data + tp->size, bytes); | |
448 | if ((sz = tp->size + bytes) >= hdr && tp->size < hdr) | |
449 | memmove(tp->header, tp->data, hdr); | |
450 | tp->size = sz; | |
451 | addr += bytes; | |
452 | if (sz == msh) { | |
453 | xmit_seg(s); | |
454 | memmove(tp->data, tp->header, hdr); | |
455 | tp->size = hdr; | |
456 | } | |
457 | } while (split_size -= bytes); | |
458 | } else if (!tp->tse && tp->cptse) { | |
459 | // context descriptor TSE is not set, while data descriptor TSE is set | |
460 | DBGOUT(TXERR, "TCP segmentaion Error\n"); | |
461 | } else { | |
462 | cpu_physical_memory_read(addr, tp->data + tp->size, split_size); | |
463 | tp->size += split_size; | |
7c23b892 | 464 | } |
7c23b892 AZ |
465 | |
466 | if (!(txd_lower & E1000_TXD_CMD_EOP)) | |
467 | return; | |
1b0009db | 468 | if (!(tp->tse && tp->cptse && tp->size < hdr)) |
7c23b892 AZ |
469 | xmit_seg(s); |
470 | tp->tso_frames = 0; | |
471 | tp->sum_needed = 0; | |
8f2e8d1f | 472 | tp->vlan_needed = 0; |
7c23b892 | 473 | tp->size = 0; |
1b0009db | 474 | tp->cptse = 0; |
7c23b892 AZ |
475 | } |
476 | ||
477 | static uint32_t | |
478 | txdesc_writeback(target_phys_addr_t base, struct e1000_tx_desc *dp) | |
479 | { | |
480 | uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data); | |
481 | ||
482 | if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS))) | |
483 | return 0; | |
484 | txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) & | |
485 | ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU); | |
486 | dp->upper.data = cpu_to_le32(txd_upper); | |
487 | cpu_physical_memory_write(base + ((char *)&dp->upper - (char *)dp), | |
488 | (void *)&dp->upper, sizeof(dp->upper)); | |
489 | return E1000_ICR_TXDW; | |
490 | } | |
491 | ||
492 | static void | |
493 | start_xmit(E1000State *s) | |
494 | { | |
495 | target_phys_addr_t base; | |
496 | struct e1000_tx_desc desc; | |
497 | uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE; | |
498 | ||
499 | if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) { | |
500 | DBGOUT(TX, "tx disabled\n"); | |
501 | return; | |
502 | } | |
503 | ||
504 | while (s->mac_reg[TDH] != s->mac_reg[TDT]) { | |
505 | base = ((uint64_t)s->mac_reg[TDBAH] << 32) + s->mac_reg[TDBAL] + | |
506 | sizeof(struct e1000_tx_desc) * s->mac_reg[TDH]; | |
507 | cpu_physical_memory_read(base, (void *)&desc, sizeof(desc)); | |
508 | ||
509 | DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH], | |
6106075b | 510 | (void *)(intptr_t)desc.buffer_addr, desc.lower.data, |
7c23b892 AZ |
511 | desc.upper.data); |
512 | ||
513 | process_tx_desc(s, &desc); | |
514 | cause |= txdesc_writeback(base, &desc); | |
515 | ||
516 | if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN]) | |
517 | s->mac_reg[TDH] = 0; | |
518 | /* | |
519 | * the following could happen only if guest sw assigns | |
520 | * bogus values to TDT/TDLEN. | |
521 | * there's nothing too intelligent we could do about this. | |
522 | */ | |
523 | if (s->mac_reg[TDH] == tdh_start) { | |
524 | DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n", | |
525 | tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]); | |
526 | break; | |
527 | } | |
528 | } | |
529 | set_ics(s, 0, cause); | |
530 | } | |
531 | ||
532 | static int | |
533 | receive_filter(E1000State *s, const uint8_t *buf, int size) | |
534 | { | |
535 | static uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; | |
536 | static int mta_shift[] = {4, 3, 2, 0}; | |
537 | uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp; | |
538 | ||
8f2e8d1f AL |
539 | if (is_vlan_packet(s, buf) && vlan_rx_filter_enabled(s)) { |
540 | uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14)); | |
541 | uint32_t vfta = le32_to_cpup((uint32_t *)(s->mac_reg + VFTA) + | |
542 | ((vid >> 5) & 0x7f)); | |
543 | if ((vfta & (1 << (vid & 0x1f))) == 0) | |
544 | return 0; | |
545 | } | |
546 | ||
7c23b892 AZ |
547 | if (rctl & E1000_RCTL_UPE) // promiscuous |
548 | return 1; | |
549 | ||
550 | if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast | |
551 | return 1; | |
552 | ||
553 | if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast)) | |
554 | return 1; | |
555 | ||
556 | for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) { | |
557 | if (!(rp[1] & E1000_RAH_AV)) | |
558 | continue; | |
559 | ra[0] = cpu_to_le32(rp[0]); | |
560 | ra[1] = cpu_to_le32(rp[1]); | |
561 | if (!memcmp(buf, (uint8_t *)ra, 6)) { | |
562 | DBGOUT(RXFILTER, | |
563 | "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n", | |
564 | (int)(rp - s->mac_reg - RA)/2, | |
565 | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); | |
566 | return 1; | |
567 | } | |
568 | } | |
569 | DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n", | |
570 | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); | |
571 | ||
572 | f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3]; | |
573 | f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff; | |
574 | if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f))) | |
575 | return 1; | |
576 | DBGOUT(RXFILTER, | |
577 | "dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n", | |
578 | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], | |
579 | (rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5, | |
580 | s->mac_reg[MTA + (f >> 5)]); | |
581 | ||
582 | return 0; | |
583 | } | |
584 | ||
99ed7e30 AL |
585 | static void |
586 | e1000_set_link_status(VLANClientState *vc) | |
587 | { | |
588 | E1000State *s = vc->opaque; | |
589 | uint32_t old_status = s->mac_reg[STATUS]; | |
590 | ||
591 | if (vc->link_down) | |
592 | s->mac_reg[STATUS] &= ~E1000_STATUS_LU; | |
593 | else | |
594 | s->mac_reg[STATUS] |= E1000_STATUS_LU; | |
595 | ||
596 | if (s->mac_reg[STATUS] != old_status) | |
597 | set_ics(s, 0, E1000_ICR_LSC); | |
598 | } | |
599 | ||
7c23b892 | 600 | static int |
e3f5ec2b | 601 | e1000_can_receive(VLANClientState *vc) |
7c23b892 | 602 | { |
e3f5ec2b | 603 | E1000State *s = vc->opaque; |
7c23b892 | 604 | |
4105de67 | 605 | return (s->mac_reg[RCTL] & E1000_RCTL_EN); |
7c23b892 AZ |
606 | } |
607 | ||
4f1c942b | 608 | static ssize_t |
e3f5ec2b | 609 | e1000_receive(VLANClientState *vc, const uint8_t *buf, size_t size) |
7c23b892 | 610 | { |
e3f5ec2b | 611 | E1000State *s = vc->opaque; |
7c23b892 AZ |
612 | struct e1000_rx_desc desc; |
613 | target_phys_addr_t base; | |
614 | unsigned int n, rdt; | |
615 | uint32_t rdh_start; | |
8f2e8d1f AL |
616 | uint16_t vlan_special = 0; |
617 | uint8_t vlan_status = 0, vlan_offset = 0; | |
7c23b892 AZ |
618 | |
619 | if (!(s->mac_reg[RCTL] & E1000_RCTL_EN)) | |
4f1c942b | 620 | return -1; |
7c23b892 AZ |
621 | |
622 | if (size > s->rxbuf_size) { | |
cda9046b MM |
623 | DBGOUT(RX, "packet too large for buffers (%lu > %d)\n", |
624 | (unsigned long)size, s->rxbuf_size); | |
4f1c942b | 625 | return -1; |
7c23b892 AZ |
626 | } |
627 | ||
628 | if (!receive_filter(s, buf, size)) | |
4f1c942b | 629 | return size; |
7c23b892 | 630 | |
8f2e8d1f AL |
631 | if (vlan_enabled(s) && is_vlan_packet(s, buf)) { |
632 | vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(buf + 14))); | |
633 | memmove((void *)(buf + 4), buf, 12); | |
634 | vlan_status = E1000_RXD_STAT_VP; | |
635 | vlan_offset = 4; | |
636 | size -= 4; | |
637 | } | |
638 | ||
7c23b892 AZ |
639 | rdh_start = s->mac_reg[RDH]; |
640 | size += 4; // for the header | |
641 | do { | |
642 | if (s->mac_reg[RDH] == s->mac_reg[RDT] && s->check_rxov) { | |
643 | set_ics(s, 0, E1000_ICS_RXO); | |
4f1c942b | 644 | return -1; |
7c23b892 AZ |
645 | } |
646 | base = ((uint64_t)s->mac_reg[RDBAH] << 32) + s->mac_reg[RDBAL] + | |
647 | sizeof(desc) * s->mac_reg[RDH]; | |
648 | cpu_physical_memory_read(base, (void *)&desc, sizeof(desc)); | |
8f2e8d1f AL |
649 | desc.special = vlan_special; |
650 | desc.status |= (vlan_status | E1000_RXD_STAT_DD); | |
7c23b892 AZ |
651 | if (desc.buffer_addr) { |
652 | cpu_physical_memory_write(le64_to_cpu(desc.buffer_addr), | |
8f2e8d1f | 653 | (void *)(buf + vlan_offset), size); |
7c23b892 AZ |
654 | desc.length = cpu_to_le16(size); |
655 | desc.status |= E1000_RXD_STAT_EOP|E1000_RXD_STAT_IXSM; | |
656 | } else // as per intel docs; skip descriptors with null buf addr | |
657 | DBGOUT(RX, "Null RX descriptor!!\n"); | |
658 | cpu_physical_memory_write(base, (void *)&desc, sizeof(desc)); | |
659 | ||
660 | if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN]) | |
661 | s->mac_reg[RDH] = 0; | |
662 | s->check_rxov = 1; | |
663 | /* see comment in start_xmit; same here */ | |
664 | if (s->mac_reg[RDH] == rdh_start) { | |
665 | DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n", | |
666 | rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]); | |
667 | set_ics(s, 0, E1000_ICS_RXO); | |
4f1c942b | 668 | return -1; |
7c23b892 AZ |
669 | } |
670 | } while (desc.buffer_addr == 0); | |
671 | ||
672 | s->mac_reg[GPRC]++; | |
673 | s->mac_reg[TPR]++; | |
674 | n = s->mac_reg[TORL]; | |
675 | if ((s->mac_reg[TORL] += size) < n) | |
676 | s->mac_reg[TORH]++; | |
677 | ||
678 | n = E1000_ICS_RXT0; | |
679 | if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH]) | |
680 | rdt += s->mac_reg[RDLEN] / sizeof(desc); | |
bf16cc8f AL |
681 | if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >> |
682 | s->rxbuf_min_shift) | |
7c23b892 AZ |
683 | n |= E1000_ICS_RXDMT0; |
684 | ||
685 | set_ics(s, 0, n); | |
4f1c942b MM |
686 | |
687 | return size; | |
7c23b892 AZ |
688 | } |
689 | ||
690 | static uint32_t | |
691 | mac_readreg(E1000State *s, int index) | |
692 | { | |
693 | return s->mac_reg[index]; | |
694 | } | |
695 | ||
696 | static uint32_t | |
697 | mac_icr_read(E1000State *s, int index) | |
698 | { | |
699 | uint32_t ret = s->mac_reg[ICR]; | |
700 | ||
701 | DBGOUT(INTERRUPT, "ICR read: %x\n", ret); | |
702 | set_interrupt_cause(s, 0, 0); | |
703 | return ret; | |
704 | } | |
705 | ||
706 | static uint32_t | |
707 | mac_read_clr4(E1000State *s, int index) | |
708 | { | |
709 | uint32_t ret = s->mac_reg[index]; | |
710 | ||
711 | s->mac_reg[index] = 0; | |
712 | return ret; | |
713 | } | |
714 | ||
715 | static uint32_t | |
716 | mac_read_clr8(E1000State *s, int index) | |
717 | { | |
718 | uint32_t ret = s->mac_reg[index]; | |
719 | ||
720 | s->mac_reg[index] = 0; | |
721 | s->mac_reg[index-1] = 0; | |
722 | return ret; | |
723 | } | |
724 | ||
725 | static void | |
726 | mac_writereg(E1000State *s, int index, uint32_t val) | |
727 | { | |
728 | s->mac_reg[index] = val; | |
729 | } | |
730 | ||
731 | static void | |
732 | set_rdt(E1000State *s, int index, uint32_t val) | |
733 | { | |
734 | s->check_rxov = 0; | |
735 | s->mac_reg[index] = val & 0xffff; | |
736 | } | |
737 | ||
738 | static void | |
739 | set_16bit(E1000State *s, int index, uint32_t val) | |
740 | { | |
741 | s->mac_reg[index] = val & 0xffff; | |
742 | } | |
743 | ||
744 | static void | |
745 | set_dlen(E1000State *s, int index, uint32_t val) | |
746 | { | |
747 | s->mac_reg[index] = val & 0xfff80; | |
748 | } | |
749 | ||
750 | static void | |
751 | set_tctl(E1000State *s, int index, uint32_t val) | |
752 | { | |
753 | s->mac_reg[index] = val; | |
754 | s->mac_reg[TDT] &= 0xffff; | |
755 | start_xmit(s); | |
756 | } | |
757 | ||
758 | static void | |
759 | set_icr(E1000State *s, int index, uint32_t val) | |
760 | { | |
761 | DBGOUT(INTERRUPT, "set_icr %x\n", val); | |
762 | set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val); | |
763 | } | |
764 | ||
765 | static void | |
766 | set_imc(E1000State *s, int index, uint32_t val) | |
767 | { | |
768 | s->mac_reg[IMS] &= ~val; | |
769 | set_ics(s, 0, 0); | |
770 | } | |
771 | ||
772 | static void | |
773 | set_ims(E1000State *s, int index, uint32_t val) | |
774 | { | |
775 | s->mac_reg[IMS] |= val; | |
776 | set_ics(s, 0, 0); | |
777 | } | |
778 | ||
779 | #define getreg(x) [x] = mac_readreg | |
780 | static uint32_t (*macreg_readops[])(E1000State *, int) = { | |
781 | getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL), | |
782 | getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL), | |
783 | getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS), | |
784 | getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL), | |
8f2e8d1f | 785 | getreg(RDH), getreg(RDT), getreg(VET), |
7c23b892 AZ |
786 | |
787 | [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4, | |
788 | [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4, | |
789 | [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read, | |
790 | [CRCERRS ... MPC] = &mac_readreg, | |
791 | [RA ... RA+31] = &mac_readreg, | |
792 | [MTA ... MTA+127] = &mac_readreg, | |
8f2e8d1f | 793 | [VFTA ... VFTA+127] = &mac_readreg, |
7c23b892 | 794 | }; |
b1503cda | 795 | enum { NREADOPS = ARRAY_SIZE(macreg_readops) }; |
7c23b892 AZ |
796 | |
797 | #define putreg(x) [x] = mac_writereg | |
798 | static void (*macreg_writeops[])(E1000State *, int, uint32_t) = { | |
799 | putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC), | |
800 | putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH), | |
cab3c825 | 801 | putreg(RDBAL), putreg(LEDCTL), putreg(VET), |
7c23b892 AZ |
802 | [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl, |
803 | [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics, | |
804 | [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt, | |
805 | [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr, | |
cab3c825 | 806 | [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl, |
7c23b892 AZ |
807 | [RA ... RA+31] = &mac_writereg, |
808 | [MTA ... MTA+127] = &mac_writereg, | |
8f2e8d1f | 809 | [VFTA ... VFTA+127] = &mac_writereg, |
7c23b892 | 810 | }; |
b1503cda | 811 | enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) }; |
7c23b892 AZ |
812 | |
813 | static void | |
814 | e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) | |
815 | { | |
816 | E1000State *s = opaque; | |
8da3ff18 | 817 | unsigned int index = (addr & 0x1ffff) >> 2; |
7c23b892 | 818 | |
6b59fc74 AJ |
819 | #ifdef TARGET_WORDS_BIGENDIAN |
820 | val = bswap32(val); | |
821 | #endif | |
7c23b892 | 822 | if (index < NWRITEOPS && macreg_writeops[index]) |
6b59fc74 | 823 | macreg_writeops[index](s, index, val); |
7c23b892 AZ |
824 | else if (index < NREADOPS && macreg_readops[index]) |
825 | DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04x\n", index<<2, val); | |
826 | else | |
827 | DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08x\n", | |
828 | index<<2, val); | |
829 | } | |
830 | ||
831 | static void | |
832 | e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) | |
833 | { | |
834 | // emulate hw without byte enables: no RMW | |
835 | e1000_mmio_writel(opaque, addr & ~3, | |
6b59fc74 | 836 | (val & 0xffff) << (8*(addr & 3))); |
7c23b892 AZ |
837 | } |
838 | ||
839 | static void | |
840 | e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) | |
841 | { | |
842 | // emulate hw without byte enables: no RMW | |
843 | e1000_mmio_writel(opaque, addr & ~3, | |
6b59fc74 | 844 | (val & 0xff) << (8*(addr & 3))); |
7c23b892 AZ |
845 | } |
846 | ||
847 | static uint32_t | |
848 | e1000_mmio_readl(void *opaque, target_phys_addr_t addr) | |
849 | { | |
850 | E1000State *s = opaque; | |
8da3ff18 | 851 | unsigned int index = (addr & 0x1ffff) >> 2; |
7c23b892 AZ |
852 | |
853 | if (index < NREADOPS && macreg_readops[index]) | |
6b59fc74 AJ |
854 | { |
855 | uint32_t val = macreg_readops[index](s, index); | |
856 | #ifdef TARGET_WORDS_BIGENDIAN | |
857 | val = bswap32(val); | |
858 | #endif | |
859 | return val; | |
860 | } | |
7c23b892 AZ |
861 | DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2); |
862 | return 0; | |
863 | } | |
864 | ||
865 | static uint32_t | |
866 | e1000_mmio_readb(void *opaque, target_phys_addr_t addr) | |
867 | { | |
6b59fc74 | 868 | return ((e1000_mmio_readl(opaque, addr & ~3)) >> |
7c23b892 AZ |
869 | (8 * (addr & 3))) & 0xff; |
870 | } | |
871 | ||
872 | static uint32_t | |
873 | e1000_mmio_readw(void *opaque, target_phys_addr_t addr) | |
874 | { | |
6b59fc74 AJ |
875 | return ((e1000_mmio_readl(opaque, addr & ~3)) >> |
876 | (8 * (addr & 3))) & 0xffff; | |
7c23b892 AZ |
877 | } |
878 | ||
88b4e9db | 879 | static const int mac_regtosave[] = { |
7c23b892 AZ |
880 | CTRL, EECD, EERD, GPRC, GPTC, ICR, ICS, IMC, IMS, |
881 | LEDCTL, MANC, MDIC, MPC, PBA, RCTL, RDBAH, RDBAL, RDH, | |
882 | RDLEN, RDT, STATUS, SWSM, TCTL, TDBAH, TDBAL, TDH, TDLEN, | |
883 | TDT, TORH, TORL, TOTH, TOTL, TPR, TPT, TXDCTL, WUFC, | |
8f2e8d1f | 884 | VET, |
7c23b892 | 885 | }; |
b1503cda | 886 | enum { MAC_NSAVE = ARRAY_SIZE(mac_regtosave) }; |
7c23b892 | 887 | |
88b4e9db | 888 | static const struct { |
7c23b892 AZ |
889 | int size; |
890 | int array0; | |
8f2e8d1f | 891 | } mac_regarraystosave[] = { {32, RA}, {128, MTA}, {128, VFTA} }; |
b1503cda | 892 | enum { MAC_NARRAYS = ARRAY_SIZE(mac_regarraystosave) }; |
7c23b892 AZ |
893 | |
894 | static void | |
895 | nic_save(QEMUFile *f, void *opaque) | |
896 | { | |
897 | E1000State *s = (E1000State *)opaque; | |
898 | int i, j; | |
899 | ||
900 | pci_device_save(&s->dev, f); | |
8da3ff18 | 901 | qemu_put_be32(f, 0); |
7c23b892 AZ |
902 | qemu_put_be32s(f, &s->rxbuf_size); |
903 | qemu_put_be32s(f, &s->rxbuf_min_shift); | |
904 | qemu_put_be32s(f, &s->eecd_state.val_in); | |
905 | qemu_put_be16s(f, &s->eecd_state.bitnum_in); | |
906 | qemu_put_be16s(f, &s->eecd_state.bitnum_out); | |
907 | qemu_put_be16s(f, &s->eecd_state.reading); | |
908 | qemu_put_be32s(f, &s->eecd_state.old_eecd); | |
909 | qemu_put_8s(f, &s->tx.ipcss); | |
910 | qemu_put_8s(f, &s->tx.ipcso); | |
911 | qemu_put_be16s(f, &s->tx.ipcse); | |
912 | qemu_put_8s(f, &s->tx.tucss); | |
913 | qemu_put_8s(f, &s->tx.tucso); | |
914 | qemu_put_be16s(f, &s->tx.tucse); | |
915 | qemu_put_be32s(f, &s->tx.paylen); | |
916 | qemu_put_8s(f, &s->tx.hdr_len); | |
917 | qemu_put_be16s(f, &s->tx.mss); | |
918 | qemu_put_be16s(f, &s->tx.size); | |
919 | qemu_put_be16s(f, &s->tx.tso_frames); | |
920 | qemu_put_8s(f, &s->tx.sum_needed); | |
b6c4f71f BS |
921 | qemu_put_s8s(f, &s->tx.ip); |
922 | qemu_put_s8s(f, &s->tx.tcp); | |
7c23b892 AZ |
923 | qemu_put_buffer(f, s->tx.header, sizeof s->tx.header); |
924 | qemu_put_buffer(f, s->tx.data, sizeof s->tx.data); | |
925 | for (i = 0; i < 64; i++) | |
926 | qemu_put_be16s(f, s->eeprom_data + i); | |
927 | for (i = 0; i < 0x20; i++) | |
928 | qemu_put_be16s(f, s->phy_reg + i); | |
929 | for (i = 0; i < MAC_NSAVE; i++) | |
930 | qemu_put_be32s(f, s->mac_reg + mac_regtosave[i]); | |
931 | for (i = 0; i < MAC_NARRAYS; i++) | |
932 | for (j = 0; j < mac_regarraystosave[i].size; j++) | |
933 | qemu_put_be32s(f, | |
934 | s->mac_reg + mac_regarraystosave[i].array0 + j); | |
935 | } | |
936 | ||
937 | static int | |
938 | nic_load(QEMUFile *f, void *opaque, int version_id) | |
939 | { | |
940 | E1000State *s = (E1000State *)opaque; | |
941 | int i, j, ret; | |
942 | ||
943 | if ((ret = pci_device_load(&s->dev, f)) < 0) | |
944 | return ret; | |
18fdb1c5 | 945 | if (version_id == 1) |
b6c4f71f | 946 | qemu_get_sbe32s(f, &i); /* once some unused instance id */ |
8da3ff18 | 947 | qemu_get_be32(f); /* Ignored. Was mmio_base. */ |
7c23b892 AZ |
948 | qemu_get_be32s(f, &s->rxbuf_size); |
949 | qemu_get_be32s(f, &s->rxbuf_min_shift); | |
950 | qemu_get_be32s(f, &s->eecd_state.val_in); | |
951 | qemu_get_be16s(f, &s->eecd_state.bitnum_in); | |
952 | qemu_get_be16s(f, &s->eecd_state.bitnum_out); | |
953 | qemu_get_be16s(f, &s->eecd_state.reading); | |
954 | qemu_get_be32s(f, &s->eecd_state.old_eecd); | |
955 | qemu_get_8s(f, &s->tx.ipcss); | |
956 | qemu_get_8s(f, &s->tx.ipcso); | |
957 | qemu_get_be16s(f, &s->tx.ipcse); | |
958 | qemu_get_8s(f, &s->tx.tucss); | |
959 | qemu_get_8s(f, &s->tx.tucso); | |
960 | qemu_get_be16s(f, &s->tx.tucse); | |
961 | qemu_get_be32s(f, &s->tx.paylen); | |
962 | qemu_get_8s(f, &s->tx.hdr_len); | |
963 | qemu_get_be16s(f, &s->tx.mss); | |
964 | qemu_get_be16s(f, &s->tx.size); | |
965 | qemu_get_be16s(f, &s->tx.tso_frames); | |
966 | qemu_get_8s(f, &s->tx.sum_needed); | |
b6c4f71f BS |
967 | qemu_get_s8s(f, &s->tx.ip); |
968 | qemu_get_s8s(f, &s->tx.tcp); | |
7c23b892 AZ |
969 | qemu_get_buffer(f, s->tx.header, sizeof s->tx.header); |
970 | qemu_get_buffer(f, s->tx.data, sizeof s->tx.data); | |
971 | for (i = 0; i < 64; i++) | |
972 | qemu_get_be16s(f, s->eeprom_data + i); | |
973 | for (i = 0; i < 0x20; i++) | |
974 | qemu_get_be16s(f, s->phy_reg + i); | |
975 | for (i = 0; i < MAC_NSAVE; i++) | |
976 | qemu_get_be32s(f, s->mac_reg + mac_regtosave[i]); | |
977 | for (i = 0; i < MAC_NARRAYS; i++) | |
978 | for (j = 0; j < mac_regarraystosave[i].size; j++) | |
979 | qemu_get_be32s(f, | |
980 | s->mac_reg + mac_regarraystosave[i].array0 + j); | |
3dcd219f | 981 | update_irqs(s); |
7c23b892 AZ |
982 | return 0; |
983 | } | |
984 | ||
88b4e9db | 985 | static const uint16_t e1000_eeprom_template[64] = { |
7c23b892 AZ |
986 | 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000, |
987 | 0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040, | |
988 | 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700, | |
989 | 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706, | |
990 | 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff, | |
991 | 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, | |
992 | 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, | |
993 | 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000, | |
994 | }; | |
995 | ||
88b4e9db | 996 | static const uint16_t phy_reg_init[] = { |
7c23b892 AZ |
997 | [PHY_CTRL] = 0x1140, [PHY_STATUS] = 0x796d, // link initially up |
998 | [PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT, | |
999 | [PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360, | |
1000 | [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1, | |
1001 | [PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00, | |
700f6e2c | 1002 | [M88E1000_PHY_SPEC_STATUS] = 0xac00, |
7c23b892 AZ |
1003 | }; |
1004 | ||
88b4e9db | 1005 | static const uint32_t mac_reg_init[] = { |
7c23b892 AZ |
1006 | [PBA] = 0x00100030, |
1007 | [LEDCTL] = 0x602, | |
1008 | [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 | | |
1009 | E1000_CTRL_SPD_1000 | E1000_CTRL_SLU, | |
1010 | [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE | | |
1011 | E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK | | |
1012 | E1000_STATUS_SPEED_1000 | E1000_STATUS_FD | | |
1013 | E1000_STATUS_LU, | |
1014 | [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN | | |
1015 | E1000_MANC_ARP_EN | E1000_MANC_0298_EN | | |
1016 | E1000_MANC_RMCP_EN, | |
1017 | }; | |
1018 | ||
1019 | /* PCI interface */ | |
1020 | ||
1021 | static CPUWriteMemoryFunc *e1000_mmio_write[] = { | |
1022 | e1000_mmio_writeb, e1000_mmio_writew, e1000_mmio_writel | |
1023 | }; | |
1024 | ||
1025 | static CPUReadMemoryFunc *e1000_mmio_read[] = { | |
1026 | e1000_mmio_readb, e1000_mmio_readw, e1000_mmio_readl | |
1027 | }; | |
1028 | ||
1029 | static void | |
1030 | e1000_mmio_map(PCIDevice *pci_dev, int region_num, | |
1031 | uint32_t addr, uint32_t size, int type) | |
1032 | { | |
1033 | E1000State *d = (E1000State *)pci_dev; | |
f65ed4c1 AL |
1034 | int i; |
1035 | const uint32_t excluded_regs[] = { | |
1036 | E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS, | |
1037 | E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE | |
1038 | }; | |
1039 | ||
7c23b892 AZ |
1040 | |
1041 | DBGOUT(MMIO, "e1000_mmio_map addr=0x%08x 0x%08x\n", addr, size); | |
1042 | ||
7c23b892 | 1043 | cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index); |
f65ed4c1 AL |
1044 | qemu_register_coalesced_mmio(addr, excluded_regs[0]); |
1045 | ||
1046 | for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++) | |
1047 | qemu_register_coalesced_mmio(addr + excluded_regs[i] + 4, | |
1048 | excluded_regs[i + 1] - | |
1049 | excluded_regs[i] - 4); | |
7c23b892 AZ |
1050 | } |
1051 | ||
b946a153 AL |
1052 | static void |
1053 | e1000_cleanup(VLANClientState *vc) | |
1054 | { | |
1055 | E1000State *d = vc->opaque; | |
1056 | ||
1057 | unregister_savevm("e1000", d); | |
1058 | } | |
1059 | ||
4b09be85 AL |
1060 | static int |
1061 | pci_e1000_uninit(PCIDevice *dev) | |
1062 | { | |
1063 | E1000State *d = (E1000State *) dev; | |
1064 | ||
1065 | cpu_unregister_io_memory(d->mmio_index); | |
1066 | ||
1067 | return 0; | |
1068 | } | |
1069 | ||
32c86e95 BS |
1070 | static void e1000_reset(void *opaque) |
1071 | { | |
1072 | E1000State *d = opaque; | |
1073 | ||
1074 | memset(d->phy_reg, 0, sizeof d->phy_reg); | |
1075 | memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init); | |
1076 | memset(d->mac_reg, 0, sizeof d->mac_reg); | |
1077 | memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init); | |
1078 | d->rxbuf_min_shift = 1; | |
1079 | memset(&d->tx, 0, sizeof d->tx); | |
3dcd219f | 1080 | update_irqs(d); |
32c86e95 BS |
1081 | } |
1082 | ||
9d07d757 | 1083 | static void pci_e1000_init(PCIDevice *pci_dev) |
7c23b892 | 1084 | { |
9d07d757 | 1085 | E1000State *d = (E1000State *)pci_dev; |
7c23b892 | 1086 | uint8_t *pci_conf; |
7c23b892 | 1087 | uint16_t checksum = 0; |
7ccfb2eb | 1088 | static const char info_str[] = "e1000"; |
7c23b892 | 1089 | int i; |
9d07d757 | 1090 | uint8_t macaddr[6]; |
aff427a1 | 1091 | |
7c23b892 | 1092 | pci_conf = d->dev.config; |
7c23b892 | 1093 | |
deb54399 AL |
1094 | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
1095 | pci_config_set_device_id(pci_conf, E1000_DEVID); | |
7c23b892 AZ |
1096 | *(uint16_t *)(pci_conf+0x04) = cpu_to_le16(0x0407); |
1097 | *(uint16_t *)(pci_conf+0x06) = cpu_to_le16(0x0010); | |
1098 | pci_conf[0x08] = 0x03; | |
173a543b | 1099 | pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); |
7c23b892 AZ |
1100 | pci_conf[0x0c] = 0x10; |
1101 | ||
1102 | pci_conf[0x3d] = 1; // interrupt pin 0 | |
1103 | ||
1eed09cb | 1104 | d->mmio_index = cpu_register_io_memory(e1000_mmio_read, |
7c23b892 AZ |
1105 | e1000_mmio_write, d); |
1106 | ||
28c2c264 | 1107 | pci_register_bar((PCIDevice *)d, 0, PNPMMIO_SIZE, |
7c23b892 AZ |
1108 | PCI_ADDRESS_SPACE_MEM, e1000_mmio_map); |
1109 | ||
28c2c264 | 1110 | pci_register_bar((PCIDevice *)d, 1, IOPORT_SIZE, |
7c23b892 AZ |
1111 | PCI_ADDRESS_SPACE_IO, ioport_map); |
1112 | ||
7c23b892 AZ |
1113 | memmove(d->eeprom_data, e1000_eeprom_template, |
1114 | sizeof e1000_eeprom_template); | |
9d07d757 | 1115 | qdev_get_macaddr(&d->dev.qdev, macaddr); |
7c23b892 | 1116 | for (i = 0; i < 3; i++) |
9d07d757 | 1117 | d->eeprom_data[i] = (macaddr[2*i+1]<<8) | macaddr[2*i]; |
7c23b892 AZ |
1118 | for (i = 0; i < EEPROM_CHECKSUM_REG; i++) |
1119 | checksum += d->eeprom_data[i]; | |
1120 | checksum = (uint16_t) EEPROM_SUM - checksum; | |
1121 | d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum; | |
1122 | ||
9d07d757 | 1123 | d->vc = qdev_get_vlan_client(&d->dev.qdev, |
463af534 MM |
1124 | e1000_can_receive, e1000_receive, |
1125 | NULL, e1000_cleanup, d); | |
99ed7e30 | 1126 | d->vc->link_status_changed = e1000_set_link_status; |
7c23b892 | 1127 | |
9d07d757 | 1128 | qemu_format_nic_info_str(d->vc, macaddr); |
7c23b892 | 1129 | |
18fdb1c5 | 1130 | register_savevm(info_str, -1, 2, nic_save, nic_load, d); |
4b09be85 | 1131 | d->dev.unregister = pci_e1000_uninit; |
32c86e95 BS |
1132 | qemu_register_reset(e1000_reset, 0, d); |
1133 | e1000_reset(d); | |
9d07d757 | 1134 | } |
72da4208 | 1135 | |
9d07d757 PB |
1136 | static void e1000_register_devices(void) |
1137 | { | |
1138 | pci_qdev_register("e1000", sizeof(E1000State), pci_e1000_init); | |
7c23b892 | 1139 | } |
9d07d757 PB |
1140 | |
1141 | device_init(e1000_register_devices) |