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e1000: PHY loopback mode support
[mirror_qemu.git] / hw / e1000.c
CommitLineData
7c23b892
AZ		 1/*
2 * QEMU e1000 emulation
3 *
2758aa52
MT		 4 * Software developer's manual:
5 * http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf
6 *
7c23b892
AZ		 7 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
8 * Copyright (c) 2008 Qumranet
9 * Based on work done by:
10 * Copyright (c) 2007 Dan Aloni
11 * Copyright (c) 2004 Antony T Curtis
12 *
13 * This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU Lesser General Public
15 * License as published by the Free Software Foundation; either
16 * version 2 of the License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 * Lesser General Public License for more details.
22 *
23 * You should have received a copy of the GNU Lesser General Public
8167ee88 24 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7c23b892
AZ		 25 */
26
27
28#include "hw.h"
29#include "pci.h"
30#include "net.h"
7200ac3c 31#include "net/checksum.h"
fbdaa002 32#include "loader.h"
1ca4d09a 33#include "sysemu.h"
62ecbd35 34#include "dma.h"
7c23b892 35
7c23b892
AZ		 36#include "e1000_hw.h"
37
27124888 38#define E1000_DEBUG
7c23b892 39
27124888 40#ifdef E1000_DEBUG
7c23b892
AZ		 41enum {
42 DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
43 DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
44 DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
45 DEBUG_RXFILTER, DEBUG_NOTYET,
46};
47#define DBGBIT(x) (1<<DEBUG_##x)
48static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
49
6c7f4b47 50#define DBGOUT(what, fmt, ...) do { \
7c23b892 51 if (debugflags & DBGBIT(what)) \
6c7f4b47 52 fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \
7c23b892
AZ		 53 } while (0)
54#else
6c7f4b47 55#define DBGOUT(what, fmt, ...) do {} while (0)
7c23b892
AZ		 56#endif
57
58#define IOPORT_SIZE 0x40
e94bbefe 59#define PNPMMIO_SIZE 0x20000
78aeb23e 60#define MIN_BUF_SIZE 60 /* Min. octets in an ethernet frame sans FCS */
7c23b892
AZ		 61
62/*
63 * HW models:
64 * E1000_DEV_ID_82540EM works with Windows and Linux
65 * E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22,
66 * appears to perform better than 82540EM, but breaks with Linux 2.6.18
67 * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
68 * Others never tested
69 */
70enum { E1000_DEVID = E1000_DEV_ID_82540EM };
71
72/*
73 * May need to specify additional MAC-to-PHY entries --
74 * Intel's Windows driver refuses to initialize unless they match
75 */
76enum {
77 PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 :
78 E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 :
79 /* default to E1000_DEV_ID_82540EM */ 0xc20
80};
81
82typedef struct E1000State_st {
83 PCIDevice dev;
a03e2aec 84 NICState *nic;
fbdaa002 85 NICConf conf;
ad00a9b9
AK		 86 MemoryRegion mmio;
87 MemoryRegion io;
7c23b892
AZ		 88
89 uint32_t mac_reg[0x8000];
90 uint16_t phy_reg[0x20];
91 uint16_t eeprom_data[64];
92
93 uint32_t rxbuf_size;
94 uint32_t rxbuf_min_shift;
95 int check_rxov;
96 struct e1000_tx {
97 unsigned char header[256];
8f2e8d1f 98 unsigned char vlan_header[4];
b10fec9b 99 /* Fields vlan and data must not be reordered or separated. */
8f2e8d1f 100 unsigned char vlan[4];
7c23b892
AZ		 101 unsigned char data[0x10000];
102 uint16_t size;
103 unsigned char sum_needed;
8f2e8d1f 104 unsigned char vlan_needed;
7c23b892
AZ		 105 uint8_t ipcss;
106 uint8_t ipcso;
107 uint16_t ipcse;
108 uint8_t tucss;
109 uint8_t tucso;
110 uint16_t tucse;
111 uint8_t hdr_len;
112 uint16_t mss;
113 uint32_t paylen;
114 uint16_t tso_frames;
115 char tse;
b6c4f71f
BS		 116 int8_t ip;
117 int8_t tcp;
1b0009db 118 char cptse; // current packet tse bit
7c23b892
AZ		 119 } tx;
120
121 struct {
122 uint32_t val_in; // shifted in from guest driver
123 uint16_t bitnum_in;
124 uint16_t bitnum_out;
125 uint16_t reading;
126 uint32_t old_eecd;
127 } eecd_state;
128} E1000State;
129
130#define defreg(x) x = (E1000_##x>>2)
131enum {
132 defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
133 defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
134 defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC),
135 defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH),
136 defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT),
137 defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
138 defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
139 defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
140 defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
8f2e8d1f
AL		 141 defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA),
142 defreg(VET),
7c23b892
AZ		 143};
144
145enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
88b4e9db 146static const char phy_regcap[0x20] = {
7c23b892
AZ		 147 [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
148 [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
149 [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
150 [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
151 [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
700f6e2c 152 [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R
7c23b892
AZ		 153};
154
814cd3ac
MT		 155static const uint16_t phy_reg_init[] = {
156 [PHY_CTRL] = 0x1140, [PHY_STATUS] = 0x796d, // link initially up
157 [PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT,
158 [PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360,
159 [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1,
160 [PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00,
161 [M88E1000_PHY_SPEC_STATUS] = 0xac00,
162};
163
164static const uint32_t mac_reg_init[] = {
165 [PBA] = 0x00100030,
166 [LEDCTL] = 0x602,
167 [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
168 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU,
169 [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
170 E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK |
171 E1000_STATUS_SPEED_1000 | E1000_STATUS_FD |
172 E1000_STATUS_LU,
173 [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN |
174 E1000_MANC_ARP_EN | E1000_MANC_0298_EN |
175 E1000_MANC_RMCP_EN,
176};
177
7c23b892
AZ		 178static void
179set_interrupt_cause(E1000State *s, int index, uint32_t val)
180{
181 if (val)
182 val |= E1000_ICR_INT_ASSERTED;
183 s->mac_reg[ICR] = val;
b1332393 184 s->mac_reg[ICS] = val;
bc26e55a 185 qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
7c23b892
AZ		 186}
187
188static void
189set_ics(E1000State *s, int index, uint32_t val)
190{
191 DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR],
192 s->mac_reg[IMS]);
193 set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);
194}
195
196static int
197rxbufsize(uint32_t v)
198{
199 v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 |
200 E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 |
201 E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256;
202 switch (v) {
203 case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384:
204 return 16384;
205 case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192:
206 return 8192;
207 case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096:
208 return 4096;
209 case E1000_RCTL_SZ_1024:
210 return 1024;
211 case E1000_RCTL_SZ_512:
212 return 512;
213 case E1000_RCTL_SZ_256:
214 return 256;
215 }
216 return 2048;
217}
218
814cd3ac
MT		 219static void e1000_reset(void *opaque)
220{
221 E1000State *d = opaque;
222
223 memset(d->phy_reg, 0, sizeof d->phy_reg);
224 memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
225 memset(d->mac_reg, 0, sizeof d->mac_reg);
226 memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
227 d->rxbuf_min_shift = 1;
228 memset(&d->tx, 0, sizeof d->tx);
229
230 if (d->nic->nc.link_down) {
231 d->mac_reg[STATUS] &= ~E1000_STATUS_LU;
232 d->phy_reg[PHY_STATUS] &= ~MII_SR_LINK_STATUS;
233 }
234}
235
cab3c825
KW		 236static void
237set_ctrl(E1000State *s, int index, uint32_t val)
238{
239 /* RST is self clearing */
240 s->mac_reg[CTRL] = val & ~E1000_CTRL_RST;
241}
242
7c23b892
AZ		 243static void
244set_rx_control(E1000State *s, int index, uint32_t val)
245{
246 s->mac_reg[RCTL] = val;
247 s->rxbuf_size = rxbufsize(val);
248 s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1;
249 DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],
250 s->mac_reg[RCTL]);
251}
252
253static void
254set_mdic(E1000State *s, int index, uint32_t val)
255{
256 uint32_t data = val & E1000_MDIC_DATA_MASK;
257 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
258
259 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy #
260 val = s->mac_reg[MDIC] | E1000_MDIC_ERROR;
261 else if (val & E1000_MDIC_OP_READ) {
262 DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);
263 if (!(phy_regcap[addr] & PHY_R)) {
264 DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr);
265 val |= E1000_MDIC_ERROR;
266 } else
267 val = (val ^ data) | s->phy_reg[addr];
268 } else if (val & E1000_MDIC_OP_WRITE) {
269 DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);
270 if (!(phy_regcap[addr] & PHY_W)) {
271 DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr);
272 val |= E1000_MDIC_ERROR;
273 } else
274 s->phy_reg[addr] = data;
275 }
276 s->mac_reg[MDIC] = val | E1000_MDIC_READY;
17fbbb0b
JW		 277
278 if (val & E1000_MDIC_INT_EN) {
279 set_ics(s, 0, E1000_ICR_MDAC);
280 }
7c23b892
AZ		 281}
282
283static uint32_t
284get_eecd(E1000State *s, int index)
285{
286 uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd;
287
288 DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n",
289 s->eecd_state.bitnum_out, s->eecd_state.reading);
290 if (!s->eecd_state.reading ||
291 ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >>
292 ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1)
293 ret |= E1000_EECD_DO;
294 return ret;
295}
296
297static void
298set_eecd(E1000State *s, int index, uint32_t val)
299{
300 uint32_t oldval = s->eecd_state.old_eecd;
301
302 s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
303 E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
9651ac55
IT		 304 if (!(E1000_EECD_CS & val)) // CS inactive; nothing to do
305 return;
306 if (E1000_EECD_CS & (val ^ oldval)) { // CS rise edge; reset state
307 s->eecd_state.val_in = 0;
308 s->eecd_state.bitnum_in = 0;
309 s->eecd_state.bitnum_out = 0;
310 s->eecd_state.reading = 0;
311 }
7c23b892
AZ		 312 if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge
313 return;
314 if (!(E1000_EECD_SK & val)) { // falling edge
315 s->eecd_state.bitnum_out++;
316 return;
317 }
7c23b892
AZ		 318 s->eecd_state.val_in <<= 1;
319 if (val & E1000_EECD_DI)
320 s->eecd_state.val_in |= 1;
321 if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) {
322 s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1;
323 s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) ==
324 EEPROM_READ_OPCODE_MICROWIRE);
325 }
326 DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
327 s->eecd_state.bitnum_in, s->eecd_state.bitnum_out,
328 s->eecd_state.reading);
329}
330
331static uint32_t
332flash_eerd_read(E1000State *s, int x)
333{
334 unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START;
335
b1332393
BP		 336 if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0)
337 return (s->mac_reg[EERD]);
338
7c23b892 339 if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG)
b1332393
BP		 340 return (E1000_EEPROM_RW_REG_DONE | r);
341
342 return ((s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) |
343 E1000_EEPROM_RW_REG_DONE | r);
7c23b892
AZ		 344}
345
7c23b892
AZ		 346static void
347putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse)
348{
c6a6a5e3
AL		 349 uint32_t sum;
350
7c23b892
AZ		 351 if (cse && cse < n)
352 n = cse + 1;
c6a6a5e3
AL		 353 if (sloc < n-1) {
354 sum = net_checksum_add(n-css, data+css);
7c23b892 355 cpu_to_be16wu((uint16_t *)(data + sloc),
c6a6a5e3
AL		 356 net_checksum_finish(sum));
357 }
7c23b892
AZ		 358}
359
8f2e8d1f
AL		 360static inline int
361vlan_enabled(E1000State *s)
362{
363 return ((s->mac_reg[CTRL] & E1000_CTRL_VME) != 0);
364}
365
366static inline int
367vlan_rx_filter_enabled(E1000State *s)
368{
369 return ((s->mac_reg[RCTL] & E1000_RCTL_VFE) != 0);
370}
371
372static inline int
373is_vlan_packet(E1000State *s, const uint8_t *buf)
374{
375 return (be16_to_cpup((uint16_t *)(buf + 12)) ==
376 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
377}
378
379static inline int
380is_vlan_txd(uint32_t txd_lower)
381{
382 return ((txd_lower & E1000_TXD_CMD_VLE) != 0);
383}
384
55e8d1ce
MT		 385/* FCS aka Ethernet CRC-32. We don't get it from backends and can't
386 * fill it in, just pad descriptor length by 4 bytes unless guest
a05e8a6e 387 * told us to strip it off the packet. */
55e8d1ce
MT		 388static inline int
389fcs_len(E1000State *s)
390{
391 return (s->mac_reg[RCTL] & E1000_RCTL_SECRC) ? 0 : 4;
392}
393
93e37d76
JW		 394static void
395e1000_send_packet(E1000State *s, const uint8_t *buf, int size)
396{
397 if (s->phy_reg[PHY_CTRL] & MII_CR_LOOPBACK) {
398 s->nic->nc.info->receive(&s->nic->nc, buf, size);
399 } else {
400 qemu_send_packet(&s->nic->nc, buf, size);
401 }
402}
403
7c23b892
AZ		 404static void
405xmit_seg(E1000State *s)
406{
407 uint16_t len, *sp;
408 unsigned int frames = s->tx.tso_frames, css, sofar, n;
409 struct e1000_tx *tp = &s->tx;
410
1b0009db 411 if (tp->tse && tp->cptse) {
7c23b892
AZ		 412 css = tp->ipcss;
413 DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
414 frames, tp->size, css);
415 if (tp->ip) { // IPv4
416 cpu_to_be16wu((uint16_t *)(tp->data+css+2),
417 tp->size - css);
418 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
419 be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
420 } else // IPv6
421 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
422 tp->size - css);
423 css = tp->tucss;
424 len = tp->size - css;
425 DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
426 if (tp->tcp) {
427 sofar = frames * tp->mss;
428 cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq
88738c09 429 be32_to_cpupu((uint32_t *)(tp->data+css+4))+sofar);
7c23b892
AZ		 430 if (tp->paylen - sofar > tp->mss)
431 tp->data[css + 13] &= ~9; // PSH, FIN
432 } else // UDP
433 cpu_to_be16wu((uint16_t *)(tp->data+css+4), len);
434 if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
e685b4eb 435 unsigned int phsum;
7c23b892
AZ		 436 // add pseudo-header length before checksum calculation
437 sp = (uint16_t *)(tp->data + tp->tucso);
e685b4eb
AW		 438 phsum = be16_to_cpup(sp) + len;
439 phsum = (phsum >> 16) + (phsum & 0xffff);
440 cpu_to_be16wu(sp, phsum);
7c23b892
AZ		 441 }
442 tp->tso_frames++;
443 }
444
445 if (tp->sum_needed & E1000_TXD_POPTS_TXSM)
446 putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse);
447 if (tp->sum_needed & E1000_TXD_POPTS_IXSM)
448 putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse);
8f2e8d1f 449 if (tp->vlan_needed) {
b10fec9b
SW		 450 memmove(tp->vlan, tp->data, 4);
451 memmove(tp->data, tp->data + 4, 8);
8f2e8d1f 452 memcpy(tp->data + 8, tp->vlan_header, 4);
93e37d76 453 e1000_send_packet(s, tp->vlan, tp->size + 4);
8f2e8d1f 454 } else
93e37d76 455 e1000_send_packet(s, tp->data, tp->size);
7c23b892
AZ		 456 s->mac_reg[TPT]++;
457 s->mac_reg[GPTC]++;
458 n = s->mac_reg[TOTL];
459 if ((s->mac_reg[TOTL] += s->tx.size) < n)
460 s->mac_reg[TOTH]++;
461}
462
463static void
464process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
465{
466 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
467 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
468 unsigned int split_size = txd_lower & 0xffff, bytes, sz, op;
469 unsigned int msh = 0xfffff, hdr = 0;
470 uint64_t addr;
471 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
472 struct e1000_tx *tp = &s->tx;
473
474 if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor
475 op = le32_to_cpu(xp->cmd_and_length);
476 tp->ipcss = xp->lower_setup.ip_fields.ipcss;
477 tp->ipcso = xp->lower_setup.ip_fields.ipcso;
478 tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse);
479 tp->tucss = xp->upper_setup.tcp_fields.tucss;
480 tp->tucso = xp->upper_setup.tcp_fields.tucso;
481 tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse);
482 tp->paylen = op & 0xfffff;
483 tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len;
484 tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss);
485 tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0;
486 tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
487 tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
488 tp->tso_frames = 0;
489 if (tp->tucso == 0) { // this is probably wrong
490 DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
491 tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
492 }
493 return;
1b0009db
AZ		 494 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
495 // data descriptor
735e77ec
SH		 496 if (tp->size == 0) {
497 tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
498 }
1b0009db 499 tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0;
43ad7e3e 500 } else {
1b0009db
AZ		 501 // legacy descriptor
502 tp->cptse = 0;
43ad7e3e 503 }
7c23b892 504
8f2e8d1f
AL		 505 if (vlan_enabled(s) && is_vlan_txd(txd_lower) &&
506 (tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) {
507 tp->vlan_needed = 1;
508 cpu_to_be16wu((uint16_t *)(tp->vlan_header),
509 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
510 cpu_to_be16wu((uint16_t *)(tp->vlan_header + 2),
511 le16_to_cpu(dp->upper.fields.special));
512 }
513
7c23b892 514 addr = le64_to_cpu(dp->buffer_addr);
1b0009db 515 if (tp->tse && tp->cptse) {
7c23b892
AZ		 516 hdr = tp->hdr_len;
517 msh = hdr + tp->mss;
1b0009db
AZ		 518 do {
519 bytes = split_size;
520 if (tp->size + bytes > msh)
521 bytes = msh - tp->size;
65f82df0
AL		 522
523 bytes = MIN(sizeof(tp->data) - tp->size, bytes);
62ecbd35 524 pci_dma_read(&s->dev, addr, tp->data + tp->size, bytes);
1b0009db
AZ		 525 if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
526 memmove(tp->header, tp->data, hdr);
527 tp->size = sz;
528 addr += bytes;
529 if (sz == msh) {
530 xmit_seg(s);
531 memmove(tp->data, tp->header, hdr);
532 tp->size = hdr;
533 }
534 } while (split_size -= bytes);
535 } else if (!tp->tse && tp->cptse) {
536 // context descriptor TSE is not set, while data descriptor TSE is set
362f5fb5 537 DBGOUT(TXERR, "TCP segmentation error\n");
1b0009db 538 } else {
65f82df0 539 split_size = MIN(sizeof(tp->data) - tp->size, split_size);
62ecbd35 540 pci_dma_read(&s->dev, addr, tp->data + tp->size, split_size);
1b0009db 541 tp->size += split_size;
7c23b892 542 }
7c23b892
AZ		 543
544 if (!(txd_lower & E1000_TXD_CMD_EOP))
545 return;
1b0009db 546 if (!(tp->tse && tp->cptse && tp->size < hdr))
7c23b892
AZ		 547 xmit_seg(s);
548 tp->tso_frames = 0;
549 tp->sum_needed = 0;
8f2e8d1f 550 tp->vlan_needed = 0;
7c23b892 551 tp->size = 0;
1b0009db 552 tp->cptse = 0;
7c23b892
AZ		 553}
554
555static uint32_t
62ecbd35 556txdesc_writeback(E1000State *s, dma_addr_t base, struct e1000_tx_desc *dp)
7c23b892
AZ		 557{
558 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
559
560 if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
561 return 0;
562 txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) &
563 ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU);
564 dp->upper.data = cpu_to_le32(txd_upper);
62ecbd35 565 pci_dma_write(&s->dev, base + ((char *)&dp->upper - (char *)dp),
00c3a05b 566 &dp->upper, sizeof(dp->upper));
7c23b892
AZ		 567 return E1000_ICR_TXDW;
568}
569
d17161f6
KW		 570static uint64_t tx_desc_base(E1000State *s)
571{
572 uint64_t bah = s->mac_reg[TDBAH];
573 uint64_t bal = s->mac_reg[TDBAL] & ~0xf;
574
575 return (bah << 32) + bal;
576}
577
7c23b892
AZ		 578static void
579start_xmit(E1000State *s)
580{
62ecbd35 581 dma_addr_t base;
7c23b892
AZ		 582 struct e1000_tx_desc desc;
583 uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
584
585 if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) {
586 DBGOUT(TX, "tx disabled\n");
587 return;
588 }
589
590 while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
d17161f6 591 base = tx_desc_base(s) +
7c23b892 592 sizeof(struct e1000_tx_desc) * s->mac_reg[TDH];
00c3a05b 593 pci_dma_read(&s->dev, base, &desc, sizeof(desc));
7c23b892
AZ		 594
595 DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
6106075b 596 (void *)(intptr_t)desc.buffer_addr, desc.lower.data,
7c23b892
AZ		 597 desc.upper.data);
598
599 process_tx_desc(s, &desc);
62ecbd35 600 cause |= txdesc_writeback(s, base, &desc);
7c23b892
AZ		 601
602 if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN])
603 s->mac_reg[TDH] = 0;
604 /*
605 * the following could happen only if guest sw assigns
606 * bogus values to TDT/TDLEN.
607 * there's nothing too intelligent we could do about this.
608 */
609 if (s->mac_reg[TDH] == tdh_start) {
610 DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n",
611 tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]);
612 break;
613 }
614 }
615 set_ics(s, 0, cause);
616}
617
618static int
619receive_filter(E1000State *s, const uint8_t *buf, int size)
620{
af2960f9
BS		 621 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
622 static const int mta_shift[] = {4, 3, 2, 0};
7c23b892
AZ		 623 uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp;
624
8f2e8d1f
AL		 625 if (is_vlan_packet(s, buf) && vlan_rx_filter_enabled(s)) {
626 uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14));
627 uint32_t vfta = le32_to_cpup((uint32_t *)(s->mac_reg + VFTA) +
628 ((vid >> 5) & 0x7f));
629 if ((vfta & (1 << (vid & 0x1f))) == 0)
630 return 0;
631 }
632
7c23b892
AZ		 633 if (rctl & E1000_RCTL_UPE) // promiscuous
634 return 1;
635
636 if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast
637 return 1;
638
639 if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast))
640 return 1;
641
642 for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) {
643 if (!(rp[1] & E1000_RAH_AV))
644 continue;
645 ra[0] = cpu_to_le32(rp[0]);
646 ra[1] = cpu_to_le32(rp[1]);
647 if (!memcmp(buf, (uint8_t *)ra, 6)) {
648 DBGOUT(RXFILTER,
649 "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
650 (int)(rp - s->mac_reg - RA)/2,
651 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
652 return 1;
653 }
654 }
655 DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n",
656 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
657
658 f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
659 f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff;
660 if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f)))
661 return 1;
662 DBGOUT(RXFILTER,
663 "dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n",
664 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
665 (rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5,
666 s->mac_reg[MTA + (f >> 5)]);
667
668 return 0;
669}
670
99ed7e30 671static void
a03e2aec 672e1000_set_link_status(VLANClientState *nc)
99ed7e30 673{
a03e2aec 674 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
99ed7e30
AL		 675 uint32_t old_status = s->mac_reg[STATUS];
676
d4044c2a 677 if (nc->link_down) {
99ed7e30 678 s->mac_reg[STATUS] &= ~E1000_STATUS_LU;
d4044c2a
BM		 679 s->phy_reg[PHY_STATUS] &= ~MII_SR_LINK_STATUS;
680 } else {
99ed7e30 681 s->mac_reg[STATUS] |= E1000_STATUS_LU;
d4044c2a
BM		 682 s->phy_reg[PHY_STATUS] |= MII_SR_LINK_STATUS;
683 }
99ed7e30
AL		 684
685 if (s->mac_reg[STATUS] != old_status)
686 set_ics(s, 0, E1000_ICR_LSC);
687}
688
322fd48a
MT		 689static bool e1000_has_rxbufs(E1000State *s, size_t total_size)
690{
691 int bufs;
692 /* Fast-path short packets */
693 if (total_size <= s->rxbuf_size) {
694 return s->mac_reg[RDH] != s->mac_reg[RDT] || !s->check_rxov;
695 }
696 if (s->mac_reg[RDH] < s->mac_reg[RDT]) {
697 bufs = s->mac_reg[RDT] - s->mac_reg[RDH];
698 } else if (s->mac_reg[RDH] > s->mac_reg[RDT] || !s->check_rxov) {
699 bufs = s->mac_reg[RDLEN] / sizeof(struct e1000_rx_desc) +
700 s->mac_reg[RDT] - s->mac_reg[RDH];
701 } else {
702 return false;
703 }
704 return total_size <= bufs * s->rxbuf_size;
705}
706
6cdfab28
MT		 707static int
708e1000_can_receive(VLANClientState *nc)
709{
710 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
711
712 return (s->mac_reg[RCTL] & E1000_RCTL_EN) && e1000_has_rxbufs(s, 1);
713}
714
d17161f6
KW		 715static uint64_t rx_desc_base(E1000State *s)
716{
717 uint64_t bah = s->mac_reg[RDBAH];
718 uint64_t bal = s->mac_reg[RDBAL] & ~0xf;
719
720 return (bah << 32) + bal;
721}
722
4f1c942b 723static ssize_t
a03e2aec 724e1000_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
7c23b892 725{
a03e2aec 726 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
7c23b892 727 struct e1000_rx_desc desc;
62ecbd35 728 dma_addr_t base;
7c23b892
AZ		 729 unsigned int n, rdt;
730 uint32_t rdh_start;
8f2e8d1f
AL		 731 uint16_t vlan_special = 0;
732 uint8_t vlan_status = 0, vlan_offset = 0;
78aeb23e 733 uint8_t min_buf[MIN_BUF_SIZE];
b19487e2
MT		 734 size_t desc_offset;
735 size_t desc_size;
736 size_t total_size;
7c23b892
AZ		 737
738 if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))
4f1c942b 739 return -1;
7c23b892 740
78aeb23e
SH		 741 /* Pad to minimum Ethernet frame length */
742 if (size < sizeof(min_buf)) {
743 memcpy(min_buf, buf, size);
744 memset(&min_buf[size], 0, sizeof(min_buf) - size);
745 buf = min_buf;
746 size = sizeof(min_buf);
747 }
748
7c23b892 749 if (!receive_filter(s, buf, size))
4f1c942b 750 return size;
7c23b892 751
8f2e8d1f
AL		 752 if (vlan_enabled(s) && is_vlan_packet(s, buf)) {
753 vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(buf + 14)));
98835fe3 754 memmove((uint8_t *)buf + 4, buf, 12);
8f2e8d1f
AL		 755 vlan_status = E1000_RXD_STAT_VP;
756 vlan_offset = 4;
757 size -= 4;
758 }
759
7c23b892 760 rdh_start = s->mac_reg[RDH];
b19487e2
MT		 761 desc_offset = 0;
762 total_size = size + fcs_len(s);
322fd48a
MT		 763 if (!e1000_has_rxbufs(s, total_size)) {
764 set_ics(s, 0, E1000_ICS_RXO);
765 return -1;
766 }
7c23b892 767 do {
b19487e2
MT		 768 desc_size = total_size - desc_offset;
769 if (desc_size > s->rxbuf_size) {
770 desc_size = s->rxbuf_size;
771 }
d17161f6 772 base = rx_desc_base(s) + sizeof(desc) * s->mac_reg[RDH];
00c3a05b 773 pci_dma_read(&s->dev, base, &desc, sizeof(desc));
8f2e8d1f
AL		 774 desc.special = vlan_special;
775 desc.status |= (vlan_status | E1000_RXD_STAT_DD);
7c23b892 776 if (desc.buffer_addr) {
b19487e2
MT		 777 if (desc_offset < size) {
778 size_t copy_size = size - desc_offset;
779 if (copy_size > s->rxbuf_size) {
780 copy_size = s->rxbuf_size;
781 }
62ecbd35 782 pci_dma_write(&s->dev, le64_to_cpu(desc.buffer_addr),
00c3a05b 783 buf + desc_offset + vlan_offset, copy_size);
b19487e2
MT		 784 }
785 desc_offset += desc_size;
ee912ccf 786 desc.length = cpu_to_le16(desc_size);
b19487e2 787 if (desc_offset >= total_size) {
b19487e2
MT		 788 desc.status |= E1000_RXD_STAT_EOP | E1000_RXD_STAT_IXSM;
789 } else {
ee912ccf
MT		 790 /* Guest zeroing out status is not a hardware requirement.
791 Clear EOP in case guest didn't do it. */
792 desc.status &= ~E1000_RXD_STAT_EOP;
b19487e2 793 }
43ad7e3e 794 } else { // as per intel docs; skip descriptors with null buf addr
7c23b892 795 DBGOUT(RX, "Null RX descriptor!!\n");
43ad7e3e 796 }
00c3a05b 797 pci_dma_write(&s->dev, base, &desc, sizeof(desc));
7c23b892
AZ		 798
799 if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])
800 s->mac_reg[RDH] = 0;
801 s->check_rxov = 1;
802 /* see comment in start_xmit; same here */
803 if (s->mac_reg[RDH] == rdh_start) {
804 DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",
805 rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);
806 set_ics(s, 0, E1000_ICS_RXO);
4f1c942b 807 return -1;
7c23b892 808 }
b19487e2 809 } while (desc_offset < total_size);
7c23b892
AZ		 810
811 s->mac_reg[GPRC]++;
812 s->mac_reg[TPR]++;
a05e8a6e
MT		 813 /* TOR - Total Octets Received:
814 * This register includes bytes received in a packet from the <Destination
815 * Address> field through the <CRC> field, inclusively.
816 */
817 n = s->mac_reg[TORL] + size + /* Always include FCS length. */ 4;
818 if (n < s->mac_reg[TORL])
7c23b892 819 s->mac_reg[TORH]++;
a05e8a6e 820 s->mac_reg[TORL] = n;
7c23b892
AZ		 821
822 n = E1000_ICS_RXT0;
823 if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
824 rdt += s->mac_reg[RDLEN] / sizeof(desc);
bf16cc8f
AL		 825 if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >>
826 s->rxbuf_min_shift)
7c23b892
AZ		 827 n |= E1000_ICS_RXDMT0;
828
829 set_ics(s, 0, n);
4f1c942b
MM		 830
831 return size;
7c23b892
AZ		 832}
833
834static uint32_t
835mac_readreg(E1000State *s, int index)
836{
837 return s->mac_reg[index];
838}
839
840static uint32_t
841mac_icr_read(E1000State *s, int index)
842{
843 uint32_t ret = s->mac_reg[ICR];
844
845 DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
846 set_interrupt_cause(s, 0, 0);
847 return ret;
848}
849
850static uint32_t
851mac_read_clr4(E1000State *s, int index)
852{
853 uint32_t ret = s->mac_reg[index];
854
855 s->mac_reg[index] = 0;
856 return ret;
857}
858
859static uint32_t
860mac_read_clr8(E1000State *s, int index)
861{
862 uint32_t ret = s->mac_reg[index];
863
864 s->mac_reg[index] = 0;
865 s->mac_reg[index-1] = 0;
866 return ret;
867}
868
869static void
870mac_writereg(E1000State *s, int index, uint32_t val)
871{
872 s->mac_reg[index] = val;
873}
874
875static void
876set_rdt(E1000State *s, int index, uint32_t val)
877{
878 s->check_rxov = 0;
879 s->mac_reg[index] = val & 0xffff;
880}
881
882static void
883set_16bit(E1000State *s, int index, uint32_t val)
884{
885 s->mac_reg[index] = val & 0xffff;
886}
887
888static void
889set_dlen(E1000State *s, int index, uint32_t val)
890{
891 s->mac_reg[index] = val & 0xfff80;
892}
893
894static void
895set_tctl(E1000State *s, int index, uint32_t val)
896{
897 s->mac_reg[index] = val;
898 s->mac_reg[TDT] &= 0xffff;
899 start_xmit(s);
900}
901
902static void
903set_icr(E1000State *s, int index, uint32_t val)
904{
905 DBGOUT(INTERRUPT, "set_icr %x\n", val);
906 set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);
907}
908
909static void
910set_imc(E1000State *s, int index, uint32_t val)
911{
912 s->mac_reg[IMS] &= ~val;
913 set_ics(s, 0, 0);
914}
915
916static void
917set_ims(E1000State *s, int index, uint32_t val)
918{
919 s->mac_reg[IMS] |= val;
920 set_ics(s, 0, 0);
921}
922
923#define getreg(x) [x] = mac_readreg
924static uint32_t (*macreg_readops[])(E1000State *, int) = {
925 getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
926 getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
927 getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
928 getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
b1332393 929 getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
a00b2335
KA		 930 getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
931 getreg(TDLEN), getreg(RDLEN),
7c23b892
AZ		 932
933 [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4,
934 [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4,
935 [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read,
936 [CRCERRS ... MPC] = &mac_readreg,
937 [RA ... RA+31] = &mac_readreg,
938 [MTA ... MTA+127] = &mac_readreg,
8f2e8d1f 939 [VFTA ... VFTA+127] = &mac_readreg,
7c23b892 940};
b1503cda 941enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
7c23b892
AZ		 942
943#define putreg(x) [x] = mac_writereg
944static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
945 putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
946 putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
cab3c825 947 putreg(RDBAL), putreg(LEDCTL), putreg(VET),
7c23b892
AZ		 948 [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
949 [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
950 [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
951 [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
cab3c825 952 [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
7c23b892
AZ		 953 [RA ... RA+31] = &mac_writereg,
954 [MTA ... MTA+127] = &mac_writereg,
8f2e8d1f 955 [VFTA ... VFTA+127] = &mac_writereg,
7c23b892 956};
b1503cda 957enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
7c23b892
AZ		 958
959static void
ad00a9b9
AK		 960e1000_mmio_write(void *opaque, target_phys_addr_t addr, uint64_t val,
961 unsigned size)
7c23b892
AZ		 962{
963 E1000State *s = opaque;
8da3ff18 964 unsigned int index = (addr & 0x1ffff) >> 2;
7c23b892 965
43ad7e3e 966 if (index < NWRITEOPS && macreg_writeops[index]) {
6b59fc74 967 macreg_writeops[index](s, index, val);
43ad7e3e 968 } else if (index < NREADOPS && macreg_readops[index]) {
ad00a9b9 969 DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04"PRIx64"\n", index<<2, val);
43ad7e3e 970 } else {
ad00a9b9 971 DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08"PRIx64"\n",
7c23b892 972 index<<2, val);
43ad7e3e 973 }
7c23b892
AZ		 974}
975
ad00a9b9
AK		 976static uint64_t
977e1000_mmio_read(void *opaque, target_phys_addr_t addr, unsigned size)
7c23b892
AZ		 978{
979 E1000State *s = opaque;
8da3ff18 980 unsigned int index = (addr & 0x1ffff) >> 2;
7c23b892
AZ		 981
982 if (index < NREADOPS && macreg_readops[index])
6b59fc74 983 {
32600a30 984 return macreg_readops[index](s, index);
6b59fc74 985 }
7c23b892
AZ		 986 DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
987 return 0;
988}
989
ad00a9b9
AK		 990static const MemoryRegionOps e1000_mmio_ops = {
991 .read = e1000_mmio_read,
992 .write = e1000_mmio_write,
993 .endianness = DEVICE_LITTLE_ENDIAN,
994 .impl = {
995 .min_access_size = 4,
996 .max_access_size = 4,
997 },
998};
999
1000static uint64_t e1000_io_read(void *opaque, target_phys_addr_t addr,
1001 unsigned size)
7c23b892 1002{
ad00a9b9
AK		 1003 E1000State *s = opaque;
1004
1005 (void)s;
1006 return 0;
7c23b892
AZ		 1007}
1008
ad00a9b9
AK		 1009static void e1000_io_write(void *opaque, target_phys_addr_t addr,
1010 uint64_t val, unsigned size)
7c23b892 1011{
ad00a9b9
AK		 1012 E1000State *s = opaque;
1013
1014 (void)s;
7c23b892
AZ		 1015}
1016
ad00a9b9
AK		 1017static const MemoryRegionOps e1000_io_ops = {
1018 .read = e1000_io_read,
1019 .write = e1000_io_write,
1020 .endianness = DEVICE_LITTLE_ENDIAN,
1021};
1022
e482dc3e 1023static bool is_version_1(void *opaque, int version_id)
7c23b892 1024{
e482dc3e 1025 return version_id == 1;
7c23b892
AZ		 1026}
1027
e482dc3e
JQ		 1028static const VMStateDescription vmstate_e1000 = {
1029 .name = "e1000",
1030 .version_id = 2,
1031 .minimum_version_id = 1,
1032 .minimum_version_id_old = 1,
1033 .fields = (VMStateField []) {
1034 VMSTATE_PCI_DEVICE(dev, E1000State),
1035 VMSTATE_UNUSED_TEST(is_version_1, 4), /* was instance id */
1036 VMSTATE_UNUSED(4), /* Was mmio_base. */
1037 VMSTATE_UINT32(rxbuf_size, E1000State),
1038 VMSTATE_UINT32(rxbuf_min_shift, E1000State),
1039 VMSTATE_UINT32(eecd_state.val_in, E1000State),
1040 VMSTATE_UINT16(eecd_state.bitnum_in, E1000State),
1041 VMSTATE_UINT16(eecd_state.bitnum_out, E1000State),
1042 VMSTATE_UINT16(eecd_state.reading, E1000State),
1043 VMSTATE_UINT32(eecd_state.old_eecd, E1000State),
1044 VMSTATE_UINT8(tx.ipcss, E1000State),
1045 VMSTATE_UINT8(tx.ipcso, E1000State),
1046 VMSTATE_UINT16(tx.ipcse, E1000State),
1047 VMSTATE_UINT8(tx.tucss, E1000State),
1048 VMSTATE_UINT8(tx.tucso, E1000State),
1049 VMSTATE_UINT16(tx.tucse, E1000State),
1050 VMSTATE_UINT32(tx.paylen, E1000State),
1051 VMSTATE_UINT8(tx.hdr_len, E1000State),
1052 VMSTATE_UINT16(tx.mss, E1000State),
1053 VMSTATE_UINT16(tx.size, E1000State),
1054 VMSTATE_UINT16(tx.tso_frames, E1000State),
1055 VMSTATE_UINT8(tx.sum_needed, E1000State),
1056 VMSTATE_INT8(tx.ip, E1000State),
1057 VMSTATE_INT8(tx.tcp, E1000State),
1058 VMSTATE_BUFFER(tx.header, E1000State),
1059 VMSTATE_BUFFER(tx.data, E1000State),
1060 VMSTATE_UINT16_ARRAY(eeprom_data, E1000State, 64),
1061 VMSTATE_UINT16_ARRAY(phy_reg, E1000State, 0x20),
1062 VMSTATE_UINT32(mac_reg[CTRL], E1000State),
1063 VMSTATE_UINT32(mac_reg[EECD], E1000State),
1064 VMSTATE_UINT32(mac_reg[EERD], E1000State),
1065 VMSTATE_UINT32(mac_reg[GPRC], E1000State),
1066 VMSTATE_UINT32(mac_reg[GPTC], E1000State),
1067 VMSTATE_UINT32(mac_reg[ICR], E1000State),
1068 VMSTATE_UINT32(mac_reg[ICS], E1000State),
1069 VMSTATE_UINT32(mac_reg[IMC], E1000State),
1070 VMSTATE_UINT32(mac_reg[IMS], E1000State),
1071 VMSTATE_UINT32(mac_reg[LEDCTL], E1000State),
1072 VMSTATE_UINT32(mac_reg[MANC], E1000State),
1073 VMSTATE_UINT32(mac_reg[MDIC], E1000State),
1074 VMSTATE_UINT32(mac_reg[MPC], E1000State),
1075 VMSTATE_UINT32(mac_reg[PBA], E1000State),
1076 VMSTATE_UINT32(mac_reg[RCTL], E1000State),
1077 VMSTATE_UINT32(mac_reg[RDBAH], E1000State),
1078 VMSTATE_UINT32(mac_reg[RDBAL], E1000State),
1079 VMSTATE_UINT32(mac_reg[RDH], E1000State),
1080 VMSTATE_UINT32(mac_reg[RDLEN], E1000State),
1081 VMSTATE_UINT32(mac_reg[RDT], E1000State),
1082 VMSTATE_UINT32(mac_reg[STATUS], E1000State),
1083 VMSTATE_UINT32(mac_reg[SWSM], E1000State),
1084 VMSTATE_UINT32(mac_reg[TCTL], E1000State),
1085 VMSTATE_UINT32(mac_reg[TDBAH], E1000State),
1086 VMSTATE_UINT32(mac_reg[TDBAL], E1000State),
1087 VMSTATE_UINT32(mac_reg[TDH], E1000State),
1088 VMSTATE_UINT32(mac_reg[TDLEN], E1000State),
1089 VMSTATE_UINT32(mac_reg[TDT], E1000State),
1090 VMSTATE_UINT32(mac_reg[TORH], E1000State),
1091 VMSTATE_UINT32(mac_reg[TORL], E1000State),
1092 VMSTATE_UINT32(mac_reg[TOTH], E1000State),
1093 VMSTATE_UINT32(mac_reg[TOTL], E1000State),
1094 VMSTATE_UINT32(mac_reg[TPR], E1000State),
1095 VMSTATE_UINT32(mac_reg[TPT], E1000State),
1096 VMSTATE_UINT32(mac_reg[TXDCTL], E1000State),
1097 VMSTATE_UINT32(mac_reg[WUFC], E1000State),
1098 VMSTATE_UINT32(mac_reg[VET], E1000State),
1099 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32),
1100 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, 128),
1101 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA, 128),
1102 VMSTATE_END_OF_LIST()
1103 }
1104};
7c23b892 1105
88b4e9db 1106static const uint16_t e1000_eeprom_template[64] = {
7c23b892
AZ		 1107 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,
1108 0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040,
1109 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,
1110 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,
1111 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,
1112 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1113 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1114 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000,
1115};
1116
7c23b892
AZ		 1117/* PCI interface */
1118
7c23b892 1119static void
ad00a9b9 1120e1000_mmio_setup(E1000State *d)
7c23b892 1121{
f65ed4c1
AL		 1122 int i;
1123 const uint32_t excluded_regs[] = {
1124 E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
1125 E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
1126 };
1127
ad00a9b9
AK		 1128 memory_region_init_io(&d->mmio, &e1000_mmio_ops, d, "e1000-mmio",
1129 PNPMMIO_SIZE);
1130 memory_region_add_coalescing(&d->mmio, 0, excluded_regs[0]);
f65ed4c1 1131 for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++)
ad00a9b9
AK		 1132 memory_region_add_coalescing(&d->mmio, excluded_regs[i] + 4,
1133 excluded_regs[i+1] - excluded_regs[i] - 4);
1134 memory_region_init_io(&d->io, &e1000_io_ops, d, "e1000-io", IOPORT_SIZE);
7c23b892
AZ		 1135}
1136
b946a153 1137static void
a03e2aec 1138e1000_cleanup(VLANClientState *nc)
b946a153 1139{
a03e2aec 1140 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
b946a153 1141
a03e2aec 1142 s->nic = NULL;
b946a153
AL		 1143}
1144
4b09be85
AL		 1145static int
1146pci_e1000_uninit(PCIDevice *dev)
1147{
7d9e52bd 1148 E1000State *d = DO_UPCAST(E1000State, dev, dev);
4b09be85 1149
ad00a9b9
AK		 1150 memory_region_destroy(&d->mmio);
1151 memory_region_destroy(&d->io);
a03e2aec 1152 qemu_del_vlan_client(&d->nic->nc);
4b09be85
AL		 1153 return 0;
1154}
1155
a03e2aec
MM		 1156static NetClientInfo net_e1000_info = {
1157 .type = NET_CLIENT_TYPE_NIC,
1158 .size = sizeof(NICState),
1159 .can_receive = e1000_can_receive,
1160 .receive = e1000_receive,
1161 .cleanup = e1000_cleanup,
1162 .link_status_changed = e1000_set_link_status,
1163};
1164
81a322d4 1165static int pci_e1000_init(PCIDevice *pci_dev)
7c23b892 1166{
7d9e52bd 1167 E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
7c23b892 1168 uint8_t *pci_conf;
7c23b892 1169 uint16_t checksum = 0;
7c23b892 1170 int i;
fbdaa002 1171 uint8_t *macaddr;
aff427a1 1172
7c23b892 1173 pci_conf = d->dev.config;
7c23b892 1174
a9cbacb0
MT		 1175 /* TODO: RST# value should be 0, PCI spec 6.2.4 */
1176 pci_conf[PCI_CACHE_LINE_SIZE] = 0x10;
7c23b892 1177
817e0b6f 1178 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
7c23b892 1179
ad00a9b9 1180 e1000_mmio_setup(d);
7c23b892 1181
e824b2cc 1182 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
7c23b892 1183
e824b2cc 1184 pci_register_bar(&d->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->io);
7c23b892 1185
7c23b892
AZ		 1186 memmove(d->eeprom_data, e1000_eeprom_template,
1187 sizeof e1000_eeprom_template);
fbdaa002
GH		 1188 qemu_macaddr_default_if_unset(&d->conf.macaddr);
1189 macaddr = d->conf.macaddr.a;
7c23b892 1190 for (i = 0; i < 3; i++)
9d07d757 1191 d->eeprom_data[i] = (macaddr[2*i+1]<<8) | macaddr[2*i];
7c23b892
AZ		 1192 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1193 checksum += d->eeprom_data[i];
1194 checksum = (uint16_t) EEPROM_SUM - checksum;
1195 d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum;
1196
a03e2aec 1197 d->nic = qemu_new_nic(&net_e1000_info, &d->conf,
f79f2bfc 1198 object_get_typename(OBJECT(d)), d->dev.qdev.id, d);
7c23b892 1199
a03e2aec 1200 qemu_format_nic_info_str(&d->nic->nc, macaddr);
1ca4d09a
GN		 1201
1202 add_boot_device_path(d->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
1203
81a322d4 1204 return 0;
9d07d757 1205}
72da4208 1206
fbdaa002
GH		 1207static void qdev_e1000_reset(DeviceState *dev)
1208{
1209 E1000State *d = DO_UPCAST(E1000State, dev.qdev, dev);
1210 e1000_reset(d);
1211}
1212
40021f08
AL		 1213static Property e1000_properties[] = {
1214 DEFINE_NIC_PROPERTIES(E1000State, conf),
1215 DEFINE_PROP_END_OF_LIST(),
1216};
1217
1218static void e1000_class_init(ObjectClass *klass, void *data)
1219{
39bffca2 1220 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 1221 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1222
1223 k->init = pci_e1000_init;
1224 k->exit = pci_e1000_uninit;
1225 k->romfile = "pxe-e1000.rom";
1226 k->vendor_id = PCI_VENDOR_ID_INTEL;
1227 k->device_id = E1000_DEVID;
1228 k->revision = 0x03;
1229 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
39bffca2
AL		 1230 dc->desc = "Intel Gigabit Ethernet";
1231 dc->reset = qdev_e1000_reset;
1232 dc->vmsd = &vmstate_e1000;
1233 dc->props = e1000_properties;
40021f08
AL		 1234}
1235
39bffca2
AL		 1236static TypeInfo e1000_info = {
1237 .name = "e1000",
1238 .parent = TYPE_PCI_DEVICE,
1239 .instance_size = sizeof(E1000State),
1240 .class_init = e1000_class_init,
0aab0d3a
GH		 1241};
1242
83f7d43a 1243static void e1000_register_types(void)
9d07d757 1244{
39bffca2 1245 type_register_static(&e1000_info);
7c23b892 1246}
9d07d757 1247
83f7d43a 1248type_init(e1000_register_types)
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