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7c23b892
AZ		 1/*
2 * QEMU e1000 emulation
3 *
4 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
5 * Copyright (c) 2008 Qumranet
6 * Based on work done by:
7 * Copyright (c) 2007 Dan Aloni
8 * Copyright (c) 2004 Antony T Curtis
9 *
10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2 of the License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
8167ee88 21 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7c23b892
AZ		 22 */
23
24
25#include "hw.h"
26#include "pci.h"
27#include "net.h"
fbdaa002 28#include "loader.h"
7c23b892 29
7c23b892
AZ		 30#include "e1000_hw.h"
31
32#define DEBUG
33
34#ifdef DEBUG
35enum {
36 DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
37 DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
38 DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
39 DEBUG_RXFILTER, DEBUG_NOTYET,
40};
41#define DBGBIT(x) (1<<DEBUG_##x)
42static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
43
6c7f4b47 44#define DBGOUT(what, fmt, ...) do { \
7c23b892 45 if (debugflags & DBGBIT(what)) \
6c7f4b47 46 fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \
7c23b892
AZ		 47 } while (0)
48#else
6c7f4b47 49#define DBGOUT(what, fmt, ...) do {} while (0)
7c23b892
AZ		 50#endif
51
52#define IOPORT_SIZE 0x40
e94bbefe 53#define PNPMMIO_SIZE 0x20000
7c23b892
AZ		 54
55/*
56 * HW models:
57 * E1000_DEV_ID_82540EM works with Windows and Linux
58 * E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22,
59 * appears to perform better than 82540EM, but breaks with Linux 2.6.18
60 * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
61 * Others never tested
62 */
63enum { E1000_DEVID = E1000_DEV_ID_82540EM };
64
65/*
66 * May need to specify additional MAC-to-PHY entries --
67 * Intel's Windows driver refuses to initialize unless they match
68 */
69enum {
70 PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 :
71 E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 :
72 /* default to E1000_DEV_ID_82540EM */ 0xc20
73};
74
75typedef struct E1000State_st {
76 PCIDevice dev;
77 VLANClientState *vc;
fbdaa002 78 NICConf conf;
7c23b892
AZ		 79 int mmio_index;
80
81 uint32_t mac_reg[0x8000];
82 uint16_t phy_reg[0x20];
83 uint16_t eeprom_data[64];
84
85 uint32_t rxbuf_size;
86 uint32_t rxbuf_min_shift;
87 int check_rxov;
88 struct e1000_tx {
89 unsigned char header[256];
8f2e8d1f
AL		 90 unsigned char vlan_header[4];
91 unsigned char vlan[4];
7c23b892
AZ		 92 unsigned char data[0x10000];
93 uint16_t size;
94 unsigned char sum_needed;
8f2e8d1f 95 unsigned char vlan_needed;
7c23b892
AZ		 96 uint8_t ipcss;
97 uint8_t ipcso;
98 uint16_t ipcse;
99 uint8_t tucss;
100 uint8_t tucso;
101 uint16_t tucse;
102 uint8_t hdr_len;
103 uint16_t mss;
104 uint32_t paylen;
105 uint16_t tso_frames;
106 char tse;
b6c4f71f
BS		 107 int8_t ip;
108 int8_t tcp;
1b0009db 109 char cptse; // current packet tse bit
7c23b892
AZ		 110 } tx;
111
112 struct {
113 uint32_t val_in; // shifted in from guest driver
114 uint16_t bitnum_in;
115 uint16_t bitnum_out;
116 uint16_t reading;
117 uint32_t old_eecd;
118 } eecd_state;
119} E1000State;
120
121#define defreg(x) x = (E1000_##x>>2)
122enum {
123 defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
124 defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
125 defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC),
126 defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH),
127 defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT),
128 defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
129 defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
130 defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
131 defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
8f2e8d1f
AL		 132 defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA),
133 defreg(VET),
7c23b892
AZ		 134};
135
136enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
88b4e9db 137static const char phy_regcap[0x20] = {
7c23b892
AZ		 138 [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
139 [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
140 [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
141 [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
142 [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
700f6e2c 143 [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R
7c23b892
AZ		 144};
145
146static void
147ioport_map(PCIDevice *pci_dev, int region_num, uint32_t addr,
148 uint32_t size, int type)
149{
150 DBGOUT(IO, "e1000_ioport_map addr=0x%04x size=0x%08x\n", addr, size);
151}
152
153static void
154set_interrupt_cause(E1000State *s, int index, uint32_t val)
155{
156 if (val)
157 val |= E1000_ICR_INT_ASSERTED;
158 s->mac_reg[ICR] = val;
b1332393 159 s->mac_reg[ICS] = val;
bc26e55a 160 qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
7c23b892
AZ		 161}
162
163static void
164set_ics(E1000State *s, int index, uint32_t val)
165{
166 DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR],
167 s->mac_reg[IMS]);
168 set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);
169}
170
171static int
172rxbufsize(uint32_t v)
173{
174 v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 |
175 E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 |
176 E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256;
177 switch (v) {
178 case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384:
179 return 16384;
180 case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192:
181 return 8192;
182 case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096:
183 return 4096;
184 case E1000_RCTL_SZ_1024:
185 return 1024;
186 case E1000_RCTL_SZ_512:
187 return 512;
188 case E1000_RCTL_SZ_256:
189 return 256;
190 }
191 return 2048;
192}
193
cab3c825
KW		 194static void
195set_ctrl(E1000State *s, int index, uint32_t val)
196{
197 /* RST is self clearing */
198 s->mac_reg[CTRL] = val & ~E1000_CTRL_RST;
199}
200
7c23b892
AZ		 201static void
202set_rx_control(E1000State *s, int index, uint32_t val)
203{
204 s->mac_reg[RCTL] = val;
205 s->rxbuf_size = rxbufsize(val);
206 s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1;
207 DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],
208 s->mac_reg[RCTL]);
209}
210
211static void
212set_mdic(E1000State *s, int index, uint32_t val)
213{
214 uint32_t data = val & E1000_MDIC_DATA_MASK;
215 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
216
217 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy #
218 val = s->mac_reg[MDIC] | E1000_MDIC_ERROR;
219 else if (val & E1000_MDIC_OP_READ) {
220 DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);
221 if (!(phy_regcap[addr] & PHY_R)) {
222 DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr);
223 val |= E1000_MDIC_ERROR;
224 } else
225 val = (val ^ data) | s->phy_reg[addr];
226 } else if (val & E1000_MDIC_OP_WRITE) {
227 DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);
228 if (!(phy_regcap[addr] & PHY_W)) {
229 DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr);
230 val |= E1000_MDIC_ERROR;
231 } else
232 s->phy_reg[addr] = data;
233 }
234 s->mac_reg[MDIC] = val | E1000_MDIC_READY;
235 set_ics(s, 0, E1000_ICR_MDAC);
236}
237
238static uint32_t
239get_eecd(E1000State *s, int index)
240{
241 uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd;
242
243 DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n",
244 s->eecd_state.bitnum_out, s->eecd_state.reading);
245 if (!s->eecd_state.reading ||
246 ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >>
247 ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1)
248 ret |= E1000_EECD_DO;
249 return ret;
250}
251
252static void
253set_eecd(E1000State *s, int index, uint32_t val)
254{
255 uint32_t oldval = s->eecd_state.old_eecd;
256
257 s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
258 E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
259 if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge
260 return;
261 if (!(E1000_EECD_SK & val)) { // falling edge
262 s->eecd_state.bitnum_out++;
263 return;
264 }
265 if (!(val & E1000_EECD_CS)) { // rising, no CS (EEPROM reset)
266 memset(&s->eecd_state, 0, sizeof s->eecd_state);
356c7ff4
NS		 267 /*
268 * restore old_eecd's E1000_EECD_SK (known to be on)
269 * to avoid false detection of a clock edge
270 */
271 s->eecd_state.old_eecd = E1000_EECD_SK;
7c23b892
AZ		 272 return;
273 }
274 s->eecd_state.val_in <<= 1;
275 if (val & E1000_EECD_DI)
276 s->eecd_state.val_in |= 1;
277 if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) {
278 s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1;
279 s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) ==
280 EEPROM_READ_OPCODE_MICROWIRE);
281 }
282 DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
283 s->eecd_state.bitnum_in, s->eecd_state.bitnum_out,
284 s->eecd_state.reading);
285}
286
287static uint32_t
288flash_eerd_read(E1000State *s, int x)
289{
290 unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START;
291
b1332393
BP		 292 if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0)
293 return (s->mac_reg[EERD]);
294
7c23b892 295 if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG)
b1332393
BP		 296 return (E1000_EEPROM_RW_REG_DONE | r);
297
298 return ((s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) |
299 E1000_EEPROM_RW_REG_DONE | r);
7c23b892
AZ		 300}
301
7c23b892
AZ		 302static void
303putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse)
304{
c6a6a5e3
AL		 305 uint32_t sum;
306
7c23b892
AZ		 307 if (cse && cse < n)
308 n = cse + 1;
c6a6a5e3
AL		 309 if (sloc < n-1) {
310 sum = net_checksum_add(n-css, data+css);
7c23b892 311 cpu_to_be16wu((uint16_t *)(data + sloc),
c6a6a5e3
AL		 312 net_checksum_finish(sum));
313 }
7c23b892
AZ		 314}
315
8f2e8d1f
AL		 316static inline int
317vlan_enabled(E1000State *s)
318{
319 return ((s->mac_reg[CTRL] & E1000_CTRL_VME) != 0);
320}
321
322static inline int
323vlan_rx_filter_enabled(E1000State *s)
324{
325 return ((s->mac_reg[RCTL] & E1000_RCTL_VFE) != 0);
326}
327
328static inline int
329is_vlan_packet(E1000State *s, const uint8_t *buf)
330{
331 return (be16_to_cpup((uint16_t *)(buf + 12)) ==
332 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
333}
334
335static inline int
336is_vlan_txd(uint32_t txd_lower)
337{
338 return ((txd_lower & E1000_TXD_CMD_VLE) != 0);
339}
340
7c23b892
AZ		 341static void
342xmit_seg(E1000State *s)
343{
344 uint16_t len, *sp;
345 unsigned int frames = s->tx.tso_frames, css, sofar, n;
346 struct e1000_tx *tp = &s->tx;
347
1b0009db 348 if (tp->tse && tp->cptse) {
7c23b892
AZ		 349 css = tp->ipcss;
350 DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
351 frames, tp->size, css);
352 if (tp->ip) { // IPv4
353 cpu_to_be16wu((uint16_t *)(tp->data+css+2),
354 tp->size - css);
355 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
356 be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
357 } else // IPv6
358 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
359 tp->size - css);
360 css = tp->tucss;
361 len = tp->size - css;
362 DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
363 if (tp->tcp) {
364 sofar = frames * tp->mss;
365 cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq
88738c09 366 be32_to_cpupu((uint32_t *)(tp->data+css+4))+sofar);
7c23b892
AZ		 367 if (tp->paylen - sofar > tp->mss)
368 tp->data[css + 13] &= ~9; // PSH, FIN
369 } else // UDP
370 cpu_to_be16wu((uint16_t *)(tp->data+css+4), len);
371 if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
372 // add pseudo-header length before checksum calculation
373 sp = (uint16_t *)(tp->data + tp->tucso);
374 cpu_to_be16wu(sp, be16_to_cpup(sp) + len);
375 }
376 tp->tso_frames++;
377 }
378
379 if (tp->sum_needed & E1000_TXD_POPTS_TXSM)
380 putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse);
381 if (tp->sum_needed & E1000_TXD_POPTS_IXSM)
382 putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse);
8f2e8d1f
AL		 383 if (tp->vlan_needed) {
384 memmove(tp->vlan, tp->data, 12);
385 memcpy(tp->data + 8, tp->vlan_header, 4);
386 qemu_send_packet(s->vc, tp->vlan, tp->size + 4);
387 } else
388 qemu_send_packet(s->vc, tp->data, tp->size);
7c23b892
AZ		 389 s->mac_reg[TPT]++;
390 s->mac_reg[GPTC]++;
391 n = s->mac_reg[TOTL];
392 if ((s->mac_reg[TOTL] += s->tx.size) < n)
393 s->mac_reg[TOTH]++;
394}
395
396static void
397process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
398{
399 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
400 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
401 unsigned int split_size = txd_lower & 0xffff, bytes, sz, op;
402 unsigned int msh = 0xfffff, hdr = 0;
403 uint64_t addr;
404 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
405 struct e1000_tx *tp = &s->tx;
406
407 if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor
408 op = le32_to_cpu(xp->cmd_and_length);
409 tp->ipcss = xp->lower_setup.ip_fields.ipcss;
410 tp->ipcso = xp->lower_setup.ip_fields.ipcso;
411 tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse);
412 tp->tucss = xp->upper_setup.tcp_fields.tucss;
413 tp->tucso = xp->upper_setup.tcp_fields.tucso;
414 tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse);
415 tp->paylen = op & 0xfffff;
416 tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len;
417 tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss);
418 tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0;
419 tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
420 tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
421 tp->tso_frames = 0;
422 if (tp->tucso == 0) { // this is probably wrong
423 DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
424 tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
425 }
426 return;
1b0009db
AZ		 427 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
428 // data descriptor
7c23b892 429 tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
1b0009db
AZ		 430 tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0;
431 } else
432 // legacy descriptor
433 tp->cptse = 0;
7c23b892 434
8f2e8d1f
AL		 435 if (vlan_enabled(s) && is_vlan_txd(txd_lower) &&
436 (tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) {
437 tp->vlan_needed = 1;
438 cpu_to_be16wu((uint16_t *)(tp->vlan_header),
439 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
440 cpu_to_be16wu((uint16_t *)(tp->vlan_header + 2),
441 le16_to_cpu(dp->upper.fields.special));
442 }
443
7c23b892 444 addr = le64_to_cpu(dp->buffer_addr);
1b0009db 445 if (tp->tse && tp->cptse) {
7c23b892
AZ		 446 hdr = tp->hdr_len;
447 msh = hdr + tp->mss;
1b0009db
AZ		 448 do {
449 bytes = split_size;
450 if (tp->size + bytes > msh)
451 bytes = msh - tp->size;
452 cpu_physical_memory_read(addr, tp->data + tp->size, bytes);
453 if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
454 memmove(tp->header, tp->data, hdr);
455 tp->size = sz;
456 addr += bytes;
457 if (sz == msh) {
458 xmit_seg(s);
459 memmove(tp->data, tp->header, hdr);
460 tp->size = hdr;
461 }
462 } while (split_size -= bytes);
463 } else if (!tp->tse && tp->cptse) {
464 // context descriptor TSE is not set, while data descriptor TSE is set
465 DBGOUT(TXERR, "TCP segmentaion Error\n");
466 } else {
467 cpu_physical_memory_read(addr, tp->data + tp->size, split_size);
468 tp->size += split_size;
7c23b892 469 }
7c23b892
AZ		 470
471 if (!(txd_lower & E1000_TXD_CMD_EOP))
472 return;
1b0009db 473 if (!(tp->tse && tp->cptse && tp->size < hdr))
7c23b892
AZ		 474 xmit_seg(s);
475 tp->tso_frames = 0;
476 tp->sum_needed = 0;
8f2e8d1f 477 tp->vlan_needed = 0;
7c23b892 478 tp->size = 0;
1b0009db 479 tp->cptse = 0;
7c23b892
AZ		 480}
481
482static uint32_t
c227f099 483txdesc_writeback(target_phys_addr_t base, struct e1000_tx_desc *dp)
7c23b892
AZ		 484{
485 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
486
487 if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
488 return 0;
489 txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) &
490 ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU);
491 dp->upper.data = cpu_to_le32(txd_upper);
492 cpu_physical_memory_write(base + ((char *)&dp->upper - (char *)dp),
493 (void *)&dp->upper, sizeof(dp->upper));
494 return E1000_ICR_TXDW;
495}
496
497static void
498start_xmit(E1000State *s)
499{
c227f099 500 target_phys_addr_t base;
7c23b892
AZ		 501 struct e1000_tx_desc desc;
502 uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
503
504 if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) {
505 DBGOUT(TX, "tx disabled\n");
506 return;
507 }
508
509 while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
510 base = ((uint64_t)s->mac_reg[TDBAH] << 32) + s->mac_reg[TDBAL] +
511 sizeof(struct e1000_tx_desc) * s->mac_reg[TDH];
512 cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));
513
514 DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
6106075b 515 (void *)(intptr_t)desc.buffer_addr, desc.lower.data,
7c23b892
AZ		 516 desc.upper.data);
517
518 process_tx_desc(s, &desc);
519 cause |= txdesc_writeback(base, &desc);
520
521 if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN])
522 s->mac_reg[TDH] = 0;
523 /*
524 * the following could happen only if guest sw assigns
525 * bogus values to TDT/TDLEN.
526 * there's nothing too intelligent we could do about this.
527 */
528 if (s->mac_reg[TDH] == tdh_start) {
529 DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n",
530 tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]);
531 break;
532 }
533 }
534 set_ics(s, 0, cause);
535}
536
537static int
538receive_filter(E1000State *s, const uint8_t *buf, int size)
539{
540 static uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
541 static int mta_shift[] = {4, 3, 2, 0};
542 uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp;
543
8f2e8d1f
AL		 544 if (is_vlan_packet(s, buf) && vlan_rx_filter_enabled(s)) {
545 uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14));
546 uint32_t vfta = le32_to_cpup((uint32_t *)(s->mac_reg + VFTA) +
547 ((vid >> 5) & 0x7f));
548 if ((vfta & (1 << (vid & 0x1f))) == 0)
549 return 0;
550 }
551
7c23b892
AZ		 552 if (rctl & E1000_RCTL_UPE) // promiscuous
553 return 1;
554
555 if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast
556 return 1;
557
558 if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast))
559 return 1;
560
561 for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) {
562 if (!(rp[1] & E1000_RAH_AV))
563 continue;
564 ra[0] = cpu_to_le32(rp[0]);
565 ra[1] = cpu_to_le32(rp[1]);
566 if (!memcmp(buf, (uint8_t *)ra, 6)) {
567 DBGOUT(RXFILTER,
568 "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
569 (int)(rp - s->mac_reg - RA)/2,
570 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
571 return 1;
572 }
573 }
574 DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n",
575 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
576
577 f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
578 f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff;
579 if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f)))
580 return 1;
581 DBGOUT(RXFILTER,
582 "dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n",
583 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
584 (rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5,
585 s->mac_reg[MTA + (f >> 5)]);
586
587 return 0;
588}
589
99ed7e30
AL		 590static void
591e1000_set_link_status(VLANClientState *vc)
592{
593 E1000State *s = vc->opaque;
594 uint32_t old_status = s->mac_reg[STATUS];
595
596 if (vc->link_down)
597 s->mac_reg[STATUS] &= ~E1000_STATUS_LU;
598 else
599 s->mac_reg[STATUS] |= E1000_STATUS_LU;
600
601 if (s->mac_reg[STATUS] != old_status)
602 set_ics(s, 0, E1000_ICR_LSC);
603}
604
7c23b892 605static int
e3f5ec2b 606e1000_can_receive(VLANClientState *vc)
7c23b892 607{
e3f5ec2b 608 E1000State *s = vc->opaque;
7c23b892 609
4105de67 610 return (s->mac_reg[RCTL] & E1000_RCTL_EN);
7c23b892
AZ		 611}
612
4f1c942b 613static ssize_t
e3f5ec2b 614e1000_receive(VLANClientState *vc, const uint8_t *buf, size_t size)
7c23b892 615{
e3f5ec2b 616 E1000State *s = vc->opaque;
7c23b892 617 struct e1000_rx_desc desc;
c227f099 618 target_phys_addr_t base;
7c23b892
AZ		 619 unsigned int n, rdt;
620 uint32_t rdh_start;
8f2e8d1f
AL		 621 uint16_t vlan_special = 0;
622 uint8_t vlan_status = 0, vlan_offset = 0;
7c23b892
AZ		 623
624 if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))
4f1c942b 625 return -1;
7c23b892
AZ		 626
627 if (size > s->rxbuf_size) {
cda9046b
MM		 628 DBGOUT(RX, "packet too large for buffers (%lu > %d)\n",
629 (unsigned long)size, s->rxbuf_size);
4f1c942b 630 return -1;
7c23b892
AZ		 631 }
632
633 if (!receive_filter(s, buf, size))
4f1c942b 634 return size;
7c23b892 635
8f2e8d1f
AL		 636 if (vlan_enabled(s) && is_vlan_packet(s, buf)) {
637 vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(buf + 14)));
638 memmove((void *)(buf + 4), buf, 12);
639 vlan_status = E1000_RXD_STAT_VP;
640 vlan_offset = 4;
641 size -= 4;
642 }
643
7c23b892
AZ		 644 rdh_start = s->mac_reg[RDH];
645 size += 4; // for the header
646 do {
647 if (s->mac_reg[RDH] == s->mac_reg[RDT] && s->check_rxov) {
648 set_ics(s, 0, E1000_ICS_RXO);
4f1c942b 649 return -1;
7c23b892
AZ		 650 }
651 base = ((uint64_t)s->mac_reg[RDBAH] << 32) + s->mac_reg[RDBAL] +
652 sizeof(desc) * s->mac_reg[RDH];
653 cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));
8f2e8d1f
AL		 654 desc.special = vlan_special;
655 desc.status |= (vlan_status | E1000_RXD_STAT_DD);
7c23b892
AZ		 656 if (desc.buffer_addr) {
657 cpu_physical_memory_write(le64_to_cpu(desc.buffer_addr),
8f2e8d1f 658 (void *)(buf + vlan_offset), size);
7c23b892
AZ		 659 desc.length = cpu_to_le16(size);
660 desc.status |= E1000_RXD_STAT_EOP|E1000_RXD_STAT_IXSM;
661 } else // as per intel docs; skip descriptors with null buf addr
662 DBGOUT(RX, "Null RX descriptor!!\n");
663 cpu_physical_memory_write(base, (void *)&desc, sizeof(desc));
664
665 if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])
666 s->mac_reg[RDH] = 0;
667 s->check_rxov = 1;
668 /* see comment in start_xmit; same here */
669 if (s->mac_reg[RDH] == rdh_start) {
670 DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",
671 rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);
672 set_ics(s, 0, E1000_ICS_RXO);
4f1c942b 673 return -1;
7c23b892
AZ		 674 }
675 } while (desc.buffer_addr == 0);
676
677 s->mac_reg[GPRC]++;
678 s->mac_reg[TPR]++;
679 n = s->mac_reg[TORL];
680 if ((s->mac_reg[TORL] += size) < n)
681 s->mac_reg[TORH]++;
682
683 n = E1000_ICS_RXT0;
684 if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
685 rdt += s->mac_reg[RDLEN] / sizeof(desc);
bf16cc8f
AL		 686 if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >>
687 s->rxbuf_min_shift)
7c23b892
AZ		 688 n |= E1000_ICS_RXDMT0;
689
690 set_ics(s, 0, n);
4f1c942b
MM		 691
692 return size;
7c23b892
AZ		 693}
694
695static uint32_t
696mac_readreg(E1000State *s, int index)
697{
698 return s->mac_reg[index];
699}
700
701static uint32_t
702mac_icr_read(E1000State *s, int index)
703{
704 uint32_t ret = s->mac_reg[ICR];
705
706 DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
707 set_interrupt_cause(s, 0, 0);
708 return ret;
709}
710
711static uint32_t
712mac_read_clr4(E1000State *s, int index)
713{
714 uint32_t ret = s->mac_reg[index];
715
716 s->mac_reg[index] = 0;
717 return ret;
718}
719
720static uint32_t
721mac_read_clr8(E1000State *s, int index)
722{
723 uint32_t ret = s->mac_reg[index];
724
725 s->mac_reg[index] = 0;
726 s->mac_reg[index-1] = 0;
727 return ret;
728}
729
730static void
731mac_writereg(E1000State *s, int index, uint32_t val)
732{
733 s->mac_reg[index] = val;
734}
735
736static void
737set_rdt(E1000State *s, int index, uint32_t val)
738{
739 s->check_rxov = 0;
740 s->mac_reg[index] = val & 0xffff;
741}
742
743static void
744set_16bit(E1000State *s, int index, uint32_t val)
745{
746 s->mac_reg[index] = val & 0xffff;
747}
748
749static void
750set_dlen(E1000State *s, int index, uint32_t val)
751{
752 s->mac_reg[index] = val & 0xfff80;
753}
754
755static void
756set_tctl(E1000State *s, int index, uint32_t val)
757{
758 s->mac_reg[index] = val;
759 s->mac_reg[TDT] &= 0xffff;
760 start_xmit(s);
761}
762
763static void
764set_icr(E1000State *s, int index, uint32_t val)
765{
766 DBGOUT(INTERRUPT, "set_icr %x\n", val);
767 set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);
768}
769
770static void
771set_imc(E1000State *s, int index, uint32_t val)
772{
773 s->mac_reg[IMS] &= ~val;
774 set_ics(s, 0, 0);
775}
776
777static void
778set_ims(E1000State *s, int index, uint32_t val)
779{
780 s->mac_reg[IMS] |= val;
781 set_ics(s, 0, 0);
782}
783
784#define getreg(x) [x] = mac_readreg
785static uint32_t (*macreg_readops[])(E1000State *, int) = {
786 getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
787 getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
788 getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
789 getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
b1332393 790 getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
7c23b892
AZ		 791
792 [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4,
793 [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4,
794 [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read,
795 [CRCERRS ... MPC] = &mac_readreg,
796 [RA ... RA+31] = &mac_readreg,
797 [MTA ... MTA+127] = &mac_readreg,
8f2e8d1f 798 [VFTA ... VFTA+127] = &mac_readreg,
7c23b892 799};
b1503cda 800enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
7c23b892
AZ		 801
802#define putreg(x) [x] = mac_writereg
803static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
804 putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
805 putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
cab3c825 806 putreg(RDBAL), putreg(LEDCTL), putreg(VET),
7c23b892
AZ		 807 [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
808 [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
809 [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
810 [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
cab3c825 811 [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
7c23b892
AZ		 812 [RA ... RA+31] = &mac_writereg,
813 [MTA ... MTA+127] = &mac_writereg,
8f2e8d1f 814 [VFTA ... VFTA+127] = &mac_writereg,
7c23b892 815};
b1503cda 816enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
7c23b892
AZ		 817
818static void
c227f099 819e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
7c23b892
AZ		 820{
821 E1000State *s = opaque;
8da3ff18 822 unsigned int index = (addr & 0x1ffff) >> 2;
7c23b892 823
6b59fc74
AJ		 824#ifdef TARGET_WORDS_BIGENDIAN
825 val = bswap32(val);
826#endif
7c23b892 827 if (index < NWRITEOPS && macreg_writeops[index])
6b59fc74 828 macreg_writeops[index](s, index, val);
7c23b892
AZ		 829 else if (index < NREADOPS && macreg_readops[index])
830 DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04x\n", index<<2, val);
831 else
832 DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08x\n",
833 index<<2, val);
834}
835
836static void
c227f099 837e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
7c23b892
AZ		 838{
839 // emulate hw without byte enables: no RMW
840 e1000_mmio_writel(opaque, addr & ~3,
6b59fc74 841 (val & 0xffff) << (8*(addr & 3)));
7c23b892
AZ		 842}
843
844static void
c227f099 845e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
7c23b892
AZ		 846{
847 // emulate hw without byte enables: no RMW
848 e1000_mmio_writel(opaque, addr & ~3,
6b59fc74 849 (val & 0xff) << (8*(addr & 3)));
7c23b892
AZ		 850}
851
852static uint32_t
c227f099 853e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
7c23b892
AZ		 854{
855 E1000State *s = opaque;
8da3ff18 856 unsigned int index = (addr & 0x1ffff) >> 2;
7c23b892
AZ		 857
858 if (index < NREADOPS && macreg_readops[index])
6b59fc74
AJ		 859 {
860 uint32_t val = macreg_readops[index](s, index);
861#ifdef TARGET_WORDS_BIGENDIAN
862 val = bswap32(val);
863#endif
864 return val;
865 }
7c23b892
AZ		 866 DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
867 return 0;
868}
869
870static uint32_t
c227f099 871e1000_mmio_readb(void *opaque, target_phys_addr_t addr)
7c23b892 872{
6b59fc74 873 return ((e1000_mmio_readl(opaque, addr & ~3)) >>
7c23b892
AZ		 874 (8 * (addr & 3))) & 0xff;
875}
876
877static uint32_t
c227f099 878e1000_mmio_readw(void *opaque, target_phys_addr_t addr)
7c23b892 879{
6b59fc74
AJ		 880 return ((e1000_mmio_readl(opaque, addr & ~3)) >>
881 (8 * (addr & 3))) & 0xffff;
7c23b892
AZ		 882}
883
e482dc3e 884static bool is_version_1(void *opaque, int version_id)
7c23b892 885{
e482dc3e 886 return version_id == 1;
7c23b892
AZ		 887}
888
e482dc3e
JQ		 889static const VMStateDescription vmstate_e1000 = {
890 .name = "e1000",
891 .version_id = 2,
892 .minimum_version_id = 1,
893 .minimum_version_id_old = 1,
894 .fields = (VMStateField []) {
895 VMSTATE_PCI_DEVICE(dev, E1000State),
896 VMSTATE_UNUSED_TEST(is_version_1, 4), /* was instance id */
897 VMSTATE_UNUSED(4), /* Was mmio_base. */
898 VMSTATE_UINT32(rxbuf_size, E1000State),
899 VMSTATE_UINT32(rxbuf_min_shift, E1000State),
900 VMSTATE_UINT32(eecd_state.val_in, E1000State),
901 VMSTATE_UINT16(eecd_state.bitnum_in, E1000State),
902 VMSTATE_UINT16(eecd_state.bitnum_out, E1000State),
903 VMSTATE_UINT16(eecd_state.reading, E1000State),
904 VMSTATE_UINT32(eecd_state.old_eecd, E1000State),
905 VMSTATE_UINT8(tx.ipcss, E1000State),
906 VMSTATE_UINT8(tx.ipcso, E1000State),
907 VMSTATE_UINT16(tx.ipcse, E1000State),
908 VMSTATE_UINT8(tx.tucss, E1000State),
909 VMSTATE_UINT8(tx.tucso, E1000State),
910 VMSTATE_UINT16(tx.tucse, E1000State),
911 VMSTATE_UINT32(tx.paylen, E1000State),
912 VMSTATE_UINT8(tx.hdr_len, E1000State),
913 VMSTATE_UINT16(tx.mss, E1000State),
914 VMSTATE_UINT16(tx.size, E1000State),
915 VMSTATE_UINT16(tx.tso_frames, E1000State),
916 VMSTATE_UINT8(tx.sum_needed, E1000State),
917 VMSTATE_INT8(tx.ip, E1000State),
918 VMSTATE_INT8(tx.tcp, E1000State),
919 VMSTATE_BUFFER(tx.header, E1000State),
920 VMSTATE_BUFFER(tx.data, E1000State),
921 VMSTATE_UINT16_ARRAY(eeprom_data, E1000State, 64),
922 VMSTATE_UINT16_ARRAY(phy_reg, E1000State, 0x20),
923 VMSTATE_UINT32(mac_reg[CTRL], E1000State),
924 VMSTATE_UINT32(mac_reg[EECD], E1000State),
925 VMSTATE_UINT32(mac_reg[EERD], E1000State),
926 VMSTATE_UINT32(mac_reg[GPRC], E1000State),
927 VMSTATE_UINT32(mac_reg[GPTC], E1000State),
928 VMSTATE_UINT32(mac_reg[ICR], E1000State),
929 VMSTATE_UINT32(mac_reg[ICS], E1000State),
930 VMSTATE_UINT32(mac_reg[IMC], E1000State),
931 VMSTATE_UINT32(mac_reg[IMS], E1000State),
932 VMSTATE_UINT32(mac_reg[LEDCTL], E1000State),
933 VMSTATE_UINT32(mac_reg[MANC], E1000State),
934 VMSTATE_UINT32(mac_reg[MDIC], E1000State),
935 VMSTATE_UINT32(mac_reg[MPC], E1000State),
936 VMSTATE_UINT32(mac_reg[PBA], E1000State),
937 VMSTATE_UINT32(mac_reg[RCTL], E1000State),
938 VMSTATE_UINT32(mac_reg[RDBAH], E1000State),
939 VMSTATE_UINT32(mac_reg[RDBAL], E1000State),
940 VMSTATE_UINT32(mac_reg[RDH], E1000State),
941 VMSTATE_UINT32(mac_reg[RDLEN], E1000State),
942 VMSTATE_UINT32(mac_reg[RDT], E1000State),
943 VMSTATE_UINT32(mac_reg[STATUS], E1000State),
944 VMSTATE_UINT32(mac_reg[SWSM], E1000State),
945 VMSTATE_UINT32(mac_reg[TCTL], E1000State),
946 VMSTATE_UINT32(mac_reg[TDBAH], E1000State),
947 VMSTATE_UINT32(mac_reg[TDBAL], E1000State),
948 VMSTATE_UINT32(mac_reg[TDH], E1000State),
949 VMSTATE_UINT32(mac_reg[TDLEN], E1000State),
950 VMSTATE_UINT32(mac_reg[TDT], E1000State),
951 VMSTATE_UINT32(mac_reg[TORH], E1000State),
952 VMSTATE_UINT32(mac_reg[TORL], E1000State),
953 VMSTATE_UINT32(mac_reg[TOTH], E1000State),
954 VMSTATE_UINT32(mac_reg[TOTL], E1000State),
955 VMSTATE_UINT32(mac_reg[TPR], E1000State),
956 VMSTATE_UINT32(mac_reg[TPT], E1000State),
957 VMSTATE_UINT32(mac_reg[TXDCTL], E1000State),
958 VMSTATE_UINT32(mac_reg[WUFC], E1000State),
959 VMSTATE_UINT32(mac_reg[VET], E1000State),
960 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32),
961 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, 128),
962 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA, 128),
963 VMSTATE_END_OF_LIST()
964 }
965};
7c23b892 966
88b4e9db 967static const uint16_t e1000_eeprom_template[64] = {
7c23b892
AZ		 968 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,
969 0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040,
970 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,
971 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,
972 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,
973 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
974 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
975 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000,
976};
977
88b4e9db 978static const uint16_t phy_reg_init[] = {
7c23b892
AZ		 979 [PHY_CTRL] = 0x1140, [PHY_STATUS] = 0x796d, // link initially up
980 [PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT,
981 [PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360,
982 [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1,
983 [PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00,
700f6e2c 984 [M88E1000_PHY_SPEC_STATUS] = 0xac00,
7c23b892
AZ		 985};
986
88b4e9db 987static const uint32_t mac_reg_init[] = {
7c23b892
AZ		 988 [PBA] = 0x00100030,
989 [LEDCTL] = 0x602,
990 [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
991 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU,
992 [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
993 E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK |
994 E1000_STATUS_SPEED_1000 | E1000_STATUS_FD |
995 E1000_STATUS_LU,
996 [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN |
997 E1000_MANC_ARP_EN | E1000_MANC_0298_EN |
998 E1000_MANC_RMCP_EN,
999};
1000
1001/* PCI interface */
1002
d60efc6b 1003static CPUWriteMemoryFunc * const e1000_mmio_write[] = {
7c23b892
AZ		 1004 e1000_mmio_writeb, e1000_mmio_writew, e1000_mmio_writel
1005};
1006
d60efc6b 1007static CPUReadMemoryFunc * const e1000_mmio_read[] = {
7c23b892
AZ		 1008 e1000_mmio_readb, e1000_mmio_readw, e1000_mmio_readl
1009};
1010
1011static void
1012e1000_mmio_map(PCIDevice *pci_dev, int region_num,
1013 uint32_t addr, uint32_t size, int type)
1014{
7d9e52bd 1015 E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
f65ed4c1
AL		 1016 int i;
1017 const uint32_t excluded_regs[] = {
1018 E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
1019 E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
1020 };
1021
7c23b892
AZ		 1022
1023 DBGOUT(MMIO, "e1000_mmio_map addr=0x%08x 0x%08x\n", addr, size);
1024
7c23b892 1025 cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index);
f65ed4c1
AL		 1026 qemu_register_coalesced_mmio(addr, excluded_regs[0]);
1027
1028 for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++)
1029 qemu_register_coalesced_mmio(addr + excluded_regs[i] + 4,
1030 excluded_regs[i + 1] -
1031 excluded_regs[i] - 4);
7c23b892
AZ		 1032}
1033
b946a153
AL		 1034static void
1035e1000_cleanup(VLANClientState *vc)
1036{
1037 E1000State *d = vc->opaque;
1038
fbdaa002 1039 d->vc = NULL;
b946a153
AL		 1040}
1041
4b09be85
AL		 1042static int
1043pci_e1000_uninit(PCIDevice *dev)
1044{
7d9e52bd 1045 E1000State *d = DO_UPCAST(E1000State, dev, dev);
4b09be85
AL		 1046
1047 cpu_unregister_io_memory(d->mmio_index);
fbdaa002 1048 qemu_del_vlan_client(d->vc);
e482dc3e 1049 vmstate_unregister(&vmstate_e1000, d);
4b09be85
AL		 1050 return 0;
1051}
1052
32c86e95
BS		 1053static void e1000_reset(void *opaque)
1054{
1055 E1000State *d = opaque;
1056
1057 memset(d->phy_reg, 0, sizeof d->phy_reg);
1058 memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
1059 memset(d->mac_reg, 0, sizeof d->mac_reg);
1060 memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
1061 d->rxbuf_min_shift = 1;
1062 memset(&d->tx, 0, sizeof d->tx);
1063}
1064
81a322d4 1065static int pci_e1000_init(PCIDevice *pci_dev)
7c23b892 1066{
7d9e52bd 1067 E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
7c23b892 1068 uint8_t *pci_conf;
7c23b892 1069 uint16_t checksum = 0;
7c23b892 1070 int i;
fbdaa002 1071 uint8_t *macaddr;
aff427a1 1072
7c23b892 1073 pci_conf = d->dev.config;
7c23b892 1074
deb54399
AL		 1075 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
1076 pci_config_set_device_id(pci_conf, E1000_DEVID);
7c23b892
AZ		 1077 *(uint16_t *)(pci_conf+0x04) = cpu_to_le16(0x0407);
1078 *(uint16_t *)(pci_conf+0x06) = cpu_to_le16(0x0010);
1079 pci_conf[0x08] = 0x03;
173a543b 1080 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
7c23b892
AZ		 1081 pci_conf[0x0c] = 0x10;
1082
1083 pci_conf[0x3d] = 1; // interrupt pin 0
1084
1eed09cb 1085 d->mmio_index = cpu_register_io_memory(e1000_mmio_read,
7c23b892
AZ		 1086 e1000_mmio_write, d);
1087
28c2c264 1088 pci_register_bar((PCIDevice *)d, 0, PNPMMIO_SIZE,
7c23b892
AZ		 1089 PCI_ADDRESS_SPACE_MEM, e1000_mmio_map);
1090
28c2c264 1091 pci_register_bar((PCIDevice *)d, 1, IOPORT_SIZE,
7c23b892
AZ		 1092 PCI_ADDRESS_SPACE_IO, ioport_map);
1093
7c23b892
AZ		 1094 memmove(d->eeprom_data, e1000_eeprom_template,
1095 sizeof e1000_eeprom_template);
fbdaa002
GH		 1096 qemu_macaddr_default_if_unset(&d->conf.macaddr);
1097 macaddr = d->conf.macaddr.a;
7c23b892 1098 for (i = 0; i < 3; i++)
9d07d757 1099 d->eeprom_data[i] = (macaddr[2*i+1]<<8) | macaddr[2*i];
7c23b892
AZ		 1100 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1101 checksum += d->eeprom_data[i];
1102 checksum = (uint16_t) EEPROM_SUM - checksum;
1103 d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum;
1104
fbdaa002
GH		 1105 d->vc = qemu_new_vlan_client(NET_CLIENT_TYPE_NIC,
1106 d->conf.vlan, d->conf.peer,
1107 d->dev.qdev.info->name, d->dev.qdev.id,
1108 e1000_can_receive, e1000_receive, NULL,
463af534 1109 NULL, e1000_cleanup, d);
99ed7e30 1110 d->vc->link_status_changed = e1000_set_link_status;
7c23b892 1111
9d07d757 1112 qemu_format_nic_info_str(d->vc, macaddr);
7c23b892 1113
e482dc3e 1114 vmstate_register(-1, &vmstate_e1000, d);
32c86e95 1115 e1000_reset(d);
fbdaa002
GH		 1116
1117#if 0 /* rom bev support is broken -> can't load unconditionally */
1118 if (!pci_dev->qdev.hotplugged) {
1119 static int loaded = 0;
1120 if (!loaded) {
1121 rom_add_option("pxe-e1000.bin");
1122 loaded = 1;
1123 }
1124 }
1125#endif
81a322d4 1126 return 0;
9d07d757 1127}
72da4208 1128
fbdaa002
GH		 1129static void qdev_e1000_reset(DeviceState *dev)
1130{
1131 E1000State *d = DO_UPCAST(E1000State, dev.qdev, dev);
1132 e1000_reset(d);
1133}
1134
0aab0d3a 1135static PCIDeviceInfo e1000_info = {
fbdaa002
GH		 1136 .qdev.name = "e1000",
1137 .qdev.desc = "Intel Gigabit Ethernet",
1138 .qdev.size = sizeof(E1000State),
1139 .qdev.reset = qdev_e1000_reset,
1140 .init = pci_e1000_init,
1141 .exit = pci_e1000_uninit,
1142 .qdev.props = (Property[]) {
1143 DEFINE_NIC_PROPERTIES(E1000State, conf),
1144 DEFINE_PROP_END_OF_LIST(),
1145 }
0aab0d3a
GH		 1146};
1147
9d07d757
PB		 1148static void e1000_register_devices(void)
1149{
0aab0d3a 1150 pci_qdev_register(&e1000_info);
7c23b892 1151}
9d07d757
PB		 1152
1153device_init(e1000_register_devices)
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