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7c23b892
AZ		 1/*
2 * QEMU e1000 emulation
3 *
2758aa52
MT		 4 * Software developer's manual:
5 * http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf
6 *
7c23b892
AZ		 7 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
8 * Copyright (c) 2008 Qumranet
9 * Based on work done by:
10 * Copyright (c) 2007 Dan Aloni
11 * Copyright (c) 2004 Antony T Curtis
12 *
13 * This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU Lesser General Public
15 * License as published by the Free Software Foundation; either
16 * version 2 of the License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 * Lesser General Public License for more details.
22 *
23 * You should have received a copy of the GNU Lesser General Public
8167ee88 24 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7c23b892
AZ		 25 */
26
27
28#include "hw.h"
a2cb15b0 29#include "pci/pci.h"
7c23b892 30#include "net.h"
7200ac3c 31#include "net/checksum.h"
fbdaa002 32#include "loader.h"
1ca4d09a 33#include "sysemu.h"
62ecbd35 34#include "dma.h"
7c23b892 35
7c23b892
AZ		 36#include "e1000_hw.h"
37
27124888 38#define E1000_DEBUG
7c23b892 39
27124888 40#ifdef E1000_DEBUG
7c23b892
AZ		 41enum {
42 DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
43 DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
44 DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
f9c1cdf4 45 DEBUG_RXFILTER, DEBUG_PHY, DEBUG_NOTYET,
7c23b892
AZ		 46};
47#define DBGBIT(x) (1<<DEBUG_##x)
48static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
49
6c7f4b47 50#define DBGOUT(what, fmt, ...) do { \
7c23b892 51 if (debugflags & DBGBIT(what)) \
6c7f4b47 52 fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \
7c23b892
AZ		 53 } while (0)
54#else
6c7f4b47 55#define DBGOUT(what, fmt, ...) do {} while (0)
7c23b892
AZ		 56#endif
57
58#define IOPORT_SIZE 0x40
e94bbefe 59#define PNPMMIO_SIZE 0x20000
78aeb23e 60#define MIN_BUF_SIZE 60 /* Min. octets in an ethernet frame sans FCS */
7c23b892 61
b0d9ffcd
MC		 62/* this is the size past which hardware will drop packets when setting LPE=0 */
63#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
64
7c23b892
AZ		 65/*
66 * HW models:
67 * E1000_DEV_ID_82540EM works with Windows and Linux
68 * E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22,
69 * appears to perform better than 82540EM, but breaks with Linux 2.6.18
70 * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
71 * Others never tested
72 */
73enum { E1000_DEVID = E1000_DEV_ID_82540EM };
74
75/*
76 * May need to specify additional MAC-to-PHY entries --
77 * Intel's Windows driver refuses to initialize unless they match
78 */
79enum {
80 PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 :
81 E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 :
82 /* default to E1000_DEV_ID_82540EM */ 0xc20
83};
84
85typedef struct E1000State_st {
86 PCIDevice dev;
a03e2aec 87 NICState *nic;
fbdaa002 88 NICConf conf;
ad00a9b9
AK		 89 MemoryRegion mmio;
90 MemoryRegion io;
7c23b892
AZ		 91
92 uint32_t mac_reg[0x8000];
93 uint16_t phy_reg[0x20];
94 uint16_t eeprom_data[64];
95
96 uint32_t rxbuf_size;
97 uint32_t rxbuf_min_shift;
7c23b892
AZ		 98 struct e1000_tx {
99 unsigned char header[256];
8f2e8d1f 100 unsigned char vlan_header[4];
b10fec9b 101 /* Fields vlan and data must not be reordered or separated. */
8f2e8d1f 102 unsigned char vlan[4];
7c23b892
AZ		 103 unsigned char data[0x10000];
104 uint16_t size;
105 unsigned char sum_needed;
8f2e8d1f 106 unsigned char vlan_needed;
7c23b892
AZ		 107 uint8_t ipcss;
108 uint8_t ipcso;
109 uint16_t ipcse;
110 uint8_t tucss;
111 uint8_t tucso;
112 uint16_t tucse;
113 uint8_t hdr_len;
114 uint16_t mss;
115 uint32_t paylen;
116 uint16_t tso_frames;
117 char tse;
b6c4f71f
BS		 118 int8_t ip;
119 int8_t tcp;
1b0009db 120 char cptse; // current packet tse bit
7c23b892
AZ		 121 } tx;
122
123 struct {
124 uint32_t val_in; // shifted in from guest driver
125 uint16_t bitnum_in;
126 uint16_t bitnum_out;
127 uint16_t reading;
128 uint32_t old_eecd;
129 } eecd_state;
b9d03e35
JW		 130
131 QEMUTimer *autoneg_timer;
7c23b892
AZ		 132} E1000State;
133
134#define defreg(x) x = (E1000_##x>>2)
135enum {
136 defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
137 defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
138 defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC),
139 defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH),
140 defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT),
141 defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
142 defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
143 defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
144 defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
8f2e8d1f
AL		 145 defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA),
146 defreg(VET),
7c23b892
AZ		 147};
148
71aadd3c
JW		 149static void
150e1000_link_down(E1000State *s)
151{
152 s->mac_reg[STATUS] &= ~E1000_STATUS_LU;
153 s->phy_reg[PHY_STATUS] &= ~MII_SR_LINK_STATUS;
154}
155
156static void
157e1000_link_up(E1000State *s)
158{
159 s->mac_reg[STATUS] |= E1000_STATUS_LU;
160 s->phy_reg[PHY_STATUS] |= MII_SR_LINK_STATUS;
161}
162
b9d03e35
JW		 163static void
164set_phy_ctrl(E1000State *s, int index, uint16_t val)
165{
166 if ((val & MII_CR_AUTO_NEG_EN) && (val & MII_CR_RESTART_AUTO_NEG)) {
167 s->nic->nc.link_down = true;
168 e1000_link_down(s);
169 s->phy_reg[PHY_STATUS] &= ~MII_SR_AUTONEG_COMPLETE;
170 DBGOUT(PHY, "Start link auto negotiation\n");
171 qemu_mod_timer(s->autoneg_timer, qemu_get_clock_ms(vm_clock) + 500);
172 }
173}
174
175static void
176e1000_autoneg_timer(void *opaque)
177{
178 E1000State *s = opaque;
179 s->nic->nc.link_down = false;
180 e1000_link_up(s);
181 s->phy_reg[PHY_STATUS] |= MII_SR_AUTONEG_COMPLETE;
182 DBGOUT(PHY, "Auto negotiation is completed\n");
183}
184
185static void (*phyreg_writeops[])(E1000State *, int, uint16_t) = {
186 [PHY_CTRL] = set_phy_ctrl,
187};
188
189enum { NPHYWRITEOPS = ARRAY_SIZE(phyreg_writeops) };
190
7c23b892 191enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
88b4e9db 192static const char phy_regcap[0x20] = {
7c23b892
AZ		 193 [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
194 [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
195 [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
196 [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
197 [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
700f6e2c 198 [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R
7c23b892
AZ		 199};
200
814cd3ac 201static const uint16_t phy_reg_init[] = {
b9d03e35
JW		 202 [PHY_CTRL] = 0x1140,
203 [PHY_STATUS] = 0x794d, /* link initially up with not completed autoneg */
814cd3ac
MT		 204 [PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT,
205 [PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360,
206 [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1,
207 [PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00,
208 [M88E1000_PHY_SPEC_STATUS] = 0xac00,
209};
210
211static const uint32_t mac_reg_init[] = {
212 [PBA] = 0x00100030,
213 [LEDCTL] = 0x602,
214 [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
215 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU,
216 [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
217 E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK |
218 E1000_STATUS_SPEED_1000 | E1000_STATUS_FD |
219 E1000_STATUS_LU,
220 [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN |
221 E1000_MANC_ARP_EN | E1000_MANC_0298_EN |
222 E1000_MANC_RMCP_EN,
223};
224
7c23b892
AZ		 225static void
226set_interrupt_cause(E1000State *s, int index, uint32_t val)
227{
f1219091
JW		 228 if (val && (E1000_DEVID >= E1000_DEV_ID_82547EI_MOBILE)) {
229 /* Only for 8257x */
7c23b892 230 val |= E1000_ICR_INT_ASSERTED;
f1219091 231 }
7c23b892 232 s->mac_reg[ICR] = val;
b1332393 233 s->mac_reg[ICS] = val;
bc26e55a 234 qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
7c23b892
AZ		 235}
236
237static void
238set_ics(E1000State *s, int index, uint32_t val)
239{
240 DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR],
241 s->mac_reg[IMS]);
242 set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);
243}
244
245static int
246rxbufsize(uint32_t v)
247{
248 v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 |
249 E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 |
250 E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256;
251 switch (v) {
252 case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384:
253 return 16384;
254 case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192:
255 return 8192;
256 case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096:
257 return 4096;
258 case E1000_RCTL_SZ_1024:
259 return 1024;
260 case E1000_RCTL_SZ_512:
261 return 512;
262 case E1000_RCTL_SZ_256:
263 return 256;
264 }
265 return 2048;
266}
267
814cd3ac
MT		 268static void e1000_reset(void *opaque)
269{
270 E1000State *d = opaque;
372254c6
GS		 271 uint8_t *macaddr = d->conf.macaddr.a;
272 int i;
814cd3ac 273
b9d03e35 274 qemu_del_timer(d->autoneg_timer);
814cd3ac
MT		 275 memset(d->phy_reg, 0, sizeof d->phy_reg);
276 memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
277 memset(d->mac_reg, 0, sizeof d->mac_reg);
278 memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
279 d->rxbuf_min_shift = 1;
280 memset(&d->tx, 0, sizeof d->tx);
281
282 if (d->nic->nc.link_down) {
71aadd3c 283 e1000_link_down(d);
814cd3ac 284 }
372254c6
GS		 285
286 /* Some guests expect pre-initialized RAH/RAL (AddrValid flag + MACaddr) */
287 d->mac_reg[RA] = 0;
288 d->mac_reg[RA + 1] = E1000_RAH_AV;
289 for (i = 0; i < 4; i++) {
290 d->mac_reg[RA] |= macaddr[i] << (8 * i);
291 d->mac_reg[RA + 1] |= (i < 2) ? macaddr[i + 4] << (8 * i) : 0;
292 }
814cd3ac
MT		 293}
294
cab3c825
KW		 295static void
296set_ctrl(E1000State *s, int index, uint32_t val)
297{
298 /* RST is self clearing */
299 s->mac_reg[CTRL] = val & ~E1000_CTRL_RST;
300}
301
7c23b892
AZ		 302static void
303set_rx_control(E1000State *s, int index, uint32_t val)
304{
305 s->mac_reg[RCTL] = val;
306 s->rxbuf_size = rxbufsize(val);
307 s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1;
308 DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],
309 s->mac_reg[RCTL]);
e8b4c680 310 qemu_flush_queued_packets(&s->nic->nc);
7c23b892
AZ		 311}
312
313static void
314set_mdic(E1000State *s, int index, uint32_t val)
315{
316 uint32_t data = val & E1000_MDIC_DATA_MASK;
317 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
318
319 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy #
320 val = s->mac_reg[MDIC] | E1000_MDIC_ERROR;
321 else if (val & E1000_MDIC_OP_READ) {
322 DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);
323 if (!(phy_regcap[addr] & PHY_R)) {
324 DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr);
325 val |= E1000_MDIC_ERROR;
326 } else
327 val = (val ^ data) | s->phy_reg[addr];
328 } else if (val & E1000_MDIC_OP_WRITE) {
329 DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);
330 if (!(phy_regcap[addr] & PHY_W)) {
331 DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr);
332 val |= E1000_MDIC_ERROR;
b9d03e35
JW		 333 } else {
334 if (addr < NPHYWRITEOPS && phyreg_writeops[addr]) {
335 phyreg_writeops[addr](s, index, data);
336 }
7c23b892 337 s->phy_reg[addr] = data;
b9d03e35 338 }
7c23b892
AZ		 339 }
340 s->mac_reg[MDIC] = val | E1000_MDIC_READY;
17fbbb0b
JW		 341
342 if (val & E1000_MDIC_INT_EN) {
343 set_ics(s, 0, E1000_ICR_MDAC);
344 }
7c23b892
AZ		 345}
346
347static uint32_t
348get_eecd(E1000State *s, int index)
349{
350 uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd;
351
352 DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n",
353 s->eecd_state.bitnum_out, s->eecd_state.reading);
354 if (!s->eecd_state.reading ||
355 ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >>
356 ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1)
357 ret |= E1000_EECD_DO;
358 return ret;
359}
360
361static void
362set_eecd(E1000State *s, int index, uint32_t val)
363{
364 uint32_t oldval = s->eecd_state.old_eecd;
365
366 s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
367 E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
9651ac55
IT		 368 if (!(E1000_EECD_CS & val)) // CS inactive; nothing to do
369 return;
370 if (E1000_EECD_CS & (val ^ oldval)) { // CS rise edge; reset state
371 s->eecd_state.val_in = 0;
372 s->eecd_state.bitnum_in = 0;
373 s->eecd_state.bitnum_out = 0;
374 s->eecd_state.reading = 0;
375 }
7c23b892
AZ		 376 if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge
377 return;
378 if (!(E1000_EECD_SK & val)) { // falling edge
379 s->eecd_state.bitnum_out++;
380 return;
381 }
7c23b892
AZ		 382 s->eecd_state.val_in <<= 1;
383 if (val & E1000_EECD_DI)
384 s->eecd_state.val_in |= 1;
385 if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) {
386 s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1;
387 s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) ==
388 EEPROM_READ_OPCODE_MICROWIRE);
389 }
390 DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
391 s->eecd_state.bitnum_in, s->eecd_state.bitnum_out,
392 s->eecd_state.reading);
393}
394
395static uint32_t
396flash_eerd_read(E1000State *s, int x)
397{
398 unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START;
399
b1332393
BP		 400 if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0)
401 return (s->mac_reg[EERD]);
402
7c23b892 403 if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG)
b1332393
BP		 404 return (E1000_EEPROM_RW_REG_DONE | r);
405
406 return ((s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) |
407 E1000_EEPROM_RW_REG_DONE | r);
7c23b892
AZ		 408}
409
7c23b892
AZ		 410static void
411putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse)
412{
c6a6a5e3
AL		 413 uint32_t sum;
414
7c23b892
AZ		 415 if (cse && cse < n)
416 n = cse + 1;
c6a6a5e3
AL		 417 if (sloc < n-1) {
418 sum = net_checksum_add(n-css, data+css);
7c23b892 419 cpu_to_be16wu((uint16_t *)(data + sloc),
c6a6a5e3
AL		 420 net_checksum_finish(sum));
421 }
7c23b892
AZ		 422}
423
8f2e8d1f
AL		 424static inline int
425vlan_enabled(E1000State *s)
426{
427 return ((s->mac_reg[CTRL] & E1000_CTRL_VME) != 0);
428}
429
430static inline int
431vlan_rx_filter_enabled(E1000State *s)
432{
433 return ((s->mac_reg[RCTL] & E1000_RCTL_VFE) != 0);
434}
435
436static inline int
437is_vlan_packet(E1000State *s, const uint8_t *buf)
438{
439 return (be16_to_cpup((uint16_t *)(buf + 12)) ==
440 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
441}
442
443static inline int
444is_vlan_txd(uint32_t txd_lower)
445{
446 return ((txd_lower & E1000_TXD_CMD_VLE) != 0);
447}
448
55e8d1ce
MT		 449/* FCS aka Ethernet CRC-32. We don't get it from backends and can't
450 * fill it in, just pad descriptor length by 4 bytes unless guest
a05e8a6e 451 * told us to strip it off the packet. */
55e8d1ce
MT		 452static inline int
453fcs_len(E1000State *s)
454{
455 return (s->mac_reg[RCTL] & E1000_RCTL_SECRC) ? 0 : 4;
456}
457
93e37d76
JW		 458static void
459e1000_send_packet(E1000State *s, const uint8_t *buf, int size)
460{
461 if (s->phy_reg[PHY_CTRL] & MII_CR_LOOPBACK) {
462 s->nic->nc.info->receive(&s->nic->nc, buf, size);
463 } else {
464 qemu_send_packet(&s->nic->nc, buf, size);
465 }
466}
467
7c23b892
AZ		 468static void
469xmit_seg(E1000State *s)
470{
471 uint16_t len, *sp;
472 unsigned int frames = s->tx.tso_frames, css, sofar, n;
473 struct e1000_tx *tp = &s->tx;
474
1b0009db 475 if (tp->tse && tp->cptse) {
7c23b892
AZ		 476 css = tp->ipcss;
477 DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
478 frames, tp->size, css);
479 if (tp->ip) { // IPv4
480 cpu_to_be16wu((uint16_t *)(tp->data+css+2),
481 tp->size - css);
482 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
483 be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
484 } else // IPv6
485 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
486 tp->size - css);
487 css = tp->tucss;
488 len = tp->size - css;
489 DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
490 if (tp->tcp) {
491 sofar = frames * tp->mss;
492 cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq
88738c09 493 be32_to_cpupu((uint32_t *)(tp->data+css+4))+sofar);
7c23b892
AZ		 494 if (tp->paylen - sofar > tp->mss)
495 tp->data[css + 13] &= ~9; // PSH, FIN
496 } else // UDP
497 cpu_to_be16wu((uint16_t *)(tp->data+css+4), len);
498 if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
e685b4eb 499 unsigned int phsum;
7c23b892
AZ		 500 // add pseudo-header length before checksum calculation
501 sp = (uint16_t *)(tp->data + tp->tucso);
e685b4eb
AW		 502 phsum = be16_to_cpup(sp) + len;
503 phsum = (phsum >> 16) + (phsum & 0xffff);
504 cpu_to_be16wu(sp, phsum);
7c23b892
AZ		 505 }
506 tp->tso_frames++;
507 }
508
509 if (tp->sum_needed & E1000_TXD_POPTS_TXSM)
510 putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse);
511 if (tp->sum_needed & E1000_TXD_POPTS_IXSM)
512 putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse);
8f2e8d1f 513 if (tp->vlan_needed) {
b10fec9b
SW		 514 memmove(tp->vlan, tp->data, 4);
515 memmove(tp->data, tp->data + 4, 8);
8f2e8d1f 516 memcpy(tp->data + 8, tp->vlan_header, 4);
93e37d76 517 e1000_send_packet(s, tp->vlan, tp->size + 4);
8f2e8d1f 518 } else
93e37d76 519 e1000_send_packet(s, tp->data, tp->size);
7c23b892
AZ		 520 s->mac_reg[TPT]++;
521 s->mac_reg[GPTC]++;
522 n = s->mac_reg[TOTL];
523 if ((s->mac_reg[TOTL] += s->tx.size) < n)
524 s->mac_reg[TOTH]++;
525}
526
527static void
528process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
529{
530 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
531 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
532 unsigned int split_size = txd_lower & 0xffff, bytes, sz, op;
533 unsigned int msh = 0xfffff, hdr = 0;
534 uint64_t addr;
535 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
536 struct e1000_tx *tp = &s->tx;
537
538 if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor
539 op = le32_to_cpu(xp->cmd_and_length);
540 tp->ipcss = xp->lower_setup.ip_fields.ipcss;
541 tp->ipcso = xp->lower_setup.ip_fields.ipcso;
542 tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse);
543 tp->tucss = xp->upper_setup.tcp_fields.tucss;
544 tp->tucso = xp->upper_setup.tcp_fields.tucso;
545 tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse);
546 tp->paylen = op & 0xfffff;
547 tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len;
548 tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss);
549 tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0;
550 tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
551 tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
552 tp->tso_frames = 0;
553 if (tp->tucso == 0) { // this is probably wrong
554 DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
555 tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
556 }
557 return;
1b0009db
AZ		 558 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
559 // data descriptor
735e77ec
SH		 560 if (tp->size == 0) {
561 tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
562 }
1b0009db 563 tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0;
43ad7e3e 564 } else {
1b0009db
AZ		 565 // legacy descriptor
566 tp->cptse = 0;
43ad7e3e 567 }
7c23b892 568
8f2e8d1f
AL		 569 if (vlan_enabled(s) && is_vlan_txd(txd_lower) &&
570 (tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) {
571 tp->vlan_needed = 1;
572 cpu_to_be16wu((uint16_t *)(tp->vlan_header),
573 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
574 cpu_to_be16wu((uint16_t *)(tp->vlan_header + 2),
575 le16_to_cpu(dp->upper.fields.special));
576 }
577
7c23b892 578 addr = le64_to_cpu(dp->buffer_addr);
1b0009db 579 if (tp->tse && tp->cptse) {
7c23b892
AZ		 580 hdr = tp->hdr_len;
581 msh = hdr + tp->mss;
1b0009db
AZ		 582 do {
583 bytes = split_size;
584 if (tp->size + bytes > msh)
585 bytes = msh - tp->size;
65f82df0
AL		 586
587 bytes = MIN(sizeof(tp->data) - tp->size, bytes);
62ecbd35 588 pci_dma_read(&s->dev, addr, tp->data + tp->size, bytes);
1b0009db
AZ		 589 if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
590 memmove(tp->header, tp->data, hdr);
591 tp->size = sz;
592 addr += bytes;
593 if (sz == msh) {
594 xmit_seg(s);
595 memmove(tp->data, tp->header, hdr);
596 tp->size = hdr;
597 }
598 } while (split_size -= bytes);
599 } else if (!tp->tse && tp->cptse) {
600 // context descriptor TSE is not set, while data descriptor TSE is set
362f5fb5 601 DBGOUT(TXERR, "TCP segmentation error\n");
1b0009db 602 } else {
65f82df0 603 split_size = MIN(sizeof(tp->data) - tp->size, split_size);
62ecbd35 604 pci_dma_read(&s->dev, addr, tp->data + tp->size, split_size);
1b0009db 605 tp->size += split_size;
7c23b892 606 }
7c23b892
AZ		 607
608 if (!(txd_lower & E1000_TXD_CMD_EOP))
609 return;
1b0009db 610 if (!(tp->tse && tp->cptse && tp->size < hdr))
7c23b892
AZ		 611 xmit_seg(s);
612 tp->tso_frames = 0;
613 tp->sum_needed = 0;
8f2e8d1f 614 tp->vlan_needed = 0;
7c23b892 615 tp->size = 0;
1b0009db 616 tp->cptse = 0;
7c23b892
AZ		 617}
618
619static uint32_t
62ecbd35 620txdesc_writeback(E1000State *s, dma_addr_t base, struct e1000_tx_desc *dp)
7c23b892
AZ		 621{
622 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
623
624 if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
625 return 0;
626 txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) &
627 ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU);
628 dp->upper.data = cpu_to_le32(txd_upper);
62ecbd35 629 pci_dma_write(&s->dev, base + ((char *)&dp->upper - (char *)dp),
00c3a05b 630 &dp->upper, sizeof(dp->upper));
7c23b892
AZ		 631 return E1000_ICR_TXDW;
632}
633
d17161f6
KW		 634static uint64_t tx_desc_base(E1000State *s)
635{
636 uint64_t bah = s->mac_reg[TDBAH];
637 uint64_t bal = s->mac_reg[TDBAL] & ~0xf;
638
639 return (bah << 32) + bal;
640}
641
7c23b892
AZ		 642static void
643start_xmit(E1000State *s)
644{
62ecbd35 645 dma_addr_t base;
7c23b892
AZ		 646 struct e1000_tx_desc desc;
647 uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
648
649 if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) {
650 DBGOUT(TX, "tx disabled\n");
651 return;
652 }
653
654 while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
d17161f6 655 base = tx_desc_base(s) +
7c23b892 656 sizeof(struct e1000_tx_desc) * s->mac_reg[TDH];
00c3a05b 657 pci_dma_read(&s->dev, base, &desc, sizeof(desc));
7c23b892
AZ		 658
659 DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
6106075b 660 (void *)(intptr_t)desc.buffer_addr, desc.lower.data,
7c23b892
AZ		 661 desc.upper.data);
662
663 process_tx_desc(s, &desc);
62ecbd35 664 cause |= txdesc_writeback(s, base, &desc);
7c23b892
AZ		 665
666 if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN])
667 s->mac_reg[TDH] = 0;
668 /*
669 * the following could happen only if guest sw assigns
670 * bogus values to TDT/TDLEN.
671 * there's nothing too intelligent we could do about this.
672 */
673 if (s->mac_reg[TDH] == tdh_start) {
674 DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n",
675 tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]);
676 break;
677 }
678 }
679 set_ics(s, 0, cause);
680}
681
682static int
683receive_filter(E1000State *s, const uint8_t *buf, int size)
684{
af2960f9
BS		 685 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
686 static const int mta_shift[] = {4, 3, 2, 0};
7c23b892
AZ		 687 uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp;
688
8f2e8d1f
AL		 689 if (is_vlan_packet(s, buf) && vlan_rx_filter_enabled(s)) {
690 uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14));
691 uint32_t vfta = le32_to_cpup((uint32_t *)(s->mac_reg + VFTA) +
692 ((vid >> 5) & 0x7f));
693 if ((vfta & (1 << (vid & 0x1f))) == 0)
694 return 0;
695 }
696
7c23b892
AZ		 697 if (rctl & E1000_RCTL_UPE) // promiscuous
698 return 1;
699
700 if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast
701 return 1;
702
703 if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast))
704 return 1;
705
706 for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) {
707 if (!(rp[1] & E1000_RAH_AV))
708 continue;
709 ra[0] = cpu_to_le32(rp[0]);
710 ra[1] = cpu_to_le32(rp[1]);
711 if (!memcmp(buf, (uint8_t *)ra, 6)) {
712 DBGOUT(RXFILTER,
713 "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
714 (int)(rp - s->mac_reg - RA)/2,
715 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
716 return 1;
717 }
718 }
719 DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n",
720 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
721
722 f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
723 f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff;
724 if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f)))
725 return 1;
726 DBGOUT(RXFILTER,
727 "dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n",
728 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
729 (rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5,
730 s->mac_reg[MTA + (f >> 5)]);
731
732 return 0;
733}
734
99ed7e30 735static void
4e68f7a0 736e1000_set_link_status(NetClientState *nc)
99ed7e30 737{
a03e2aec 738 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
99ed7e30
AL		 739 uint32_t old_status = s->mac_reg[STATUS];
740
d4044c2a 741 if (nc->link_down) {
71aadd3c 742 e1000_link_down(s);
d4044c2a 743 } else {
71aadd3c 744 e1000_link_up(s);
d4044c2a 745 }
99ed7e30
AL		 746
747 if (s->mac_reg[STATUS] != old_status)
748 set_ics(s, 0, E1000_ICR_LSC);
749}
750
322fd48a
MT		 751static bool e1000_has_rxbufs(E1000State *s, size_t total_size)
752{
753 int bufs;
754 /* Fast-path short packets */
755 if (total_size <= s->rxbuf_size) {
e5b8b0d4 756 return s->mac_reg[RDH] != s->mac_reg[RDT];
322fd48a
MT		 757 }
758 if (s->mac_reg[RDH] < s->mac_reg[RDT]) {
759 bufs = s->mac_reg[RDT] - s->mac_reg[RDH];
e5b8b0d4 760 } else if (s->mac_reg[RDH] > s->mac_reg[RDT]) {
322fd48a
MT		 761 bufs = s->mac_reg[RDLEN] / sizeof(struct e1000_rx_desc) +
762 s->mac_reg[RDT] - s->mac_reg[RDH];
763 } else {
764 return false;
765 }
766 return total_size <= bufs * s->rxbuf_size;
767}
768
6cdfab28 769static int
4e68f7a0 770e1000_can_receive(NetClientState *nc)
6cdfab28
MT		 771{
772 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
773
774 return (s->mac_reg[RCTL] & E1000_RCTL_EN) && e1000_has_rxbufs(s, 1);
775}
776
d17161f6
KW		 777static uint64_t rx_desc_base(E1000State *s)
778{
779 uint64_t bah = s->mac_reg[RDBAH];
780 uint64_t bal = s->mac_reg[RDBAL] & ~0xf;
781
782 return (bah << 32) + bal;
783}
784
4f1c942b 785static ssize_t
4e68f7a0 786e1000_receive(NetClientState *nc, const uint8_t *buf, size_t size)
7c23b892 787{
a03e2aec 788 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
7c23b892 789 struct e1000_rx_desc desc;
62ecbd35 790 dma_addr_t base;
7c23b892
AZ		 791 unsigned int n, rdt;
792 uint32_t rdh_start;
8f2e8d1f
AL		 793 uint16_t vlan_special = 0;
794 uint8_t vlan_status = 0, vlan_offset = 0;
78aeb23e 795 uint8_t min_buf[MIN_BUF_SIZE];
b19487e2
MT		 796 size_t desc_offset;
797 size_t desc_size;
798 size_t total_size;
7c23b892
AZ		 799
800 if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))
4f1c942b 801 return -1;
7c23b892 802
78aeb23e
SH		 803 /* Pad to minimum Ethernet frame length */
804 if (size < sizeof(min_buf)) {
805 memcpy(min_buf, buf, size);
806 memset(&min_buf[size], 0, sizeof(min_buf) - size);
807 buf = min_buf;
808 size = sizeof(min_buf);
809 }
810
b0d9ffcd
MC		 811 /* Discard oversized packets if !LPE and !SBP. */
812 if (size > MAXIMUM_ETHERNET_VLAN_SIZE
813 && !(s->mac_reg[RCTL] & E1000_RCTL_LPE)
814 && !(s->mac_reg[RCTL] & E1000_RCTL_SBP)) {
815 return size;
816 }
817
7c23b892 818 if (!receive_filter(s, buf, size))
4f1c942b 819 return size;
7c23b892 820
8f2e8d1f
AL		 821 if (vlan_enabled(s) && is_vlan_packet(s, buf)) {
822 vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(buf + 14)));
98835fe3 823 memmove((uint8_t *)buf + 4, buf, 12);
8f2e8d1f
AL		 824 vlan_status = E1000_RXD_STAT_VP;
825 vlan_offset = 4;
826 size -= 4;
827 }
828
7c23b892 829 rdh_start = s->mac_reg[RDH];
b19487e2
MT		 830 desc_offset = 0;
831 total_size = size + fcs_len(s);
322fd48a
MT		 832 if (!e1000_has_rxbufs(s, total_size)) {
833 set_ics(s, 0, E1000_ICS_RXO);
834 return -1;
835 }
7c23b892 836 do {
b19487e2
MT		 837 desc_size = total_size - desc_offset;
838 if (desc_size > s->rxbuf_size) {
839 desc_size = s->rxbuf_size;
840 }
d17161f6 841 base = rx_desc_base(s) + sizeof(desc) * s->mac_reg[RDH];
00c3a05b 842 pci_dma_read(&s->dev, base, &desc, sizeof(desc));
8f2e8d1f
AL		 843 desc.special = vlan_special;
844 desc.status |= (vlan_status | E1000_RXD_STAT_DD);
7c23b892 845 if (desc.buffer_addr) {
b19487e2
MT		 846 if (desc_offset < size) {
847 size_t copy_size = size - desc_offset;
848 if (copy_size > s->rxbuf_size) {
849 copy_size = s->rxbuf_size;
850 }
62ecbd35 851 pci_dma_write(&s->dev, le64_to_cpu(desc.buffer_addr),
00c3a05b 852 buf + desc_offset + vlan_offset, copy_size);
b19487e2
MT		 853 }
854 desc_offset += desc_size;
ee912ccf 855 desc.length = cpu_to_le16(desc_size);
b19487e2 856 if (desc_offset >= total_size) {
b19487e2
MT		 857 desc.status |= E1000_RXD_STAT_EOP | E1000_RXD_STAT_IXSM;
858 } else {
ee912ccf
MT		 859 /* Guest zeroing out status is not a hardware requirement.
860 Clear EOP in case guest didn't do it. */
861 desc.status &= ~E1000_RXD_STAT_EOP;
b19487e2 862 }
43ad7e3e 863 } else { // as per intel docs; skip descriptors with null buf addr
7c23b892 864 DBGOUT(RX, "Null RX descriptor!!\n");
43ad7e3e 865 }
00c3a05b 866 pci_dma_write(&s->dev, base, &desc, sizeof(desc));
7c23b892
AZ		 867
868 if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])
869 s->mac_reg[RDH] = 0;
7c23b892
AZ		 870 /* see comment in start_xmit; same here */
871 if (s->mac_reg[RDH] == rdh_start) {
872 DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",
873 rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);
874 set_ics(s, 0, E1000_ICS_RXO);
4f1c942b 875 return -1;
7c23b892 876 }
b19487e2 877 } while (desc_offset < total_size);
7c23b892
AZ		 878
879 s->mac_reg[GPRC]++;
880 s->mac_reg[TPR]++;
a05e8a6e
MT		 881 /* TOR - Total Octets Received:
882 * This register includes bytes received in a packet from the <Destination
883 * Address> field through the <CRC> field, inclusively.
884 */
885 n = s->mac_reg[TORL] + size + /* Always include FCS length. */ 4;
886 if (n < s->mac_reg[TORL])
7c23b892 887 s->mac_reg[TORH]++;
a05e8a6e 888 s->mac_reg[TORL] = n;
7c23b892
AZ		 889
890 n = E1000_ICS_RXT0;
891 if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
892 rdt += s->mac_reg[RDLEN] / sizeof(desc);
bf16cc8f
AL		 893 if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >>
894 s->rxbuf_min_shift)
7c23b892
AZ		 895 n |= E1000_ICS_RXDMT0;
896
897 set_ics(s, 0, n);
4f1c942b
MM		 898
899 return size;
7c23b892
AZ		 900}
901
902static uint32_t
903mac_readreg(E1000State *s, int index)
904{
905 return s->mac_reg[index];
906}
907
908static uint32_t
909mac_icr_read(E1000State *s, int index)
910{
911 uint32_t ret = s->mac_reg[ICR];
912
913 DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
914 set_interrupt_cause(s, 0, 0);
915 return ret;
916}
917
918static uint32_t
919mac_read_clr4(E1000State *s, int index)
920{
921 uint32_t ret = s->mac_reg[index];
922
923 s->mac_reg[index] = 0;
924 return ret;
925}
926
927static uint32_t
928mac_read_clr8(E1000State *s, int index)
929{
930 uint32_t ret = s->mac_reg[index];
931
932 s->mac_reg[index] = 0;
933 s->mac_reg[index-1] = 0;
934 return ret;
935}
936
937static void
938mac_writereg(E1000State *s, int index, uint32_t val)
939{
940 s->mac_reg[index] = val;
941}
942
943static void
944set_rdt(E1000State *s, int index, uint32_t val)
945{
7c23b892 946 s->mac_reg[index] = val & 0xffff;
e8b4c680
PB		 947 if (e1000_has_rxbufs(s, 1)) {
948 qemu_flush_queued_packets(&s->nic->nc);
949 }
7c23b892
AZ		 950}
951
952static void
953set_16bit(E1000State *s, int index, uint32_t val)
954{
955 s->mac_reg[index] = val & 0xffff;
956}
957
958static void
959set_dlen(E1000State *s, int index, uint32_t val)
960{
961 s->mac_reg[index] = val & 0xfff80;
962}
963
964static void
965set_tctl(E1000State *s, int index, uint32_t val)
966{
967 s->mac_reg[index] = val;
968 s->mac_reg[TDT] &= 0xffff;
969 start_xmit(s);
970}
971
972static void
973set_icr(E1000State *s, int index, uint32_t val)
974{
975 DBGOUT(INTERRUPT, "set_icr %x\n", val);
976 set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);
977}
978
979static void
980set_imc(E1000State *s, int index, uint32_t val)
981{
982 s->mac_reg[IMS] &= ~val;
983 set_ics(s, 0, 0);
984}
985
986static void
987set_ims(E1000State *s, int index, uint32_t val)
988{
989 s->mac_reg[IMS] |= val;
990 set_ics(s, 0, 0);
991}
992
993#define getreg(x) [x] = mac_readreg
994static uint32_t (*macreg_readops[])(E1000State *, int) = {
995 getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
996 getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
997 getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
998 getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
b1332393 999 getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
a00b2335
KA		 1000 getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
1001 getreg(TDLEN), getreg(RDLEN),
7c23b892
AZ		 1002
1003 [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4,
1004 [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4,
1005 [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read,
1006 [CRCERRS ... MPC] = &mac_readreg,
1007 [RA ... RA+31] = &mac_readreg,
1008 [MTA ... MTA+127] = &mac_readreg,
8f2e8d1f 1009 [VFTA ... VFTA+127] = &mac_readreg,
7c23b892 1010};
b1503cda 1011enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
7c23b892
AZ		 1012
1013#define putreg(x) [x] = mac_writereg
1014static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
1015 putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
1016 putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
cab3c825 1017 putreg(RDBAL), putreg(LEDCTL), putreg(VET),
7c23b892
AZ		 1018 [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
1019 [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
1020 [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
1021 [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
cab3c825 1022 [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
7c23b892
AZ		 1023 [RA ... RA+31] = &mac_writereg,
1024 [MTA ... MTA+127] = &mac_writereg,
8f2e8d1f 1025 [VFTA ... VFTA+127] = &mac_writereg,
7c23b892 1026};
b9d03e35 1027
b1503cda 1028enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
7c23b892
AZ		 1029
1030static void
a8170e5e 1031e1000_mmio_write(void *opaque, hwaddr addr, uint64_t val,
ad00a9b9 1032 unsigned size)
7c23b892
AZ		 1033{
1034 E1000State *s = opaque;
8da3ff18 1035 unsigned int index = (addr & 0x1ffff) >> 2;
7c23b892 1036
43ad7e3e 1037 if (index < NWRITEOPS && macreg_writeops[index]) {
6b59fc74 1038 macreg_writeops[index](s, index, val);
43ad7e3e 1039 } else if (index < NREADOPS && macreg_readops[index]) {
ad00a9b9 1040 DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04"PRIx64"\n", index<<2, val);
43ad7e3e 1041 } else {
ad00a9b9 1042 DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08"PRIx64"\n",
7c23b892 1043 index<<2, val);
43ad7e3e 1044 }
7c23b892
AZ		 1045}
1046
ad00a9b9 1047static uint64_t
a8170e5e 1048e1000_mmio_read(void *opaque, hwaddr addr, unsigned size)
7c23b892
AZ		 1049{
1050 E1000State *s = opaque;
8da3ff18 1051 unsigned int index = (addr & 0x1ffff) >> 2;
7c23b892
AZ		 1052
1053 if (index < NREADOPS && macreg_readops[index])
6b59fc74 1054 {
32600a30 1055 return macreg_readops[index](s, index);
6b59fc74 1056 }
7c23b892
AZ		 1057 DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
1058 return 0;
1059}
1060
ad00a9b9
AK		 1061static const MemoryRegionOps e1000_mmio_ops = {
1062 .read = e1000_mmio_read,
1063 .write = e1000_mmio_write,
1064 .endianness = DEVICE_LITTLE_ENDIAN,
1065 .impl = {
1066 .min_access_size = 4,
1067 .max_access_size = 4,
1068 },
1069};
1070
a8170e5e 1071static uint64_t e1000_io_read(void *opaque, hwaddr addr,
ad00a9b9 1072 unsigned size)
7c23b892 1073{
ad00a9b9
AK		 1074 E1000State *s = opaque;
1075
1076 (void)s;
1077 return 0;
7c23b892
AZ		 1078}
1079
a8170e5e 1080static void e1000_io_write(void *opaque, hwaddr addr,
ad00a9b9 1081 uint64_t val, unsigned size)
7c23b892 1082{
ad00a9b9
AK		 1083 E1000State *s = opaque;
1084
1085 (void)s;
7c23b892
AZ		 1086}
1087
ad00a9b9
AK		 1088static const MemoryRegionOps e1000_io_ops = {
1089 .read = e1000_io_read,
1090 .write = e1000_io_write,
1091 .endianness = DEVICE_LITTLE_ENDIAN,
1092};
1093
e482dc3e 1094static bool is_version_1(void *opaque, int version_id)
7c23b892 1095{
e482dc3e 1096 return version_id == 1;
7c23b892
AZ		 1097}
1098
e4b82364
AK		 1099static int e1000_post_load(void *opaque, int version_id)
1100{
1101 E1000State *s = opaque;
1102
1103 /* nc.link_down can't be migrated, so infer link_down according
1104 * to link status bit in mac_reg[STATUS] */
1105 s->nic->nc.link_down = (s->mac_reg[STATUS] & E1000_STATUS_LU) == 0;
1106
1107 return 0;
1108}
1109
e482dc3e
JQ		 1110static const VMStateDescription vmstate_e1000 = {
1111 .name = "e1000",
1112 .version_id = 2,
1113 .minimum_version_id = 1,
1114 .minimum_version_id_old = 1,
e4b82364 1115 .post_load = e1000_post_load,
e482dc3e
JQ		 1116 .fields = (VMStateField []) {
1117 VMSTATE_PCI_DEVICE(dev, E1000State),
1118 VMSTATE_UNUSED_TEST(is_version_1, 4), /* was instance id */
1119 VMSTATE_UNUSED(4), /* Was mmio_base. */
1120 VMSTATE_UINT32(rxbuf_size, E1000State),
1121 VMSTATE_UINT32(rxbuf_min_shift, E1000State),
1122 VMSTATE_UINT32(eecd_state.val_in, E1000State),
1123 VMSTATE_UINT16(eecd_state.bitnum_in, E1000State),
1124 VMSTATE_UINT16(eecd_state.bitnum_out, E1000State),
1125 VMSTATE_UINT16(eecd_state.reading, E1000State),
1126 VMSTATE_UINT32(eecd_state.old_eecd, E1000State),
1127 VMSTATE_UINT8(tx.ipcss, E1000State),
1128 VMSTATE_UINT8(tx.ipcso, E1000State),
1129 VMSTATE_UINT16(tx.ipcse, E1000State),
1130 VMSTATE_UINT8(tx.tucss, E1000State),
1131 VMSTATE_UINT8(tx.tucso, E1000State),
1132 VMSTATE_UINT16(tx.tucse, E1000State),
1133 VMSTATE_UINT32(tx.paylen, E1000State),
1134 VMSTATE_UINT8(tx.hdr_len, E1000State),
1135 VMSTATE_UINT16(tx.mss, E1000State),
1136 VMSTATE_UINT16(tx.size, E1000State),
1137 VMSTATE_UINT16(tx.tso_frames, E1000State),
1138 VMSTATE_UINT8(tx.sum_needed, E1000State),
1139 VMSTATE_INT8(tx.ip, E1000State),
1140 VMSTATE_INT8(tx.tcp, E1000State),
1141 VMSTATE_BUFFER(tx.header, E1000State),
1142 VMSTATE_BUFFER(tx.data, E1000State),
1143 VMSTATE_UINT16_ARRAY(eeprom_data, E1000State, 64),
1144 VMSTATE_UINT16_ARRAY(phy_reg, E1000State, 0x20),
1145 VMSTATE_UINT32(mac_reg[CTRL], E1000State),
1146 VMSTATE_UINT32(mac_reg[EECD], E1000State),
1147 VMSTATE_UINT32(mac_reg[EERD], E1000State),
1148 VMSTATE_UINT32(mac_reg[GPRC], E1000State),
1149 VMSTATE_UINT32(mac_reg[GPTC], E1000State),
1150 VMSTATE_UINT32(mac_reg[ICR], E1000State),
1151 VMSTATE_UINT32(mac_reg[ICS], E1000State),
1152 VMSTATE_UINT32(mac_reg[IMC], E1000State),
1153 VMSTATE_UINT32(mac_reg[IMS], E1000State),
1154 VMSTATE_UINT32(mac_reg[LEDCTL], E1000State),
1155 VMSTATE_UINT32(mac_reg[MANC], E1000State),
1156 VMSTATE_UINT32(mac_reg[MDIC], E1000State),
1157 VMSTATE_UINT32(mac_reg[MPC], E1000State),
1158 VMSTATE_UINT32(mac_reg[PBA], E1000State),
1159 VMSTATE_UINT32(mac_reg[RCTL], E1000State),
1160 VMSTATE_UINT32(mac_reg[RDBAH], E1000State),
1161 VMSTATE_UINT32(mac_reg[RDBAL], E1000State),
1162 VMSTATE_UINT32(mac_reg[RDH], E1000State),
1163 VMSTATE_UINT32(mac_reg[RDLEN], E1000State),
1164 VMSTATE_UINT32(mac_reg[RDT], E1000State),
1165 VMSTATE_UINT32(mac_reg[STATUS], E1000State),
1166 VMSTATE_UINT32(mac_reg[SWSM], E1000State),
1167 VMSTATE_UINT32(mac_reg[TCTL], E1000State),
1168 VMSTATE_UINT32(mac_reg[TDBAH], E1000State),
1169 VMSTATE_UINT32(mac_reg[TDBAL], E1000State),
1170 VMSTATE_UINT32(mac_reg[TDH], E1000State),
1171 VMSTATE_UINT32(mac_reg[TDLEN], E1000State),
1172 VMSTATE_UINT32(mac_reg[TDT], E1000State),
1173 VMSTATE_UINT32(mac_reg[TORH], E1000State),
1174 VMSTATE_UINT32(mac_reg[TORL], E1000State),
1175 VMSTATE_UINT32(mac_reg[TOTH], E1000State),
1176 VMSTATE_UINT32(mac_reg[TOTL], E1000State),
1177 VMSTATE_UINT32(mac_reg[TPR], E1000State),
1178 VMSTATE_UINT32(mac_reg[TPT], E1000State),
1179 VMSTATE_UINT32(mac_reg[TXDCTL], E1000State),
1180 VMSTATE_UINT32(mac_reg[WUFC], E1000State),
1181 VMSTATE_UINT32(mac_reg[VET], E1000State),
1182 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32),
1183 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, 128),
1184 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA, 128),
1185 VMSTATE_END_OF_LIST()
1186 }
1187};
7c23b892 1188
88b4e9db 1189static const uint16_t e1000_eeprom_template[64] = {
7c23b892
AZ		 1190 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,
1191 0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040,
1192 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,
1193 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,
1194 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,
1195 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1196 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1197 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000,
1198};
1199
7c23b892
AZ		 1200/* PCI interface */
1201
7c23b892 1202static void
ad00a9b9 1203e1000_mmio_setup(E1000State *d)
7c23b892 1204{
f65ed4c1
AL		 1205 int i;
1206 const uint32_t excluded_regs[] = {
1207 E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
1208 E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
1209 };
1210
ad00a9b9
AK		 1211 memory_region_init_io(&d->mmio, &e1000_mmio_ops, d, "e1000-mmio",
1212 PNPMMIO_SIZE);
1213 memory_region_add_coalescing(&d->mmio, 0, excluded_regs[0]);
f65ed4c1 1214 for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++)
ad00a9b9
AK		 1215 memory_region_add_coalescing(&d->mmio, excluded_regs[i] + 4,
1216 excluded_regs[i+1] - excluded_regs[i] - 4);
1217 memory_region_init_io(&d->io, &e1000_io_ops, d, "e1000-io", IOPORT_SIZE);
7c23b892
AZ		 1218}
1219
b946a153 1220static void
4e68f7a0 1221e1000_cleanup(NetClientState *nc)
b946a153 1222{
a03e2aec 1223 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
b946a153 1224
a03e2aec 1225 s->nic = NULL;
b946a153
AL		 1226}
1227
f90c2bcd 1228static void
4b09be85
AL		 1229pci_e1000_uninit(PCIDevice *dev)
1230{
7d9e52bd 1231 E1000State *d = DO_UPCAST(E1000State, dev, dev);
4b09be85 1232
b9d03e35
JW		 1233 qemu_del_timer(d->autoneg_timer);
1234 qemu_free_timer(d->autoneg_timer);
ad00a9b9
AK		 1235 memory_region_destroy(&d->mmio);
1236 memory_region_destroy(&d->io);
b20c6b9e 1237 qemu_del_net_client(&d->nic->nc);
4b09be85
AL		 1238}
1239
a03e2aec 1240static NetClientInfo net_e1000_info = {
2be64a68 1241 .type = NET_CLIENT_OPTIONS_KIND_NIC,
a03e2aec
MM		 1242 .size = sizeof(NICState),
1243 .can_receive = e1000_can_receive,
1244 .receive = e1000_receive,
1245 .cleanup = e1000_cleanup,
1246 .link_status_changed = e1000_set_link_status,
1247};
1248
81a322d4 1249static int pci_e1000_init(PCIDevice *pci_dev)
7c23b892 1250{
7d9e52bd 1251 E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
7c23b892 1252 uint8_t *pci_conf;
7c23b892 1253 uint16_t checksum = 0;
7c23b892 1254 int i;
fbdaa002 1255 uint8_t *macaddr;
aff427a1 1256
7c23b892 1257 pci_conf = d->dev.config;
7c23b892 1258
a9cbacb0
MT		 1259 /* TODO: RST# value should be 0, PCI spec 6.2.4 */
1260 pci_conf[PCI_CACHE_LINE_SIZE] = 0x10;
7c23b892 1261
817e0b6f 1262 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
7c23b892 1263
ad00a9b9 1264 e1000_mmio_setup(d);
7c23b892 1265
e824b2cc 1266 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
7c23b892 1267
e824b2cc 1268 pci_register_bar(&d->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->io);
7c23b892 1269
7c23b892
AZ		 1270 memmove(d->eeprom_data, e1000_eeprom_template,
1271 sizeof e1000_eeprom_template);
fbdaa002
GH		 1272 qemu_macaddr_default_if_unset(&d->conf.macaddr);
1273 macaddr = d->conf.macaddr.a;
7c23b892 1274 for (i = 0; i < 3; i++)
9d07d757 1275 d->eeprom_data[i] = (macaddr[2*i+1]<<8) | macaddr[2*i];
7c23b892
AZ		 1276 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1277 checksum += d->eeprom_data[i];
1278 checksum = (uint16_t) EEPROM_SUM - checksum;
1279 d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum;
1280
a03e2aec 1281 d->nic = qemu_new_nic(&net_e1000_info, &d->conf,
f79f2bfc 1282 object_get_typename(OBJECT(d)), d->dev.qdev.id, d);
7c23b892 1283
a03e2aec 1284 qemu_format_nic_info_str(&d->nic->nc, macaddr);
1ca4d09a
GN		 1285
1286 add_boot_device_path(d->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
1287
b9d03e35
JW		 1288 d->autoneg_timer = qemu_new_timer_ms(vm_clock, e1000_autoneg_timer, d);
1289
81a322d4 1290 return 0;
9d07d757 1291}
72da4208 1292
fbdaa002
GH		 1293static void qdev_e1000_reset(DeviceState *dev)
1294{
1295 E1000State *d = DO_UPCAST(E1000State, dev.qdev, dev);
1296 e1000_reset(d);
1297}
1298
40021f08
AL		 1299static Property e1000_properties[] = {
1300 DEFINE_NIC_PROPERTIES(E1000State, conf),
1301 DEFINE_PROP_END_OF_LIST(),
1302};
1303
1304static void e1000_class_init(ObjectClass *klass, void *data)
1305{
39bffca2 1306 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 1307 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1308
1309 k->init = pci_e1000_init;
1310 k->exit = pci_e1000_uninit;
1311 k->romfile = "pxe-e1000.rom";
1312 k->vendor_id = PCI_VENDOR_ID_INTEL;
1313 k->device_id = E1000_DEVID;
1314 k->revision = 0x03;
1315 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
39bffca2
AL		 1316 dc->desc = "Intel Gigabit Ethernet";
1317 dc->reset = qdev_e1000_reset;
1318 dc->vmsd = &vmstate_e1000;
1319 dc->props = e1000_properties;
40021f08
AL		 1320}
1321
39bffca2
AL		 1322static TypeInfo e1000_info = {
1323 .name = "e1000",
1324 .parent = TYPE_PCI_DEVICE,
1325 .instance_size = sizeof(E1000State),
1326 .class_init = e1000_class_init,
0aab0d3a
GH		 1327};
1328
83f7d43a 1329static void e1000_register_types(void)
9d07d757 1330{
39bffca2 1331 type_register_static(&e1000_info);
7c23b892 1332}
9d07d757 1333
83f7d43a 1334type_init(e1000_register_types)
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