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hw/escc: Drop duplicate definition of 'disabled' property
[mirror_qemu.git] / hw / eepro100.c
CommitLineData
663e8e51
TS		 1/*
2 * QEMU i8255x (PRO100) emulation
3 *
1b4f97d6 4 * Copyright (C) 2006-2011 Stefan Weil
663e8e51
TS		 5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
230a167c 9 * This program is free software: you can redistribute it and/or modify
663e8e51 10 * it under the terms of the GNU General Public License as published by
230a167c
SW		 11 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) version 3 or any later version.
663e8e51
TS		 13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
230a167c 20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
663e8e51
TS		 21 *
22 * Tested features (i82559):
e5e23ab8 23 * PXE boot (i386 guest, i386 / mips / mipsel / ppc host) ok
663e8e51
TS		 24 * Linux networking (i386) ok
25 *
26 * Untested:
663e8e51
TS		 27 * Windows networking
28 *
29 * References:
30 *
31 * Intel 8255x 10/100 Mbps Ethernet Controller Family
32 * Open Source Software Developer Manual
ba19f2de
SW		 33 *
34 * TODO:
35 * * PHY emulation should be separated from nic emulation.
36 * Most nic emulations could share the same phy code.
37 * * i82550 is untested. It is programmed like the i82559.
38 * * i82562 is untested. It is programmed like the i82559.
39 * * Power management (i82558 and later) is not implemented.
40 * * Wake-on-LAN is not implemented.
663e8e51
TS		 41 */
42
663e8e51 43#include <stddef.h> /* offsetof */
87ecb68b
PB		 44#include "hw.h"
45#include "pci.h"
46#include "net.h"
663e8e51 47#include "eeprom93xx.h"
1ca4d09a 48#include "sysemu.h"
16ef60c9 49#include "dma.h"
663e8e51 50
792f1d63
SW		 51/* QEMU sends frames smaller than 60 bytes to ethernet nics.
52 * Such frames are rejected by real nics and their emulations.
53 * To avoid this behaviour, other nic emulations pad received
54 * frames. The following definition enables this padding for
55 * eepro100, too. We keep the define around in case it might
56 * become useful the future if the core networking is ever
57 * changed to pad short packets itself. */
58#define CONFIG_PAD_RECEIVED_FRAMES
59
663e8e51
TS		 60#define KiB 1024
61
aac443e6 62/* Debug EEPRO100 card. */
ce0e58b3
SW		 63#if 0
64# define DEBUG_EEPRO100
65#endif
663e8e51
TS		 66
67#ifdef DEBUG_EEPRO100
001faf32 68#define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
663e8e51 69#else
001faf32 70#define logout(fmt, ...) ((void)0)
663e8e51
TS		 71#endif
72
73/* Set flags to 0 to disable debug output. */
aac443e6
SW		 74#define INT 1 /* interrupt related actions */
75#define MDI 1 /* mdi related actions */
76#define OTHER 1
77#define RXTX 1
78#define EEPROM 1 /* eeprom related actions */
663e8e51
TS		 79
80#define TRACE(flag, command) ((flag) ? (command) : (void)0)
81
7f1e9d4e 82#define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
663e8e51
TS		 83
84#define MAX_ETH_FRAME_SIZE 1514
85
86/* This driver supports several different devices which are declared here. */
c4c270e2 87#define i82550 0x82550
663e8e51 88#define i82551 0x82551
c4c270e2 89#define i82557A 0x82557a
663e8e51
TS		 90#define i82557B 0x82557b
91#define i82557C 0x82557c
c4c270e2 92#define i82558A 0x82558a
663e8e51 93#define i82558B 0x82558b
c4c270e2
SW		 94#define i82559A 0x82559a
95#define i82559B 0x82559b
663e8e51
TS		 96#define i82559C 0x82559c
97#define i82559ER 0x82559e
98#define i82562 0x82562
db667a12 99#define i82801 0x82801
663e8e51 100
aac443e6 101/* Use 64 word EEPROM. TODO: could be a runtime option. */
663e8e51
TS		 102#define EEPROM_SIZE 64
103
104#define PCI_MEM_SIZE (4 * KiB)
105#define PCI_IO_SIZE 64
106#define PCI_FLASH_SIZE (128 * KiB)
107
108#define BIT(n) (1 << (n))
109#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
110
111/* The SCB accepts the following controls for the Tx and Rx units: */
112#define CU_NOP 0x0000 /* No operation. */
113#define CU_START 0x0010 /* CU start. */
114#define CU_RESUME 0x0020 /* CU resume. */
115#define CU_STATSADDR 0x0040 /* Load dump counters address. */
116#define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
117#define CU_CMD_BASE 0x0060 /* Load CU base address. */
118#define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
119#define CU_SRESUME 0x00a0 /* CU static resume. */
120
121#define RU_NOP 0x0000
122#define RX_START 0x0001
123#define RX_RESUME 0x0002
e824012b 124#define RU_ABORT 0x0004
663e8e51
TS		 125#define RX_ADDR_LOAD 0x0006
126#define RX_RESUMENR 0x0007
127#define INT_MASK 0x0100
128#define DRVR_INT 0x0200 /* Driver generated interrupt. */
129
558c8634 130typedef struct {
39bffca2
AL		 131 const char *name;
132 const char *desc;
40021f08
AL		 133 uint16_t device_id;
134 uint8_t revision;
135 uint16_t subsystem_vendor_id;
136 uint16_t subsystem_id;
137
558c8634 138 uint32_t device;
558c8634
SW		 139 uint8_t stats_size;
140 bool has_extended_tcb_support;
141 bool power_management;
142} E100PCIDeviceInfo;
143
663e8e51
TS		 144/* Offsets to the various registers.
145 All accesses need not be longword aligned. */
e5e23ab8 146typedef enum {
0908bba1 147 SCBStatus = 0, /* Status Word. */
663e8e51
TS		 148 SCBAck = 1,
149 SCBCmd = 2, /* Rx/Command Unit command and status. */
150 SCBIntmask = 3,
151 SCBPointer = 4, /* General purpose pointer. */
152 SCBPort = 8, /* Misc. commands and operands. */
0908bba1
SW		 153 SCBflash = 12, /* Flash memory control. */
154 SCBeeprom = 14, /* EEPROM control. */
663e8e51
TS		 155 SCBCtrlMDI = 16, /* MDI interface control. */
156 SCBEarlyRx = 20, /* Early receive byte count. */
0908bba1
SW		 157 SCBFlow = 24, /* Flow Control. */
158 SCBpmdr = 27, /* Power Management Driver. */
159 SCBgctrl = 28, /* General Control. */
160 SCBgstat = 29, /* General Status. */
e5e23ab8 161} E100RegisterOffset;
663e8e51
TS		 162
163/* A speedo3 transmit buffer descriptor with two buffers... */
164typedef struct {
165 uint16_t status;
166 uint16_t command;
167 uint32_t link; /* void * */
7b8737de 168 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
663e8e51
TS		 169 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
170 uint8_t tx_threshold; /* transmit threshold */
171 uint8_t tbd_count; /* TBD number */
e7493b25
SW		 172#if 0
173 /* This constitutes two "TBD" entries: hdr and data */
174 uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
175 int32_t tx_buf_size0; /* Length of Tx hdr. */
176 uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
177 int32_t tx_buf_size1; /* Length of Tx data. */
178#endif
c227f099 179} eepro100_tx_t;
663e8e51
TS		 180
181/* Receive frame descriptor. */
182typedef struct {
183 int16_t status;
184 uint16_t command;
185 uint32_t link; /* struct RxFD * */
186 uint32_t rx_buf_addr; /* void * */
187 uint16_t count;
188 uint16_t size;
27112f18 189 /* Ethernet frame data follows. */
c227f099 190} eepro100_rx_t;
663e8e51 191
ced5296a
SW		 192typedef enum {
193 COMMAND_EL = BIT(15),
194 COMMAND_S = BIT(14),
195 COMMAND_I = BIT(13),
196 COMMAND_NC = BIT(4),
197 COMMAND_SF = BIT(3),
198 COMMAND_CMD = BITS(2, 0),
199} scb_command_bit;
200
201typedef enum {
202 STATUS_C = BIT(15),
203 STATUS_OK = BIT(13),
204} scb_status_bit;
205
663e8e51
TS		 206typedef struct {
207 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
cc02c66c
SW		 208 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
209 tx_multiple_collisions, tx_total_collisions;
663e8e51 210 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
cc02c66c
SW		 211 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
212 rx_short_frame_errors;
663e8e51
TS		 213 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
214 uint16_t xmt_tco_frames, rcv_tco_frames;
ba42b646
SW		 215 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
216 uint32_t reserved[4];
c227f099 217} eepro100_stats_t;
663e8e51
TS		 218
219typedef enum {
220 cu_idle = 0,
221 cu_suspended = 1,
222 cu_active = 2,
223 cu_lpq_active = 2,
224 cu_hqp_active = 3
c227f099 225} cu_state_t;
663e8e51
TS		 226
227typedef enum {
228 ru_idle = 0,
229 ru_suspended = 1,
230 ru_no_resources = 2,
231 ru_ready = 4
c227f099 232} ru_state_t;
663e8e51 233
663e8e51 234typedef struct {
273a2142 235 PCIDevice dev;
010ec629
SW		 236 /* Hash register (multicast mask array, multiple individual addresses). */
237 uint8_t mult[8];
5e6ffdde
AK		 238 MemoryRegion mmio_bar;
239 MemoryRegion io_bar;
240 MemoryRegion flash_bar;
e00e365e 241 NICState *nic;
508ef936 242 NICConf conf;
663e8e51
TS		 243 uint8_t scb_stat; /* SCB stat/ack byte */
244 uint8_t int_stat; /* PCI interrupt status */
3706c43f 245 /* region must not be saved by nic_save. */
663e8e51 246 uint16_t mdimem[32];
c227f099 247 eeprom_t *eeprom;
663e8e51 248 uint32_t device; /* device variant */
663e8e51
TS		 249 /* (cu_base + cu_offset) address the next command block in the command block list. */
250 uint32_t cu_base; /* CU base address */
251 uint32_t cu_offset; /* CU address offset */
252 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
253 uint32_t ru_base; /* RU base address */
254 uint32_t ru_offset; /* RU address offset */
c227f099 255 uint32_t statsaddr; /* pointer to eepro100_stats_t */
ba42b646 256
f3a52e50
SW		 257 /* Temporary status information (no need to save these values),
258 * used while processing CU commands. */
259 eepro100_tx_t tx; /* transmit buffer descriptor */
260 uint32_t cb_address; /* = cu_base + cu_offset */
261
ba42b646
SW		 262 /* Statistical counters. Also used for wake-up packet (i82559). */
263 eepro100_stats_t statistics;
264
e5e23ab8
SW		 265 /* Data in mem is always in the byte order of the controller (le).
266 * It must be dword aligned to allow direct access to 32 bit values. */
3a93113a 267 uint8_t mem[PCI_MEM_SIZE] __attribute__((aligned(8)));
e5e23ab8 268
663e8e51
TS		 269 /* Configuration bytes. */
270 uint8_t configuration[22];
271
151b2986
JQ		 272 /* vmstate for each particular nic */
273 VMStateDescription *vmstate;
ba42b646
SW		 274
275 /* Quasi static device properties (no need to save them). */
276 uint16_t stats_size;
277 bool has_extended_tcb_support;
663e8e51
TS		 278} EEPRO100State;
279
6cded3a4
SW		 280/* Word indices in EEPROM. */
281typedef enum {
282 EEPROM_CNFG_MDIX = 0x03,
283 EEPROM_ID = 0x05,
284 EEPROM_PHY_ID = 0x06,
285 EEPROM_VENDOR_ID = 0x0c,
286 EEPROM_CONFIG_ASF = 0x0d,
287 EEPROM_DEVICE_ID = 0x23,
288 EEPROM_SMBUS_ADDR = 0x90,
289} EEPROMOffset;
290
b1e87018
SW		 291/* Bit values for EEPROM ID word. */
292typedef enum {
293 EEPROM_ID_MDM = BIT(0), /* Modem */
294 EEPROM_ID_STB = BIT(1), /* Standby Enable */
295 EEPROM_ID_WMR = BIT(2), /* ??? */
296 EEPROM_ID_WOL = BIT(5), /* Wake on LAN */
297 EEPROM_ID_DPD = BIT(6), /* Deep Power Down */
298 EEPROM_ID_ALT = BIT(7), /* */
299 /* BITS(10, 8) device revision */
300 EEPROM_ID_BD = BIT(11), /* boot disable */
301 EEPROM_ID_ID = BIT(13), /* id bit */
302 /* BITS(15, 14) signature */
303 EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */
304} eeprom_id_bit;
305
663e8e51
TS		 306/* Default values for MDI (PHY) registers */
307static const uint16_t eepro100_mdi_default[] = {
308 /* MDI Registers 0 - 6, 7 */
309 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
310 /* MDI Registers 8 - 15 */
311 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
312 /* MDI Registers 16 - 31 */
313 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
314 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
315};
316
317/* Readonly mask for MDI (PHY) registers */
318static const uint16_t eepro100_mdi_mask[] = {
319 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
320 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
321 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
322 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
323};
324
69f3ce78
SW		 325#define POLYNOMIAL 0x04c11db6
326
40021f08
AL		 327static E100PCIDeviceInfo *eepro100_get_class(EEPRO100State *s);
328
69f3ce78
SW		 329/* From FreeBSD (locally modified). */
330static unsigned e100_compute_mcast_idx(const uint8_t *ep)
331{
332 uint32_t crc;
333 int carry, i, j;
334 uint8_t b;
335
336 crc = 0xffffffff;
337 for (i = 0; i < 6; i++) {
338 b = *ep++;
339 for (j = 0; j < 8; j++) {
340 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
341 crc <<= 1;
342 b >>= 1;
343 if (carry) {
344 crc = ((crc ^ POLYNOMIAL) | carry);
345 }
346 }
347 }
348 return (crc & BITS(7, 2)) >> 2;
349}
350
e5e23ab8
SW		 351/* Read a 16 bit control/status (CSR) register. */
352static uint16_t e100_read_reg2(EEPRO100State *s, E100RegisterOffset addr)
353{
354 assert(!((uintptr_t)&s->mem[addr] & 1));
355 return le16_to_cpup((uint16_t *)&s->mem[addr]);
356}
357
358/* Read a 32 bit control/status (CSR) register. */
359static uint32_t e100_read_reg4(EEPRO100State *s, E100RegisterOffset addr)
360{
361 assert(!((uintptr_t)&s->mem[addr] & 3));
362 return le32_to_cpup((uint32_t *)&s->mem[addr]);
363}
364
365/* Write a 16 bit control/status (CSR) register. */
366static void e100_write_reg2(EEPRO100State *s, E100RegisterOffset addr,
367 uint16_t val)
368{
369 assert(!((uintptr_t)&s->mem[addr] & 1));
370 cpu_to_le16w((uint16_t *)&s->mem[addr], val);
371}
372
373/* Read a 32 bit control/status (CSR) register. */
374static void e100_write_reg4(EEPRO100State *s, E100RegisterOffset addr,
375 uint32_t val)
376{
377 assert(!((uintptr_t)&s->mem[addr] & 3));
378 cpu_to_le32w((uint32_t *)&s->mem[addr], val);
379}
380
663e8e51
TS		 381#if defined(DEBUG_EEPRO100)
382static const char *nic_dump(const uint8_t * buf, unsigned size)
383{
384 static char dump[3 * 16 + 1];
385 char *p = &dump[0];
aac443e6 386 if (size > 16) {
663e8e51 387 size = 16;
aac443e6 388 }
663e8e51
TS		 389 while (size-- > 0) {
390 p += sprintf(p, " %02x", *buf++);
391 }
392 return dump;
393}
394#endif /* DEBUG_EEPRO100 */
395
396enum scb_stat_ack {
397 stat_ack_not_ours = 0x00,
398 stat_ack_sw_gen = 0x04,
399 stat_ack_rnr = 0x10,
400 stat_ack_cu_idle = 0x20,
401 stat_ack_frame_rx = 0x40,
402 stat_ack_cu_cmd_done = 0x80,
403 stat_ack_not_present = 0xFF,
404 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
405 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
406};
407
408static void disable_interrupt(EEPRO100State * s)
409{
410 if (s->int_stat) {
aac443e6 411 TRACE(INT, logout("interrupt disabled\n"));
273a2142 412 qemu_irq_lower(s->dev.irq[0]);
663e8e51
TS		 413 s->int_stat = 0;
414 }
415}
416
417static void enable_interrupt(EEPRO100State * s)
418{
419 if (!s->int_stat) {
aac443e6 420 TRACE(INT, logout("interrupt enabled\n"));
273a2142 421 qemu_irq_raise(s->dev.irq[0]);
663e8e51
TS		 422 s->int_stat = 1;
423 }
424}
425
426static void eepro100_acknowledge(EEPRO100State * s)
427{
428 s->scb_stat &= ~s->mem[SCBAck];
429 s->mem[SCBAck] = s->scb_stat;
430 if (s->scb_stat == 0) {
431 disable_interrupt(s);
432 }
433}
434
e715c8e8 435static void eepro100_interrupt(EEPRO100State * s, uint8_t status)
663e8e51
TS		 436{
437 uint8_t mask = ~s->mem[SCBIntmask];
e715c8e8
SW		 438 s->mem[SCBAck] |= status;
439 status = s->scb_stat = s->mem[SCBAck];
440 status &= (mask | 0x0f);
e7493b25
SW		 441#if 0
442 status &= (~s->mem[SCBIntmask] | 0x0xf);
443#endif
e715c8e8 444 if (status && (mask & 0x01)) {
663e8e51
TS		 445 /* SCB mask and SCB Bit M do not disable interrupt. */
446 enable_interrupt(s);
447 } else if (s->int_stat) {
448 disable_interrupt(s);
449 }
450}
451
452static void eepro100_cx_interrupt(EEPRO100State * s)
453{
454 /* CU completed action command. */
455 /* Transmit not ok (82557 only, not in emulation). */
456 eepro100_interrupt(s, 0x80);
457}
458
459static void eepro100_cna_interrupt(EEPRO100State * s)
460{
461 /* CU left the active state. */
462 eepro100_interrupt(s, 0x20);
463}
464
465static void eepro100_fr_interrupt(EEPRO100State * s)
466{
467 /* RU received a complete frame. */
468 eepro100_interrupt(s, 0x40);
469}
470
663e8e51
TS		 471static void eepro100_rnr_interrupt(EEPRO100State * s)
472{
473 /* RU is not ready. */
474 eepro100_interrupt(s, 0x10);
475}
663e8e51
TS		 476
477static void eepro100_mdi_interrupt(EEPRO100State * s)
478{
479 /* MDI completed read or write cycle. */
480 eepro100_interrupt(s, 0x08);
481}
482
483static void eepro100_swi_interrupt(EEPRO100State * s)
484{
485 /* Software has requested an interrupt. */
486 eepro100_interrupt(s, 0x04);
487}
488
489#if 0
490static void eepro100_fcp_interrupt(EEPRO100State * s)
491{
492 /* Flow control pause interrupt (82558 and later). */
493 eepro100_interrupt(s, 0x01);
494}
495#endif
496
40021f08 497static void e100_pci_reset(EEPRO100State * s)
663e8e51 498{
40021f08 499 E100PCIDeviceInfo *info = eepro100_get_class(s);
663e8e51 500 uint32_t device = s->device;
273a2142 501 uint8_t *pci_conf = s->dev.config;
663e8e51 502
aac443e6 503 TRACE(OTHER, logout("%p\n", s));
663e8e51 504
663e8e51 505 /* PCI Status */
ae543b49
SW		 506 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
507 PCI_STATUS_FAST_BACK);
663e8e51 508 /* PCI Latency Timer */
15e89f59 509 pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */
ae543b49 510 /* Capability Pointer is set by PCI framework. */
f62719ca
SW		 511 /* Interrupt Line */
512 /* Interrupt Pin */
513 pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1); /* interrupt pin A */
663e8e51 514 /* Minimum Grant */
15e89f59 515 pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08);
663e8e51 516 /* Maximum Latency */
15e89f59 517 pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18);
663e8e51 518
40021f08
AL		 519 s->stats_size = info->stats_size;
520 s->has_extended_tcb_support = info->has_extended_tcb_support;
558c8634 521
663e8e51 522 switch (device) {
ba42b646 523 case i82550:
663e8e51 524 case i82551:
ba42b646 525 case i82557A:
663e8e51 526 case i82557B:
663e8e51 527 case i82557C:
ba42b646 528 case i82558A:
663e8e51 529 case i82558B:
ba42b646 530 case i82559A:
ba42b646 531 case i82559B:
558c8634
SW		 532 case i82559ER:
533 case i82562:
db667a12 534 case i82801:
663e8e51 535 case i82559C:
663e8e51 536 break;
663e8e51
TS		 537 default:
538 logout("Device %X is undefined!\n", device);
539 }
540
3dec59a1
SW		 541 /* Standard TxCB. */
542 s->configuration[6] |= BIT(4);
543
558c8634 544 /* Standard statistical counters. */
ba42b646
SW		 545 s->configuration[6] |= BIT(5);
546
547 if (s->stats_size == 80) {
548 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
549 if (s->configuration[6] & BIT(2)) {
550 /* TCO statistical counters. */
551 assert(s->configuration[6] & BIT(5));
552 } else {
553 if (s->configuration[6] & BIT(5)) {
554 /* No extended statistical counters, i82557 compatible. */
555 s->stats_size = 64;
556 } else {
557 /* i82558 compatible. */
558 s->stats_size = 76;
559 }
560 }
561 } else {
562 if (s->configuration[6] & BIT(5)) {
563 /* No extended statistical counters. */
564 s->stats_size = 64;
565 }
566 }
567 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
568
40021f08 569 if (info->power_management) {
ba42b646 570 /* Power Management Capabilities */
8bbd1ce2 571 int cfg_offset = 0xdc;
ca77089d
IY		 572 int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
573 cfg_offset, PCI_PM_SIZEOF);
8bbd1ce2
MT		 574 assert(r >= 0);
575 pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
ae543b49 576#if 0 /* TODO: replace dummy code for power management emulation. */
8bbd1ce2
MT		 577 /* TODO: Power Management Control / Status. */
578 pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000);
579 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
580 pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000);
ae543b49 581#endif
ba42b646
SW		 582 }
583
584#if EEPROM_SIZE > 0
663e8e51 585 if (device == i82557C || device == i82558B || device == i82559C) {
e7493b25
SW		 586 /*
587 TODO: get vendor id from EEPROM for i82557C or later.
588 TODO: get device id from EEPROM for i82557C or later.
589 TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
590 TODO: header type is determined by EEPROM for i82559.
591 TODO: get subsystem id from EEPROM for i82557C or later.
592 TODO: get subsystem vendor id from EEPROM for i82557C or later.
593 TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
594 TODO: capability pointer depends on EEPROM for i82558.
595 */
663e8e51
TS		 596 logout("Get device id and revision from EEPROM!!!\n");
597 }
ba42b646 598#endif /* EEPROM_SIZE > 0 */
663e8e51
TS		 599}
600
601static void nic_selective_reset(EEPRO100State * s)
602{
603 size_t i;
604 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
e7493b25
SW		 605#if 0
606 eeprom93xx_reset(s->eeprom);
607#endif
508ef936 608 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
b1e87018 609 eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID;
f4e94dfe
RD		 610 if (s->device == i82557B || s->device == i82557C)
611 eeprom_contents[5] = 0x0100;
6cded3a4 612 eeprom_contents[EEPROM_PHY_ID] = 1;
663e8e51
TS		 613 uint16_t sum = 0;
614 for (i = 0; i < EEPROM_SIZE - 1; i++) {
615 sum += eeprom_contents[i];
616 }
617 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
aac443e6 618 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
663e8e51
TS		 619
620 memset(s->mem, 0, sizeof(s->mem));
e5e23ab8 621 e100_write_reg4(s, SCBCtrlMDI, BIT(21));
663e8e51
TS		 622
623 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
624 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
625}
626
627static void nic_reset(void *opaque)
628{
769cf7a5 629 EEPRO100State *s = opaque;
aac443e6 630 TRACE(OTHER, logout("%p\n", s));
010ec629 631 /* TODO: Clearing of hash register for selective reset, too? */
7b8737de 632 memset(&s->mult[0], 0, sizeof(s->mult));
663e8e51
TS		 633 nic_selective_reset(s);
634}
635
636#if defined(DEBUG_EEPRO100)
b8f6ba0d 637static const char * const e100_reg[PCI_IO_SIZE / 4] = {
663e8e51
TS		 638 "Command/Status",
639 "General Pointer",
640 "Port",
641 "EEPROM/Flash Control",
642 "MDI Control",
643 "Receive DMA Byte Count",
b8f6ba0d 644 "Flow Control",
663e8e51
TS		 645 "General Status/Control"
646};
647
648static char *regname(uint32_t addr)
649{
ec169288 650 static char buf[32];
663e8e51 651 if (addr < PCI_IO_SIZE) {
b8f6ba0d 652 const char *r = e100_reg[addr / 4];
663e8e51 653 if (r != 0) {
41cbc23c 654 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
663e8e51 655 } else {
41cbc23c 656 snprintf(buf, sizeof(buf), "0x%02x", addr);
663e8e51
TS		 657 }
658 } else {
41cbc23c 659 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
663e8e51
TS		 660 }
661 return buf;
662}
663#endif /* DEBUG_EEPRO100 */
664
663e8e51
TS		 665/*****************************************************************************
666 *
667 * Command emulation.
668 *
669 ****************************************************************************/
670
671#if 0
672static uint16_t eepro100_read_command(EEPRO100State * s)
673{
674 uint16_t val = 0xffff;
e7493b25 675 TRACE(OTHER, logout("val=0x%04x\n", val));
663e8e51
TS		 676 return val;
677}
678#endif
679
680/* Commands that can be put in a command list entry. */
681enum commands {
682 CmdNOp = 0,
683 CmdIASetup = 1,
684 CmdConfigure = 2,
685 CmdMulticastList = 3,
686 CmdTx = 4,
687 CmdTDR = 5, /* load microcode */
688 CmdDump = 6,
689 CmdDiagnose = 7,
690
691 /* And some extra flags: */
692 CmdSuspend = 0x4000, /* Suspend after completion. */
693 CmdIntr = 0x2000, /* Interrupt after completion. */
694 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
695};
696
c227f099 697static cu_state_t get_cu_state(EEPRO100State * s)
663e8e51 698{
ced5296a 699 return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6);
663e8e51
TS		 700}
701
c227f099 702static void set_cu_state(EEPRO100State * s, cu_state_t state)
663e8e51 703{
ced5296a 704 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6);
663e8e51
TS		 705}
706
c227f099 707static ru_state_t get_ru_state(EEPRO100State * s)
663e8e51 708{
ced5296a 709 return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2);
663e8e51
TS		 710}
711
c227f099 712static void set_ru_state(EEPRO100State * s, ru_state_t state)
663e8e51 713{
ced5296a 714 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2);
663e8e51
TS		 715}
716
717static void dump_statistics(EEPRO100State * s)
718{
719 /* Dump statistical data. Most data is never changed by the emulation
720 * and always 0, so we first just copy the whole block and then those
721 * values which really matter.
722 * Number of data should check configuration!!!
723 */
e965d4bc 724 pci_dma_write(&s->dev, s->statsaddr, &s->statistics, s->stats_size);
16ef60c9
EGM		 725 stl_le_pci_dma(&s->dev, s->statsaddr + 0,
726 s->statistics.tx_good_frames);
727 stl_le_pci_dma(&s->dev, s->statsaddr + 36,
728 s->statistics.rx_good_frames);
729 stl_le_pci_dma(&s->dev, s->statsaddr + 48,
730 s->statistics.rx_resource_errors);
731 stl_le_pci_dma(&s->dev, s->statsaddr + 60,
732 s->statistics.rx_short_frame_errors);
e7493b25 733#if 0
16ef60c9
EGM		 734 stw_le_pci_dma(&s->dev, s->statsaddr + 76, s->statistics.xmt_tco_frames);
735 stw_le_pci_dma(&s->dev, s->statsaddr + 78, s->statistics.rcv_tco_frames);
e7493b25
SW		 736 missing("CU dump statistical counters");
737#endif
663e8e51
TS		 738}
739
3d0f4b9b
SW		 740static void read_cb(EEPRO100State *s)
741{
e965d4bc 742 pci_dma_read(&s->dev, s->cb_address, &s->tx, sizeof(s->tx));
3d0f4b9b
SW		 743 s->tx.status = le16_to_cpu(s->tx.status);
744 s->tx.command = le16_to_cpu(s->tx.command);
745 s->tx.link = le32_to_cpu(s->tx.link);
746 s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr);
747 s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes);
748}
749
f3a52e50
SW		 750static void tx_command(EEPRO100State *s)
751{
7b8737de 752 uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
f3a52e50
SW		 753 uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
754 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
755 uint8_t buf[2600];
756 uint16_t size = 0;
757 uint32_t tbd_address = s->cb_address + 0x10;
758 TRACE(RXTX, logout
759 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
760 tbd_array, tcb_bytes, s->tx.tbd_count));
761
762 if (tcb_bytes > 2600) {
763 logout("TCB byte count too large, using 2600\n");
764 tcb_bytes = 2600;
765 }
766 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
767 logout
768 ("illegal values of TBD array address and TCB byte count!\n");
769 }
770 assert(tcb_bytes <= sizeof(buf));
771 while (size < tcb_bytes) {
16ef60c9
EGM		 772 uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev, tbd_address);
773 uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev, tbd_address + 4);
e7493b25 774#if 0
16ef60c9 775 uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev, tbd_address + 6);
e7493b25 776#endif
f3a52e50
SW		 777 tbd_address += 8;
778 TRACE(RXTX, logout
779 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
780 tx_buffer_address, tx_buffer_size));
781 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
16ef60c9 782 pci_dma_read(&s->dev, tx_buffer_address, &buf[size], tx_buffer_size);
f3a52e50
SW		 783 size += tx_buffer_size;
784 }
785 if (tbd_array == 0xffffffff) {
786 /* Simplified mode. Was already handled by code above. */
787 } else {
788 /* Flexible mode. */
789 uint8_t tbd_count = 0;
790 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
791 /* Extended Flexible TCB. */
792 for (; tbd_count < 2; tbd_count++) {
16ef60c9
EGM		 793 uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev,
794 tbd_address);
795 uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev,
796 tbd_address + 4);
797 uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev,
798 tbd_address + 6);
f3a52e50
SW		 799 tbd_address += 8;
800 TRACE(RXTX, logout
801 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
802 tx_buffer_address, tx_buffer_size));
803 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
16ef60c9
EGM		 804 pci_dma_read(&s->dev, tx_buffer_address,
805 &buf[size], tx_buffer_size);
f3a52e50
SW		 806 size += tx_buffer_size;
807 if (tx_buffer_el & 1) {
808 break;
809 }
810 }
811 }
812 tbd_address = tbd_array;
813 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
16ef60c9
EGM		 814 uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev, tbd_address);
815 uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev, tbd_address + 4);
816 uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev, tbd_address + 6);
f3a52e50
SW		 817 tbd_address += 8;
818 TRACE(RXTX, logout
819 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
820 tx_buffer_address, tx_buffer_size));
821 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
16ef60c9
EGM		 822 pci_dma_read(&s->dev, tx_buffer_address,
823 &buf[size], tx_buffer_size);
f3a52e50
SW		 824 size += tx_buffer_size;
825 if (tx_buffer_el & 1) {
826 break;
827 }
828 }
829 }
830 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
831 qemu_send_packet(&s->nic->nc, buf, size);
832 s->statistics.tx_good_frames++;
833 /* Transmit with bad status would raise an CX/TNO interrupt.
834 * (82557 only). Emulation never has bad status. */
e7493b25
SW		 835#if 0
836 eepro100_cx_interrupt(s);
837#endif
f3a52e50
SW		 838}
839
7b8737de
SW		 840static void set_multicast_list(EEPRO100State *s)
841{
842 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
843 uint16_t i;
844 memset(&s->mult[0], 0, sizeof(s->mult));
845 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
846 for (i = 0; i < multicast_count; i += 6) {
847 uint8_t multicast_addr[6];
16ef60c9 848 pci_dma_read(&s->dev, s->cb_address + 10 + i, multicast_addr, 6);
7b8737de 849 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
69f3ce78 850 unsigned mcast_idx = e100_compute_mcast_idx(multicast_addr);
7b8737de
SW		 851 assert(mcast_idx < 64);
852 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
853 }
854}
855
5fa9a0ae 856static void action_command(EEPRO100State *s)
663e8e51 857{
5fa9a0ae 858 for (;;) {
3d0f4b9b
SW		 859 bool bit_el;
860 bool bit_s;
861 bool bit_i;
862 bool bit_nc;
75f5a6cc 863 uint16_t ok_status = STATUS_OK;
3d0f4b9b
SW		 864 s->cb_address = s->cu_base + s->cu_offset;
865 read_cb(s);
866 bit_el = ((s->tx.command & COMMAND_EL) != 0);
867 bit_s = ((s->tx.command & COMMAND_S) != 0);
868 bit_i = ((s->tx.command & COMMAND_I) != 0);
869 bit_nc = ((s->tx.command & COMMAND_NC) != 0);
870#if 0
871 bool bit_sf = ((s->tx.command & COMMAND_SF) != 0);
872#endif
873 s->cu_offset = s->tx.link;
874 TRACE(OTHER,
875 logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
876 s->tx.status, s->tx.command, s->tx.link));
877 switch (s->tx.command & COMMAND_CMD) {
663e8e51
TS		 878 case CmdNOp:
879 /* Do nothing. */
880 break;
881 case CmdIASetup:
16ef60c9 882 pci_dma_read(&s->dev, s->cb_address + 8, &s->conf.macaddr.a[0], 6);
ce0e58b3 883 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
663e8e51
TS		 884 break;
885 case CmdConfigure:
16ef60c9
EGM		 886 pci_dma_read(&s->dev, s->cb_address + 8,
887 &s->configuration[0], sizeof(s->configuration));
010ec629
SW		 888 TRACE(OTHER, logout("configuration: %s\n",
889 nic_dump(&s->configuration[0], 16)));
890 TRACE(OTHER, logout("configuration: %s\n",
891 nic_dump(&s->configuration[16],
892 ARRAY_SIZE(s->configuration) - 16)));
893 if (s->configuration[20] & BIT(6)) {
894 TRACE(OTHER, logout("Multiple IA bit\n"));
895 }
663e8e51
TS		 896 break;
897 case CmdMulticastList:
7b8737de 898 set_multicast_list(s);
663e8e51
TS		 899 break;
900 case CmdTx:
7f1e9d4e
KW		 901 if (bit_nc) {
902 missing("CmdTx: NC = 0");
75f5a6cc 903 ok_status = 0;
7f1e9d4e
KW		 904 break;
905 }
f3a52e50 906 tx_command(s);
663e8e51
TS		 907 break;
908 case CmdTDR:
aac443e6 909 TRACE(OTHER, logout("load microcode\n"));
663e8e51
TS		 910 /* Starting with offset 8, the command contains
911 * 64 dwords microcode which we just ignore here. */
912 break;
f80a7fc3
SW		 913 case CmdDiagnose:
914 TRACE(OTHER, logout("diagnose\n"));
915 /* Make sure error flag is not set. */
916 s->tx.status = 0;
917 break;
663e8e51
TS		 918 default:
919 missing("undefined command");
75f5a6cc 920 ok_status = 0;
7f1e9d4e 921 break;
663e8e51 922 }
7f1e9d4e 923 /* Write new status. */
16ef60c9
EGM		 924 stw_le_pci_dma(&s->dev, s->cb_address,
925 s->tx.status | ok_status | STATUS_C);
663e8e51
TS		 926 if (bit_i) {
927 /* CU completed action. */
928 eepro100_cx_interrupt(s);
929 }
930 if (bit_el) {
aac443e6 931 /* CU becomes idle. Terminate command loop. */
663e8e51
TS		 932 set_cu_state(s, cu_idle);
933 eepro100_cna_interrupt(s);
5fa9a0ae 934 break;
663e8e51 935 } else if (bit_s) {
5fa9a0ae 936 /* CU becomes suspended. Terminate command loop. */
663e8e51
TS		 937 set_cu_state(s, cu_suspended);
938 eepro100_cna_interrupt(s);
5fa9a0ae 939 break;
663e8e51
TS		 940 } else {
941 /* More entries in list. */
aac443e6 942 TRACE(OTHER, logout("CU list with at least one more entry\n"));
663e8e51 943 }
5fa9a0ae
SW		 944 }
945 TRACE(OTHER, logout("CU list empty\n"));
946 /* List is empty. Now CU is idle or suspended. */
947}
948
949static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
950{
cb25a3fb 951 cu_state_t cu_state;
5fa9a0ae
SW		 952 switch (val) {
953 case CU_NOP:
954 /* No operation. */
955 break;
956 case CU_START:
cb25a3fb
SW		 957 cu_state = get_cu_state(s);
958 if (cu_state != cu_idle && cu_state != cu_suspended) {
959 /* Intel documentation says that CU must be idle or suspended
960 * for the CU start command. */
961 logout("unexpected CU state is %u\n", cu_state);
5fa9a0ae
SW		 962 }
963 set_cu_state(s, cu_active);
27a05006 964 s->cu_offset = e100_read_reg4(s, SCBPointer);
5fa9a0ae 965 action_command(s);
663e8e51
TS		 966 break;
967 case CU_RESUME:
968 if (get_cu_state(s) != cu_suspended) {
969 logout("bad CU resume from CU state %u\n", get_cu_state(s));
970 /* Workaround for bad Linux eepro100 driver which resumes
971 * from idle state. */
e7493b25
SW		 972#if 0
973 missing("cu resume");
974#endif
663e8e51
TS		 975 set_cu_state(s, cu_suspended);
976 }
977 if (get_cu_state(s) == cu_suspended) {
aac443e6 978 TRACE(OTHER, logout("CU resuming\n"));
663e8e51 979 set_cu_state(s, cu_active);
5fa9a0ae 980 action_command(s);
663e8e51
TS		 981 }
982 break;
983 case CU_STATSADDR:
984 /* Load dump counters address. */
27a05006 985 s->statsaddr = e100_read_reg4(s, SCBPointer);
c16ada98
SW		 986 TRACE(OTHER, logout("val=0x%02x (dump counters address)\n", val));
987 if (s->statsaddr & 3) {
988 /* Memory must be Dword aligned. */
989 logout("unaligned dump counters address\n");
990 /* Handling of misaligned addresses is undefined.
991 * Here we align the address by ignoring the lower bits. */
992 /* TODO: Test unaligned dump counter address on real hardware. */
993 s->statsaddr &= ~3;
994 }
663e8e51
TS		 995 break;
996 case CU_SHOWSTATS:
997 /* Dump statistical counters. */
aac443e6 998 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
663e8e51 999 dump_statistics(s);
16ef60c9 1000 stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa005);
663e8e51
TS		 1001 break;
1002 case CU_CMD_BASE:
1003 /* Load CU base. */
aac443e6 1004 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
27a05006 1005 s->cu_base = e100_read_reg4(s, SCBPointer);
663e8e51
TS		 1006 break;
1007 case CU_DUMPSTATS:
1008 /* Dump and reset statistical counters. */
aac443e6 1009 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
663e8e51 1010 dump_statistics(s);
16ef60c9 1011 stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa007);
663e8e51
TS		 1012 memset(&s->statistics, 0, sizeof(s->statistics));
1013 break;
1014 case CU_SRESUME:
1015 /* CU static resume. */
1016 missing("CU static resume");
1017 break;
1018 default:
1019 missing("Undefined CU command");
1020 }
1021}
1022
1023static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
1024{
1025 switch (val) {
1026 case RU_NOP:
1027 /* No operation. */
1028 break;
1029 case RX_START:
1030 /* RU start. */
1031 if (get_ru_state(s) != ru_idle) {
1032 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
e7493b25
SW		 1033#if 0
1034 assert(!"wrong RU state");
1035#endif
663e8e51
TS		 1036 }
1037 set_ru_state(s, ru_ready);
27a05006 1038 s->ru_offset = e100_read_reg4(s, SCBPointer);
aac443e6 1039 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
663e8e51
TS		 1040 break;
1041 case RX_RESUME:
1042 /* Restart RU. */
1043 if (get_ru_state(s) != ru_suspended) {
1044 logout("RU state is %u, should be %u\n", get_ru_state(s),
1045 ru_suspended);
e7493b25
SW		 1046#if 0
1047 assert(!"wrong RU state");
1048#endif
663e8e51
TS		 1049 }
1050 set_ru_state(s, ru_ready);
1051 break;
e824012b
SW		 1052 case RU_ABORT:
1053 /* RU abort. */
1054 if (get_ru_state(s) == ru_ready) {
1055 eepro100_rnr_interrupt(s);
1056 }
1057 set_ru_state(s, ru_idle);
1058 break;
663e8e51
TS		 1059 case RX_ADDR_LOAD:
1060 /* Load RU base. */
aac443e6 1061 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
27a05006 1062 s->ru_base = e100_read_reg4(s, SCBPointer);
663e8e51
TS		 1063 break;
1064 default:
1065 logout("val=0x%02x (undefined RU command)\n", val);
1066 missing("Undefined SU command");
1067 }
1068}
1069
1070static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1071{
1072 eepro100_ru_command(s, val & 0x0f);
1073 eepro100_cu_command(s, val & 0xf0);
1074 if ((val) == 0) {
aac443e6 1075 TRACE(OTHER, logout("val=0x%02x\n", val));
663e8e51
TS		 1076 }
1077 /* Clear command byte after command was accepted. */
1078 s->mem[SCBCmd] = 0;
1079}
1080
1081/*****************************************************************************
1082 *
1083 * EEPROM emulation.
1084 *
1085 ****************************************************************************/
1086
1087#define EEPROM_CS 0x02
1088#define EEPROM_SK 0x01
1089#define EEPROM_DI 0x04
1090#define EEPROM_DO 0x08
1091
1092static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1093{
e5e23ab8 1094 uint16_t val = e100_read_reg2(s, SCBeeprom);
663e8e51
TS		 1095 if (eeprom93xx_read(s->eeprom)) {
1096 val |= EEPROM_DO;
1097 } else {
1098 val &= ~EEPROM_DO;
1099 }
aac443e6 1100 TRACE(EEPROM, logout("val=0x%04x\n", val));
663e8e51
TS		 1101 return val;
1102}
1103
c227f099 1104static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
663e8e51 1105{
aac443e6 1106 TRACE(EEPROM, logout("val=0x%02x\n", val));
663e8e51 1107
ebabb67a 1108 /* mask unwritable bits */
e7493b25
SW		 1109#if 0
1110 val = SET_MASKED(val, 0x31, eeprom->value);
1111#endif
663e8e51
TS		 1112
1113 int eecs = ((val & EEPROM_CS) != 0);
1114 int eesk = ((val & EEPROM_SK) != 0);
1115 int eedi = ((val & EEPROM_DI) != 0);
1116 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1117}
1118
663e8e51
TS		 1119/*****************************************************************************
1120 *
1121 * MDI emulation.
1122 *
1123 ****************************************************************************/
1124
1125#if defined(DEBUG_EEPRO100)
6a0b9cc9 1126static const char * const mdi_op_name[] = {
663e8e51
TS		 1127 "opcode 0",
1128 "write",
1129 "read",
1130 "opcode 3"
1131};
1132
6a0b9cc9 1133static const char * const mdi_reg_name[] = {
663e8e51
TS		 1134 "Control",
1135 "Status",
1136 "PHY Identification (Word 1)",
1137 "PHY Identification (Word 2)",
1138 "Auto-Negotiation Advertisement",
1139 "Auto-Negotiation Link Partner Ability",
1140 "Auto-Negotiation Expansion"
1141};
aac443e6
SW		 1142
1143static const char *reg2name(uint8_t reg)
1144{
1145 static char buffer[10];
1146 const char *p = buffer;
1147 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1148 p = mdi_reg_name[reg];
1149 } else {
1150 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1151 }
1152 return p;
1153}
663e8e51
TS		 1154#endif /* DEBUG_EEPRO100 */
1155
1156static uint32_t eepro100_read_mdi(EEPRO100State * s)
1157{
e5e23ab8 1158 uint32_t val = e100_read_reg4(s, SCBCtrlMDI);
663e8e51
TS		 1159
1160#ifdef DEBUG_EEPRO100
1161 uint8_t raiseint = (val & BIT(29)) >> 29;
1162 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1163 uint8_t phy = (val & BITS(25, 21)) >> 21;
1164 uint8_t reg = (val & BITS(20, 16)) >> 16;
1165 uint16_t data = (val & BITS(15, 0));
1166#endif
1167 /* Emulation takes no time to finish MDI transaction. */
1168 val |= BIT(28);
1169 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1170 val, raiseint, mdi_op_name[opcode], phy,
aac443e6 1171 reg2name(reg), data));
663e8e51
TS		 1172 return val;
1173}
1174
0113f48d 1175static void eepro100_write_mdi(EEPRO100State *s)
663e8e51 1176{
0113f48d 1177 uint32_t val = e100_read_reg4(s, SCBCtrlMDI);
663e8e51
TS		 1178 uint8_t raiseint = (val & BIT(29)) >> 29;
1179 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1180 uint8_t phy = (val & BITS(25, 21)) >> 21;
1181 uint8_t reg = (val & BITS(20, 16)) >> 16;
1182 uint16_t data = (val & BITS(15, 0));
aac443e6
SW		 1183 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1184 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
663e8e51
TS		 1185 if (phy != 1) {
1186 /* Unsupported PHY address. */
e7493b25
SW		 1187#if 0
1188 logout("phy must be 1 but is %u\n", phy);
1189#endif
663e8e51
TS		 1190 data = 0;
1191 } else if (opcode != 1 && opcode != 2) {
1192 /* Unsupported opcode. */
1193 logout("opcode must be 1 or 2 but is %u\n", opcode);
1194 data = 0;
1195 } else if (reg > 6) {
1196 /* Unsupported register. */
1197 logout("register must be 0...6 but is %u\n", reg);
1198 data = 0;
1199 } else {
1200 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1201 val, raiseint, mdi_op_name[opcode], phy,
aac443e6 1202 reg2name(reg), data));
663e8e51
TS		 1203 if (opcode == 1) {
1204 /* MDI write */
1205 switch (reg) {
1206 case 0: /* Control Register */
1207 if (data & 0x8000) {
1208 /* Reset status and control registers to default. */
1209 s->mdimem[0] = eepro100_mdi_default[0];
1210 s->mdimem[1] = eepro100_mdi_default[1];
1211 data = s->mdimem[reg];
1212 } else {
1213 /* Restart Auto Configuration = Normal Operation */
1214 data &= ~0x0200;
1215 }
1216 break;
1217 case 1: /* Status Register */
1218 missing("not writable");
1219 data = s->mdimem[reg];
1220 break;
1221 case 2: /* PHY Identification Register (Word 1) */
1222 case 3: /* PHY Identification Register (Word 2) */
1223 missing("not implemented");
1224 break;
1225 case 4: /* Auto-Negotiation Advertisement Register */
1226 case 5: /* Auto-Negotiation Link Partner Ability Register */
1227 break;
1228 case 6: /* Auto-Negotiation Expansion Register */
1229 default:
1230 missing("not implemented");
1231 }
1232 s->mdimem[reg] = data;
1233 } else if (opcode == 2) {
1234 /* MDI read */
1235 switch (reg) {
1236 case 0: /* Control Register */
1237 if (data & 0x8000) {
1238 /* Reset status and control registers to default. */
1239 s->mdimem[0] = eepro100_mdi_default[0];
1240 s->mdimem[1] = eepro100_mdi_default[1];
1241 }
1242 break;
1243 case 1: /* Status Register */
1244 s->mdimem[reg] |= 0x0020;
1245 break;
1246 case 2: /* PHY Identification Register (Word 1) */
1247 case 3: /* PHY Identification Register (Word 2) */
1248 case 4: /* Auto-Negotiation Advertisement Register */
1249 break;
1250 case 5: /* Auto-Negotiation Link Partner Ability Register */
1251 s->mdimem[reg] = 0x41fe;
1252 break;
1253 case 6: /* Auto-Negotiation Expansion Register */
1254 s->mdimem[reg] = 0x0001;
1255 break;
1256 }
1257 data = s->mdimem[reg];
1258 }
1259 /* Emulation takes no time to finish MDI transaction.
1260 * Set MDI bit in SCB status register. */
1261 s->mem[SCBAck] |= 0x08;
1262 val |= BIT(28);
1263 if (raiseint) {
1264 eepro100_mdi_interrupt(s);
1265 }
1266 }
1267 val = (val & 0xffff0000) + data;
e5e23ab8 1268 e100_write_reg4(s, SCBCtrlMDI, val);
663e8e51
TS		 1269}
1270
1271/*****************************************************************************
1272 *
1273 * Port emulation.
1274 *
1275 ****************************************************************************/
1276
1277#define PORT_SOFTWARE_RESET 0
1278#define PORT_SELFTEST 1
1279#define PORT_SELECTIVE_RESET 2
1280#define PORT_DUMP 3
1281#define PORT_SELECTION_MASK 3
1282
1283typedef struct {
1284 uint32_t st_sign; /* Self Test Signature */
1285 uint32_t st_result; /* Self Test Results */
c227f099 1286} eepro100_selftest_t;
663e8e51
TS		 1287
1288static uint32_t eepro100_read_port(EEPRO100State * s)
1289{
1290 return 0;
1291}
1292
3fd3d0b4 1293static void eepro100_write_port(EEPRO100State *s)
663e8e51 1294{
3fd3d0b4 1295 uint32_t val = e100_read_reg4(s, SCBPort);
663e8e51
TS		 1296 uint32_t address = (val & ~PORT_SELECTION_MASK);
1297 uint8_t selection = (val & PORT_SELECTION_MASK);
1298 switch (selection) {
1299 case PORT_SOFTWARE_RESET:
1300 nic_reset(s);
1301 break;
1302 case PORT_SELFTEST:
aac443e6 1303 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
c227f099 1304 eepro100_selftest_t data;
16ef60c9 1305 pci_dma_read(&s->dev, address, (uint8_t *) &data, sizeof(data));
663e8e51
TS		 1306 data.st_sign = 0xffffffff;
1307 data.st_result = 0;
16ef60c9 1308 pci_dma_write(&s->dev, address, (uint8_t *) &data, sizeof(data));
663e8e51
TS		 1309 break;
1310 case PORT_SELECTIVE_RESET:
aac443e6 1311 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
663e8e51
TS		 1312 nic_selective_reset(s);
1313 break;
1314 default:
1315 logout("val=0x%08x\n", val);
1316 missing("unknown port selection");
1317 }
1318}
1319
1320/*****************************************************************************
1321 *
1322 * General hardware emulation.
1323 *
1324 ****************************************************************************/
1325
1326static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1327{
ef476062 1328 uint8_t val = 0;
663e8e51 1329 if (addr <= sizeof(s->mem) - sizeof(val)) {
e5e23ab8 1330 val = s->mem[addr];
663e8e51
TS		 1331 }
1332
1333 switch (addr) {
1334 case SCBStatus:
663e8e51 1335 case SCBAck:
aac443e6 1336 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1337 break;
1338 case SCBCmd:
aac443e6 1339 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
e7493b25
SW		 1340#if 0
1341 val = eepro100_read_command(s);
1342#endif
663e8e51
TS		 1343 break;
1344 case SCBIntmask:
aac443e6 1345 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1346 break;
1347 case SCBPort + 3:
aac443e6 1348 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1349 break;
1350 case SCBeeprom:
1351 val = eepro100_read_eeprom(s);
1352 break;
0113f48d
SW		 1353 case SCBCtrlMDI:
1354 case SCBCtrlMDI + 1:
1355 case SCBCtrlMDI + 2:
1356 case SCBCtrlMDI + 3:
1357 val = (uint8_t)(eepro100_read_mdi(s) >> (8 * (addr & 3)));
1358 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1359 break;
0908bba1 1360 case SCBpmdr: /* Power Management Driver Register */
663e8e51 1361 val = 0;
aac443e6 1362 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51 1363 break;
a39bd017
SW		 1364 case SCBgctrl: /* General Control Register */
1365 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1366 break;
0908bba1 1367 case SCBgstat: /* General Status Register */
663e8e51
TS		 1368 /* 100 Mbps full duplex, valid link */
1369 val = 0x07;
aac443e6 1370 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
663e8e51
TS		 1371 break;
1372 default:
1373 logout("addr=%s val=0x%02x\n", regname(addr), val);
1374 missing("unknown byte read");
1375 }
1376 return val;
1377}
1378
1379static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1380{
ef476062 1381 uint16_t val = 0;
663e8e51 1382 if (addr <= sizeof(s->mem) - sizeof(val)) {
e5e23ab8 1383 val = e100_read_reg2(s, addr);
663e8e51
TS		 1384 }
1385
663e8e51
TS		 1386 switch (addr) {
1387 case SCBStatus:
dbbaaff6 1388 case SCBCmd:
aac443e6 1389 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
663e8e51
TS		 1390 break;
1391 case SCBeeprom:
1392 val = eepro100_read_eeprom(s);
aac443e6 1393 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
663e8e51 1394 break;
0113f48d
SW		 1395 case SCBCtrlMDI:
1396 case SCBCtrlMDI + 2:
1397 val = (uint16_t)(eepro100_read_mdi(s) >> (8 * (addr & 3)));
1398 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1399 break;
663e8e51
TS		 1400 default:
1401 logout("addr=%s val=0x%04x\n", regname(addr), val);
1402 missing("unknown word read");
1403 }
1404 return val;
1405}
1406
1407static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1408{
ef476062 1409 uint32_t val = 0;
663e8e51 1410 if (addr <= sizeof(s->mem) - sizeof(val)) {
e5e23ab8 1411 val = e100_read_reg4(s, addr);
663e8e51
TS		 1412 }
1413
1414 switch (addr) {
1415 case SCBStatus:
aac443e6 1416 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
663e8e51
TS		 1417 break;
1418 case SCBPointer:
aac443e6 1419 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
663e8e51
TS		 1420 break;
1421 case SCBPort:
1422 val = eepro100_read_port(s);
aac443e6 1423 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
663e8e51 1424 break;
072476ea
SW		 1425 case SCBflash:
1426 val = eepro100_read_eeprom(s);
1427 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1428 break;
663e8e51
TS		 1429 case SCBCtrlMDI:
1430 val = eepro100_read_mdi(s);
1431 break;
1432 default:
1433 logout("addr=%s val=0x%08x\n", regname(addr), val);
1434 missing("unknown longword read");
1435 }
1436 return val;
1437}
1438
1439static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1440{
e74818f3
SW		 1441 /* SCBStatus is readonly. */
1442 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
e5e23ab8 1443 s->mem[addr] = val;
663e8e51
TS		 1444 }
1445
663e8e51
TS		 1446 switch (addr) {
1447 case SCBStatus:
1b4f97d6 1448 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1449 break;
1450 case SCBAck:
1b4f97d6 1451 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1452 eepro100_acknowledge(s);
1453 break;
1454 case SCBCmd:
1b4f97d6 1455 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1456 eepro100_write_command(s, val);
1457 break;
1458 case SCBIntmask:
1b4f97d6 1459 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1460 if (val & BIT(1)) {
1461 eepro100_swi_interrupt(s);
1462 }
1463 eepro100_interrupt(s, 0);
1464 break;
27a05006
SW		 1465 case SCBPointer:
1466 case SCBPointer + 1:
1467 case SCBPointer + 2:
1468 case SCBPointer + 3:
1469 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1470 break;
3fd3d0b4
SW		 1471 case SCBPort:
1472 case SCBPort + 1:
1473 case SCBPort + 2:
1474 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1475 break;
663e8e51 1476 case SCBPort + 3:
3fd3d0b4
SW		 1477 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1478 eepro100_write_port(s);
1479 break;
aac443e6 1480 case SCBFlow: /* does not exist on 82557 */
3257d2b6
TS		 1481 case SCBFlow + 1:
1482 case SCBFlow + 2:
0908bba1 1483 case SCBpmdr: /* does not exist on 82557 */
aac443e6 1484 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1485 break;
1486 case SCBeeprom:
1b4f97d6 1487 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1488 eepro100_write_eeprom(s->eeprom, val);
1489 break;
0113f48d
SW		 1490 case SCBCtrlMDI:
1491 case SCBCtrlMDI + 1:
1492 case SCBCtrlMDI + 2:
1493 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1494 break;
1495 case SCBCtrlMDI + 3:
1496 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1497 eepro100_write_mdi(s);
1498 break;
663e8e51
TS		 1499 default:
1500 logout("addr=%s val=0x%02x\n", regname(addr), val);
1501 missing("unknown byte write");
1502 }
1503}
1504
1505static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1506{
e74818f3
SW		 1507 /* SCBStatus is readonly. */
1508 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
e5e23ab8 1509 e100_write_reg2(s, addr, val);
663e8e51
TS		 1510 }
1511
663e8e51
TS		 1512 switch (addr) {
1513 case SCBStatus:
1b4f97d6 1514 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
e74818f3 1515 s->mem[SCBAck] = (val >> 8);
663e8e51
TS		 1516 eepro100_acknowledge(s);
1517 break;
1518 case SCBCmd:
1b4f97d6 1519 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
663e8e51
TS		 1520 eepro100_write_command(s, val);
1521 eepro100_write1(s, SCBIntmask, val >> 8);
1522 break;
27a05006
SW		 1523 case SCBPointer:
1524 case SCBPointer + 2:
1525 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1526 break;
3fd3d0b4
SW		 1527 case SCBPort:
1528 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1529 break;
1530 case SCBPort + 2:
1531 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1532 eepro100_write_port(s);
1533 break;
663e8e51 1534 case SCBeeprom:
1b4f97d6 1535 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
663e8e51
TS		 1536 eepro100_write_eeprom(s->eeprom, val);
1537 break;
0113f48d
SW		 1538 case SCBCtrlMDI:
1539 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1540 break;
1541 case SCBCtrlMDI + 2:
1542 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1543 eepro100_write_mdi(s);
1544 break;
663e8e51
TS		 1545 default:
1546 logout("addr=%s val=0x%04x\n", regname(addr), val);
1547 missing("unknown word write");
1548 }
1549}
1550
1551static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1552{
1553 if (addr <= sizeof(s->mem) - sizeof(val)) {
e5e23ab8 1554 e100_write_reg4(s, addr, val);
663e8e51
TS		 1555 }
1556
1557 switch (addr) {
1558 case SCBPointer:
27a05006 1559 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
663e8e51
TS		 1560 break;
1561 case SCBPort:
aac443e6 1562 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
3fd3d0b4 1563 eepro100_write_port(s);
663e8e51 1564 break;
072476ea
SW		 1565 case SCBflash:
1566 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1567 val = val >> 16;
1568 eepro100_write_eeprom(s->eeprom, val);
1569 break;
663e8e51 1570 case SCBCtrlMDI:
0113f48d
SW		 1571 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1572 eepro100_write_mdi(s);
663e8e51
TS		 1573 break;
1574 default:
1575 logout("addr=%s val=0x%08x\n", regname(addr), val);
1576 missing("unknown longword write");
1577 }
1578}
1579
5e6ffdde
AK		 1580static uint64_t eepro100_read(void *opaque, target_phys_addr_t addr,
1581 unsigned size)
663e8e51
TS		 1582{
1583 EEPRO100State *s = opaque;
663e8e51 1584
5e6ffdde
AK		 1585 switch (size) {
1586 case 1: return eepro100_read1(s, addr);
1587 case 2: return eepro100_read2(s, addr);
1588 case 4: return eepro100_read4(s, addr);
1589 default: abort();
1590 }
663e8e51
TS		 1591}
1592
5e6ffdde
AK		 1593static void eepro100_write(void *opaque, target_phys_addr_t addr,
1594 uint64_t data, unsigned size)
663e8e51
TS		 1595{
1596 EEPRO100State *s = opaque;
663e8e51 1597
5e6ffdde
AK		 1598 switch (size) {
1599 case 1: return eepro100_write1(s, addr, data);
1600 case 2: return eepro100_write2(s, addr, data);
1601 case 4: return eepro100_write4(s, addr, data);
1602 default: abort();
1603 }
663e8e51
TS		 1604}
1605
5e6ffdde
AK		 1606static const MemoryRegionOps eepro100_ops = {
1607 .read = eepro100_read,
1608 .write = eepro100_write,
1609 .endianness = DEVICE_LITTLE_ENDIAN,
663e8e51
TS		 1610};
1611
e00e365e 1612static int nic_can_receive(VLANClientState *nc)
663e8e51 1613{
e00e365e 1614 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
aac443e6 1615 TRACE(RXTX, logout("%p\n", s));
663e8e51 1616 return get_ru_state(s) == ru_ready;
e7493b25
SW		 1617#if 0
1618 return !eepro100_buffer_full(s);
1619#endif
663e8e51
TS		 1620}
1621
e00e365e 1622static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size)
663e8e51
TS		 1623{
1624 /* TODO:
1625 * - Magic packets should set bit 30 in power management driver register.
1626 * - Interesting packets should set bit 29 in power management driver register.
1627 */
e00e365e 1628 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
663e8e51 1629 uint16_t rfd_status = 0xa000;
792f1d63
SW		 1630#if defined(CONFIG_PAD_RECEIVED_FRAMES)
1631 uint8_t min_buf[60];
1632#endif
663e8e51
TS		 1633 static const uint8_t broadcast_macaddr[6] =
1634 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1635
792f1d63
SW		 1636#if defined(CONFIG_PAD_RECEIVED_FRAMES)
1637 /* Pad to minimum Ethernet frame length */
1638 if (size < sizeof(min_buf)) {
1639 memcpy(min_buf, buf, size);
1640 memset(&min_buf[size], 0, sizeof(min_buf) - size);
1641 buf = min_buf;
1642 size = sizeof(min_buf);
1643 }
1644#endif
1645
663e8e51
TS		 1646 if (s->configuration[8] & 0x80) {
1647 /* CSMA is disabled. */
1648 logout("%p received while CSMA is disabled\n", s);
4f1c942b 1649 return -1;
792f1d63 1650#if !defined(CONFIG_PAD_RECEIVED_FRAMES)
ced5296a 1651 } else if (size < 64 && (s->configuration[7] & BIT(0))) {
663e8e51
TS		 1652 /* Short frame and configuration byte 7/0 (discard short receive) set:
1653 * Short frame is discarded */
067d01de 1654 logout("%p received short frame (%zu byte)\n", s, size);
663e8e51 1655 s->statistics.rx_short_frame_errors++;
e7493b25
SW		 1656 return -1;
1657#endif
ced5296a 1658 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
663e8e51
TS		 1659 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1660 * Long frames are discarded. */
067d01de 1661 logout("%p received long frame (%zu byte), ignored\n", s, size);
4f1c942b 1662 return -1;
e7493b25 1663 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */
663e8e51
TS		 1664 /* Frame matches individual address. */
1665 /* TODO: check configuration byte 15/4 (ignore U/L). */
067d01de 1666 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
663e8e51
TS		 1667 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1668 /* Broadcast frame. */
067d01de 1669 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
663e8e51 1670 rfd_status |= 0x0002;
7b8737de 1671 } else if (buf[0] & 0x01) {
663e8e51 1672 /* Multicast frame. */
7b8737de 1673 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
7f1e9d4e 1674 if (s->configuration[21] & BIT(3)) {
7b8737de
SW		 1675 /* Multicast all bit is set, receive all multicast frames. */
1676 } else {
69f3ce78 1677 unsigned mcast_idx = e100_compute_mcast_idx(buf);
7b8737de
SW		 1678 assert(mcast_idx < 64);
1679 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1680 /* Multicast frame is allowed in hash table. */
ced5296a 1681 } else if (s->configuration[15] & BIT(0)) {
7b8737de
SW		 1682 /* Promiscuous: receive all. */
1683 rfd_status |= 0x0004;
1684 } else {
1685 TRACE(RXTX, logout("%p multicast ignored\n", s));
1686 return -1;
1687 }
663e8e51 1688 }
7b8737de 1689 /* TODO: Next not for promiscuous mode? */
663e8e51 1690 rfd_status |= 0x0002;
ced5296a 1691 } else if (s->configuration[15] & BIT(0)) {
663e8e51 1692 /* Promiscuous: receive all. */
067d01de 1693 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
663e8e51 1694 rfd_status |= 0x0004;
010ec629
SW		 1695 } else if (s->configuration[20] & BIT(6)) {
1696 /* Multiple IA bit set. */
1697 unsigned mcast_idx = compute_mcast_idx(buf);
1698 assert(mcast_idx < 64);
1699 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1700 TRACE(RXTX, logout("%p accepted, multiple IA bit set\n", s));
1701 } else {
1702 TRACE(RXTX, logout("%p frame ignored, multiple IA bit set\n", s));
1703 return -1;
1704 }
663e8e51 1705 } else {
067d01de 1706 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
aac443e6 1707 nic_dump(buf, size)));
4f1c942b 1708 return size;
663e8e51
TS		 1709 }
1710
1711 if (get_ru_state(s) != ru_ready) {
aac443e6
SW		 1712 /* No resources available. */
1713 logout("no resources, state=%u\n", get_ru_state(s));
e824012b
SW		 1714 /* TODO: RNR interrupt only at first failed frame? */
1715 eepro100_rnr_interrupt(s);
663e8e51 1716 s->statistics.rx_resource_errors++;
e7493b25
SW		 1717#if 0
1718 assert(!"no resources");
1719#endif
4f1c942b 1720 return -1;
663e8e51 1721 }
e7493b25 1722 /* !!! */
c227f099 1723 eepro100_rx_t rx;
16ef60c9 1724 pci_dma_read(&s->dev, s->ru_base + s->ru_offset,
e965d4bc 1725 &rx, sizeof(eepro100_rx_t));
663e8e51
TS		 1726 uint16_t rfd_command = le16_to_cpu(rx.command);
1727 uint16_t rfd_size = le16_to_cpu(rx.size);
7f1e9d4e
KW		 1728
1729 if (size > rfd_size) {
1730 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1731 "(%zu bytes); data truncated\n", rfd_size, size);
1732 size = rfd_size;
1733 }
792f1d63 1734#if !defined(CONFIG_PAD_RECEIVED_FRAMES)
663e8e51
TS		 1735 if (size < 64) {
1736 rfd_status |= 0x0080;
1737 }
792f1d63 1738#endif
aac443e6
SW		 1739 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1740 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
16ef60c9
EGM		 1741 stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset +
1742 offsetof(eepro100_rx_t, status), rfd_status);
1743 stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset +
1744 offsetof(eepro100_rx_t, count), size);
663e8e51 1745 /* Early receive interrupt not supported. */
e7493b25
SW		 1746#if 0
1747 eepro100_er_interrupt(s);
1748#endif
663e8e51 1749 /* Receive CRC Transfer not supported. */
ced5296a 1750 if (s->configuration[18] & BIT(2)) {
7f1e9d4e
KW		 1751 missing("Receive CRC Transfer");
1752 return -1;
1753 }
663e8e51 1754 /* TODO: check stripping enable bit. */
e7493b25
SW		 1755#if 0
1756 assert(!(s->configuration[17] & BIT(0)));
1757#endif
16ef60c9
EGM		 1758 pci_dma_write(&s->dev, s->ru_base + s->ru_offset +
1759 sizeof(eepro100_rx_t), buf, size);
663e8e51
TS		 1760 s->statistics.rx_good_frames++;
1761 eepro100_fr_interrupt(s);
1762 s->ru_offset = le32_to_cpu(rx.link);
ced5296a 1763 if (rfd_command & COMMAND_EL) {
663e8e51 1764 /* EL bit is set, so this was the last frame. */
7f1e9d4e
KW		 1765 logout("receive: Running out of frames\n");
1766 set_ru_state(s, ru_suspended);
663e8e51 1767 }
ced5296a 1768 if (rfd_command & COMMAND_S) {
663e8e51
TS		 1769 /* S bit is set. */
1770 set_ru_state(s, ru_suspended);
1771 }
4f1c942b 1772 return size;
663e8e51
TS		 1773}
1774
151b2986
JQ		 1775static const VMStateDescription vmstate_eepro100 = {
1776 .version_id = 3,
1777 .minimum_version_id = 2,
1778 .minimum_version_id_old = 2,
1779 .fields = (VMStateField []) {
1780 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1781 VMSTATE_UNUSED(32),
1782 VMSTATE_BUFFER(mult, EEPRO100State),
1783 VMSTATE_BUFFER(mem, EEPRO100State),
1784 /* Save all members of struct between scb_stat and mem. */
1785 VMSTATE_UINT8(scb_stat, EEPRO100State),
1786 VMSTATE_UINT8(int_stat, EEPRO100State),
1787 VMSTATE_UNUSED(3*4),
1788 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1789 VMSTATE_UNUSED(19*4),
1790 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1791 /* The eeprom should be saved and restored by its own routines. */
1792 VMSTATE_UINT32(device, EEPRO100State),
1793 /* TODO check device. */
151b2986
JQ		 1794 VMSTATE_UINT32(cu_base, EEPRO100State),
1795 VMSTATE_UINT32(cu_offset, EEPRO100State),
1796 VMSTATE_UINT32(ru_base, EEPRO100State),
1797 VMSTATE_UINT32(ru_offset, EEPRO100State),
1798 VMSTATE_UINT32(statsaddr, EEPRO100State),
ba42b646 1799 /* Save eepro100_stats_t statistics. */
151b2986
JQ		 1800 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1801 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1802 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1803 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1804 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1805 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1806 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1807 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1808 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1809 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1810 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1811 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1812 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1813 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1814 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1815 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1816 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1817 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1818 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1819 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1820 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
151b2986
JQ		 1821 /* Configuration bytes. */
1822 VMSTATE_BUFFER(configuration, EEPRO100State),
1823 VMSTATE_END_OF_LIST()
aac443e6 1824 }
151b2986 1825};
663e8e51 1826
e00e365e 1827static void nic_cleanup(VLANClientState *nc)
b946a153 1828{
e00e365e 1829 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
b946a153 1830
e00e365e 1831 s->nic = NULL;
b946a153
AL		 1832}
1833
c4c270e2 1834static int pci_nic_uninit(PCIDevice *pci_dev)
b946a153 1835{
c4c270e2 1836 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
b946a153 1837
5e6ffdde
AK		 1838 memory_region_destroy(&s->mmio_bar);
1839 memory_region_destroy(&s->io_bar);
1840 memory_region_destroy(&s->flash_bar);
0be71e32 1841 vmstate_unregister(&pci_dev->qdev, s->vmstate, s);
5fce2b3e 1842 eeprom93xx_free(&pci_dev->qdev, s->eeprom);
e00e365e 1843 qemu_del_vlan_client(&s->nic->nc);
b946a153
AL		 1844 return 0;
1845}
1846
e00e365e 1847static NetClientInfo net_eepro100_info = {
2be64a68 1848 .type = NET_CLIENT_OPTIONS_KIND_NIC,
e00e365e
MM		 1849 .size = sizeof(NICState),
1850 .can_receive = nic_can_receive,
1851 .receive = nic_receive,
1852 .cleanup = nic_cleanup,
1853};
1854
558c8634 1855static int e100_nic_init(PCIDevice *pci_dev)
663e8e51 1856{
273a2142 1857 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
40021f08 1858 E100PCIDeviceInfo *info = eepro100_get_class(s);
663e8e51 1859
aac443e6 1860 TRACE(OTHER, logout("\n"));
663e8e51 1861
40021f08 1862 s->device = info->device;
663e8e51 1863
40021f08 1864 e100_pci_reset(s);
663e8e51
TS		 1865
1866 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1867 * i82559 and later support 64 or 256 word EEPROM. */
5fce2b3e 1868 s->eeprom = eeprom93xx_new(&pci_dev->qdev, EEPROM_SIZE);
663e8e51
TS		 1869
1870 /* Handler for memory-mapped I/O */
5e6ffdde
AK		 1871 memory_region_init_io(&s->mmio_bar, &eepro100_ops, s, "eepro100-mmio",
1872 PCI_MEM_SIZE);
e824b2cc 1873 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->mmio_bar);
5e6ffdde
AK		 1874 memory_region_init_io(&s->io_bar, &eepro100_ops, s, "eepro100-io",
1875 PCI_IO_SIZE);
e824b2cc 1876 pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
5e6ffdde
AK		 1877 /* FIXME: flash aliases to mmio?! */
1878 memory_region_init_io(&s->flash_bar, &eepro100_ops, s, "eepro100-flash",
1879 PCI_FLASH_SIZE);
e824b2cc 1880 pci_register_bar(&s->dev, 2, 0, &s->flash_bar);
663e8e51 1881
508ef936 1882 qemu_macaddr_default_if_unset(&s->conf.macaddr);
ce0e58b3 1883 logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
663e8e51
TS		 1884
1885 nic_reset(s);
1886
e00e365e 1887 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
f79f2bfc 1888 object_get_typename(OBJECT(pci_dev)), pci_dev->qdev.id, s);
663e8e51 1889
e00e365e
MM		 1890 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1891 TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
663e8e51 1892
a08d4367 1893 qemu_register_reset(nic_reset, s);
663e8e51 1894
7267c094 1895 s->vmstate = g_malloc(sizeof(vmstate_eepro100));
151b2986 1896 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
e00e365e 1897 s->vmstate->name = s->nic->nc.model;
0be71e32 1898 vmstate_register(&pci_dev->qdev, -1, s->vmstate, s);
4e9df06a 1899
1ca4d09a
GN		 1900 add_boot_device_path(s->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
1901
81a322d4 1902 return 0;
663e8e51
TS		 1903}
1904
558c8634 1905static E100PCIDeviceInfo e100_devices[] = {
0aab0d3a 1906 {
39bffca2
AL		 1907 .name = "i82550",
1908 .desc = "Intel i82550 Ethernet",
558c8634
SW		 1909 .device = i82550,
1910 /* TODO: check device id. */
40021f08 1911 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
558c8634 1912 /* Revision ID: 0x0c, 0x0d, 0x0e. */
40021f08 1913 .revision = 0x0e,
558c8634
SW		 1914 /* TODO: check size of statistical counters. */
1915 .stats_size = 80,
1916 /* TODO: check extended tcb support. */
1917 .has_extended_tcb_support = true,
1918 .power_management = true,
c4c270e2 1919 },{
39bffca2
AL		 1920 .name = "i82551",
1921 .desc = "Intel i82551 Ethernet",
558c8634 1922 .device = i82551,
40021f08 1923 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
558c8634 1924 /* Revision ID: 0x0f, 0x10. */
40021f08 1925 .revision = 0x0f,
558c8634
SW		 1926 /* TODO: check size of statistical counters. */
1927 .stats_size = 80,
1928 .has_extended_tcb_support = true,
1929 .power_management = true,
0aab0d3a 1930 },{
39bffca2
AL		 1931 .name = "i82557a",
1932 .desc = "Intel i82557A Ethernet",
558c8634 1933 .device = i82557A,
40021f08
AL		 1934 .device_id = PCI_DEVICE_ID_INTEL_82557,
1935 .revision = 0x01,
558c8634 1936 .power_management = false,
c4c270e2 1937 },{
39bffca2
AL		 1938 .name = "i82557b",
1939 .desc = "Intel i82557B Ethernet",
558c8634 1940 .device = i82557B,
40021f08
AL		 1941 .device_id = PCI_DEVICE_ID_INTEL_82557,
1942 .revision = 0x02,
558c8634 1943 .power_management = false,
c4c270e2 1944 },{
39bffca2
AL		 1945 .name = "i82557c",
1946 .desc = "Intel i82557C Ethernet",
558c8634 1947 .device = i82557C,
40021f08
AL		 1948 .device_id = PCI_DEVICE_ID_INTEL_82557,
1949 .revision = 0x03,
558c8634 1950 .power_management = false,
c4c270e2 1951 },{
39bffca2
AL		 1952 .name = "i82558a",
1953 .desc = "Intel i82558A Ethernet",
558c8634 1954 .device = i82558A,
40021f08
AL		 1955 .device_id = PCI_DEVICE_ID_INTEL_82557,
1956 .revision = 0x04,
558c8634
SW		 1957 .stats_size = 76,
1958 .has_extended_tcb_support = true,
1959 .power_management = true,
c4c270e2 1960 },{
39bffca2
AL		 1961 .name = "i82558b",
1962 .desc = "Intel i82558B Ethernet",
558c8634 1963 .device = i82558B,
40021f08
AL		 1964 .device_id = PCI_DEVICE_ID_INTEL_82557,
1965 .revision = 0x05,
558c8634
SW		 1966 .stats_size = 76,
1967 .has_extended_tcb_support = true,
1968 .power_management = true,
c4c270e2 1969 },{
39bffca2
AL		 1970 .name = "i82559a",
1971 .desc = "Intel i82559A Ethernet",
558c8634 1972 .device = i82559A,
40021f08
AL		 1973 .device_id = PCI_DEVICE_ID_INTEL_82557,
1974 .revision = 0x06,
558c8634
SW		 1975 .stats_size = 80,
1976 .has_extended_tcb_support = true,
1977 .power_management = true,
c4c270e2 1978 },{
39bffca2
AL		 1979 .name = "i82559b",
1980 .desc = "Intel i82559B Ethernet",
558c8634 1981 .device = i82559B,
40021f08
AL		 1982 .device_id = PCI_DEVICE_ID_INTEL_82557,
1983 .revision = 0x07,
558c8634
SW		 1984 .stats_size = 80,
1985 .has_extended_tcb_support = true,
1986 .power_management = true,
0aab0d3a 1987 },{
39bffca2
AL		 1988 .name = "i82559c",
1989 .desc = "Intel i82559C Ethernet",
558c8634 1990 .device = i82559C,
40021f08 1991 .device_id = PCI_DEVICE_ID_INTEL_82557,
558c8634 1992#if 0
40021f08 1993 .revision = 0x08,
558c8634
SW		 1994#endif
1995 /* TODO: Windows wants revision id 0x0c. */
40021f08 1996 .revision = 0x0c,
ad03502b 1997#if EEPROM_SIZE > 0
40021f08
AL		 1998 .subsystem_vendor_id = PCI_VENDOR_ID_INTEL,
1999 .subsystem_id = 0x0040,
ad03502b 2000#endif
558c8634
SW		 2001 .stats_size = 80,
2002 .has_extended_tcb_support = true,
2003 .power_management = true,
c4c270e2 2004 },{
39bffca2
AL		 2005 .name = "i82559er",
2006 .desc = "Intel i82559ER Ethernet",
558c8634 2007 .device = i82559ER,
40021f08
AL		 2008 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2009 .revision = 0x09,
558c8634
SW		 2010 .stats_size = 80,
2011 .has_extended_tcb_support = true,
2012 .power_management = true,
0aab0d3a 2013 },{
39bffca2
AL		 2014 .name = "i82562",
2015 .desc = "Intel i82562 Ethernet",
558c8634
SW		 2016 .device = i82562,
2017 /* TODO: check device id. */
40021f08 2018 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
558c8634 2019 /* TODO: wrong revision id. */
40021f08 2020 .revision = 0x0e,
558c8634
SW		 2021 .stats_size = 80,
2022 .has_extended_tcb_support = true,
2023 .power_management = true,
db667a12
SW		 2024 },{
2025 /* Toshiba Tecra 8200. */
39bffca2
AL		 2026 .name = "i82801",
2027 .desc = "Intel i82801 Ethernet",
db667a12 2028 .device = i82801,
40021f08
AL		 2029 .device_id = 0x2449,
2030 .revision = 0x03,
db667a12
SW		 2031 .stats_size = 80,
2032 .has_extended_tcb_support = true,
2033 .power_management = true,
0aab0d3a
GH		 2034 }
2035};
2036
40021f08
AL		 2037static E100PCIDeviceInfo *eepro100_get_class_by_name(const char *typename)
2038{
2039 E100PCIDeviceInfo *info = NULL;
2040 int i;
2041
2042 /* This is admittedly awkward but also temporary. QOM allows for
2043 * parameterized typing and for subclassing both of which would suitable
2044 * handle what's going on here. But class_data is already being used as
2045 * a stop-gap hack to allow incremental qdev conversion so we cannot use it
2046 * right now. Once we merge the final QOM series, we can come back here and
2047 * do this in a much more elegant fashion.
2048 */
2049 for (i = 0; i < ARRAY_SIZE(e100_devices); i++) {
39bffca2 2050 if (strcmp(e100_devices[i].name, typename) == 0) {
40021f08
AL		 2051 info = &e100_devices[i];
2052 break;
2053 }
2054 }
2055 assert(info != NULL);
2056
2057 return info;
2058}
2059
2060static E100PCIDeviceInfo *eepro100_get_class(EEPRO100State *s)
2061{
2062 return eepro100_get_class_by_name(object_get_typename(OBJECT(s)));
2063}
2064
39bffca2
AL		 2065static Property e100_properties[] = {
2066 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2067 DEFINE_PROP_END_OF_LIST(),
2068};
2069
40021f08
AL		 2070static void eepro100_class_init(ObjectClass *klass, void *data)
2071{
39bffca2 2072 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 2073 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2074 E100PCIDeviceInfo *info;
2075
2076 info = eepro100_get_class_by_name(object_class_get_name(klass));
2077
39bffca2
AL		 2078 dc->props = e100_properties;
2079 dc->desc = info->desc;
40021f08
AL		 2080 k->vendor_id = PCI_VENDOR_ID_INTEL;
2081 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
2082 k->romfile = "pxe-eepro100.rom";
2083 k->init = e100_nic_init;
2084 k->exit = pci_nic_uninit;
2085 k->device_id = info->device_id;
2086 k->revision = info->revision;
2087 k->subsystem_vendor_id = info->subsystem_vendor_id;
2088 k->subsystem_id = info->subsystem_id;
2089}
2090
83f7d43a 2091static void eepro100_register_types(void)
663e8e51 2092{
558c8634
SW		 2093 size_t i;
2094 for (i = 0; i < ARRAY_SIZE(e100_devices); i++) {
39bffca2
AL		 2095 TypeInfo type_info = {};
2096 E100PCIDeviceInfo *info = &e100_devices[i];
40021f08 2097
39bffca2
AL		 2098 type_info.name = info->name;
2099 type_info.parent = TYPE_PCI_DEVICE;
2100 type_info.class_init = eepro100_class_init;
2101 type_info.instance_size = sizeof(EEPRO100State);
40021f08 2102
39bffca2 2103 type_register(&type_info);
558c8634 2104 }
663e8e51
TS		 2105}
2106
83f7d43a 2107type_init(eepro100_register_types)
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