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663e8e51 TS |
1 | /* |
2 | * QEMU i8255x (PRO100) emulation | |
3 | * | |
4 | * Copyright (c) 2006-2007 Stefan Weil | |
5 | * | |
6 | * Portions of the code are copies from grub / etherboot eepro100.c | |
7 | * and linux e100.c. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
8167ee88 | 20 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
663e8e51 TS |
21 | * |
22 | * Tested features (i82559): | |
23 | * PXE boot (i386) no valid link | |
24 | * Linux networking (i386) ok | |
25 | * | |
26 | * Untested: | |
27 | * non-i386 platforms | |
28 | * Windows networking | |
29 | * | |
30 | * References: | |
31 | * | |
32 | * Intel 8255x 10/100 Mbps Ethernet Controller Family | |
33 | * Open Source Software Developer Manual | |
34 | */ | |
35 | ||
36 | #if defined(TARGET_I386) | |
37 | # warning "PXE boot still not working!" | |
38 | #endif | |
39 | ||
663e8e51 | 40 | #include <stddef.h> /* offsetof */ |
b84a5c6f | 41 | #include <stdbool.h> |
87ecb68b PB |
42 | #include "hw.h" |
43 | #include "pci.h" | |
44 | #include "net.h" | |
663e8e51 TS |
45 | #include "eeprom93xx.h" |
46 | ||
47 | /* Common declarations for all PCI devices. */ | |
48 | ||
663e8e51 TS |
49 | #define PCI_CONFIG_8(offset, value) \ |
50 | (pci_conf[offset] = (value)) | |
51 | #define PCI_CONFIG_16(offset, value) \ | |
52 | (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value)) | |
53 | #define PCI_CONFIG_32(offset, value) \ | |
54 | (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value)) | |
55 | ||
56 | #define KiB 1024 | |
57 | ||
aac443e6 | 58 | /* Debug EEPRO100 card. */ |
663e8e51 TS |
59 | //~ #define DEBUG_EEPRO100 |
60 | ||
61 | #ifdef DEBUG_EEPRO100 | |
001faf32 | 62 | #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__) |
663e8e51 | 63 | #else |
001faf32 | 64 | #define logout(fmt, ...) ((void)0) |
663e8e51 TS |
65 | #endif |
66 | ||
67 | /* Set flags to 0 to disable debug output. */ | |
aac443e6 SW |
68 | #define INT 1 /* interrupt related actions */ |
69 | #define MDI 1 /* mdi related actions */ | |
70 | #define OTHER 1 | |
71 | #define RXTX 1 | |
72 | #define EEPROM 1 /* eeprom related actions */ | |
663e8e51 TS |
73 | |
74 | #define TRACE(flag, command) ((flag) ? (command) : (void)0) | |
75 | ||
7f1e9d4e | 76 | #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n") |
663e8e51 TS |
77 | |
78 | #define MAX_ETH_FRAME_SIZE 1514 | |
79 | ||
80 | /* This driver supports several different devices which are declared here. */ | |
c4c270e2 | 81 | #define i82550 0x82550 |
663e8e51 | 82 | #define i82551 0x82551 |
c4c270e2 | 83 | #define i82557A 0x82557a |
663e8e51 TS |
84 | #define i82557B 0x82557b |
85 | #define i82557C 0x82557c | |
c4c270e2 | 86 | #define i82558A 0x82558a |
663e8e51 | 87 | #define i82558B 0x82558b |
c4c270e2 SW |
88 | #define i82559A 0x82559a |
89 | #define i82559B 0x82559b | |
663e8e51 TS |
90 | #define i82559C 0x82559c |
91 | #define i82559ER 0x82559e | |
92 | #define i82562 0x82562 | |
93 | ||
aac443e6 | 94 | /* Use 64 word EEPROM. TODO: could be a runtime option. */ |
663e8e51 TS |
95 | #define EEPROM_SIZE 64 |
96 | ||
97 | #define PCI_MEM_SIZE (4 * KiB) | |
98 | #define PCI_IO_SIZE 64 | |
99 | #define PCI_FLASH_SIZE (128 * KiB) | |
100 | ||
101 | #define BIT(n) (1 << (n)) | |
102 | #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) | |
103 | ||
104 | /* The SCB accepts the following controls for the Tx and Rx units: */ | |
105 | #define CU_NOP 0x0000 /* No operation. */ | |
106 | #define CU_START 0x0010 /* CU start. */ | |
107 | #define CU_RESUME 0x0020 /* CU resume. */ | |
108 | #define CU_STATSADDR 0x0040 /* Load dump counters address. */ | |
109 | #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */ | |
110 | #define CU_CMD_BASE 0x0060 /* Load CU base address. */ | |
111 | #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */ | |
112 | #define CU_SRESUME 0x00a0 /* CU static resume. */ | |
113 | ||
114 | #define RU_NOP 0x0000 | |
115 | #define RX_START 0x0001 | |
116 | #define RX_RESUME 0x0002 | |
117 | #define RX_ABORT 0x0004 | |
118 | #define RX_ADDR_LOAD 0x0006 | |
119 | #define RX_RESUMENR 0x0007 | |
120 | #define INT_MASK 0x0100 | |
121 | #define DRVR_INT 0x0200 /* Driver generated interrupt. */ | |
122 | ||
663e8e51 TS |
123 | /* Offsets to the various registers. |
124 | All accesses need not be longword aligned. */ | |
125 | enum speedo_offsets { | |
126 | SCBStatus = 0, | |
127 | SCBAck = 1, | |
128 | SCBCmd = 2, /* Rx/Command Unit command and status. */ | |
129 | SCBIntmask = 3, | |
130 | SCBPointer = 4, /* General purpose pointer. */ | |
131 | SCBPort = 8, /* Misc. commands and operands. */ | |
132 | SCBflash = 12, SCBeeprom = 14, /* EEPROM and flash memory control. */ | |
133 | SCBCtrlMDI = 16, /* MDI interface control. */ | |
134 | SCBEarlyRx = 20, /* Early receive byte count. */ | |
3257d2b6 | 135 | SCBFlow = 24, |
663e8e51 TS |
136 | }; |
137 | ||
138 | /* A speedo3 transmit buffer descriptor with two buffers... */ | |
139 | typedef struct { | |
140 | uint16_t status; | |
141 | uint16_t command; | |
142 | uint32_t link; /* void * */ | |
143 | uint32_t tx_desc_addr; /* transmit buffer decsriptor array address. */ | |
144 | uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */ | |
145 | uint8_t tx_threshold; /* transmit threshold */ | |
146 | uint8_t tbd_count; /* TBD number */ | |
147 | //~ /* This constitutes two "TBD" entries: hdr and data */ | |
148 | //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */ | |
149 | //~ int32_t tx_buf_size0; /* Length of Tx hdr. */ | |
150 | //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */ | |
151 | //~ int32_t tx_buf_size1; /* Length of Tx data. */ | |
c227f099 | 152 | } eepro100_tx_t; |
663e8e51 TS |
153 | |
154 | /* Receive frame descriptor. */ | |
155 | typedef struct { | |
156 | int16_t status; | |
157 | uint16_t command; | |
158 | uint32_t link; /* struct RxFD * */ | |
159 | uint32_t rx_buf_addr; /* void * */ | |
160 | uint16_t count; | |
161 | uint16_t size; | |
162 | char packet[MAX_ETH_FRAME_SIZE + 4]; | |
c227f099 | 163 | } eepro100_rx_t; |
663e8e51 TS |
164 | |
165 | typedef struct { | |
166 | uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions, | |
167 | tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions, | |
168 | tx_multiple_collisions, tx_total_collisions; | |
169 | uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors, | |
170 | rx_resource_errors, rx_overrun_errors, rx_cdt_errors, | |
171 | rx_short_frame_errors; | |
172 | uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported; | |
173 | uint16_t xmt_tco_frames, rcv_tco_frames; | |
ba42b646 SW |
174 | /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */ |
175 | uint32_t reserved[4]; | |
c227f099 | 176 | } eepro100_stats_t; |
663e8e51 TS |
177 | |
178 | typedef enum { | |
179 | cu_idle = 0, | |
180 | cu_suspended = 1, | |
181 | cu_active = 2, | |
182 | cu_lpq_active = 2, | |
183 | cu_hqp_active = 3 | |
c227f099 | 184 | } cu_state_t; |
663e8e51 TS |
185 | |
186 | typedef enum { | |
187 | ru_idle = 0, | |
188 | ru_suspended = 1, | |
189 | ru_no_resources = 2, | |
190 | ru_ready = 4 | |
c227f099 | 191 | } ru_state_t; |
663e8e51 | 192 | |
663e8e51 | 193 | typedef struct { |
273a2142 | 194 | PCIDevice dev; |
663e8e51 TS |
195 | uint8_t mult[8]; /* multicast mask array */ |
196 | int mmio_index; | |
663e8e51 | 197 | VLANClientState *vc; |
508ef936 | 198 | NICConf conf; |
663e8e51 TS |
199 | uint8_t scb_stat; /* SCB stat/ack byte */ |
200 | uint8_t int_stat; /* PCI interrupt status */ | |
3706c43f | 201 | /* region must not be saved by nic_save. */ |
663e8e51 | 202 | uint32_t region[3]; /* PCI region addresses */ |
663e8e51 | 203 | uint16_t mdimem[32]; |
c227f099 | 204 | eeprom_t *eeprom; |
663e8e51 TS |
205 | uint32_t device; /* device variant */ |
206 | uint32_t pointer; | |
207 | /* (cu_base + cu_offset) address the next command block in the command block list. */ | |
208 | uint32_t cu_base; /* CU base address */ | |
209 | uint32_t cu_offset; /* CU address offset */ | |
210 | /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */ | |
211 | uint32_t ru_base; /* RU base address */ | |
212 | uint32_t ru_offset; /* RU address offset */ | |
c227f099 | 213 | uint32_t statsaddr; /* pointer to eepro100_stats_t */ |
ba42b646 SW |
214 | |
215 | /* Statistical counters. Also used for wake-up packet (i82559). */ | |
216 | eepro100_stats_t statistics; | |
217 | ||
663e8e51 TS |
218 | #if 0 |
219 | uint16_t status; | |
220 | #endif | |
221 | ||
222 | /* Configuration bytes. */ | |
223 | uint8_t configuration[22]; | |
224 | ||
225 | /* Data in mem is always in the byte order of the controller (le). */ | |
226 | uint8_t mem[PCI_MEM_SIZE]; | |
151b2986 JQ |
227 | /* vmstate for each particular nic */ |
228 | VMStateDescription *vmstate; | |
ba42b646 SW |
229 | |
230 | /* Quasi static device properties (no need to save them). */ | |
231 | uint16_t stats_size; | |
232 | bool has_extended_tcb_support; | |
663e8e51 TS |
233 | } EEPRO100State; |
234 | ||
235 | /* Default values for MDI (PHY) registers */ | |
236 | static const uint16_t eepro100_mdi_default[] = { | |
237 | /* MDI Registers 0 - 6, 7 */ | |
238 | 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000, | |
239 | /* MDI Registers 8 - 15 */ | |
240 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
241 | /* MDI Registers 16 - 31 */ | |
242 | 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
243 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
244 | }; | |
245 | ||
246 | /* Readonly mask for MDI (PHY) registers */ | |
247 | static const uint16_t eepro100_mdi_mask[] = { | |
248 | 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000, | |
249 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
250 | 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, | |
251 | 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
252 | }; | |
253 | ||
ba42b646 SW |
254 | /* XXX: optimize */ |
255 | static void stl_le_phys(target_phys_addr_t addr, uint32_t val) | |
256 | { | |
257 | val = cpu_to_le32(val); | |
258 | cpu_physical_memory_write(addr, (const uint8_t *)&val, sizeof(val)); | |
259 | } | |
260 | ||
663e8e51 TS |
261 | #define POLYNOMIAL 0x04c11db6 |
262 | ||
263 | /* From FreeBSD */ | |
264 | /* XXX: optimize */ | |
265 | static int compute_mcast_idx(const uint8_t * ep) | |
266 | { | |
267 | uint32_t crc; | |
268 | int carry, i, j; | |
269 | uint8_t b; | |
270 | ||
271 | crc = 0xffffffff; | |
272 | for (i = 0; i < 6; i++) { | |
273 | b = *ep++; | |
274 | for (j = 0; j < 8; j++) { | |
275 | carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); | |
276 | crc <<= 1; | |
277 | b >>= 1; | |
aac443e6 | 278 | if (carry) { |
663e8e51 | 279 | crc = ((crc ^ POLYNOMIAL) | carry); |
aac443e6 | 280 | } |
663e8e51 TS |
281 | } |
282 | } | |
283 | return (crc >> 26); | |
284 | } | |
285 | ||
286 | #if defined(DEBUG_EEPRO100) | |
287 | static const char *nic_dump(const uint8_t * buf, unsigned size) | |
288 | { | |
289 | static char dump[3 * 16 + 1]; | |
290 | char *p = &dump[0]; | |
aac443e6 | 291 | if (size > 16) { |
663e8e51 | 292 | size = 16; |
aac443e6 | 293 | } |
663e8e51 TS |
294 | while (size-- > 0) { |
295 | p += sprintf(p, " %02x", *buf++); | |
296 | } | |
297 | return dump; | |
298 | } | |
299 | #endif /* DEBUG_EEPRO100 */ | |
300 | ||
301 | enum scb_stat_ack { | |
302 | stat_ack_not_ours = 0x00, | |
303 | stat_ack_sw_gen = 0x04, | |
304 | stat_ack_rnr = 0x10, | |
305 | stat_ack_cu_idle = 0x20, | |
306 | stat_ack_frame_rx = 0x40, | |
307 | stat_ack_cu_cmd_done = 0x80, | |
308 | stat_ack_not_present = 0xFF, | |
309 | stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx), | |
310 | stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done), | |
311 | }; | |
312 | ||
313 | static void disable_interrupt(EEPRO100State * s) | |
314 | { | |
315 | if (s->int_stat) { | |
aac443e6 | 316 | TRACE(INT, logout("interrupt disabled\n")); |
273a2142 | 317 | qemu_irq_lower(s->dev.irq[0]); |
663e8e51 TS |
318 | s->int_stat = 0; |
319 | } | |
320 | } | |
321 | ||
322 | static void enable_interrupt(EEPRO100State * s) | |
323 | { | |
324 | if (!s->int_stat) { | |
aac443e6 | 325 | TRACE(INT, logout("interrupt enabled\n")); |
273a2142 | 326 | qemu_irq_raise(s->dev.irq[0]); |
663e8e51 TS |
327 | s->int_stat = 1; |
328 | } | |
329 | } | |
330 | ||
331 | static void eepro100_acknowledge(EEPRO100State * s) | |
332 | { | |
333 | s->scb_stat &= ~s->mem[SCBAck]; | |
334 | s->mem[SCBAck] = s->scb_stat; | |
335 | if (s->scb_stat == 0) { | |
336 | disable_interrupt(s); | |
337 | } | |
338 | } | |
339 | ||
340 | static void eepro100_interrupt(EEPRO100State * s, uint8_t stat) | |
341 | { | |
342 | uint8_t mask = ~s->mem[SCBIntmask]; | |
343 | s->mem[SCBAck] |= stat; | |
344 | stat = s->scb_stat = s->mem[SCBAck]; | |
345 | stat &= (mask | 0x0f); | |
346 | //~ stat &= (~s->mem[SCBIntmask] | 0x0xf); | |
347 | if (stat && (mask & 0x01)) { | |
348 | /* SCB mask and SCB Bit M do not disable interrupt. */ | |
349 | enable_interrupt(s); | |
350 | } else if (s->int_stat) { | |
351 | disable_interrupt(s); | |
352 | } | |
353 | } | |
354 | ||
355 | static void eepro100_cx_interrupt(EEPRO100State * s) | |
356 | { | |
357 | /* CU completed action command. */ | |
358 | /* Transmit not ok (82557 only, not in emulation). */ | |
359 | eepro100_interrupt(s, 0x80); | |
360 | } | |
361 | ||
362 | static void eepro100_cna_interrupt(EEPRO100State * s) | |
363 | { | |
364 | /* CU left the active state. */ | |
365 | eepro100_interrupt(s, 0x20); | |
366 | } | |
367 | ||
368 | static void eepro100_fr_interrupt(EEPRO100State * s) | |
369 | { | |
370 | /* RU received a complete frame. */ | |
371 | eepro100_interrupt(s, 0x40); | |
372 | } | |
373 | ||
374 | #if 0 | |
375 | static void eepro100_rnr_interrupt(EEPRO100State * s) | |
376 | { | |
377 | /* RU is not ready. */ | |
378 | eepro100_interrupt(s, 0x10); | |
379 | } | |
380 | #endif | |
381 | ||
382 | static void eepro100_mdi_interrupt(EEPRO100State * s) | |
383 | { | |
384 | /* MDI completed read or write cycle. */ | |
385 | eepro100_interrupt(s, 0x08); | |
386 | } | |
387 | ||
388 | static void eepro100_swi_interrupt(EEPRO100State * s) | |
389 | { | |
390 | /* Software has requested an interrupt. */ | |
391 | eepro100_interrupt(s, 0x04); | |
392 | } | |
393 | ||
394 | #if 0 | |
395 | static void eepro100_fcp_interrupt(EEPRO100State * s) | |
396 | { | |
397 | /* Flow control pause interrupt (82558 and later). */ | |
398 | eepro100_interrupt(s, 0x01); | |
399 | } | |
400 | #endif | |
401 | ||
402 | static void pci_reset(EEPRO100State * s) | |
403 | { | |
404 | uint32_t device = s->device; | |
273a2142 | 405 | uint8_t *pci_conf = s->dev.config; |
ba42b646 | 406 | bool power_management = 1; |
663e8e51 | 407 | |
aac443e6 | 408 | TRACE(OTHER, logout("%p\n", s)); |
663e8e51 TS |
409 | |
410 | /* PCI Vendor ID */ | |
deb54399 | 411 | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
d6fd1e66 | 412 | /* PCI Device ID depends on device and is set below. */ |
663e8e51 TS |
413 | /* PCI Command */ |
414 | PCI_CONFIG_16(PCI_COMMAND, 0x0000); | |
415 | /* PCI Status */ | |
416 | PCI_CONFIG_16(PCI_STATUS, 0x2800); | |
417 | /* PCI Revision ID */ | |
418 | PCI_CONFIG_8(PCI_REVISION_ID, 0x08); | |
419 | /* PCI Class Code */ | |
420 | PCI_CONFIG_8(0x09, 0x00); | |
173a543b | 421 | pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); |
663e8e51 TS |
422 | /* PCI Cache Line Size */ |
423 | /* check cache line size!!! */ | |
424 | //~ PCI_CONFIG_8(0x0c, 0x00); | |
425 | /* PCI Latency Timer */ | |
426 | PCI_CONFIG_8(0x0d, 0x20); // latency timer = 32 clocks | |
427 | /* PCI Header Type */ | |
428 | /* BIST (built-in self test) */ | |
429 | #if defined(TARGET_I386) | |
430 | // !!! workaround for buggy bios | |
0392a017 | 431 | //~ #define PCI_BASE_ADDRESS_MEM_PREFETCH 0 |
663e8e51 TS |
432 | #endif |
433 | #if 0 | |
434 | /* PCI Base Address Registers */ | |
435 | /* CSR Memory Mapped Base Address */ | |
436 | PCI_CONFIG_32(PCI_BASE_ADDRESS_0, | |
0392a017 IY |
437 | PCI_BASE_ADDRESS_SPACE_MEMORY | |
438 | PCI_BASE_ADDRESS_MEM_PREFETCH); | |
663e8e51 | 439 | /* CSR I/O Mapped Base Address */ |
0392a017 | 440 | PCI_CONFIG_32(PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_SPACE_IO); |
663e8e51 TS |
441 | #if 0 |
442 | /* Flash Memory Mapped Base Address */ | |
0392a017 IY |
443 | PCI_CONFIG_32(PCI_BASE_ADDRESS_2, |
444 | 0xfffe0000 | PCI_BASE_ADDRESS_SPACE_MEMORY); | |
663e8e51 TS |
445 | #endif |
446 | #endif | |
447 | /* Expansion ROM Base Address (depends on boot disable!!!) */ | |
448 | PCI_CONFIG_32(0x30, 0x00000000); | |
449 | /* Capability Pointer */ | |
450 | PCI_CONFIG_8(0x34, 0xdc); | |
aac443e6 | 451 | /* Interrupt Line */ |
663e8e51 TS |
452 | /* Interrupt Pin */ |
453 | PCI_CONFIG_8(0x3d, 1); // interrupt pin 0 | |
454 | /* Minimum Grant */ | |
455 | PCI_CONFIG_8(0x3e, 0x08); | |
456 | /* Maximum Latency */ | |
457 | PCI_CONFIG_8(0x3f, 0x18); | |
663e8e51 TS |
458 | |
459 | switch (device) { | |
ba42b646 SW |
460 | case i82550: |
461 | // TODO: check device id. | |
462 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); | |
463 | /* Revision ID: 0x0c, 0x0d, 0x0e. */ | |
464 | PCI_CONFIG_8(PCI_REVISION_ID, 0x0e); | |
465 | // TODO: check size of statistical counters. | |
466 | s->stats_size = 80; | |
467 | // TODO: check extended tcb support. | |
468 | s->has_extended_tcb_support = 1; | |
469 | break; | |
663e8e51 | 470 | case i82551: |
d6fd1e66 | 471 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); |
ba42b646 | 472 | /* Revision ID: 0x0f, 0x10. */ |
663e8e51 | 473 | PCI_CONFIG_8(PCI_REVISION_ID, 0x0f); |
ba42b646 SW |
474 | // TODO: check size of statistical counters. |
475 | s->stats_size = 80; | |
476 | s->has_extended_tcb_support = 1; | |
477 | break; | |
478 | case i82557A: | |
479 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); | |
480 | PCI_CONFIG_8(PCI_REVISION_ID, 0x01); | |
481 | PCI_CONFIG_8(0x34, 0x00); | |
482 | power_management = 0; | |
663e8e51 TS |
483 | break; |
484 | case i82557B: | |
d6fd1e66 | 485 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
663e8e51 | 486 | PCI_CONFIG_8(PCI_REVISION_ID, 0x02); |
ba42b646 SW |
487 | PCI_CONFIG_8(0x34, 0x00); |
488 | power_management = 0; | |
663e8e51 TS |
489 | break; |
490 | case i82557C: | |
d6fd1e66 | 491 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
663e8e51 | 492 | PCI_CONFIG_8(PCI_REVISION_ID, 0x03); |
ba42b646 SW |
493 | PCI_CONFIG_8(0x34, 0x00); |
494 | power_management = 0; | |
495 | break; | |
496 | case i82558A: | |
497 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); | |
498 | PCI_CONFIG_16(PCI_STATUS, 0x0290); | |
499 | PCI_CONFIG_8(PCI_REVISION_ID, 0x04); | |
500 | s->stats_size = 76; | |
501 | s->has_extended_tcb_support = 1; | |
663e8e51 TS |
502 | break; |
503 | case i82558B: | |
d6fd1e66 | 504 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
ba42b646 | 505 | PCI_CONFIG_16(PCI_STATUS, 0x0290); |
663e8e51 | 506 | PCI_CONFIG_8(PCI_REVISION_ID, 0x05); |
ba42b646 SW |
507 | s->stats_size = 76; |
508 | s->has_extended_tcb_support = 1; | |
509 | break; | |
510 | case i82559A: | |
511 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); | |
512 | PCI_CONFIG_16(PCI_STATUS, 0x0290); | |
513 | PCI_CONFIG_8(PCI_REVISION_ID, 0x06); | |
514 | s->stats_size = 80; | |
515 | s->has_extended_tcb_support = 1; | |
516 | break; | |
517 | case i82559B: | |
518 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); | |
519 | PCI_CONFIG_16(PCI_STATUS, 0x0290); | |
520 | PCI_CONFIG_8(PCI_REVISION_ID, 0x07); | |
521 | s->stats_size = 80; | |
522 | s->has_extended_tcb_support = 1; | |
663e8e51 TS |
523 | break; |
524 | case i82559C: | |
d6fd1e66 | 525 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
ba42b646 SW |
526 | PCI_CONFIG_16(PCI_STATUS, 0x0290); |
527 | PCI_CONFIG_8(PCI_REVISION_ID, 0x08); | |
528 | // TODO: Windows wants revision id 0x0c. | |
529 | PCI_CONFIG_8(PCI_REVISION_ID, 0x0c); | |
530 | #if EEPROM_SIZE > 0 | |
531 | PCI_CONFIG_16(PCI_SUBSYSTEM_VENDOR_ID, 0x8086); | |
532 | PCI_CONFIG_16(PCI_SUBSYSTEM_ID, 0x0040); | |
533 | #endif | |
534 | s->stats_size = 80; | |
535 | s->has_extended_tcb_support = 1; | |
663e8e51 TS |
536 | break; |
537 | case i82559ER: | |
d6fd1e66 | 538 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); |
ba42b646 | 539 | PCI_CONFIG_16(PCI_STATUS, 0x0290); |
663e8e51 | 540 | PCI_CONFIG_8(PCI_REVISION_ID, 0x09); |
ba42b646 SW |
541 | s->stats_size = 80; |
542 | s->has_extended_tcb_support = 1; | |
543 | break; | |
544 | case i82562: | |
545 | // TODO: check device id. | |
546 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); | |
547 | /* TODO: wrong revision id. */ | |
548 | PCI_CONFIG_8(PCI_REVISION_ID, 0x0e); | |
549 | s->stats_size = 80; | |
550 | s->has_extended_tcb_support = 1; | |
663e8e51 | 551 | break; |
663e8e51 TS |
552 | default: |
553 | logout("Device %X is undefined!\n", device); | |
554 | } | |
555 | ||
ba42b646 SW |
556 | s->configuration[6] |= BIT(5); |
557 | ||
558 | if (s->stats_size == 80) { | |
559 | /* TODO: check TCO Statistical Counters bit. Documentation not clear. */ | |
560 | if (s->configuration[6] & BIT(2)) { | |
561 | /* TCO statistical counters. */ | |
562 | assert(s->configuration[6] & BIT(5)); | |
563 | } else { | |
564 | if (s->configuration[6] & BIT(5)) { | |
565 | /* No extended statistical counters, i82557 compatible. */ | |
566 | s->stats_size = 64; | |
567 | } else { | |
568 | /* i82558 compatible. */ | |
569 | s->stats_size = 76; | |
570 | } | |
571 | } | |
572 | } else { | |
573 | if (s->configuration[6] & BIT(5)) { | |
574 | /* No extended statistical counters. */ | |
575 | s->stats_size = 64; | |
576 | } | |
577 | } | |
578 | assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics)); | |
579 | ||
580 | if (power_management) { | |
581 | /* Power Management Capabilities */ | |
582 | PCI_CONFIG_8(0xdc, 0x01); | |
583 | /* Next Item Pointer */ | |
584 | /* Capability ID */ | |
585 | PCI_CONFIG_16(0xde, 0x7e21); | |
586 | /* TODO: Power Management Control / Status. */ | |
587 | /* TODO: Ethernet Power Consumption Registers (i82559 and later). */ | |
588 | } | |
589 | ||
590 | #if EEPROM_SIZE > 0 | |
663e8e51 | 591 | if (device == i82557C || device == i82558B || device == i82559C) { |
ba42b646 SW |
592 | // TODO: get vendor id from EEPROM for i82557C or later. |
593 | // TODO: get device id from EEPROM for i82557C or later. | |
594 | // TODO: status bit 4 can be disabled by EEPROM for i82558, i82559. | |
595 | // TODO: header type is determined by EEPROM for i82559. | |
596 | // TODO: get subsystem id from EEPROM for i82557C or later. | |
597 | // TODO: get subsystem vendor id from EEPROM for i82557C or later. | |
598 | // TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later. | |
599 | // TODO: capability pointer depends on EEPROM for i82558. | |
663e8e51 TS |
600 | logout("Get device id and revision from EEPROM!!!\n"); |
601 | } | |
ba42b646 | 602 | #endif /* EEPROM_SIZE > 0 */ |
663e8e51 TS |
603 | } |
604 | ||
605 | static void nic_selective_reset(EEPRO100State * s) | |
606 | { | |
607 | size_t i; | |
608 | uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom); | |
609 | //~ eeprom93xx_reset(s->eeprom); | |
508ef936 | 610 | memcpy(eeprom_contents, s->conf.macaddr.a, 6); |
663e8e51 | 611 | eeprom_contents[0xa] = 0x4000; |
f4e94dfe RD |
612 | if (s->device == i82557B || s->device == i82557C) |
613 | eeprom_contents[5] = 0x0100; | |
663e8e51 TS |
614 | uint16_t sum = 0; |
615 | for (i = 0; i < EEPROM_SIZE - 1; i++) { | |
616 | sum += eeprom_contents[i]; | |
617 | } | |
618 | eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum; | |
aac443e6 | 619 | TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1])); |
663e8e51 TS |
620 | |
621 | memset(s->mem, 0, sizeof(s->mem)); | |
622 | uint32_t val = BIT(21); | |
623 | memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val)); | |
624 | ||
625 | assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default)); | |
626 | memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem)); | |
627 | } | |
628 | ||
629 | static void nic_reset(void *opaque) | |
630 | { | |
769cf7a5 | 631 | EEPRO100State *s = opaque; |
aac443e6 | 632 | TRACE(OTHER, logout("%p\n", s)); |
663e8e51 TS |
633 | nic_selective_reset(s); |
634 | } | |
635 | ||
636 | #if defined(DEBUG_EEPRO100) | |
6a0b9cc9 | 637 | static const char * const reg[PCI_IO_SIZE / 4] = { |
663e8e51 TS |
638 | "Command/Status", |
639 | "General Pointer", | |
640 | "Port", | |
641 | "EEPROM/Flash Control", | |
642 | "MDI Control", | |
643 | "Receive DMA Byte Count", | |
aac443e6 | 644 | "Flow control", |
663e8e51 TS |
645 | "General Status/Control" |
646 | }; | |
647 | ||
648 | static char *regname(uint32_t addr) | |
649 | { | |
650 | static char buf[16]; | |
651 | if (addr < PCI_IO_SIZE) { | |
652 | const char *r = reg[addr / 4]; | |
653 | if (r != 0) { | |
41cbc23c | 654 | snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4); |
663e8e51 | 655 | } else { |
41cbc23c | 656 | snprintf(buf, sizeof(buf), "0x%02x", addr); |
663e8e51 TS |
657 | } |
658 | } else { | |
41cbc23c | 659 | snprintf(buf, sizeof(buf), "??? 0x%08x", addr); |
663e8e51 TS |
660 | } |
661 | return buf; | |
662 | } | |
663 | #endif /* DEBUG_EEPRO100 */ | |
664 | ||
665 | #if 0 | |
666 | static uint16_t eepro100_read_status(EEPRO100State * s) | |
667 | { | |
668 | uint16_t val = s->status; | |
aac443e6 | 669 | TRACE(OTHER, logout("val=0x%04x\n", val)); |
663e8e51 TS |
670 | return val; |
671 | } | |
672 | ||
673 | static void eepro100_write_status(EEPRO100State * s, uint16_t val) | |
674 | { | |
aac443e6 | 675 | TRACE(OTHER, logout("val=0x%04x\n", val)); |
663e8e51 TS |
676 | s->status = val; |
677 | } | |
678 | #endif | |
679 | ||
680 | /***************************************************************************** | |
681 | * | |
682 | * Command emulation. | |
683 | * | |
684 | ****************************************************************************/ | |
685 | ||
686 | #if 0 | |
687 | static uint16_t eepro100_read_command(EEPRO100State * s) | |
688 | { | |
689 | uint16_t val = 0xffff; | |
aac443e6 | 690 | //~ TRACE(OTHER, logout("val=0x%04x\n", val)); |
663e8e51 TS |
691 | return val; |
692 | } | |
693 | #endif | |
694 | ||
695 | /* Commands that can be put in a command list entry. */ | |
696 | enum commands { | |
697 | CmdNOp = 0, | |
698 | CmdIASetup = 1, | |
699 | CmdConfigure = 2, | |
700 | CmdMulticastList = 3, | |
701 | CmdTx = 4, | |
702 | CmdTDR = 5, /* load microcode */ | |
703 | CmdDump = 6, | |
704 | CmdDiagnose = 7, | |
705 | ||
706 | /* And some extra flags: */ | |
707 | CmdSuspend = 0x4000, /* Suspend after completion. */ | |
708 | CmdIntr = 0x2000, /* Interrupt after completion. */ | |
709 | CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */ | |
710 | }; | |
711 | ||
c227f099 | 712 | static cu_state_t get_cu_state(EEPRO100State * s) |
663e8e51 TS |
713 | { |
714 | return ((s->mem[SCBStatus] >> 6) & 0x03); | |
715 | } | |
716 | ||
c227f099 | 717 | static void set_cu_state(EEPRO100State * s, cu_state_t state) |
663e8e51 TS |
718 | { |
719 | s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6); | |
720 | } | |
721 | ||
c227f099 | 722 | static ru_state_t get_ru_state(EEPRO100State * s) |
663e8e51 TS |
723 | { |
724 | return ((s->mem[SCBStatus] >> 2) & 0x0f); | |
725 | } | |
726 | ||
c227f099 | 727 | static void set_ru_state(EEPRO100State * s, ru_state_t state) |
663e8e51 TS |
728 | { |
729 | s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2); | |
730 | } | |
731 | ||
732 | static void dump_statistics(EEPRO100State * s) | |
733 | { | |
734 | /* Dump statistical data. Most data is never changed by the emulation | |
735 | * and always 0, so we first just copy the whole block and then those | |
736 | * values which really matter. | |
737 | * Number of data should check configuration!!! | |
738 | */ | |
ba42b646 SW |
739 | cpu_physical_memory_write(s->statsaddr, |
740 | (uint8_t *) & s->statistics, s->stats_size); | |
741 | stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames); | |
742 | stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames); | |
743 | stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors); | |
744 | stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors); | |
745 | //~ stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames); | |
746 | //~ stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames); | |
663e8e51 TS |
747 | //~ missing("CU dump statistical counters"); |
748 | } | |
749 | ||
5fa9a0ae | 750 | static void action_command(EEPRO100State *s) |
663e8e51 | 751 | { |
5fa9a0ae SW |
752 | for (;;) { |
753 | uint32_t cb_address = s->cu_base + s->cu_offset; | |
754 | eepro100_tx_t tx; | |
663e8e51 TS |
755 | cpu_physical_memory_read(cb_address, (uint8_t *) & tx, sizeof(tx)); |
756 | uint16_t status = le16_to_cpu(tx.status); | |
757 | uint16_t command = le16_to_cpu(tx.command); | |
758 | logout | |
759 | ("val=0x%02x (cu start), status=0x%04x, command=0x%04x, link=0x%08x\n", | |
760 | val, status, command, tx.link); | |
761 | bool bit_el = ((command & 0x8000) != 0); | |
762 | bool bit_s = ((command & 0x4000) != 0); | |
763 | bool bit_i = ((command & 0x2000) != 0); | |
764 | bool bit_nc = ((command & 0x0010) != 0); | |
7f1e9d4e | 765 | bool success = true; |
663e8e51 TS |
766 | //~ bool bit_sf = ((command & 0x0008) != 0); |
767 | uint16_t cmd = command & 0x0007; | |
768 | s->cu_offset = le32_to_cpu(tx.link); | |
769 | switch (cmd) { | |
770 | case CmdNOp: | |
771 | /* Do nothing. */ | |
772 | break; | |
773 | case CmdIASetup: | |
508ef936 | 774 | cpu_physical_memory_read(cb_address + 8, &s->conf.macaddr.a[0], 6); |
aac443e6 | 775 | TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6))); |
663e8e51 TS |
776 | break; |
777 | case CmdConfigure: | |
778 | cpu_physical_memory_read(cb_address + 8, &s->configuration[0], | |
779 | sizeof(s->configuration)); | |
aac443e6 | 780 | TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16))); |
663e8e51 TS |
781 | break; |
782 | case CmdMulticastList: | |
783 | //~ missing("multicast list"); | |
784 | break; | |
785 | case CmdTx: | |
786 | (void)0; | |
787 | uint32_t tbd_array = le32_to_cpu(tx.tx_desc_addr); | |
788 | uint16_t tcb_bytes = (le16_to_cpu(tx.tcb_bytes) & 0x3fff); | |
aac443e6 | 789 | TRACE(RXTX, logout |
663e8e51 | 790 | ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n", |
aac443e6 | 791 | tbd_array, tcb_bytes, tx.tbd_count)); |
7f1e9d4e KW |
792 | |
793 | if (bit_nc) { | |
794 | missing("CmdTx: NC = 0"); | |
795 | success = false; | |
796 | break; | |
797 | } | |
663e8e51 | 798 | //~ assert(!bit_sf); |
7f1e9d4e KW |
799 | if (tcb_bytes > 2600) { |
800 | logout("TCB byte count too large, using 2600\n"); | |
801 | tcb_bytes = 2600; | |
802 | } | |
663e8e51 TS |
803 | /* Next assertion fails for local configuration. */ |
804 | //~ assert((tcb_bytes > 0) || (tbd_array != 0xffffffff)); | |
805 | if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) { | |
806 | logout | |
807 | ("illegal values of TBD array address and TCB byte count!\n"); | |
808 | } | |
24e6f355 RD |
809 | // sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes |
810 | uint8_t buf[2600]; | |
663e8e51 TS |
811 | uint16_t size = 0; |
812 | uint32_t tbd_address = cb_address + 0x10; | |
813 | assert(tcb_bytes <= sizeof(buf)); | |
814 | while (size < tcb_bytes) { | |
815 | uint32_t tx_buffer_address = ldl_phys(tbd_address); | |
816 | uint16_t tx_buffer_size = lduw_phys(tbd_address + 4); | |
817 | //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); | |
818 | tbd_address += 8; | |
aac443e6 | 819 | TRACE(RXTX, logout |
663e8e51 | 820 | ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n", |
aac443e6 | 821 | tx_buffer_address, tx_buffer_size)); |
24e6f355 | 822 | tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); |
663e8e51 TS |
823 | cpu_physical_memory_read(tx_buffer_address, &buf[size], |
824 | tx_buffer_size); | |
825 | size += tx_buffer_size; | |
826 | } | |
827 | if (tbd_array == 0xffffffff) { | |
828 | /* Simplified mode. Was already handled by code above. */ | |
829 | } else { | |
830 | /* Flexible mode. */ | |
831 | uint8_t tbd_count = 0; | |
ba42b646 | 832 | if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) { |
3f9cb1c1 | 833 | /* Extended Flexible TCB. */ |
663e8e51 TS |
834 | for (; tbd_count < 2; tbd_count++) { |
835 | uint32_t tx_buffer_address = ldl_phys(tbd_address); | |
836 | uint16_t tx_buffer_size = lduw_phys(tbd_address + 4); | |
837 | uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); | |
838 | tbd_address += 8; | |
aac443e6 | 839 | TRACE(RXTX, logout |
3f9cb1c1 | 840 | ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n", |
aac443e6 | 841 | tx_buffer_address, tx_buffer_size)); |
24e6f355 | 842 | tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); |
663e8e51 TS |
843 | cpu_physical_memory_read(tx_buffer_address, &buf[size], |
844 | tx_buffer_size); | |
845 | size += tx_buffer_size; | |
846 | if (tx_buffer_el & 1) { | |
847 | break; | |
848 | } | |
849 | } | |
850 | } | |
851 | tbd_address = tbd_array; | |
852 | for (; tbd_count < tx.tbd_count; tbd_count++) { | |
853 | uint32_t tx_buffer_address = ldl_phys(tbd_address); | |
854 | uint16_t tx_buffer_size = lduw_phys(tbd_address + 4); | |
855 | uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); | |
856 | tbd_address += 8; | |
aac443e6 | 857 | TRACE(RXTX, logout |
663e8e51 | 858 | ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n", |
aac443e6 | 859 | tx_buffer_address, tx_buffer_size)); |
24e6f355 | 860 | tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); |
663e8e51 TS |
861 | cpu_physical_memory_read(tx_buffer_address, &buf[size], |
862 | tx_buffer_size); | |
863 | size += tx_buffer_size; | |
864 | if (tx_buffer_el & 1) { | |
865 | break; | |
866 | } | |
867 | } | |
868 | } | |
aac443e6 | 869 | TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size))); |
663e8e51 TS |
870 | qemu_send_packet(s->vc, buf, size); |
871 | s->statistics.tx_good_frames++; | |
872 | /* Transmit with bad status would raise an CX/TNO interrupt. | |
873 | * (82557 only). Emulation never has bad status. */ | |
874 | //~ eepro100_cx_interrupt(s); | |
875 | break; | |
876 | case CmdTDR: | |
aac443e6 | 877 | TRACE(OTHER, logout("load microcode\n")); |
663e8e51 TS |
878 | /* Starting with offset 8, the command contains |
879 | * 64 dwords microcode which we just ignore here. */ | |
880 | break; | |
881 | default: | |
882 | missing("undefined command"); | |
7f1e9d4e KW |
883 | success = false; |
884 | break; | |
663e8e51 | 885 | } |
7f1e9d4e KW |
886 | /* Write new status. */ |
887 | stw_phys(cb_address, status | 0x8000 | (success ? 0x2000 : 0)); | |
663e8e51 TS |
888 | if (bit_i) { |
889 | /* CU completed action. */ | |
890 | eepro100_cx_interrupt(s); | |
891 | } | |
892 | if (bit_el) { | |
aac443e6 | 893 | /* CU becomes idle. Terminate command loop. */ |
663e8e51 TS |
894 | set_cu_state(s, cu_idle); |
895 | eepro100_cna_interrupt(s); | |
5fa9a0ae | 896 | break; |
663e8e51 | 897 | } else if (bit_s) { |
5fa9a0ae | 898 | /* CU becomes suspended. Terminate command loop. */ |
663e8e51 TS |
899 | set_cu_state(s, cu_suspended); |
900 | eepro100_cna_interrupt(s); | |
5fa9a0ae | 901 | break; |
663e8e51 TS |
902 | } else { |
903 | /* More entries in list. */ | |
aac443e6 | 904 | TRACE(OTHER, logout("CU list with at least one more entry\n")); |
663e8e51 | 905 | } |
5fa9a0ae SW |
906 | } |
907 | TRACE(OTHER, logout("CU list empty\n")); | |
908 | /* List is empty. Now CU is idle or suspended. */ | |
909 | } | |
910 | ||
911 | static void eepro100_cu_command(EEPRO100State * s, uint8_t val) | |
912 | { | |
913 | switch (val) { | |
914 | case CU_NOP: | |
915 | /* No operation. */ | |
916 | break; | |
917 | case CU_START: | |
918 | if (get_cu_state(s) != cu_idle) { | |
919 | /* Intel documentation says that CU must be idle for the CU | |
920 | * start command. Intel driver for Linux also starts the CU | |
921 | * from suspended state. */ | |
922 | logout("CU state is %u, should be %u\n", get_cu_state(s), cu_idle); | |
923 | //~ assert(!"wrong CU state"); | |
924 | } | |
925 | set_cu_state(s, cu_active); | |
926 | s->cu_offset = s->pointer; | |
927 | action_command(s); | |
663e8e51 TS |
928 | break; |
929 | case CU_RESUME: | |
930 | if (get_cu_state(s) != cu_suspended) { | |
931 | logout("bad CU resume from CU state %u\n", get_cu_state(s)); | |
932 | /* Workaround for bad Linux eepro100 driver which resumes | |
933 | * from idle state. */ | |
934 | //~ missing("cu resume"); | |
935 | set_cu_state(s, cu_suspended); | |
936 | } | |
937 | if (get_cu_state(s) == cu_suspended) { | |
aac443e6 | 938 | TRACE(OTHER, logout("CU resuming\n")); |
663e8e51 | 939 | set_cu_state(s, cu_active); |
5fa9a0ae | 940 | action_command(s); |
663e8e51 TS |
941 | } |
942 | break; | |
943 | case CU_STATSADDR: | |
944 | /* Load dump counters address. */ | |
945 | s->statsaddr = s->pointer; | |
aac443e6 | 946 | TRACE(OTHER, logout("val=0x%02x (status address)\n", val)); |
663e8e51 TS |
947 | break; |
948 | case CU_SHOWSTATS: | |
949 | /* Dump statistical counters. */ | |
aac443e6 | 950 | TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val)); |
663e8e51 | 951 | dump_statistics(s); |
ba42b646 | 952 | stl_le_phys(s->statsaddr + s->stats_size, 0xa005); |
663e8e51 TS |
953 | break; |
954 | case CU_CMD_BASE: | |
955 | /* Load CU base. */ | |
aac443e6 | 956 | TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val)); |
663e8e51 TS |
957 | s->cu_base = s->pointer; |
958 | break; | |
959 | case CU_DUMPSTATS: | |
960 | /* Dump and reset statistical counters. */ | |
aac443e6 | 961 | TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val)); |
663e8e51 | 962 | dump_statistics(s); |
ba42b646 | 963 | stl_le_phys(s->statsaddr + s->stats_size, 0xa007); |
663e8e51 TS |
964 | memset(&s->statistics, 0, sizeof(s->statistics)); |
965 | break; | |
966 | case CU_SRESUME: | |
967 | /* CU static resume. */ | |
968 | missing("CU static resume"); | |
969 | break; | |
970 | default: | |
971 | missing("Undefined CU command"); | |
972 | } | |
973 | } | |
974 | ||
975 | static void eepro100_ru_command(EEPRO100State * s, uint8_t val) | |
976 | { | |
977 | switch (val) { | |
978 | case RU_NOP: | |
979 | /* No operation. */ | |
980 | break; | |
981 | case RX_START: | |
982 | /* RU start. */ | |
983 | if (get_ru_state(s) != ru_idle) { | |
984 | logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle); | |
985 | //~ assert(!"wrong RU state"); | |
986 | } | |
987 | set_ru_state(s, ru_ready); | |
988 | s->ru_offset = s->pointer; | |
aac443e6 | 989 | TRACE(OTHER, logout("val=0x%02x (rx start)\n", val)); |
663e8e51 TS |
990 | break; |
991 | case RX_RESUME: | |
992 | /* Restart RU. */ | |
993 | if (get_ru_state(s) != ru_suspended) { | |
994 | logout("RU state is %u, should be %u\n", get_ru_state(s), | |
995 | ru_suspended); | |
996 | //~ assert(!"wrong RU state"); | |
997 | } | |
998 | set_ru_state(s, ru_ready); | |
999 | break; | |
1000 | case RX_ADDR_LOAD: | |
1001 | /* Load RU base. */ | |
aac443e6 | 1002 | TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val)); |
663e8e51 TS |
1003 | s->ru_base = s->pointer; |
1004 | break; | |
1005 | default: | |
1006 | logout("val=0x%02x (undefined RU command)\n", val); | |
1007 | missing("Undefined SU command"); | |
1008 | } | |
1009 | } | |
1010 | ||
1011 | static void eepro100_write_command(EEPRO100State * s, uint8_t val) | |
1012 | { | |
1013 | eepro100_ru_command(s, val & 0x0f); | |
1014 | eepro100_cu_command(s, val & 0xf0); | |
1015 | if ((val) == 0) { | |
aac443e6 | 1016 | TRACE(OTHER, logout("val=0x%02x\n", val)); |
663e8e51 TS |
1017 | } |
1018 | /* Clear command byte after command was accepted. */ | |
1019 | s->mem[SCBCmd] = 0; | |
1020 | } | |
1021 | ||
1022 | /***************************************************************************** | |
1023 | * | |
1024 | * EEPROM emulation. | |
1025 | * | |
1026 | ****************************************************************************/ | |
1027 | ||
1028 | #define EEPROM_CS 0x02 | |
1029 | #define EEPROM_SK 0x01 | |
1030 | #define EEPROM_DI 0x04 | |
1031 | #define EEPROM_DO 0x08 | |
1032 | ||
1033 | static uint16_t eepro100_read_eeprom(EEPRO100State * s) | |
1034 | { | |
1035 | uint16_t val; | |
1036 | memcpy(&val, &s->mem[SCBeeprom], sizeof(val)); | |
1037 | if (eeprom93xx_read(s->eeprom)) { | |
1038 | val |= EEPROM_DO; | |
1039 | } else { | |
1040 | val &= ~EEPROM_DO; | |
1041 | } | |
aac443e6 | 1042 | TRACE(EEPROM, logout("val=0x%04x\n", val)); |
663e8e51 TS |
1043 | return val; |
1044 | } | |
1045 | ||
c227f099 | 1046 | static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val) |
663e8e51 | 1047 | { |
aac443e6 | 1048 | TRACE(EEPROM, logout("val=0x%02x\n", val)); |
663e8e51 TS |
1049 | |
1050 | /* mask unwriteable bits */ | |
1051 | //~ val = SET_MASKED(val, 0x31, eeprom->value); | |
1052 | ||
1053 | int eecs = ((val & EEPROM_CS) != 0); | |
1054 | int eesk = ((val & EEPROM_SK) != 0); | |
1055 | int eedi = ((val & EEPROM_DI) != 0); | |
1056 | eeprom93xx_write(eeprom, eecs, eesk, eedi); | |
1057 | } | |
1058 | ||
1059 | static void eepro100_write_pointer(EEPRO100State * s, uint32_t val) | |
1060 | { | |
1061 | s->pointer = le32_to_cpu(val); | |
aac443e6 | 1062 | TRACE(OTHER, logout("val=0x%08x\n", val)); |
663e8e51 TS |
1063 | } |
1064 | ||
1065 | /***************************************************************************** | |
1066 | * | |
1067 | * MDI emulation. | |
1068 | * | |
1069 | ****************************************************************************/ | |
1070 | ||
1071 | #if defined(DEBUG_EEPRO100) | |
6a0b9cc9 | 1072 | static const char * const mdi_op_name[] = { |
663e8e51 TS |
1073 | "opcode 0", |
1074 | "write", | |
1075 | "read", | |
1076 | "opcode 3" | |
1077 | }; | |
1078 | ||
6a0b9cc9 | 1079 | static const char * const mdi_reg_name[] = { |
663e8e51 TS |
1080 | "Control", |
1081 | "Status", | |
1082 | "PHY Identification (Word 1)", | |
1083 | "PHY Identification (Word 2)", | |
1084 | "Auto-Negotiation Advertisement", | |
1085 | "Auto-Negotiation Link Partner Ability", | |
1086 | "Auto-Negotiation Expansion" | |
1087 | }; | |
aac443e6 SW |
1088 | |
1089 | static const char *reg2name(uint8_t reg) | |
1090 | { | |
1091 | static char buffer[10]; | |
1092 | const char *p = buffer; | |
1093 | if (reg < ARRAY_SIZE(mdi_reg_name)) { | |
1094 | p = mdi_reg_name[reg]; | |
1095 | } else { | |
1096 | snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg); | |
1097 | } | |
1098 | return p; | |
1099 | } | |
663e8e51 TS |
1100 | #endif /* DEBUG_EEPRO100 */ |
1101 | ||
1102 | static uint32_t eepro100_read_mdi(EEPRO100State * s) | |
1103 | { | |
1104 | uint32_t val; | |
1105 | memcpy(&val, &s->mem[0x10], sizeof(val)); | |
1106 | ||
1107 | #ifdef DEBUG_EEPRO100 | |
1108 | uint8_t raiseint = (val & BIT(29)) >> 29; | |
1109 | uint8_t opcode = (val & BITS(27, 26)) >> 26; | |
1110 | uint8_t phy = (val & BITS(25, 21)) >> 21; | |
1111 | uint8_t reg = (val & BITS(20, 16)) >> 16; | |
1112 | uint16_t data = (val & BITS(15, 0)); | |
1113 | #endif | |
1114 | /* Emulation takes no time to finish MDI transaction. */ | |
1115 | val |= BIT(28); | |
1116 | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", | |
1117 | val, raiseint, mdi_op_name[opcode], phy, | |
aac443e6 | 1118 | reg2name(reg), data)); |
663e8e51 TS |
1119 | return val; |
1120 | } | |
1121 | ||
663e8e51 TS |
1122 | static void eepro100_write_mdi(EEPRO100State * s, uint32_t val) |
1123 | { | |
1124 | uint8_t raiseint = (val & BIT(29)) >> 29; | |
1125 | uint8_t opcode = (val & BITS(27, 26)) >> 26; | |
1126 | uint8_t phy = (val & BITS(25, 21)) >> 21; | |
1127 | uint8_t reg = (val & BITS(20, 16)) >> 16; | |
1128 | uint16_t data = (val & BITS(15, 0)); | |
aac443e6 SW |
1129 | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", |
1130 | val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data)); | |
663e8e51 TS |
1131 | if (phy != 1) { |
1132 | /* Unsupported PHY address. */ | |
1133 | //~ logout("phy must be 1 but is %u\n", phy); | |
1134 | data = 0; | |
1135 | } else if (opcode != 1 && opcode != 2) { | |
1136 | /* Unsupported opcode. */ | |
1137 | logout("opcode must be 1 or 2 but is %u\n", opcode); | |
1138 | data = 0; | |
1139 | } else if (reg > 6) { | |
1140 | /* Unsupported register. */ | |
1141 | logout("register must be 0...6 but is %u\n", reg); | |
1142 | data = 0; | |
1143 | } else { | |
1144 | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", | |
1145 | val, raiseint, mdi_op_name[opcode], phy, | |
aac443e6 | 1146 | reg2name(reg), data)); |
663e8e51 TS |
1147 | if (opcode == 1) { |
1148 | /* MDI write */ | |
1149 | switch (reg) { | |
1150 | case 0: /* Control Register */ | |
1151 | if (data & 0x8000) { | |
1152 | /* Reset status and control registers to default. */ | |
1153 | s->mdimem[0] = eepro100_mdi_default[0]; | |
1154 | s->mdimem[1] = eepro100_mdi_default[1]; | |
1155 | data = s->mdimem[reg]; | |
1156 | } else { | |
1157 | /* Restart Auto Configuration = Normal Operation */ | |
1158 | data &= ~0x0200; | |
1159 | } | |
1160 | break; | |
1161 | case 1: /* Status Register */ | |
1162 | missing("not writable"); | |
1163 | data = s->mdimem[reg]; | |
1164 | break; | |
1165 | case 2: /* PHY Identification Register (Word 1) */ | |
1166 | case 3: /* PHY Identification Register (Word 2) */ | |
1167 | missing("not implemented"); | |
1168 | break; | |
1169 | case 4: /* Auto-Negotiation Advertisement Register */ | |
1170 | case 5: /* Auto-Negotiation Link Partner Ability Register */ | |
1171 | break; | |
1172 | case 6: /* Auto-Negotiation Expansion Register */ | |
1173 | default: | |
1174 | missing("not implemented"); | |
1175 | } | |
1176 | s->mdimem[reg] = data; | |
1177 | } else if (opcode == 2) { | |
1178 | /* MDI read */ | |
1179 | switch (reg) { | |
1180 | case 0: /* Control Register */ | |
1181 | if (data & 0x8000) { | |
1182 | /* Reset status and control registers to default. */ | |
1183 | s->mdimem[0] = eepro100_mdi_default[0]; | |
1184 | s->mdimem[1] = eepro100_mdi_default[1]; | |
1185 | } | |
1186 | break; | |
1187 | case 1: /* Status Register */ | |
1188 | s->mdimem[reg] |= 0x0020; | |
1189 | break; | |
1190 | case 2: /* PHY Identification Register (Word 1) */ | |
1191 | case 3: /* PHY Identification Register (Word 2) */ | |
1192 | case 4: /* Auto-Negotiation Advertisement Register */ | |
1193 | break; | |
1194 | case 5: /* Auto-Negotiation Link Partner Ability Register */ | |
1195 | s->mdimem[reg] = 0x41fe; | |
1196 | break; | |
1197 | case 6: /* Auto-Negotiation Expansion Register */ | |
1198 | s->mdimem[reg] = 0x0001; | |
1199 | break; | |
1200 | } | |
1201 | data = s->mdimem[reg]; | |
1202 | } | |
1203 | /* Emulation takes no time to finish MDI transaction. | |
1204 | * Set MDI bit in SCB status register. */ | |
1205 | s->mem[SCBAck] |= 0x08; | |
1206 | val |= BIT(28); | |
1207 | if (raiseint) { | |
1208 | eepro100_mdi_interrupt(s); | |
1209 | } | |
1210 | } | |
1211 | val = (val & 0xffff0000) + data; | |
1212 | memcpy(&s->mem[0x10], &val, sizeof(val)); | |
1213 | } | |
1214 | ||
1215 | /***************************************************************************** | |
1216 | * | |
1217 | * Port emulation. | |
1218 | * | |
1219 | ****************************************************************************/ | |
1220 | ||
1221 | #define PORT_SOFTWARE_RESET 0 | |
1222 | #define PORT_SELFTEST 1 | |
1223 | #define PORT_SELECTIVE_RESET 2 | |
1224 | #define PORT_DUMP 3 | |
1225 | #define PORT_SELECTION_MASK 3 | |
1226 | ||
1227 | typedef struct { | |
1228 | uint32_t st_sign; /* Self Test Signature */ | |
1229 | uint32_t st_result; /* Self Test Results */ | |
c227f099 | 1230 | } eepro100_selftest_t; |
663e8e51 TS |
1231 | |
1232 | static uint32_t eepro100_read_port(EEPRO100State * s) | |
1233 | { | |
1234 | return 0; | |
1235 | } | |
1236 | ||
1237 | static void eepro100_write_port(EEPRO100State * s, uint32_t val) | |
1238 | { | |
1239 | val = le32_to_cpu(val); | |
1240 | uint32_t address = (val & ~PORT_SELECTION_MASK); | |
1241 | uint8_t selection = (val & PORT_SELECTION_MASK); | |
1242 | switch (selection) { | |
1243 | case PORT_SOFTWARE_RESET: | |
1244 | nic_reset(s); | |
1245 | break; | |
1246 | case PORT_SELFTEST: | |
aac443e6 | 1247 | TRACE(OTHER, logout("selftest address=0x%08x\n", address)); |
c227f099 | 1248 | eepro100_selftest_t data; |
663e8e51 TS |
1249 | cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data)); |
1250 | data.st_sign = 0xffffffff; | |
1251 | data.st_result = 0; | |
1252 | cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data)); | |
1253 | break; | |
1254 | case PORT_SELECTIVE_RESET: | |
aac443e6 | 1255 | TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address)); |
663e8e51 TS |
1256 | nic_selective_reset(s); |
1257 | break; | |
1258 | default: | |
1259 | logout("val=0x%08x\n", val); | |
1260 | missing("unknown port selection"); | |
1261 | } | |
1262 | } | |
1263 | ||
1264 | /***************************************************************************** | |
1265 | * | |
1266 | * General hardware emulation. | |
1267 | * | |
1268 | ****************************************************************************/ | |
1269 | ||
1270 | static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr) | |
1271 | { | |
1272 | uint8_t val; | |
1273 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1274 | memcpy(&val, &s->mem[addr], sizeof(val)); | |
1275 | } | |
1276 | ||
1277 | switch (addr) { | |
1278 | case SCBStatus: | |
1279 | //~ val = eepro100_read_status(s); | |
aac443e6 | 1280 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1281 | break; |
1282 | case SCBAck: | |
1283 | //~ val = eepro100_read_status(s); | |
aac443e6 | 1284 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1285 | break; |
1286 | case SCBCmd: | |
aac443e6 | 1287 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1288 | //~ val = eepro100_read_command(s); |
1289 | break; | |
1290 | case SCBIntmask: | |
aac443e6 | 1291 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1292 | break; |
1293 | case SCBPort + 3: | |
aac443e6 | 1294 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1295 | break; |
1296 | case SCBeeprom: | |
1297 | val = eepro100_read_eeprom(s); | |
1298 | break; | |
1299 | case 0x1b: /* PMDR (power management driver register) */ | |
1300 | val = 0; | |
aac443e6 | 1301 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1302 | break; |
1303 | case 0x1d: /* general status register */ | |
1304 | /* 100 Mbps full duplex, valid link */ | |
1305 | val = 0x07; | |
aac443e6 | 1306 | TRACE(OTHER, logout("addr=General Status val=%02x\n", val)); |
663e8e51 TS |
1307 | break; |
1308 | default: | |
1309 | logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1310 | missing("unknown byte read"); | |
1311 | } | |
1312 | return val; | |
1313 | } | |
1314 | ||
1315 | static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr) | |
1316 | { | |
1317 | uint16_t val; | |
1318 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1319 | memcpy(&val, &s->mem[addr], sizeof(val)); | |
1320 | } | |
1321 | ||
663e8e51 TS |
1322 | switch (addr) { |
1323 | case SCBStatus: | |
1324 | //~ val = eepro100_read_status(s); | |
dbbaaff6 | 1325 | case SCBCmd: |
aac443e6 | 1326 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 TS |
1327 | break; |
1328 | case SCBeeprom: | |
1329 | val = eepro100_read_eeprom(s); | |
aac443e6 | 1330 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 TS |
1331 | break; |
1332 | default: | |
1333 | logout("addr=%s val=0x%04x\n", regname(addr), val); | |
1334 | missing("unknown word read"); | |
1335 | } | |
1336 | return val; | |
1337 | } | |
1338 | ||
1339 | static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr) | |
1340 | { | |
1341 | uint32_t val; | |
1342 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1343 | memcpy(&val, &s->mem[addr], sizeof(val)); | |
1344 | } | |
1345 | ||
1346 | switch (addr) { | |
1347 | case SCBStatus: | |
1348 | //~ val = eepro100_read_status(s); | |
aac443e6 | 1349 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1350 | break; |
1351 | case SCBPointer: | |
1352 | //~ val = eepro100_read_pointer(s); | |
aac443e6 | 1353 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1354 | break; |
1355 | case SCBPort: | |
1356 | val = eepro100_read_port(s); | |
aac443e6 | 1357 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1358 | break; |
1359 | case SCBCtrlMDI: | |
1360 | val = eepro100_read_mdi(s); | |
1361 | break; | |
1362 | default: | |
1363 | logout("addr=%s val=0x%08x\n", regname(addr), val); | |
1364 | missing("unknown longword read"); | |
1365 | } | |
1366 | return val; | |
1367 | } | |
1368 | ||
1369 | static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val) | |
1370 | { | |
1371 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1372 | memcpy(&s->mem[addr], &val, sizeof(val)); | |
1373 | } | |
1374 | ||
aac443e6 | 1375 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1376 | |
1377 | switch (addr) { | |
1378 | case SCBStatus: | |
1379 | //~ eepro100_write_status(s, val); | |
1380 | break; | |
1381 | case SCBAck: | |
1382 | eepro100_acknowledge(s); | |
1383 | break; | |
1384 | case SCBCmd: | |
1385 | eepro100_write_command(s, val); | |
1386 | break; | |
1387 | case SCBIntmask: | |
1388 | if (val & BIT(1)) { | |
1389 | eepro100_swi_interrupt(s); | |
1390 | } | |
1391 | eepro100_interrupt(s, 0); | |
1392 | break; | |
1393 | case SCBPort + 3: | |
aac443e6 | 1394 | case SCBFlow: /* does not exist on 82557 */ |
3257d2b6 TS |
1395 | case SCBFlow + 1: |
1396 | case SCBFlow + 2: | |
1397 | case SCBFlow + 3: | |
aac443e6 | 1398 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1399 | break; |
1400 | case SCBeeprom: | |
1401 | eepro100_write_eeprom(s->eeprom, val); | |
1402 | break; | |
1403 | default: | |
1404 | logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1405 | missing("unknown byte write"); | |
1406 | } | |
1407 | } | |
1408 | ||
1409 | static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val) | |
1410 | { | |
1411 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1412 | memcpy(&s->mem[addr], &val, sizeof(val)); | |
1413 | } | |
1414 | ||
aac443e6 | 1415 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 TS |
1416 | |
1417 | switch (addr) { | |
1418 | case SCBStatus: | |
1419 | //~ eepro100_write_status(s, val); | |
1420 | eepro100_acknowledge(s); | |
1421 | break; | |
1422 | case SCBCmd: | |
1423 | eepro100_write_command(s, val); | |
1424 | eepro100_write1(s, SCBIntmask, val >> 8); | |
1425 | break; | |
1426 | case SCBeeprom: | |
1427 | eepro100_write_eeprom(s->eeprom, val); | |
1428 | break; | |
1429 | default: | |
1430 | logout("addr=%s val=0x%04x\n", regname(addr), val); | |
1431 | missing("unknown word write"); | |
1432 | } | |
1433 | } | |
1434 | ||
1435 | static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val) | |
1436 | { | |
1437 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1438 | memcpy(&s->mem[addr], &val, sizeof(val)); | |
1439 | } | |
1440 | ||
1441 | switch (addr) { | |
1442 | case SCBPointer: | |
1443 | eepro100_write_pointer(s, val); | |
1444 | break; | |
1445 | case SCBPort: | |
aac443e6 | 1446 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1447 | eepro100_write_port(s, val); |
1448 | break; | |
1449 | case SCBCtrlMDI: | |
1450 | eepro100_write_mdi(s, val); | |
1451 | break; | |
1452 | default: | |
1453 | logout("addr=%s val=0x%08x\n", regname(addr), val); | |
1454 | missing("unknown longword write"); | |
1455 | } | |
1456 | } | |
1457 | ||
aac443e6 SW |
1458 | /***************************************************************************** |
1459 | * | |
1460 | * Port mapped I/O. | |
1461 | * | |
1462 | ****************************************************************************/ | |
1463 | ||
663e8e51 TS |
1464 | static uint32_t ioport_read1(void *opaque, uint32_t addr) |
1465 | { | |
1466 | EEPRO100State *s = opaque; | |
1467 | //~ logout("addr=%s\n", regname(addr)); | |
1468 | return eepro100_read1(s, addr - s->region[1]); | |
1469 | } | |
1470 | ||
1471 | static uint32_t ioport_read2(void *opaque, uint32_t addr) | |
1472 | { | |
1473 | EEPRO100State *s = opaque; | |
1474 | return eepro100_read2(s, addr - s->region[1]); | |
1475 | } | |
1476 | ||
1477 | static uint32_t ioport_read4(void *opaque, uint32_t addr) | |
1478 | { | |
1479 | EEPRO100State *s = opaque; | |
1480 | return eepro100_read4(s, addr - s->region[1]); | |
1481 | } | |
1482 | ||
1483 | static void ioport_write1(void *opaque, uint32_t addr, uint32_t val) | |
1484 | { | |
1485 | EEPRO100State *s = opaque; | |
1486 | //~ logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1487 | eepro100_write1(s, addr - s->region[1], val); | |
1488 | } | |
1489 | ||
1490 | static void ioport_write2(void *opaque, uint32_t addr, uint32_t val) | |
1491 | { | |
1492 | EEPRO100State *s = opaque; | |
1493 | eepro100_write2(s, addr - s->region[1], val); | |
1494 | } | |
1495 | ||
1496 | static void ioport_write4(void *opaque, uint32_t addr, uint32_t val) | |
1497 | { | |
1498 | EEPRO100State *s = opaque; | |
1499 | eepro100_write4(s, addr - s->region[1], val); | |
1500 | } | |
1501 | ||
1502 | /***********************************************************/ | |
1503 | /* PCI EEPRO100 definitions */ | |
1504 | ||
663e8e51 | 1505 | static void pci_map(PCIDevice * pci_dev, int region_num, |
6e355d90 | 1506 | pcibus_t addr, pcibus_t size, int type) |
663e8e51 | 1507 | { |
273a2142 | 1508 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
663e8e51 | 1509 | |
89e8b13c IY |
1510 | TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", " |
1511 | "size=0x%08"FMT_PCIBUS", type=%d\n", | |
aac443e6 | 1512 | region_num, addr, size, type)); |
663e8e51 TS |
1513 | |
1514 | assert(region_num == 1); | |
1515 | register_ioport_write(addr, size, 1, ioport_write1, s); | |
1516 | register_ioport_read(addr, size, 1, ioport_read1, s); | |
1517 | register_ioport_write(addr, size, 2, ioport_write2, s); | |
1518 | register_ioport_read(addr, size, 2, ioport_read2, s); | |
1519 | register_ioport_write(addr, size, 4, ioport_write4, s); | |
1520 | register_ioport_read(addr, size, 4, ioport_read4, s); | |
1521 | ||
1522 | s->region[region_num] = addr; | |
1523 | } | |
1524 | ||
aac443e6 SW |
1525 | /***************************************************************************** |
1526 | * | |
1527 | * Memory mapped I/O. | |
1528 | * | |
1529 | ****************************************************************************/ | |
1530 | ||
c227f099 | 1531 | static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
663e8e51 TS |
1532 | { |
1533 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1534 | //~ logout("addr=%s val=0x%02x\n", regname(addr), val); |
1535 | eepro100_write1(s, addr, val); | |
1536 | } | |
1537 | ||
c227f099 | 1538 | static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
663e8e51 TS |
1539 | { |
1540 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1541 | //~ logout("addr=%s val=0x%02x\n", regname(addr), val); |
1542 | eepro100_write2(s, addr, val); | |
1543 | } | |
1544 | ||
c227f099 | 1545 | static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
663e8e51 TS |
1546 | { |
1547 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1548 | //~ logout("addr=%s val=0x%02x\n", regname(addr), val); |
1549 | eepro100_write4(s, addr, val); | |
1550 | } | |
1551 | ||
c227f099 | 1552 | static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr) |
663e8e51 TS |
1553 | { |
1554 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1555 | //~ logout("addr=%s\n", regname(addr)); |
1556 | return eepro100_read1(s, addr); | |
1557 | } | |
1558 | ||
c227f099 | 1559 | static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr) |
663e8e51 TS |
1560 | { |
1561 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1562 | //~ logout("addr=%s\n", regname(addr)); |
1563 | return eepro100_read2(s, addr); | |
1564 | } | |
1565 | ||
c227f099 | 1566 | static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr) |
663e8e51 TS |
1567 | { |
1568 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1569 | //~ logout("addr=%s\n", regname(addr)); |
1570 | return eepro100_read4(s, addr); | |
1571 | } | |
1572 | ||
d60efc6b | 1573 | static CPUWriteMemoryFunc * const pci_mmio_write[] = { |
663e8e51 TS |
1574 | pci_mmio_writeb, |
1575 | pci_mmio_writew, | |
1576 | pci_mmio_writel | |
1577 | }; | |
1578 | ||
d60efc6b | 1579 | static CPUReadMemoryFunc * const pci_mmio_read[] = { |
663e8e51 TS |
1580 | pci_mmio_readb, |
1581 | pci_mmio_readw, | |
1582 | pci_mmio_readl | |
1583 | }; | |
1584 | ||
1585 | static void pci_mmio_map(PCIDevice * pci_dev, int region_num, | |
6e355d90 | 1586 | pcibus_t addr, pcibus_t size, int type) |
663e8e51 | 1587 | { |
273a2142 | 1588 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
663e8e51 | 1589 | |
89e8b13c IY |
1590 | TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", " |
1591 | "size=0x%08"FMT_PCIBUS", type=%d\n", | |
aac443e6 | 1592 | region_num, addr, size, type)); |
663e8e51 TS |
1593 | |
1594 | if (region_num == 0) { | |
1595 | /* Map control / status registers. */ | |
273a2142 JQ |
1596 | cpu_register_physical_memory(addr, size, s->mmio_index); |
1597 | s->region[region_num] = addr; | |
663e8e51 TS |
1598 | } |
1599 | } | |
1600 | ||
e3f5ec2b | 1601 | static int nic_can_receive(VLANClientState *vc) |
663e8e51 | 1602 | { |
e3f5ec2b | 1603 | EEPRO100State *s = vc->opaque; |
aac443e6 | 1604 | TRACE(RXTX, logout("%p\n", s)); |
663e8e51 TS |
1605 | return get_ru_state(s) == ru_ready; |
1606 | //~ return !eepro100_buffer_full(s); | |
1607 | } | |
1608 | ||
4f1c942b | 1609 | static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size) |
663e8e51 TS |
1610 | { |
1611 | /* TODO: | |
1612 | * - Magic packets should set bit 30 in power management driver register. | |
1613 | * - Interesting packets should set bit 29 in power management driver register. | |
1614 | */ | |
e3f5ec2b | 1615 | EEPRO100State *s = vc->opaque; |
663e8e51 TS |
1616 | uint16_t rfd_status = 0xa000; |
1617 | static const uint8_t broadcast_macaddr[6] = | |
1618 | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; | |
1619 | ||
1620 | /* TODO: check multiple IA bit. */ | |
7f1e9d4e KW |
1621 | if (s->configuration[20] & BIT(6)) { |
1622 | missing("Multiple IA bit"); | |
1623 | return -1; | |
1624 | } | |
663e8e51 TS |
1625 | |
1626 | if (s->configuration[8] & 0x80) { | |
1627 | /* CSMA is disabled. */ | |
1628 | logout("%p received while CSMA is disabled\n", s); | |
4f1c942b | 1629 | return -1; |
663e8e51 TS |
1630 | } else if (size < 64 && (s->configuration[7] & 1)) { |
1631 | /* Short frame and configuration byte 7/0 (discard short receive) set: | |
1632 | * Short frame is discarded */ | |
067d01de | 1633 | logout("%p received short frame (%zu byte)\n", s, size); |
663e8e51 | 1634 | s->statistics.rx_short_frame_errors++; |
4f1c942b | 1635 | //~ return -1; |
663e8e51 TS |
1636 | } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & 8)) { |
1637 | /* Long frame and configuration byte 18/3 (long receive ok) not set: | |
1638 | * Long frames are discarded. */ | |
067d01de | 1639 | logout("%p received long frame (%zu byte), ignored\n", s, size); |
4f1c942b | 1640 | return -1; |
508ef936 | 1641 | } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { // !!! |
663e8e51 TS |
1642 | /* Frame matches individual address. */ |
1643 | /* TODO: check configuration byte 15/4 (ignore U/L). */ | |
067d01de | 1644 | TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size)); |
663e8e51 TS |
1645 | } else if (memcmp(buf, broadcast_macaddr, 6) == 0) { |
1646 | /* Broadcast frame. */ | |
067d01de | 1647 | TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size)); |
663e8e51 TS |
1648 | rfd_status |= 0x0002; |
1649 | } else if (buf[0] & 0x01) { // !!! | |
1650 | /* Multicast frame. */ | |
067d01de | 1651 | TRACE(RXTX, logout("%p received multicast, len=%zu\n", s, size)); |
663e8e51 | 1652 | /* TODO: check multicast all bit. */ |
7f1e9d4e KW |
1653 | if (s->configuration[21] & BIT(3)) { |
1654 | missing("Multicast All bit"); | |
1655 | } | |
663e8e51 TS |
1656 | int mcast_idx = compute_mcast_idx(buf); |
1657 | if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) { | |
4f1c942b | 1658 | return size; |
663e8e51 TS |
1659 | } |
1660 | rfd_status |= 0x0002; | |
1661 | } else if (s->configuration[15] & 1) { | |
1662 | /* Promiscuous: receive all. */ | |
067d01de | 1663 | TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size)); |
663e8e51 TS |
1664 | rfd_status |= 0x0004; |
1665 | } else { | |
067d01de | 1666 | TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size, |
aac443e6 | 1667 | nic_dump(buf, size))); |
4f1c942b | 1668 | return size; |
663e8e51 TS |
1669 | } |
1670 | ||
1671 | if (get_ru_state(s) != ru_ready) { | |
aac443e6 SW |
1672 | /* No resources available. */ |
1673 | logout("no resources, state=%u\n", get_ru_state(s)); | |
663e8e51 | 1674 | s->statistics.rx_resource_errors++; |
aac443e6 | 1675 | //~ assert(!"no resources"); |
4f1c942b | 1676 | return -1; |
663e8e51 TS |
1677 | } |
1678 | //~ !!! | |
1679 | //~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}} | |
c227f099 | 1680 | eepro100_rx_t rx; |
663e8e51 | 1681 | cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx, |
c227f099 | 1682 | offsetof(eepro100_rx_t, packet)); |
663e8e51 TS |
1683 | uint16_t rfd_command = le16_to_cpu(rx.command); |
1684 | uint16_t rfd_size = le16_to_cpu(rx.size); | |
7f1e9d4e KW |
1685 | |
1686 | if (size > rfd_size) { | |
1687 | logout("Receive buffer (%" PRId16 " bytes) too small for data " | |
1688 | "(%zu bytes); data truncated\n", rfd_size, size); | |
1689 | size = rfd_size; | |
1690 | } | |
663e8e51 TS |
1691 | if (size < 64) { |
1692 | rfd_status |= 0x0080; | |
1693 | } | |
aac443e6 SW |
1694 | TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n", |
1695 | rfd_command, rx.link, rx.rx_buf_addr, rfd_size)); | |
c227f099 | 1696 | stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status), |
663e8e51 | 1697 | rfd_status); |
c227f099 | 1698 | stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size); |
663e8e51 TS |
1699 | /* Early receive interrupt not supported. */ |
1700 | //~ eepro100_er_interrupt(s); | |
1701 | /* Receive CRC Transfer not supported. */ | |
7f1e9d4e KW |
1702 | if (s->configuration[18] & 4) { |
1703 | missing("Receive CRC Transfer"); | |
1704 | return -1; | |
1705 | } | |
663e8e51 TS |
1706 | /* TODO: check stripping enable bit. */ |
1707 | //~ assert(!(s->configuration[17] & 1)); | |
1708 | cpu_physical_memory_write(s->ru_base + s->ru_offset + | |
c227f099 | 1709 | offsetof(eepro100_rx_t, packet), buf, size); |
663e8e51 TS |
1710 | s->statistics.rx_good_frames++; |
1711 | eepro100_fr_interrupt(s); | |
1712 | s->ru_offset = le32_to_cpu(rx.link); | |
1713 | if (rfd_command & 0x8000) { | |
1714 | /* EL bit is set, so this was the last frame. */ | |
7f1e9d4e KW |
1715 | logout("receive: Running out of frames\n"); |
1716 | set_ru_state(s, ru_suspended); | |
663e8e51 TS |
1717 | } |
1718 | if (rfd_command & 0x4000) { | |
1719 | /* S bit is set. */ | |
1720 | set_ru_state(s, ru_suspended); | |
1721 | } | |
4f1c942b | 1722 | return size; |
663e8e51 TS |
1723 | } |
1724 | ||
151b2986 JQ |
1725 | static const VMStateDescription vmstate_eepro100 = { |
1726 | .version_id = 3, | |
1727 | .minimum_version_id = 2, | |
1728 | .minimum_version_id_old = 2, | |
1729 | .fields = (VMStateField []) { | |
1730 | VMSTATE_PCI_DEVICE(dev, EEPRO100State), | |
1731 | VMSTATE_UNUSED(32), | |
1732 | VMSTATE_BUFFER(mult, EEPRO100State), | |
1733 | VMSTATE_BUFFER(mem, EEPRO100State), | |
1734 | /* Save all members of struct between scb_stat and mem. */ | |
1735 | VMSTATE_UINT8(scb_stat, EEPRO100State), | |
1736 | VMSTATE_UINT8(int_stat, EEPRO100State), | |
1737 | VMSTATE_UNUSED(3*4), | |
1738 | VMSTATE_MACADDR(conf.macaddr, EEPRO100State), | |
1739 | VMSTATE_UNUSED(19*4), | |
1740 | VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32), | |
1741 | /* The eeprom should be saved and restored by its own routines. */ | |
1742 | VMSTATE_UINT32(device, EEPRO100State), | |
1743 | /* TODO check device. */ | |
1744 | VMSTATE_UINT32(pointer, EEPRO100State), | |
1745 | VMSTATE_UINT32(cu_base, EEPRO100State), | |
1746 | VMSTATE_UINT32(cu_offset, EEPRO100State), | |
1747 | VMSTATE_UINT32(ru_base, EEPRO100State), | |
1748 | VMSTATE_UINT32(ru_offset, EEPRO100State), | |
1749 | VMSTATE_UINT32(statsaddr, EEPRO100State), | |
ba42b646 | 1750 | /* Save eepro100_stats_t statistics. */ |
151b2986 JQ |
1751 | VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State), |
1752 | VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State), | |
1753 | VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State), | |
1754 | VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State), | |
1755 | VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State), | |
1756 | VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State), | |
1757 | VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State), | |
1758 | VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State), | |
1759 | VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State), | |
1760 | VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State), | |
1761 | VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State), | |
1762 | VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State), | |
1763 | VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State), | |
1764 | VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State), | |
1765 | VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State), | |
1766 | VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State), | |
1767 | VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State), | |
1768 | VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State), | |
1769 | VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State), | |
1770 | VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State), | |
1771 | VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State), | |
2657c663 | 1772 | #if 0 |
151b2986 | 1773 | VMSTATE_UINT16(status, EEPRO100State), |
2657c663 | 1774 | #endif |
151b2986 JQ |
1775 | /* Configuration bytes. */ |
1776 | VMSTATE_BUFFER(configuration, EEPRO100State), | |
1777 | VMSTATE_END_OF_LIST() | |
aac443e6 | 1778 | } |
151b2986 | 1779 | }; |
663e8e51 | 1780 | |
b946a153 AL |
1781 | static void nic_cleanup(VLANClientState *vc) |
1782 | { | |
1783 | EEPRO100State *s = vc->opaque; | |
1784 | ||
508ef936 | 1785 | s->vc = NULL; |
b946a153 AL |
1786 | } |
1787 | ||
c4c270e2 | 1788 | static int pci_nic_uninit(PCIDevice *pci_dev) |
b946a153 | 1789 | { |
c4c270e2 | 1790 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
b946a153 AL |
1791 | |
1792 | cpu_unregister_io_memory(s->mmio_index); | |
151b2986 | 1793 | vmstate_unregister(s->vmstate, s); |
508ef936 GH |
1794 | eeprom93xx_free(s->eeprom); |
1795 | qemu_del_vlan_client(s->vc); | |
b946a153 AL |
1796 | return 0; |
1797 | } | |
1798 | ||
81a322d4 | 1799 | static int nic_init(PCIDevice *pci_dev, uint32_t device) |
663e8e51 | 1800 | { |
273a2142 | 1801 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
663e8e51 | 1802 | |
aac443e6 | 1803 | TRACE(OTHER, logout("\n")); |
663e8e51 | 1804 | |
663e8e51 | 1805 | s->device = device; |
663e8e51 TS |
1806 | |
1807 | pci_reset(s); | |
1808 | ||
1809 | /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM, | |
1810 | * i82559 and later support 64 or 256 word EEPROM. */ | |
1811 | s->eeprom = eeprom93xx_new(EEPROM_SIZE); | |
1812 | ||
1813 | /* Handler for memory-mapped I/O */ | |
273a2142 | 1814 | s->mmio_index = |
1eed09cb | 1815 | cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s); |
663e8e51 | 1816 | |
273a2142 | 1817 | pci_register_bar(&s->dev, 0, PCI_MEM_SIZE, |
0392a017 IY |
1818 | PCI_BASE_ADDRESS_SPACE_MEMORY | |
1819 | PCI_BASE_ADDRESS_MEM_PREFETCH, pci_mmio_map); | |
1820 | pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO, | |
663e8e51 | 1821 | pci_map); |
0392a017 | 1822 | pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY, |
663e8e51 TS |
1823 | pci_mmio_map); |
1824 | ||
508ef936 | 1825 | qemu_macaddr_default_if_unset(&s->conf.macaddr); |
663e8e51 TS |
1826 | logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6)); |
1827 | assert(s->region[1] == 0); | |
1828 | ||
1829 | nic_reset(s); | |
1830 | ||
508ef936 GH |
1831 | s->vc = qemu_new_vlan_client(NET_CLIENT_TYPE_NIC, |
1832 | s->conf.vlan, s->conf.peer, | |
1833 | pci_dev->qdev.info->name, pci_dev->qdev.id, | |
1834 | nic_can_receive, nic_receive, NULL, NULL, | |
b946a153 | 1835 | nic_cleanup, s); |
663e8e51 | 1836 | |
508ef936 | 1837 | qemu_format_nic_info_str(s->vc, s->conf.macaddr.a); |
aac443e6 | 1838 | TRACE(OTHER, logout("%s\n", s->vc->info_str)); |
663e8e51 | 1839 | |
a08d4367 | 1840 | qemu_register_reset(nic_reset, s); |
663e8e51 | 1841 | |
151b2986 JQ |
1842 | s->vmstate = qemu_malloc(sizeof(vmstate_eepro100)); |
1843 | memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100)); | |
1844 | s->vmstate->name = s->vc->model; | |
1845 | vmstate_register(-1, s->vmstate, s); | |
81a322d4 | 1846 | return 0; |
663e8e51 TS |
1847 | } |
1848 | ||
c4c270e2 SW |
1849 | static int pci_i82550_init(PCIDevice *pci_dev) |
1850 | { | |
1851 | return nic_init(pci_dev, i82550); | |
1852 | } | |
1853 | ||
1854 | static int pci_i82551_init(PCIDevice *pci_dev) | |
1855 | { | |
1856 | return nic_init(pci_dev, i82551); | |
1857 | } | |
1858 | ||
1859 | static int pci_i82557a_init(PCIDevice *pci_dev) | |
1860 | { | |
1861 | return nic_init(pci_dev, i82557A); | |
1862 | } | |
1863 | ||
1864 | static int pci_i82557b_init(PCIDevice *pci_dev) | |
1865 | { | |
1866 | return nic_init(pci_dev, i82557B); | |
1867 | } | |
1868 | ||
1869 | static int pci_i82557c_init(PCIDevice *pci_dev) | |
1870 | { | |
1871 | return nic_init(pci_dev, i82557C); | |
1872 | } | |
1873 | ||
1874 | static int pci_i82558a_init(PCIDevice *pci_dev) | |
1875 | { | |
1876 | return nic_init(pci_dev, i82558A); | |
1877 | } | |
1878 | ||
1879 | static int pci_i82558b_init(PCIDevice *pci_dev) | |
1880 | { | |
1881 | return nic_init(pci_dev, i82558B); | |
1882 | } | |
1883 | ||
1884 | static int pci_i82559a_init(PCIDevice *pci_dev) | |
1885 | { | |
1886 | return nic_init(pci_dev, i82559A); | |
1887 | } | |
1888 | ||
1889 | static int pci_i82559b_init(PCIDevice *pci_dev) | |
1890 | { | |
1891 | return nic_init(pci_dev, i82559B); | |
1892 | } | |
1893 | ||
1894 | static int pci_i82559c_init(PCIDevice *pci_dev) | |
9d07d757 | 1895 | { |
c4c270e2 | 1896 | return nic_init(pci_dev, i82559C); |
9d07d757 PB |
1897 | } |
1898 | ||
c4c270e2 | 1899 | static int pci_i82559er_init(PCIDevice *pci_dev) |
663e8e51 | 1900 | { |
c4c270e2 | 1901 | return nic_init(pci_dev, i82559ER); |
663e8e51 TS |
1902 | } |
1903 | ||
c4c270e2 | 1904 | static int pci_i82562_init(PCIDevice *pci_dev) |
663e8e51 | 1905 | { |
c4c270e2 | 1906 | return nic_init(pci_dev, i82562); |
663e8e51 TS |
1907 | } |
1908 | ||
0aab0d3a GH |
1909 | static PCIDeviceInfo eepro100_info[] = { |
1910 | { | |
c4c270e2 SW |
1911 | .qdev.name = "i82550", |
1912 | .qdev.size = sizeof(EEPRO100State), | |
1913 | .init = pci_i82550_init, | |
508ef936 GH |
1914 | .qdev.props = (Property[]) { |
1915 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1916 | DEFINE_PROP_END_OF_LIST(), | |
1917 | }, | |
c4c270e2 | 1918 | },{ |
0aab0d3a | 1919 | .qdev.name = "i82551", |
273a2142 | 1920 | .qdev.size = sizeof(EEPRO100State), |
0aab0d3a | 1921 | .init = pci_i82551_init, |
e3936fa5 | 1922 | .exit = pci_nic_uninit, |
508ef936 GH |
1923 | .qdev.props = (Property[]) { |
1924 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1925 | DEFINE_PROP_END_OF_LIST(), | |
1926 | }, | |
c4c270e2 SW |
1927 | },{ |
1928 | .qdev.name = "i82557a", | |
1929 | .qdev.size = sizeof(EEPRO100State), | |
1930 | .init = pci_i82557a_init, | |
508ef936 GH |
1931 | .qdev.props = (Property[]) { |
1932 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1933 | DEFINE_PROP_END_OF_LIST(), | |
1934 | }, | |
0aab0d3a GH |
1935 | },{ |
1936 | .qdev.name = "i82557b", | |
273a2142 | 1937 | .qdev.size = sizeof(EEPRO100State), |
0aab0d3a | 1938 | .init = pci_i82557b_init, |
e3936fa5 | 1939 | .exit = pci_nic_uninit, |
508ef936 GH |
1940 | .qdev.props = (Property[]) { |
1941 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1942 | DEFINE_PROP_END_OF_LIST(), | |
1943 | }, | |
c4c270e2 SW |
1944 | },{ |
1945 | .qdev.name = "i82557c", | |
1946 | .qdev.size = sizeof(EEPRO100State), | |
1947 | .init = pci_i82557c_init, | |
508ef936 GH |
1948 | .qdev.props = (Property[]) { |
1949 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1950 | DEFINE_PROP_END_OF_LIST(), | |
1951 | }, | |
c4c270e2 SW |
1952 | },{ |
1953 | .qdev.name = "i82558a", | |
1954 | .qdev.size = sizeof(EEPRO100State), | |
1955 | .init = pci_i82558a_init, | |
508ef936 GH |
1956 | .qdev.props = (Property[]) { |
1957 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1958 | DEFINE_PROP_END_OF_LIST(), | |
1959 | }, | |
c4c270e2 SW |
1960 | },{ |
1961 | .qdev.name = "i82558b", | |
1962 | .qdev.size = sizeof(EEPRO100State), | |
1963 | .init = pci_i82558b_init, | |
508ef936 GH |
1964 | .qdev.props = (Property[]) { |
1965 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1966 | DEFINE_PROP_END_OF_LIST(), | |
1967 | }, | |
c4c270e2 SW |
1968 | },{ |
1969 | .qdev.name = "i82559a", | |
1970 | .qdev.size = sizeof(EEPRO100State), | |
1971 | .init = pci_i82559a_init, | |
508ef936 GH |
1972 | .qdev.props = (Property[]) { |
1973 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1974 | DEFINE_PROP_END_OF_LIST(), | |
1975 | }, | |
c4c270e2 SW |
1976 | },{ |
1977 | .qdev.name = "i82559b", | |
1978 | .qdev.size = sizeof(EEPRO100State), | |
1979 | .init = pci_i82559b_init, | |
508ef936 GH |
1980 | .qdev.props = (Property[]) { |
1981 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1982 | DEFINE_PROP_END_OF_LIST(), | |
1983 | }, | |
c4c270e2 SW |
1984 | },{ |
1985 | .qdev.name = "i82559c", | |
1986 | .qdev.size = sizeof(EEPRO100State), | |
1987 | .init = pci_i82559c_init, | |
508ef936 GH |
1988 | .qdev.props = (Property[]) { |
1989 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1990 | DEFINE_PROP_END_OF_LIST(), | |
1991 | }, | |
0aab0d3a GH |
1992 | },{ |
1993 | .qdev.name = "i82559er", | |
273a2142 | 1994 | .qdev.size = sizeof(EEPRO100State), |
0aab0d3a | 1995 | .init = pci_i82559er_init, |
e3936fa5 | 1996 | .exit = pci_nic_uninit, |
508ef936 GH |
1997 | .qdev.props = (Property[]) { |
1998 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1999 | DEFINE_PROP_END_OF_LIST(), | |
2000 | }, | |
c4c270e2 SW |
2001 | },{ |
2002 | .qdev.name = "i82562", | |
2003 | .qdev.size = sizeof(EEPRO100State), | |
2004 | .init = pci_i82562_init, | |
508ef936 GH |
2005 | .qdev.props = (Property[]) { |
2006 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
2007 | DEFINE_PROP_END_OF_LIST(), | |
2008 | }, | |
0aab0d3a GH |
2009 | },{ |
2010 | /* end of list */ | |
2011 | } | |
2012 | }; | |
2013 | ||
9d07d757 | 2014 | static void eepro100_register_devices(void) |
663e8e51 | 2015 | { |
0aab0d3a | 2016 | pci_qdev_register_many(eepro100_info); |
663e8e51 TS |
2017 | } |
2018 | ||
9d07d757 | 2019 | device_init(eepro100_register_devices) |