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663e8e51 TS |
1 | /* |
2 | * QEMU i8255x (PRO100) emulation | |
3 | * | |
4 | * Copyright (c) 2006-2007 Stefan Weil | |
5 | * | |
6 | * Portions of the code are copies from grub / etherboot eepro100.c | |
7 | * and linux e100.c. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
8167ee88 | 20 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
663e8e51 TS |
21 | * |
22 | * Tested features (i82559): | |
23 | * PXE boot (i386) no valid link | |
24 | * Linux networking (i386) ok | |
25 | * | |
26 | * Untested: | |
27 | * non-i386 platforms | |
28 | * Windows networking | |
29 | * | |
30 | * References: | |
31 | * | |
32 | * Intel 8255x 10/100 Mbps Ethernet Controller Family | |
33 | * Open Source Software Developer Manual | |
34 | */ | |
35 | ||
36 | #if defined(TARGET_I386) | |
37 | # warning "PXE boot still not working!" | |
38 | #endif | |
39 | ||
663e8e51 | 40 | #include <stddef.h> /* offsetof */ |
b84a5c6f | 41 | #include <stdbool.h> |
87ecb68b PB |
42 | #include "hw.h" |
43 | #include "pci.h" | |
44 | #include "net.h" | |
663e8e51 TS |
45 | #include "eeprom93xx.h" |
46 | ||
47 | /* Common declarations for all PCI devices. */ | |
48 | ||
663e8e51 TS |
49 | #define PCI_CONFIG_8(offset, value) \ |
50 | (pci_conf[offset] = (value)) | |
51 | #define PCI_CONFIG_16(offset, value) \ | |
52 | (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value)) | |
53 | #define PCI_CONFIG_32(offset, value) \ | |
54 | (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value)) | |
55 | ||
56 | #define KiB 1024 | |
57 | ||
aac443e6 | 58 | /* Debug EEPRO100 card. */ |
663e8e51 TS |
59 | //~ #define DEBUG_EEPRO100 |
60 | ||
61 | #ifdef DEBUG_EEPRO100 | |
001faf32 | 62 | #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__) |
663e8e51 | 63 | #else |
001faf32 | 64 | #define logout(fmt, ...) ((void)0) |
663e8e51 TS |
65 | #endif |
66 | ||
67 | /* Set flags to 0 to disable debug output. */ | |
aac443e6 SW |
68 | #define INT 1 /* interrupt related actions */ |
69 | #define MDI 1 /* mdi related actions */ | |
70 | #define OTHER 1 | |
71 | #define RXTX 1 | |
72 | #define EEPROM 1 /* eeprom related actions */ | |
663e8e51 TS |
73 | |
74 | #define TRACE(flag, command) ((flag) ? (command) : (void)0) | |
75 | ||
76 | #define missing(text) assert(!"feature is missing in this emulation: " text) | |
77 | ||
78 | #define MAX_ETH_FRAME_SIZE 1514 | |
79 | ||
80 | /* This driver supports several different devices which are declared here. */ | |
81 | #define i82551 0x82551 | |
82 | #define i82557B 0x82557b | |
83 | #define i82557C 0x82557c | |
84 | #define i82558B 0x82558b | |
85 | #define i82559C 0x82559c | |
86 | #define i82559ER 0x82559e | |
87 | #define i82562 0x82562 | |
88 | ||
aac443e6 | 89 | /* Use 64 word EEPROM. TODO: could be a runtime option. */ |
663e8e51 TS |
90 | #define EEPROM_SIZE 64 |
91 | ||
92 | #define PCI_MEM_SIZE (4 * KiB) | |
93 | #define PCI_IO_SIZE 64 | |
94 | #define PCI_FLASH_SIZE (128 * KiB) | |
95 | ||
96 | #define BIT(n) (1 << (n)) | |
97 | #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) | |
98 | ||
99 | /* The SCB accepts the following controls for the Tx and Rx units: */ | |
100 | #define CU_NOP 0x0000 /* No operation. */ | |
101 | #define CU_START 0x0010 /* CU start. */ | |
102 | #define CU_RESUME 0x0020 /* CU resume. */ | |
103 | #define CU_STATSADDR 0x0040 /* Load dump counters address. */ | |
104 | #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */ | |
105 | #define CU_CMD_BASE 0x0060 /* Load CU base address. */ | |
106 | #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */ | |
107 | #define CU_SRESUME 0x00a0 /* CU static resume. */ | |
108 | ||
109 | #define RU_NOP 0x0000 | |
110 | #define RX_START 0x0001 | |
111 | #define RX_RESUME 0x0002 | |
112 | #define RX_ABORT 0x0004 | |
113 | #define RX_ADDR_LOAD 0x0006 | |
114 | #define RX_RESUMENR 0x0007 | |
115 | #define INT_MASK 0x0100 | |
116 | #define DRVR_INT 0x0200 /* Driver generated interrupt. */ | |
117 | ||
663e8e51 TS |
118 | /* Offsets to the various registers. |
119 | All accesses need not be longword aligned. */ | |
120 | enum speedo_offsets { | |
121 | SCBStatus = 0, | |
122 | SCBAck = 1, | |
123 | SCBCmd = 2, /* Rx/Command Unit command and status. */ | |
124 | SCBIntmask = 3, | |
125 | SCBPointer = 4, /* General purpose pointer. */ | |
126 | SCBPort = 8, /* Misc. commands and operands. */ | |
127 | SCBflash = 12, SCBeeprom = 14, /* EEPROM and flash memory control. */ | |
128 | SCBCtrlMDI = 16, /* MDI interface control. */ | |
129 | SCBEarlyRx = 20, /* Early receive byte count. */ | |
3257d2b6 | 130 | SCBFlow = 24, |
663e8e51 TS |
131 | }; |
132 | ||
133 | /* A speedo3 transmit buffer descriptor with two buffers... */ | |
134 | typedef struct { | |
135 | uint16_t status; | |
136 | uint16_t command; | |
137 | uint32_t link; /* void * */ | |
138 | uint32_t tx_desc_addr; /* transmit buffer decsriptor array address. */ | |
139 | uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */ | |
140 | uint8_t tx_threshold; /* transmit threshold */ | |
141 | uint8_t tbd_count; /* TBD number */ | |
142 | //~ /* This constitutes two "TBD" entries: hdr and data */ | |
143 | //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */ | |
144 | //~ int32_t tx_buf_size0; /* Length of Tx hdr. */ | |
145 | //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */ | |
146 | //~ int32_t tx_buf_size1; /* Length of Tx data. */ | |
c227f099 | 147 | } eepro100_tx_t; |
663e8e51 TS |
148 | |
149 | /* Receive frame descriptor. */ | |
150 | typedef struct { | |
151 | int16_t status; | |
152 | uint16_t command; | |
153 | uint32_t link; /* struct RxFD * */ | |
154 | uint32_t rx_buf_addr; /* void * */ | |
155 | uint16_t count; | |
156 | uint16_t size; | |
157 | char packet[MAX_ETH_FRAME_SIZE + 4]; | |
c227f099 | 158 | } eepro100_rx_t; |
663e8e51 TS |
159 | |
160 | typedef struct { | |
161 | uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions, | |
162 | tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions, | |
163 | tx_multiple_collisions, tx_total_collisions; | |
164 | uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors, | |
165 | rx_resource_errors, rx_overrun_errors, rx_cdt_errors, | |
166 | rx_short_frame_errors; | |
167 | uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported; | |
168 | uint16_t xmt_tco_frames, rcv_tco_frames; | |
169 | uint32_t complete; | |
c227f099 | 170 | } eepro100_stats_t; |
663e8e51 TS |
171 | |
172 | typedef enum { | |
173 | cu_idle = 0, | |
174 | cu_suspended = 1, | |
175 | cu_active = 2, | |
176 | cu_lpq_active = 2, | |
177 | cu_hqp_active = 3 | |
c227f099 | 178 | } cu_state_t; |
663e8e51 TS |
179 | |
180 | typedef enum { | |
181 | ru_idle = 0, | |
182 | ru_suspended = 1, | |
183 | ru_no_resources = 2, | |
184 | ru_ready = 4 | |
c227f099 | 185 | } ru_state_t; |
663e8e51 | 186 | |
663e8e51 | 187 | typedef struct { |
273a2142 | 188 | PCIDevice dev; |
663e8e51 TS |
189 | #if 1 |
190 | uint8_t cmd; | |
191 | uint32_t start; | |
192 | uint32_t stop; | |
663e8e51 TS |
193 | uint8_t mult[8]; /* multicast mask array */ |
194 | int mmio_index; | |
663e8e51 TS |
195 | VLANClientState *vc; |
196 | #endif | |
197 | uint8_t scb_stat; /* SCB stat/ack byte */ | |
198 | uint8_t int_stat; /* PCI interrupt status */ | |
199 | uint32_t region[3]; /* PCI region addresses */ | |
200 | uint8_t macaddr[6]; | |
663e8e51 | 201 | uint16_t mdimem[32]; |
c227f099 | 202 | eeprom_t *eeprom; |
663e8e51 TS |
203 | uint32_t device; /* device variant */ |
204 | uint32_t pointer; | |
205 | /* (cu_base + cu_offset) address the next command block in the command block list. */ | |
206 | uint32_t cu_base; /* CU base address */ | |
207 | uint32_t cu_offset; /* CU address offset */ | |
208 | /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */ | |
209 | uint32_t ru_base; /* RU base address */ | |
210 | uint32_t ru_offset; /* RU address offset */ | |
c227f099 | 211 | uint32_t statsaddr; /* pointer to eepro100_stats_t */ |
3031efab SW |
212 | /* Statistical counters. Also used for wake-up packet (i82559). */ |
213 | eepro100_stats_t statistics; | |
663e8e51 TS |
214 | #if 0 |
215 | uint16_t status; | |
216 | #endif | |
217 | ||
218 | /* Configuration bytes. */ | |
219 | uint8_t configuration[22]; | |
220 | ||
221 | /* Data in mem is always in the byte order of the controller (le). */ | |
222 | uint8_t mem[PCI_MEM_SIZE]; | |
223 | } EEPRO100State; | |
224 | ||
3031efab SW |
225 | /* Parameters for nic_save, nic_load. */ |
226 | static const int eepro100_instance = -1; | |
227 | static const int eepro100_version = 20090807; | |
228 | ||
663e8e51 TS |
229 | /* Default values for MDI (PHY) registers */ |
230 | static const uint16_t eepro100_mdi_default[] = { | |
231 | /* MDI Registers 0 - 6, 7 */ | |
232 | 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000, | |
233 | /* MDI Registers 8 - 15 */ | |
234 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
235 | /* MDI Registers 16 - 31 */ | |
236 | 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
237 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
238 | }; | |
239 | ||
240 | /* Readonly mask for MDI (PHY) registers */ | |
241 | static const uint16_t eepro100_mdi_mask[] = { | |
242 | 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000, | |
243 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
244 | 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, | |
245 | 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
246 | }; | |
247 | ||
248 | #define POLYNOMIAL 0x04c11db6 | |
249 | ||
250 | /* From FreeBSD */ | |
251 | /* XXX: optimize */ | |
252 | static int compute_mcast_idx(const uint8_t * ep) | |
253 | { | |
254 | uint32_t crc; | |
255 | int carry, i, j; | |
256 | uint8_t b; | |
257 | ||
258 | crc = 0xffffffff; | |
259 | for (i = 0; i < 6; i++) { | |
260 | b = *ep++; | |
261 | for (j = 0; j < 8; j++) { | |
262 | carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); | |
263 | crc <<= 1; | |
264 | b >>= 1; | |
aac443e6 | 265 | if (carry) { |
663e8e51 | 266 | crc = ((crc ^ POLYNOMIAL) | carry); |
aac443e6 | 267 | } |
663e8e51 TS |
268 | } |
269 | } | |
270 | return (crc >> 26); | |
271 | } | |
272 | ||
273 | #if defined(DEBUG_EEPRO100) | |
274 | static const char *nic_dump(const uint8_t * buf, unsigned size) | |
275 | { | |
276 | static char dump[3 * 16 + 1]; | |
277 | char *p = &dump[0]; | |
aac443e6 | 278 | if (size > 16) { |
663e8e51 | 279 | size = 16; |
aac443e6 | 280 | } |
663e8e51 TS |
281 | while (size-- > 0) { |
282 | p += sprintf(p, " %02x", *buf++); | |
283 | } | |
284 | return dump; | |
285 | } | |
286 | #endif /* DEBUG_EEPRO100 */ | |
287 | ||
288 | enum scb_stat_ack { | |
289 | stat_ack_not_ours = 0x00, | |
290 | stat_ack_sw_gen = 0x04, | |
291 | stat_ack_rnr = 0x10, | |
292 | stat_ack_cu_idle = 0x20, | |
293 | stat_ack_frame_rx = 0x40, | |
294 | stat_ack_cu_cmd_done = 0x80, | |
295 | stat_ack_not_present = 0xFF, | |
296 | stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx), | |
297 | stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done), | |
298 | }; | |
299 | ||
300 | static void disable_interrupt(EEPRO100State * s) | |
301 | { | |
302 | if (s->int_stat) { | |
aac443e6 | 303 | TRACE(INT, logout("interrupt disabled\n")); |
273a2142 | 304 | qemu_irq_lower(s->dev.irq[0]); |
663e8e51 TS |
305 | s->int_stat = 0; |
306 | } | |
307 | } | |
308 | ||
309 | static void enable_interrupt(EEPRO100State * s) | |
310 | { | |
311 | if (!s->int_stat) { | |
aac443e6 | 312 | TRACE(INT, logout("interrupt enabled\n")); |
273a2142 | 313 | qemu_irq_raise(s->dev.irq[0]); |
663e8e51 TS |
314 | s->int_stat = 1; |
315 | } | |
316 | } | |
317 | ||
318 | static void eepro100_acknowledge(EEPRO100State * s) | |
319 | { | |
320 | s->scb_stat &= ~s->mem[SCBAck]; | |
321 | s->mem[SCBAck] = s->scb_stat; | |
322 | if (s->scb_stat == 0) { | |
323 | disable_interrupt(s); | |
324 | } | |
325 | } | |
326 | ||
327 | static void eepro100_interrupt(EEPRO100State * s, uint8_t stat) | |
328 | { | |
329 | uint8_t mask = ~s->mem[SCBIntmask]; | |
330 | s->mem[SCBAck] |= stat; | |
331 | stat = s->scb_stat = s->mem[SCBAck]; | |
332 | stat &= (mask | 0x0f); | |
333 | //~ stat &= (~s->mem[SCBIntmask] | 0x0xf); | |
334 | if (stat && (mask & 0x01)) { | |
335 | /* SCB mask and SCB Bit M do not disable interrupt. */ | |
336 | enable_interrupt(s); | |
337 | } else if (s->int_stat) { | |
338 | disable_interrupt(s); | |
339 | } | |
340 | } | |
341 | ||
342 | static void eepro100_cx_interrupt(EEPRO100State * s) | |
343 | { | |
344 | /* CU completed action command. */ | |
345 | /* Transmit not ok (82557 only, not in emulation). */ | |
346 | eepro100_interrupt(s, 0x80); | |
347 | } | |
348 | ||
349 | static void eepro100_cna_interrupt(EEPRO100State * s) | |
350 | { | |
351 | /* CU left the active state. */ | |
352 | eepro100_interrupt(s, 0x20); | |
353 | } | |
354 | ||
355 | static void eepro100_fr_interrupt(EEPRO100State * s) | |
356 | { | |
357 | /* RU received a complete frame. */ | |
358 | eepro100_interrupt(s, 0x40); | |
359 | } | |
360 | ||
361 | #if 0 | |
362 | static void eepro100_rnr_interrupt(EEPRO100State * s) | |
363 | { | |
364 | /* RU is not ready. */ | |
365 | eepro100_interrupt(s, 0x10); | |
366 | } | |
367 | #endif | |
368 | ||
369 | static void eepro100_mdi_interrupt(EEPRO100State * s) | |
370 | { | |
371 | /* MDI completed read or write cycle. */ | |
372 | eepro100_interrupt(s, 0x08); | |
373 | } | |
374 | ||
375 | static void eepro100_swi_interrupt(EEPRO100State * s) | |
376 | { | |
377 | /* Software has requested an interrupt. */ | |
378 | eepro100_interrupt(s, 0x04); | |
379 | } | |
380 | ||
381 | #if 0 | |
382 | static void eepro100_fcp_interrupt(EEPRO100State * s) | |
383 | { | |
384 | /* Flow control pause interrupt (82558 and later). */ | |
385 | eepro100_interrupt(s, 0x01); | |
386 | } | |
387 | #endif | |
388 | ||
389 | static void pci_reset(EEPRO100State * s) | |
390 | { | |
391 | uint32_t device = s->device; | |
273a2142 | 392 | uint8_t *pci_conf = s->dev.config; |
663e8e51 | 393 | |
aac443e6 | 394 | TRACE(OTHER, logout("%p\n", s)); |
663e8e51 TS |
395 | |
396 | /* PCI Vendor ID */ | |
deb54399 | 397 | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
d6fd1e66 | 398 | /* PCI Device ID depends on device and is set below. */ |
663e8e51 TS |
399 | /* PCI Command */ |
400 | PCI_CONFIG_16(PCI_COMMAND, 0x0000); | |
401 | /* PCI Status */ | |
402 | PCI_CONFIG_16(PCI_STATUS, 0x2800); | |
403 | /* PCI Revision ID */ | |
404 | PCI_CONFIG_8(PCI_REVISION_ID, 0x08); | |
405 | /* PCI Class Code */ | |
406 | PCI_CONFIG_8(0x09, 0x00); | |
173a543b | 407 | pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); |
663e8e51 TS |
408 | /* PCI Cache Line Size */ |
409 | /* check cache line size!!! */ | |
410 | //~ PCI_CONFIG_8(0x0c, 0x00); | |
411 | /* PCI Latency Timer */ | |
412 | PCI_CONFIG_8(0x0d, 0x20); // latency timer = 32 clocks | |
413 | /* PCI Header Type */ | |
414 | /* BIST (built-in self test) */ | |
415 | #if defined(TARGET_I386) | |
416 | // !!! workaround for buggy bios | |
417 | //~ #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0 | |
418 | #endif | |
419 | #if 0 | |
420 | /* PCI Base Address Registers */ | |
421 | /* CSR Memory Mapped Base Address */ | |
422 | PCI_CONFIG_32(PCI_BASE_ADDRESS_0, | |
423 | PCI_ADDRESS_SPACE_MEM | PCI_ADDRESS_SPACE_MEM_PREFETCH); | |
424 | /* CSR I/O Mapped Base Address */ | |
425 | PCI_CONFIG_32(PCI_BASE_ADDRESS_1, PCI_ADDRESS_SPACE_IO); | |
426 | #if 0 | |
427 | /* Flash Memory Mapped Base Address */ | |
428 | PCI_CONFIG_32(PCI_BASE_ADDRESS_2, 0xfffe0000 | PCI_ADDRESS_SPACE_MEM); | |
429 | #endif | |
430 | #endif | |
431 | /* Expansion ROM Base Address (depends on boot disable!!!) */ | |
432 | PCI_CONFIG_32(0x30, 0x00000000); | |
433 | /* Capability Pointer */ | |
434 | PCI_CONFIG_8(0x34, 0xdc); | |
aac443e6 | 435 | /* Interrupt Line */ |
663e8e51 TS |
436 | /* Interrupt Pin */ |
437 | PCI_CONFIG_8(0x3d, 1); // interrupt pin 0 | |
438 | /* Minimum Grant */ | |
439 | PCI_CONFIG_8(0x3e, 0x08); | |
440 | /* Maximum Latency */ | |
441 | PCI_CONFIG_8(0x3f, 0x18); | |
442 | /* Power Management Capabilities / Next Item Pointer / Capability ID */ | |
443 | PCI_CONFIG_32(0xdc, 0x7e210001); | |
444 | ||
445 | switch (device) { | |
446 | case i82551: | |
d6fd1e66 | 447 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); |
663e8e51 TS |
448 | PCI_CONFIG_8(PCI_REVISION_ID, 0x0f); |
449 | break; | |
450 | case i82557B: | |
d6fd1e66 | 451 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
663e8e51 TS |
452 | PCI_CONFIG_8(PCI_REVISION_ID, 0x02); |
453 | break; | |
454 | case i82557C: | |
d6fd1e66 | 455 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
663e8e51 TS |
456 | PCI_CONFIG_8(PCI_REVISION_ID, 0x03); |
457 | break; | |
458 | case i82558B: | |
d6fd1e66 | 459 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
663e8e51 TS |
460 | PCI_CONFIG_16(PCI_STATUS, 0x2810); |
461 | PCI_CONFIG_8(PCI_REVISION_ID, 0x05); | |
462 | break; | |
463 | case i82559C: | |
d6fd1e66 | 464 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
663e8e51 TS |
465 | PCI_CONFIG_16(PCI_STATUS, 0x2810); |
466 | //~ PCI_CONFIG_8(PCI_REVISION_ID, 0x08); | |
467 | break; | |
468 | case i82559ER: | |
d6fd1e66 | 469 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); |
663e8e51 TS |
470 | PCI_CONFIG_16(PCI_STATUS, 0x2810); |
471 | PCI_CONFIG_8(PCI_REVISION_ID, 0x09); | |
472 | break; | |
473 | //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1029); | |
474 | //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1030); /* 82559 InBusiness 10/100 */ | |
475 | default: | |
476 | logout("Device %X is undefined!\n", device); | |
477 | } | |
478 | ||
479 | if (device == i82557C || device == i82558B || device == i82559C) { | |
480 | logout("Get device id and revision from EEPROM!!!\n"); | |
481 | } | |
482 | } | |
483 | ||
484 | static void nic_selective_reset(EEPRO100State * s) | |
485 | { | |
486 | size_t i; | |
487 | uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom); | |
488 | //~ eeprom93xx_reset(s->eeprom); | |
489 | memcpy(eeprom_contents, s->macaddr, 6); | |
490 | eeprom_contents[0xa] = 0x4000; | |
491 | uint16_t sum = 0; | |
492 | for (i = 0; i < EEPROM_SIZE - 1; i++) { | |
493 | sum += eeprom_contents[i]; | |
494 | } | |
495 | eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum; | |
aac443e6 | 496 | TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1])); |
663e8e51 TS |
497 | |
498 | memset(s->mem, 0, sizeof(s->mem)); | |
499 | uint32_t val = BIT(21); | |
500 | memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val)); | |
501 | ||
502 | assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default)); | |
503 | memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem)); | |
504 | } | |
505 | ||
506 | static void nic_reset(void *opaque) | |
507 | { | |
769cf7a5 | 508 | EEPRO100State *s = opaque; |
aac443e6 | 509 | TRACE(OTHER, logout("%p\n", s)); |
663e8e51 TS |
510 | nic_selective_reset(s); |
511 | } | |
512 | ||
513 | #if defined(DEBUG_EEPRO100) | |
6a0b9cc9 | 514 | static const char * const reg[PCI_IO_SIZE / 4] = { |
663e8e51 TS |
515 | "Command/Status", |
516 | "General Pointer", | |
517 | "Port", | |
518 | "EEPROM/Flash Control", | |
519 | "MDI Control", | |
520 | "Receive DMA Byte Count", | |
aac443e6 | 521 | "Flow control", |
663e8e51 TS |
522 | "General Status/Control" |
523 | }; | |
524 | ||
525 | static char *regname(uint32_t addr) | |
526 | { | |
527 | static char buf[16]; | |
528 | if (addr < PCI_IO_SIZE) { | |
529 | const char *r = reg[addr / 4]; | |
530 | if (r != 0) { | |
41cbc23c | 531 | snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4); |
663e8e51 | 532 | } else { |
41cbc23c | 533 | snprintf(buf, sizeof(buf), "0x%02x", addr); |
663e8e51 TS |
534 | } |
535 | } else { | |
41cbc23c | 536 | snprintf(buf, sizeof(buf), "??? 0x%08x", addr); |
663e8e51 TS |
537 | } |
538 | return buf; | |
539 | } | |
540 | #endif /* DEBUG_EEPRO100 */ | |
541 | ||
542 | #if 0 | |
543 | static uint16_t eepro100_read_status(EEPRO100State * s) | |
544 | { | |
545 | uint16_t val = s->status; | |
aac443e6 | 546 | TRACE(OTHER, logout("val=0x%04x\n", val)); |
663e8e51 TS |
547 | return val; |
548 | } | |
549 | ||
550 | static void eepro100_write_status(EEPRO100State * s, uint16_t val) | |
551 | { | |
aac443e6 | 552 | TRACE(OTHER, logout("val=0x%04x\n", val)); |
663e8e51 TS |
553 | s->status = val; |
554 | } | |
555 | #endif | |
556 | ||
557 | /***************************************************************************** | |
558 | * | |
559 | * Command emulation. | |
560 | * | |
561 | ****************************************************************************/ | |
562 | ||
563 | #if 0 | |
564 | static uint16_t eepro100_read_command(EEPRO100State * s) | |
565 | { | |
566 | uint16_t val = 0xffff; | |
aac443e6 | 567 | //~ TRACE(OTHER, logout("val=0x%04x\n", val)); |
663e8e51 TS |
568 | return val; |
569 | } | |
570 | #endif | |
571 | ||
0859df68 NS |
572 | static bool device_supports_eTxCB(EEPRO100State * s) |
573 | { | |
574 | return (s->device != i82557B && s->device != i82557C); | |
575 | } | |
576 | ||
663e8e51 TS |
577 | /* Commands that can be put in a command list entry. */ |
578 | enum commands { | |
579 | CmdNOp = 0, | |
580 | CmdIASetup = 1, | |
581 | CmdConfigure = 2, | |
582 | CmdMulticastList = 3, | |
583 | CmdTx = 4, | |
584 | CmdTDR = 5, /* load microcode */ | |
585 | CmdDump = 6, | |
586 | CmdDiagnose = 7, | |
587 | ||
588 | /* And some extra flags: */ | |
589 | CmdSuspend = 0x4000, /* Suspend after completion. */ | |
590 | CmdIntr = 0x2000, /* Interrupt after completion. */ | |
591 | CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */ | |
592 | }; | |
593 | ||
c227f099 | 594 | static cu_state_t get_cu_state(EEPRO100State * s) |
663e8e51 TS |
595 | { |
596 | return ((s->mem[SCBStatus] >> 6) & 0x03); | |
597 | } | |
598 | ||
c227f099 | 599 | static void set_cu_state(EEPRO100State * s, cu_state_t state) |
663e8e51 TS |
600 | { |
601 | s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6); | |
602 | } | |
603 | ||
c227f099 | 604 | static ru_state_t get_ru_state(EEPRO100State * s) |
663e8e51 TS |
605 | { |
606 | return ((s->mem[SCBStatus] >> 2) & 0x0f); | |
607 | } | |
608 | ||
c227f099 | 609 | static void set_ru_state(EEPRO100State * s, ru_state_t state) |
663e8e51 TS |
610 | { |
611 | s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2); | |
612 | } | |
613 | ||
614 | static void dump_statistics(EEPRO100State * s) | |
615 | { | |
616 | /* Dump statistical data. Most data is never changed by the emulation | |
617 | * and always 0, so we first just copy the whole block and then those | |
618 | * values which really matter. | |
619 | * Number of data should check configuration!!! | |
620 | */ | |
621 | cpu_physical_memory_write(s->statsaddr, (uint8_t *) & s->statistics, 64); | |
622 | stl_phys(s->statsaddr + 0, s->statistics.tx_good_frames); | |
623 | stl_phys(s->statsaddr + 36, s->statistics.rx_good_frames); | |
624 | stl_phys(s->statsaddr + 48, s->statistics.rx_resource_errors); | |
625 | stl_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors); | |
626 | //~ stw_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames); | |
627 | //~ stw_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames); | |
628 | //~ missing("CU dump statistical counters"); | |
629 | } | |
630 | ||
631 | static void eepro100_cu_command(EEPRO100State * s, uint8_t val) | |
632 | { | |
c227f099 | 633 | eepro100_tx_t tx; |
663e8e51 TS |
634 | uint32_t cb_address; |
635 | switch (val) { | |
636 | case CU_NOP: | |
637 | /* No operation. */ | |
638 | break; | |
639 | case CU_START: | |
640 | if (get_cu_state(s) != cu_idle) { | |
641 | /* Intel documentation says that CU must be idle for the CU | |
642 | * start command. Intel driver for Linux also starts the CU | |
643 | * from suspended state. */ | |
644 | logout("CU state is %u, should be %u\n", get_cu_state(s), cu_idle); | |
645 | //~ assert(!"wrong CU state"); | |
646 | } | |
647 | set_cu_state(s, cu_active); | |
648 | s->cu_offset = s->pointer; | |
649 | next_command: | |
650 | cb_address = s->cu_base + s->cu_offset; | |
651 | cpu_physical_memory_read(cb_address, (uint8_t *) & tx, sizeof(tx)); | |
652 | uint16_t status = le16_to_cpu(tx.status); | |
653 | uint16_t command = le16_to_cpu(tx.command); | |
654 | logout | |
655 | ("val=0x%02x (cu start), status=0x%04x, command=0x%04x, link=0x%08x\n", | |
656 | val, status, command, tx.link); | |
657 | bool bit_el = ((command & 0x8000) != 0); | |
658 | bool bit_s = ((command & 0x4000) != 0); | |
659 | bool bit_i = ((command & 0x2000) != 0); | |
660 | bool bit_nc = ((command & 0x0010) != 0); | |
661 | //~ bool bit_sf = ((command & 0x0008) != 0); | |
662 | uint16_t cmd = command & 0x0007; | |
663 | s->cu_offset = le32_to_cpu(tx.link); | |
664 | switch (cmd) { | |
665 | case CmdNOp: | |
666 | /* Do nothing. */ | |
667 | break; | |
668 | case CmdIASetup: | |
669 | cpu_physical_memory_read(cb_address + 8, &s->macaddr[0], 6); | |
aac443e6 | 670 | TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6))); |
663e8e51 TS |
671 | break; |
672 | case CmdConfigure: | |
673 | cpu_physical_memory_read(cb_address + 8, &s->configuration[0], | |
674 | sizeof(s->configuration)); | |
aac443e6 | 675 | TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16))); |
663e8e51 TS |
676 | break; |
677 | case CmdMulticastList: | |
678 | //~ missing("multicast list"); | |
679 | break; | |
680 | case CmdTx: | |
681 | (void)0; | |
682 | uint32_t tbd_array = le32_to_cpu(tx.tx_desc_addr); | |
683 | uint16_t tcb_bytes = (le16_to_cpu(tx.tcb_bytes) & 0x3fff); | |
aac443e6 | 684 | TRACE(RXTX, logout |
663e8e51 | 685 | ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n", |
aac443e6 | 686 | tbd_array, tcb_bytes, tx.tbd_count)); |
663e8e51 TS |
687 | assert(!bit_nc); |
688 | //~ assert(!bit_sf); | |
689 | assert(tcb_bytes <= 2600); | |
690 | /* Next assertion fails for local configuration. */ | |
691 | //~ assert((tcb_bytes > 0) || (tbd_array != 0xffffffff)); | |
692 | if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) { | |
693 | logout | |
694 | ("illegal values of TBD array address and TCB byte count!\n"); | |
695 | } | |
24e6f355 RD |
696 | // sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes |
697 | uint8_t buf[2600]; | |
663e8e51 TS |
698 | uint16_t size = 0; |
699 | uint32_t tbd_address = cb_address + 0x10; | |
700 | assert(tcb_bytes <= sizeof(buf)); | |
701 | while (size < tcb_bytes) { | |
702 | uint32_t tx_buffer_address = ldl_phys(tbd_address); | |
703 | uint16_t tx_buffer_size = lduw_phys(tbd_address + 4); | |
704 | //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); | |
705 | tbd_address += 8; | |
aac443e6 | 706 | TRACE(RXTX, logout |
663e8e51 | 707 | ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n", |
aac443e6 | 708 | tx_buffer_address, tx_buffer_size)); |
24e6f355 | 709 | tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); |
663e8e51 TS |
710 | cpu_physical_memory_read(tx_buffer_address, &buf[size], |
711 | tx_buffer_size); | |
712 | size += tx_buffer_size; | |
713 | } | |
714 | if (tbd_array == 0xffffffff) { | |
715 | /* Simplified mode. Was already handled by code above. */ | |
716 | } else { | |
717 | /* Flexible mode. */ | |
718 | uint8_t tbd_count = 0; | |
0859df68 | 719 | if (device_supports_eTxCB(s) && !(s->configuration[6] & BIT(4))) { |
3f9cb1c1 | 720 | /* Extended Flexible TCB. */ |
663e8e51 TS |
721 | assert(tcb_bytes == 0); |
722 | for (; tbd_count < 2; tbd_count++) { | |
723 | uint32_t tx_buffer_address = ldl_phys(tbd_address); | |
724 | uint16_t tx_buffer_size = lduw_phys(tbd_address + 4); | |
725 | uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); | |
726 | tbd_address += 8; | |
aac443e6 | 727 | TRACE(RXTX, logout |
3f9cb1c1 | 728 | ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n", |
aac443e6 | 729 | tx_buffer_address, tx_buffer_size)); |
24e6f355 | 730 | tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); |
663e8e51 TS |
731 | cpu_physical_memory_read(tx_buffer_address, &buf[size], |
732 | tx_buffer_size); | |
733 | size += tx_buffer_size; | |
734 | if (tx_buffer_el & 1) { | |
735 | break; | |
736 | } | |
737 | } | |
738 | } | |
739 | tbd_address = tbd_array; | |
740 | for (; tbd_count < tx.tbd_count; tbd_count++) { | |
741 | uint32_t tx_buffer_address = ldl_phys(tbd_address); | |
742 | uint16_t tx_buffer_size = lduw_phys(tbd_address + 4); | |
743 | uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); | |
744 | tbd_address += 8; | |
aac443e6 | 745 | TRACE(RXTX, logout |
663e8e51 | 746 | ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n", |
aac443e6 | 747 | tx_buffer_address, tx_buffer_size)); |
24e6f355 | 748 | tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); |
663e8e51 TS |
749 | cpu_physical_memory_read(tx_buffer_address, &buf[size], |
750 | tx_buffer_size); | |
751 | size += tx_buffer_size; | |
752 | if (tx_buffer_el & 1) { | |
753 | break; | |
754 | } | |
755 | } | |
756 | } | |
aac443e6 | 757 | TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size))); |
663e8e51 TS |
758 | qemu_send_packet(s->vc, buf, size); |
759 | s->statistics.tx_good_frames++; | |
760 | /* Transmit with bad status would raise an CX/TNO interrupt. | |
761 | * (82557 only). Emulation never has bad status. */ | |
762 | //~ eepro100_cx_interrupt(s); | |
763 | break; | |
764 | case CmdTDR: | |
aac443e6 | 765 | TRACE(OTHER, logout("load microcode\n")); |
663e8e51 TS |
766 | /* Starting with offset 8, the command contains |
767 | * 64 dwords microcode which we just ignore here. */ | |
768 | break; | |
769 | default: | |
770 | missing("undefined command"); | |
771 | } | |
772 | /* Write new status (success). */ | |
773 | stw_phys(cb_address, status | 0x8000 | 0x2000); | |
774 | if (bit_i) { | |
775 | /* CU completed action. */ | |
776 | eepro100_cx_interrupt(s); | |
777 | } | |
778 | if (bit_el) { | |
aac443e6 | 779 | /* CU becomes idle. Terminate command loop. */ |
663e8e51 TS |
780 | set_cu_state(s, cu_idle); |
781 | eepro100_cna_interrupt(s); | |
782 | } else if (bit_s) { | |
783 | /* CU becomes suspended. */ | |
784 | set_cu_state(s, cu_suspended); | |
785 | eepro100_cna_interrupt(s); | |
786 | } else { | |
787 | /* More entries in list. */ | |
aac443e6 | 788 | TRACE(OTHER, logout("CU list with at least one more entry\n")); |
663e8e51 TS |
789 | goto next_command; |
790 | } | |
aac443e6 | 791 | TRACE(OTHER, logout("CU list empty\n")); |
663e8e51 TS |
792 | /* List is empty. Now CU is idle or suspended. */ |
793 | break; | |
794 | case CU_RESUME: | |
795 | if (get_cu_state(s) != cu_suspended) { | |
796 | logout("bad CU resume from CU state %u\n", get_cu_state(s)); | |
797 | /* Workaround for bad Linux eepro100 driver which resumes | |
798 | * from idle state. */ | |
799 | //~ missing("cu resume"); | |
800 | set_cu_state(s, cu_suspended); | |
801 | } | |
802 | if (get_cu_state(s) == cu_suspended) { | |
aac443e6 | 803 | TRACE(OTHER, logout("CU resuming\n")); |
663e8e51 TS |
804 | set_cu_state(s, cu_active); |
805 | goto next_command; | |
806 | } | |
807 | break; | |
808 | case CU_STATSADDR: | |
809 | /* Load dump counters address. */ | |
810 | s->statsaddr = s->pointer; | |
aac443e6 | 811 | TRACE(OTHER, logout("val=0x%02x (status address)\n", val)); |
663e8e51 TS |
812 | break; |
813 | case CU_SHOWSTATS: | |
814 | /* Dump statistical counters. */ | |
aac443e6 | 815 | TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val)); |
663e8e51 TS |
816 | dump_statistics(s); |
817 | break; | |
818 | case CU_CMD_BASE: | |
819 | /* Load CU base. */ | |
aac443e6 | 820 | TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val)); |
663e8e51 TS |
821 | s->cu_base = s->pointer; |
822 | break; | |
823 | case CU_DUMPSTATS: | |
824 | /* Dump and reset statistical counters. */ | |
aac443e6 | 825 | TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val)); |
663e8e51 TS |
826 | dump_statistics(s); |
827 | memset(&s->statistics, 0, sizeof(s->statistics)); | |
828 | break; | |
829 | case CU_SRESUME: | |
830 | /* CU static resume. */ | |
831 | missing("CU static resume"); | |
832 | break; | |
833 | default: | |
834 | missing("Undefined CU command"); | |
835 | } | |
836 | } | |
837 | ||
838 | static void eepro100_ru_command(EEPRO100State * s, uint8_t val) | |
839 | { | |
840 | switch (val) { | |
841 | case RU_NOP: | |
842 | /* No operation. */ | |
843 | break; | |
844 | case RX_START: | |
845 | /* RU start. */ | |
846 | if (get_ru_state(s) != ru_idle) { | |
847 | logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle); | |
848 | //~ assert(!"wrong RU state"); | |
849 | } | |
850 | set_ru_state(s, ru_ready); | |
851 | s->ru_offset = s->pointer; | |
aac443e6 | 852 | TRACE(OTHER, logout("val=0x%02x (rx start)\n", val)); |
663e8e51 TS |
853 | break; |
854 | case RX_RESUME: | |
855 | /* Restart RU. */ | |
856 | if (get_ru_state(s) != ru_suspended) { | |
857 | logout("RU state is %u, should be %u\n", get_ru_state(s), | |
858 | ru_suspended); | |
859 | //~ assert(!"wrong RU state"); | |
860 | } | |
861 | set_ru_state(s, ru_ready); | |
862 | break; | |
863 | case RX_ADDR_LOAD: | |
864 | /* Load RU base. */ | |
aac443e6 | 865 | TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val)); |
663e8e51 TS |
866 | s->ru_base = s->pointer; |
867 | break; | |
868 | default: | |
869 | logout("val=0x%02x (undefined RU command)\n", val); | |
870 | missing("Undefined SU command"); | |
871 | } | |
872 | } | |
873 | ||
874 | static void eepro100_write_command(EEPRO100State * s, uint8_t val) | |
875 | { | |
876 | eepro100_ru_command(s, val & 0x0f); | |
877 | eepro100_cu_command(s, val & 0xf0); | |
878 | if ((val) == 0) { | |
aac443e6 | 879 | TRACE(OTHER, logout("val=0x%02x\n", val)); |
663e8e51 TS |
880 | } |
881 | /* Clear command byte after command was accepted. */ | |
882 | s->mem[SCBCmd] = 0; | |
883 | } | |
884 | ||
885 | /***************************************************************************** | |
886 | * | |
887 | * EEPROM emulation. | |
888 | * | |
889 | ****************************************************************************/ | |
890 | ||
891 | #define EEPROM_CS 0x02 | |
892 | #define EEPROM_SK 0x01 | |
893 | #define EEPROM_DI 0x04 | |
894 | #define EEPROM_DO 0x08 | |
895 | ||
896 | static uint16_t eepro100_read_eeprom(EEPRO100State * s) | |
897 | { | |
898 | uint16_t val; | |
899 | memcpy(&val, &s->mem[SCBeeprom], sizeof(val)); | |
900 | if (eeprom93xx_read(s->eeprom)) { | |
901 | val |= EEPROM_DO; | |
902 | } else { | |
903 | val &= ~EEPROM_DO; | |
904 | } | |
aac443e6 | 905 | TRACE(EEPROM, logout("val=0x%04x\n", val)); |
663e8e51 TS |
906 | return val; |
907 | } | |
908 | ||
c227f099 | 909 | static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val) |
663e8e51 | 910 | { |
aac443e6 | 911 | TRACE(EEPROM, logout("val=0x%02x\n", val)); |
663e8e51 TS |
912 | |
913 | /* mask unwriteable bits */ | |
914 | //~ val = SET_MASKED(val, 0x31, eeprom->value); | |
915 | ||
916 | int eecs = ((val & EEPROM_CS) != 0); | |
917 | int eesk = ((val & EEPROM_SK) != 0); | |
918 | int eedi = ((val & EEPROM_DI) != 0); | |
919 | eeprom93xx_write(eeprom, eecs, eesk, eedi); | |
920 | } | |
921 | ||
922 | static void eepro100_write_pointer(EEPRO100State * s, uint32_t val) | |
923 | { | |
924 | s->pointer = le32_to_cpu(val); | |
aac443e6 | 925 | TRACE(OTHER, logout("val=0x%08x\n", val)); |
663e8e51 TS |
926 | } |
927 | ||
928 | /***************************************************************************** | |
929 | * | |
930 | * MDI emulation. | |
931 | * | |
932 | ****************************************************************************/ | |
933 | ||
934 | #if defined(DEBUG_EEPRO100) | |
6a0b9cc9 | 935 | static const char * const mdi_op_name[] = { |
663e8e51 TS |
936 | "opcode 0", |
937 | "write", | |
938 | "read", | |
939 | "opcode 3" | |
940 | }; | |
941 | ||
6a0b9cc9 | 942 | static const char * const mdi_reg_name[] = { |
663e8e51 TS |
943 | "Control", |
944 | "Status", | |
945 | "PHY Identification (Word 1)", | |
946 | "PHY Identification (Word 2)", | |
947 | "Auto-Negotiation Advertisement", | |
948 | "Auto-Negotiation Link Partner Ability", | |
949 | "Auto-Negotiation Expansion" | |
950 | }; | |
aac443e6 SW |
951 | |
952 | static const char *reg2name(uint8_t reg) | |
953 | { | |
954 | static char buffer[10]; | |
955 | const char *p = buffer; | |
956 | if (reg < ARRAY_SIZE(mdi_reg_name)) { | |
957 | p = mdi_reg_name[reg]; | |
958 | } else { | |
959 | snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg); | |
960 | } | |
961 | return p; | |
962 | } | |
663e8e51 TS |
963 | #endif /* DEBUG_EEPRO100 */ |
964 | ||
965 | static uint32_t eepro100_read_mdi(EEPRO100State * s) | |
966 | { | |
967 | uint32_t val; | |
968 | memcpy(&val, &s->mem[0x10], sizeof(val)); | |
969 | ||
970 | #ifdef DEBUG_EEPRO100 | |
971 | uint8_t raiseint = (val & BIT(29)) >> 29; | |
972 | uint8_t opcode = (val & BITS(27, 26)) >> 26; | |
973 | uint8_t phy = (val & BITS(25, 21)) >> 21; | |
974 | uint8_t reg = (val & BITS(20, 16)) >> 16; | |
975 | uint16_t data = (val & BITS(15, 0)); | |
976 | #endif | |
977 | /* Emulation takes no time to finish MDI transaction. */ | |
978 | val |= BIT(28); | |
979 | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", | |
980 | val, raiseint, mdi_op_name[opcode], phy, | |
aac443e6 | 981 | reg2name(reg), data)); |
663e8e51 TS |
982 | return val; |
983 | } | |
984 | ||
663e8e51 TS |
985 | static void eepro100_write_mdi(EEPRO100State * s, uint32_t val) |
986 | { | |
987 | uint8_t raiseint = (val & BIT(29)) >> 29; | |
988 | uint8_t opcode = (val & BITS(27, 26)) >> 26; | |
989 | uint8_t phy = (val & BITS(25, 21)) >> 21; | |
990 | uint8_t reg = (val & BITS(20, 16)) >> 16; | |
991 | uint16_t data = (val & BITS(15, 0)); | |
aac443e6 SW |
992 | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", |
993 | val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data)); | |
663e8e51 TS |
994 | if (phy != 1) { |
995 | /* Unsupported PHY address. */ | |
996 | //~ logout("phy must be 1 but is %u\n", phy); | |
997 | data = 0; | |
998 | } else if (opcode != 1 && opcode != 2) { | |
999 | /* Unsupported opcode. */ | |
1000 | logout("opcode must be 1 or 2 but is %u\n", opcode); | |
1001 | data = 0; | |
1002 | } else if (reg > 6) { | |
1003 | /* Unsupported register. */ | |
1004 | logout("register must be 0...6 but is %u\n", reg); | |
1005 | data = 0; | |
1006 | } else { | |
1007 | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", | |
1008 | val, raiseint, mdi_op_name[opcode], phy, | |
aac443e6 | 1009 | reg2name(reg), data)); |
663e8e51 TS |
1010 | if (opcode == 1) { |
1011 | /* MDI write */ | |
1012 | switch (reg) { | |
1013 | case 0: /* Control Register */ | |
1014 | if (data & 0x8000) { | |
1015 | /* Reset status and control registers to default. */ | |
1016 | s->mdimem[0] = eepro100_mdi_default[0]; | |
1017 | s->mdimem[1] = eepro100_mdi_default[1]; | |
1018 | data = s->mdimem[reg]; | |
1019 | } else { | |
1020 | /* Restart Auto Configuration = Normal Operation */ | |
1021 | data &= ~0x0200; | |
1022 | } | |
1023 | break; | |
1024 | case 1: /* Status Register */ | |
1025 | missing("not writable"); | |
1026 | data = s->mdimem[reg]; | |
1027 | break; | |
1028 | case 2: /* PHY Identification Register (Word 1) */ | |
1029 | case 3: /* PHY Identification Register (Word 2) */ | |
1030 | missing("not implemented"); | |
1031 | break; | |
1032 | case 4: /* Auto-Negotiation Advertisement Register */ | |
1033 | case 5: /* Auto-Negotiation Link Partner Ability Register */ | |
1034 | break; | |
1035 | case 6: /* Auto-Negotiation Expansion Register */ | |
1036 | default: | |
1037 | missing("not implemented"); | |
1038 | } | |
1039 | s->mdimem[reg] = data; | |
1040 | } else if (opcode == 2) { | |
1041 | /* MDI read */ | |
1042 | switch (reg) { | |
1043 | case 0: /* Control Register */ | |
1044 | if (data & 0x8000) { | |
1045 | /* Reset status and control registers to default. */ | |
1046 | s->mdimem[0] = eepro100_mdi_default[0]; | |
1047 | s->mdimem[1] = eepro100_mdi_default[1]; | |
1048 | } | |
1049 | break; | |
1050 | case 1: /* Status Register */ | |
1051 | s->mdimem[reg] |= 0x0020; | |
1052 | break; | |
1053 | case 2: /* PHY Identification Register (Word 1) */ | |
1054 | case 3: /* PHY Identification Register (Word 2) */ | |
1055 | case 4: /* Auto-Negotiation Advertisement Register */ | |
1056 | break; | |
1057 | case 5: /* Auto-Negotiation Link Partner Ability Register */ | |
1058 | s->mdimem[reg] = 0x41fe; | |
1059 | break; | |
1060 | case 6: /* Auto-Negotiation Expansion Register */ | |
1061 | s->mdimem[reg] = 0x0001; | |
1062 | break; | |
1063 | } | |
1064 | data = s->mdimem[reg]; | |
1065 | } | |
1066 | /* Emulation takes no time to finish MDI transaction. | |
1067 | * Set MDI bit in SCB status register. */ | |
1068 | s->mem[SCBAck] |= 0x08; | |
1069 | val |= BIT(28); | |
1070 | if (raiseint) { | |
1071 | eepro100_mdi_interrupt(s); | |
1072 | } | |
1073 | } | |
1074 | val = (val & 0xffff0000) + data; | |
1075 | memcpy(&s->mem[0x10], &val, sizeof(val)); | |
1076 | } | |
1077 | ||
1078 | /***************************************************************************** | |
1079 | * | |
1080 | * Port emulation. | |
1081 | * | |
1082 | ****************************************************************************/ | |
1083 | ||
1084 | #define PORT_SOFTWARE_RESET 0 | |
1085 | #define PORT_SELFTEST 1 | |
1086 | #define PORT_SELECTIVE_RESET 2 | |
1087 | #define PORT_DUMP 3 | |
1088 | #define PORT_SELECTION_MASK 3 | |
1089 | ||
1090 | typedef struct { | |
1091 | uint32_t st_sign; /* Self Test Signature */ | |
1092 | uint32_t st_result; /* Self Test Results */ | |
c227f099 | 1093 | } eepro100_selftest_t; |
663e8e51 TS |
1094 | |
1095 | static uint32_t eepro100_read_port(EEPRO100State * s) | |
1096 | { | |
1097 | return 0; | |
1098 | } | |
1099 | ||
1100 | static void eepro100_write_port(EEPRO100State * s, uint32_t val) | |
1101 | { | |
1102 | val = le32_to_cpu(val); | |
1103 | uint32_t address = (val & ~PORT_SELECTION_MASK); | |
1104 | uint8_t selection = (val & PORT_SELECTION_MASK); | |
1105 | switch (selection) { | |
1106 | case PORT_SOFTWARE_RESET: | |
1107 | nic_reset(s); | |
1108 | break; | |
1109 | case PORT_SELFTEST: | |
aac443e6 | 1110 | TRACE(OTHER, logout("selftest address=0x%08x\n", address)); |
c227f099 | 1111 | eepro100_selftest_t data; |
663e8e51 TS |
1112 | cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data)); |
1113 | data.st_sign = 0xffffffff; | |
1114 | data.st_result = 0; | |
1115 | cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data)); | |
1116 | break; | |
1117 | case PORT_SELECTIVE_RESET: | |
aac443e6 | 1118 | TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address)); |
663e8e51 TS |
1119 | nic_selective_reset(s); |
1120 | break; | |
1121 | default: | |
1122 | logout("val=0x%08x\n", val); | |
1123 | missing("unknown port selection"); | |
1124 | } | |
1125 | } | |
1126 | ||
1127 | /***************************************************************************** | |
1128 | * | |
1129 | * General hardware emulation. | |
1130 | * | |
1131 | ****************************************************************************/ | |
1132 | ||
1133 | static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr) | |
1134 | { | |
1135 | uint8_t val; | |
1136 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1137 | memcpy(&val, &s->mem[addr], sizeof(val)); | |
1138 | } | |
1139 | ||
1140 | switch (addr) { | |
1141 | case SCBStatus: | |
1142 | //~ val = eepro100_read_status(s); | |
aac443e6 | 1143 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1144 | break; |
1145 | case SCBAck: | |
1146 | //~ val = eepro100_read_status(s); | |
aac443e6 | 1147 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1148 | break; |
1149 | case SCBCmd: | |
aac443e6 | 1150 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1151 | //~ val = eepro100_read_command(s); |
1152 | break; | |
1153 | case SCBIntmask: | |
aac443e6 | 1154 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1155 | break; |
1156 | case SCBPort + 3: | |
aac443e6 | 1157 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1158 | break; |
1159 | case SCBeeprom: | |
1160 | val = eepro100_read_eeprom(s); | |
1161 | break; | |
1162 | case 0x1b: /* PMDR (power management driver register) */ | |
1163 | val = 0; | |
aac443e6 | 1164 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1165 | break; |
1166 | case 0x1d: /* general status register */ | |
1167 | /* 100 Mbps full duplex, valid link */ | |
1168 | val = 0x07; | |
aac443e6 | 1169 | TRACE(OTHER, logout("addr=General Status val=%02x\n", val)); |
663e8e51 TS |
1170 | break; |
1171 | default: | |
1172 | logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1173 | missing("unknown byte read"); | |
1174 | } | |
1175 | return val; | |
1176 | } | |
1177 | ||
1178 | static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr) | |
1179 | { | |
1180 | uint16_t val; | |
1181 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1182 | memcpy(&val, &s->mem[addr], sizeof(val)); | |
1183 | } | |
1184 | ||
663e8e51 TS |
1185 | switch (addr) { |
1186 | case SCBStatus: | |
1187 | //~ val = eepro100_read_status(s); | |
aac443e6 | 1188 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 TS |
1189 | break; |
1190 | case SCBeeprom: | |
1191 | val = eepro100_read_eeprom(s); | |
aac443e6 | 1192 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 TS |
1193 | break; |
1194 | default: | |
1195 | logout("addr=%s val=0x%04x\n", regname(addr), val); | |
1196 | missing("unknown word read"); | |
1197 | } | |
1198 | return val; | |
1199 | } | |
1200 | ||
1201 | static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr) | |
1202 | { | |
1203 | uint32_t val; | |
1204 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1205 | memcpy(&val, &s->mem[addr], sizeof(val)); | |
1206 | } | |
1207 | ||
1208 | switch (addr) { | |
1209 | case SCBStatus: | |
1210 | //~ val = eepro100_read_status(s); | |
aac443e6 | 1211 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1212 | break; |
1213 | case SCBPointer: | |
1214 | //~ val = eepro100_read_pointer(s); | |
aac443e6 | 1215 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1216 | break; |
1217 | case SCBPort: | |
1218 | val = eepro100_read_port(s); | |
aac443e6 | 1219 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1220 | break; |
1221 | case SCBCtrlMDI: | |
1222 | val = eepro100_read_mdi(s); | |
1223 | break; | |
1224 | default: | |
1225 | logout("addr=%s val=0x%08x\n", regname(addr), val); | |
1226 | missing("unknown longword read"); | |
1227 | } | |
1228 | return val; | |
1229 | } | |
1230 | ||
1231 | static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val) | |
1232 | { | |
1233 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1234 | memcpy(&s->mem[addr], &val, sizeof(val)); | |
1235 | } | |
1236 | ||
aac443e6 | 1237 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1238 | |
1239 | switch (addr) { | |
1240 | case SCBStatus: | |
1241 | //~ eepro100_write_status(s, val); | |
1242 | break; | |
1243 | case SCBAck: | |
1244 | eepro100_acknowledge(s); | |
1245 | break; | |
1246 | case SCBCmd: | |
1247 | eepro100_write_command(s, val); | |
1248 | break; | |
1249 | case SCBIntmask: | |
1250 | if (val & BIT(1)) { | |
1251 | eepro100_swi_interrupt(s); | |
1252 | } | |
1253 | eepro100_interrupt(s, 0); | |
1254 | break; | |
1255 | case SCBPort + 3: | |
aac443e6 | 1256 | case SCBFlow: /* does not exist on 82557 */ |
3257d2b6 TS |
1257 | case SCBFlow + 1: |
1258 | case SCBFlow + 2: | |
1259 | case SCBFlow + 3: | |
aac443e6 | 1260 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1261 | break; |
1262 | case SCBeeprom: | |
1263 | eepro100_write_eeprom(s->eeprom, val); | |
1264 | break; | |
1265 | default: | |
1266 | logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1267 | missing("unknown byte write"); | |
1268 | } | |
1269 | } | |
1270 | ||
1271 | static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val) | |
1272 | { | |
1273 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1274 | memcpy(&s->mem[addr], &val, sizeof(val)); | |
1275 | } | |
1276 | ||
aac443e6 | 1277 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 TS |
1278 | |
1279 | switch (addr) { | |
1280 | case SCBStatus: | |
1281 | //~ eepro100_write_status(s, val); | |
1282 | eepro100_acknowledge(s); | |
1283 | break; | |
1284 | case SCBCmd: | |
1285 | eepro100_write_command(s, val); | |
1286 | eepro100_write1(s, SCBIntmask, val >> 8); | |
1287 | break; | |
1288 | case SCBeeprom: | |
1289 | eepro100_write_eeprom(s->eeprom, val); | |
1290 | break; | |
1291 | default: | |
1292 | logout("addr=%s val=0x%04x\n", regname(addr), val); | |
1293 | missing("unknown word write"); | |
1294 | } | |
1295 | } | |
1296 | ||
1297 | static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val) | |
1298 | { | |
1299 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1300 | memcpy(&s->mem[addr], &val, sizeof(val)); | |
1301 | } | |
1302 | ||
1303 | switch (addr) { | |
1304 | case SCBPointer: | |
1305 | eepro100_write_pointer(s, val); | |
1306 | break; | |
1307 | case SCBPort: | |
aac443e6 | 1308 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1309 | eepro100_write_port(s, val); |
1310 | break; | |
1311 | case SCBCtrlMDI: | |
1312 | eepro100_write_mdi(s, val); | |
1313 | break; | |
1314 | default: | |
1315 | logout("addr=%s val=0x%08x\n", regname(addr), val); | |
1316 | missing("unknown longword write"); | |
1317 | } | |
1318 | } | |
1319 | ||
aac443e6 SW |
1320 | /***************************************************************************** |
1321 | * | |
1322 | * Port mapped I/O. | |
1323 | * | |
1324 | ****************************************************************************/ | |
1325 | ||
663e8e51 TS |
1326 | static uint32_t ioport_read1(void *opaque, uint32_t addr) |
1327 | { | |
1328 | EEPRO100State *s = opaque; | |
1329 | //~ logout("addr=%s\n", regname(addr)); | |
1330 | return eepro100_read1(s, addr - s->region[1]); | |
1331 | } | |
1332 | ||
1333 | static uint32_t ioport_read2(void *opaque, uint32_t addr) | |
1334 | { | |
1335 | EEPRO100State *s = opaque; | |
1336 | return eepro100_read2(s, addr - s->region[1]); | |
1337 | } | |
1338 | ||
1339 | static uint32_t ioport_read4(void *opaque, uint32_t addr) | |
1340 | { | |
1341 | EEPRO100State *s = opaque; | |
1342 | return eepro100_read4(s, addr - s->region[1]); | |
1343 | } | |
1344 | ||
1345 | static void ioport_write1(void *opaque, uint32_t addr, uint32_t val) | |
1346 | { | |
1347 | EEPRO100State *s = opaque; | |
1348 | //~ logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1349 | eepro100_write1(s, addr - s->region[1], val); | |
1350 | } | |
1351 | ||
1352 | static void ioport_write2(void *opaque, uint32_t addr, uint32_t val) | |
1353 | { | |
1354 | EEPRO100State *s = opaque; | |
1355 | eepro100_write2(s, addr - s->region[1], val); | |
1356 | } | |
1357 | ||
1358 | static void ioport_write4(void *opaque, uint32_t addr, uint32_t val) | |
1359 | { | |
1360 | EEPRO100State *s = opaque; | |
1361 | eepro100_write4(s, addr - s->region[1], val); | |
1362 | } | |
1363 | ||
1364 | /***********************************************************/ | |
1365 | /* PCI EEPRO100 definitions */ | |
1366 | ||
663e8e51 TS |
1367 | static void pci_map(PCIDevice * pci_dev, int region_num, |
1368 | uint32_t addr, uint32_t size, int type) | |
1369 | { | |
273a2142 | 1370 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
663e8e51 | 1371 | |
aac443e6 SW |
1372 | TRACE(OTHER, logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n", |
1373 | region_num, addr, size, type)); | |
663e8e51 TS |
1374 | |
1375 | assert(region_num == 1); | |
1376 | register_ioport_write(addr, size, 1, ioport_write1, s); | |
1377 | register_ioport_read(addr, size, 1, ioport_read1, s); | |
1378 | register_ioport_write(addr, size, 2, ioport_write2, s); | |
1379 | register_ioport_read(addr, size, 2, ioport_read2, s); | |
1380 | register_ioport_write(addr, size, 4, ioport_write4, s); | |
1381 | register_ioport_read(addr, size, 4, ioport_read4, s); | |
1382 | ||
1383 | s->region[region_num] = addr; | |
1384 | } | |
1385 | ||
aac443e6 SW |
1386 | /***************************************************************************** |
1387 | * | |
1388 | * Memory mapped I/O. | |
1389 | * | |
1390 | ****************************************************************************/ | |
1391 | ||
c227f099 | 1392 | static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
663e8e51 TS |
1393 | { |
1394 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1395 | //~ logout("addr=%s val=0x%02x\n", regname(addr), val); |
1396 | eepro100_write1(s, addr, val); | |
1397 | } | |
1398 | ||
c227f099 | 1399 | static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
663e8e51 TS |
1400 | { |
1401 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1402 | //~ logout("addr=%s val=0x%02x\n", regname(addr), val); |
1403 | eepro100_write2(s, addr, val); | |
1404 | } | |
1405 | ||
c227f099 | 1406 | static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
663e8e51 TS |
1407 | { |
1408 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1409 | //~ logout("addr=%s val=0x%02x\n", regname(addr), val); |
1410 | eepro100_write4(s, addr, val); | |
1411 | } | |
1412 | ||
c227f099 | 1413 | static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr) |
663e8e51 TS |
1414 | { |
1415 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1416 | //~ logout("addr=%s\n", regname(addr)); |
1417 | return eepro100_read1(s, addr); | |
1418 | } | |
1419 | ||
c227f099 | 1420 | static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr) |
663e8e51 TS |
1421 | { |
1422 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1423 | //~ logout("addr=%s\n", regname(addr)); |
1424 | return eepro100_read2(s, addr); | |
1425 | } | |
1426 | ||
c227f099 | 1427 | static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr) |
663e8e51 TS |
1428 | { |
1429 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1430 | //~ logout("addr=%s\n", regname(addr)); |
1431 | return eepro100_read4(s, addr); | |
1432 | } | |
1433 | ||
d60efc6b | 1434 | static CPUWriteMemoryFunc * const pci_mmio_write[] = { |
663e8e51 TS |
1435 | pci_mmio_writeb, |
1436 | pci_mmio_writew, | |
1437 | pci_mmio_writel | |
1438 | }; | |
1439 | ||
d60efc6b | 1440 | static CPUReadMemoryFunc * const pci_mmio_read[] = { |
663e8e51 TS |
1441 | pci_mmio_readb, |
1442 | pci_mmio_readw, | |
1443 | pci_mmio_readl | |
1444 | }; | |
1445 | ||
1446 | static void pci_mmio_map(PCIDevice * pci_dev, int region_num, | |
1447 | uint32_t addr, uint32_t size, int type) | |
1448 | { | |
273a2142 | 1449 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
663e8e51 | 1450 | |
aac443e6 SW |
1451 | TRACE(OTHER, logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n", |
1452 | region_num, addr, size, type)); | |
663e8e51 TS |
1453 | |
1454 | if (region_num == 0) { | |
1455 | /* Map control / status registers. */ | |
273a2142 JQ |
1456 | cpu_register_physical_memory(addr, size, s->mmio_index); |
1457 | s->region[region_num] = addr; | |
663e8e51 TS |
1458 | } |
1459 | } | |
1460 | ||
e3f5ec2b | 1461 | static int nic_can_receive(VLANClientState *vc) |
663e8e51 | 1462 | { |
e3f5ec2b | 1463 | EEPRO100State *s = vc->opaque; |
aac443e6 | 1464 | TRACE(RXTX, logout("%p\n", s)); |
663e8e51 TS |
1465 | return get_ru_state(s) == ru_ready; |
1466 | //~ return !eepro100_buffer_full(s); | |
1467 | } | |
1468 | ||
4f1c942b | 1469 | static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size) |
663e8e51 TS |
1470 | { |
1471 | /* TODO: | |
1472 | * - Magic packets should set bit 30 in power management driver register. | |
1473 | * - Interesting packets should set bit 29 in power management driver register. | |
1474 | */ | |
e3f5ec2b | 1475 | EEPRO100State *s = vc->opaque; |
663e8e51 TS |
1476 | uint16_t rfd_status = 0xa000; |
1477 | static const uint8_t broadcast_macaddr[6] = | |
1478 | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; | |
1479 | ||
1480 | /* TODO: check multiple IA bit. */ | |
1481 | assert(!(s->configuration[20] & BIT(6))); | |
1482 | ||
1483 | if (s->configuration[8] & 0x80) { | |
1484 | /* CSMA is disabled. */ | |
1485 | logout("%p received while CSMA is disabled\n", s); | |
4f1c942b | 1486 | return -1; |
663e8e51 TS |
1487 | } else if (size < 64 && (s->configuration[7] & 1)) { |
1488 | /* Short frame and configuration byte 7/0 (discard short receive) set: | |
1489 | * Short frame is discarded */ | |
067d01de | 1490 | logout("%p received short frame (%zu byte)\n", s, size); |
663e8e51 | 1491 | s->statistics.rx_short_frame_errors++; |
4f1c942b | 1492 | //~ return -1; |
663e8e51 TS |
1493 | } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & 8)) { |
1494 | /* Long frame and configuration byte 18/3 (long receive ok) not set: | |
1495 | * Long frames are discarded. */ | |
067d01de | 1496 | logout("%p received long frame (%zu byte), ignored\n", s, size); |
4f1c942b | 1497 | return -1; |
663e8e51 TS |
1498 | } else if (memcmp(buf, s->macaddr, 6) == 0) { // !!! |
1499 | /* Frame matches individual address. */ | |
1500 | /* TODO: check configuration byte 15/4 (ignore U/L). */ | |
067d01de | 1501 | TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size)); |
663e8e51 TS |
1502 | } else if (memcmp(buf, broadcast_macaddr, 6) == 0) { |
1503 | /* Broadcast frame. */ | |
067d01de | 1504 | TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size)); |
663e8e51 TS |
1505 | rfd_status |= 0x0002; |
1506 | } else if (buf[0] & 0x01) { // !!! | |
1507 | /* Multicast frame. */ | |
067d01de | 1508 | TRACE(RXTX, logout("%p received multicast, len=%zu\n", s, size)); |
663e8e51 TS |
1509 | /* TODO: check multicast all bit. */ |
1510 | assert(!(s->configuration[21] & BIT(3))); | |
1511 | int mcast_idx = compute_mcast_idx(buf); | |
1512 | if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) { | |
4f1c942b | 1513 | return size; |
663e8e51 TS |
1514 | } |
1515 | rfd_status |= 0x0002; | |
1516 | } else if (s->configuration[15] & 1) { | |
1517 | /* Promiscuous: receive all. */ | |
067d01de | 1518 | TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size)); |
663e8e51 TS |
1519 | rfd_status |= 0x0004; |
1520 | } else { | |
067d01de | 1521 | TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size, |
aac443e6 | 1522 | nic_dump(buf, size))); |
4f1c942b | 1523 | return size; |
663e8e51 TS |
1524 | } |
1525 | ||
1526 | if (get_ru_state(s) != ru_ready) { | |
aac443e6 SW |
1527 | /* No resources available. */ |
1528 | logout("no resources, state=%u\n", get_ru_state(s)); | |
663e8e51 | 1529 | s->statistics.rx_resource_errors++; |
aac443e6 | 1530 | //~ assert(!"no resources"); |
4f1c942b | 1531 | return -1; |
663e8e51 TS |
1532 | } |
1533 | //~ !!! | |
1534 | //~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}} | |
c227f099 | 1535 | eepro100_rx_t rx; |
663e8e51 | 1536 | cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx, |
c227f099 | 1537 | offsetof(eepro100_rx_t, packet)); |
663e8e51 TS |
1538 | uint16_t rfd_command = le16_to_cpu(rx.command); |
1539 | uint16_t rfd_size = le16_to_cpu(rx.size); | |
1540 | assert(size <= rfd_size); | |
1541 | if (size < 64) { | |
1542 | rfd_status |= 0x0080; | |
1543 | } | |
aac443e6 SW |
1544 | TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n", |
1545 | rfd_command, rx.link, rx.rx_buf_addr, rfd_size)); | |
c227f099 | 1546 | stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status), |
663e8e51 | 1547 | rfd_status); |
c227f099 | 1548 | stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size); |
663e8e51 TS |
1549 | /* Early receive interrupt not supported. */ |
1550 | //~ eepro100_er_interrupt(s); | |
1551 | /* Receive CRC Transfer not supported. */ | |
1552 | assert(!(s->configuration[18] & 4)); | |
1553 | /* TODO: check stripping enable bit. */ | |
1554 | //~ assert(!(s->configuration[17] & 1)); | |
1555 | cpu_physical_memory_write(s->ru_base + s->ru_offset + | |
c227f099 | 1556 | offsetof(eepro100_rx_t, packet), buf, size); |
663e8e51 TS |
1557 | s->statistics.rx_good_frames++; |
1558 | eepro100_fr_interrupt(s); | |
1559 | s->ru_offset = le32_to_cpu(rx.link); | |
1560 | if (rfd_command & 0x8000) { | |
1561 | /* EL bit is set, so this was the last frame. */ | |
1562 | assert(0); | |
1563 | } | |
1564 | if (rfd_command & 0x4000) { | |
1565 | /* S bit is set. */ | |
1566 | set_ru_state(s, ru_suspended); | |
1567 | } | |
4f1c942b | 1568 | return size; |
663e8e51 TS |
1569 | } |
1570 | ||
1571 | static int nic_load(QEMUFile * f, void *opaque, int version_id) | |
1572 | { | |
769cf7a5 | 1573 | EEPRO100State *s = opaque; |
2657c663 | 1574 | int i; |
663e8e51 TS |
1575 | int ret; |
1576 | ||
3031efab | 1577 | if (version_id != eepro100_version) { |
663e8e51 | 1578 | return -EINVAL; |
663e8e51 TS |
1579 | } |
1580 | ||
3031efab SW |
1581 | ret = pci_device_load(&s->dev, f); |
1582 | if (ret < 0) { | |
1583 | return ret; | |
663e8e51 TS |
1584 | } |
1585 | ||
1586 | qemu_get_8s(f, &s->cmd); | |
1587 | qemu_get_be32s(f, &s->start); | |
1588 | qemu_get_be32s(f, &s->stop); | |
663e8e51 TS |
1589 | qemu_get_buffer(f, s->mult, 8); |
1590 | qemu_get_buffer(f, s->mem, sizeof(s->mem)); | |
1591 | ||
aac443e6 | 1592 | /* Restore all members of struct between scv_stat and mem. */ |
2657c663 AZ |
1593 | qemu_get_8s(f, &s->scb_stat); |
1594 | qemu_get_8s(f, &s->int_stat); | |
3031efab | 1595 | for (i = 0; i < ARRAY_SIZE(s->region); i++) { |
2657c663 | 1596 | qemu_get_be32s(f, &s->region[i]); |
aac443e6 | 1597 | } |
2657c663 | 1598 | qemu_get_buffer(f, s->macaddr, 6); |
3031efab | 1599 | for (i = 0; i < ARRAY_SIZE(s->mdimem); i++) { |
2657c663 | 1600 | qemu_get_be16s(f, &s->mdimem[i]); |
aac443e6 SW |
1601 | } |
1602 | /* The eeprom should be saved and restored by its own routines. */ | |
2657c663 AZ |
1603 | qemu_get_be32s(f, &s->device); |
1604 | qemu_get_be32s(f, &s->pointer); | |
1605 | qemu_get_be32s(f, &s->cu_base); | |
1606 | qemu_get_be32s(f, &s->cu_offset); | |
1607 | qemu_get_be32s(f, &s->ru_base); | |
1608 | qemu_get_be32s(f, &s->ru_offset); | |
1609 | qemu_get_be32s(f, &s->statsaddr); | |
aac443e6 | 1610 | /* Restore epro100_stats_t statistics. */ |
2657c663 AZ |
1611 | qemu_get_be32s(f, &s->statistics.tx_good_frames); |
1612 | qemu_get_be32s(f, &s->statistics.tx_max_collisions); | |
1613 | qemu_get_be32s(f, &s->statistics.tx_late_collisions); | |
1614 | qemu_get_be32s(f, &s->statistics.tx_underruns); | |
1615 | qemu_get_be32s(f, &s->statistics.tx_lost_crs); | |
1616 | qemu_get_be32s(f, &s->statistics.tx_deferred); | |
1617 | qemu_get_be32s(f, &s->statistics.tx_single_collisions); | |
1618 | qemu_get_be32s(f, &s->statistics.tx_multiple_collisions); | |
1619 | qemu_get_be32s(f, &s->statistics.tx_total_collisions); | |
1620 | qemu_get_be32s(f, &s->statistics.rx_good_frames); | |
1621 | qemu_get_be32s(f, &s->statistics.rx_crc_errors); | |
1622 | qemu_get_be32s(f, &s->statistics.rx_alignment_errors); | |
1623 | qemu_get_be32s(f, &s->statistics.rx_resource_errors); | |
1624 | qemu_get_be32s(f, &s->statistics.rx_overrun_errors); | |
1625 | qemu_get_be32s(f, &s->statistics.rx_cdt_errors); | |
1626 | qemu_get_be32s(f, &s->statistics.rx_short_frame_errors); | |
1627 | qemu_get_be32s(f, &s->statistics.fc_xmt_pause); | |
1628 | qemu_get_be32s(f, &s->statistics.fc_rcv_pause); | |
1629 | qemu_get_be32s(f, &s->statistics.fc_rcv_unsupported); | |
1630 | qemu_get_be16s(f, &s->statistics.xmt_tco_frames); | |
1631 | qemu_get_be16s(f, &s->statistics.rcv_tco_frames); | |
1632 | qemu_get_be32s(f, &s->statistics.complete); | |
1633 | #if 0 | |
1634 | qemu_get_be16s(f, &s->status); | |
1635 | #endif | |
1636 | ||
1637 | /* Configuration bytes. */ | |
1638 | qemu_get_buffer(f, s->configuration, sizeof(s->configuration)); | |
1639 | ||
663e8e51 TS |
1640 | return 0; |
1641 | } | |
1642 | ||
1643 | static void nic_save(QEMUFile * f, void *opaque) | |
1644 | { | |
769cf7a5 | 1645 | EEPRO100State *s = opaque; |
2657c663 | 1646 | int i; |
663e8e51 | 1647 | |
273a2142 | 1648 | pci_device_save(&s->dev, f); |
663e8e51 | 1649 | |
663e8e51 TS |
1650 | qemu_put_8s(f, &s->cmd); |
1651 | qemu_put_be32s(f, &s->start); | |
1652 | qemu_put_be32s(f, &s->stop); | |
663e8e51 TS |
1653 | qemu_put_buffer(f, s->mult, 8); |
1654 | qemu_put_buffer(f, s->mem, sizeof(s->mem)); | |
2657c663 | 1655 | |
aac443e6 | 1656 | /* Save all members of struct between scv_stat and mem. */ |
2657c663 AZ |
1657 | qemu_put_8s(f, &s->scb_stat); |
1658 | qemu_put_8s(f, &s->int_stat); | |
3031efab | 1659 | for (i = 0; i < ARRAY_SIZE(s->region); i++) { |
2657c663 | 1660 | qemu_put_be32s(f, &s->region[i]); |
aac443e6 | 1661 | } |
2657c663 | 1662 | qemu_put_buffer(f, s->macaddr, 6); |
3031efab | 1663 | for (i = 0; i < ARRAY_SIZE(s->mdimem); i++) { |
2657c663 | 1664 | qemu_put_be16s(f, &s->mdimem[i]); |
aac443e6 SW |
1665 | } |
1666 | /* The eeprom should be saved and restored by its own routines. */ | |
2657c663 AZ |
1667 | qemu_put_be32s(f, &s->device); |
1668 | qemu_put_be32s(f, &s->pointer); | |
1669 | qemu_put_be32s(f, &s->cu_base); | |
1670 | qemu_put_be32s(f, &s->cu_offset); | |
1671 | qemu_put_be32s(f, &s->ru_base); | |
1672 | qemu_put_be32s(f, &s->ru_offset); | |
1673 | qemu_put_be32s(f, &s->statsaddr); | |
aac443e6 | 1674 | /* Save epro100_stats_t statistics. */ |
2657c663 AZ |
1675 | qemu_put_be32s(f, &s->statistics.tx_good_frames); |
1676 | qemu_put_be32s(f, &s->statistics.tx_max_collisions); | |
1677 | qemu_put_be32s(f, &s->statistics.tx_late_collisions); | |
1678 | qemu_put_be32s(f, &s->statistics.tx_underruns); | |
1679 | qemu_put_be32s(f, &s->statistics.tx_lost_crs); | |
1680 | qemu_put_be32s(f, &s->statistics.tx_deferred); | |
1681 | qemu_put_be32s(f, &s->statistics.tx_single_collisions); | |
1682 | qemu_put_be32s(f, &s->statistics.tx_multiple_collisions); | |
1683 | qemu_put_be32s(f, &s->statistics.tx_total_collisions); | |
1684 | qemu_put_be32s(f, &s->statistics.rx_good_frames); | |
1685 | qemu_put_be32s(f, &s->statistics.rx_crc_errors); | |
1686 | qemu_put_be32s(f, &s->statistics.rx_alignment_errors); | |
1687 | qemu_put_be32s(f, &s->statistics.rx_resource_errors); | |
1688 | qemu_put_be32s(f, &s->statistics.rx_overrun_errors); | |
1689 | qemu_put_be32s(f, &s->statistics.rx_cdt_errors); | |
1690 | qemu_put_be32s(f, &s->statistics.rx_short_frame_errors); | |
1691 | qemu_put_be32s(f, &s->statistics.fc_xmt_pause); | |
1692 | qemu_put_be32s(f, &s->statistics.fc_rcv_pause); | |
1693 | qemu_put_be32s(f, &s->statistics.fc_rcv_unsupported); | |
1694 | qemu_put_be16s(f, &s->statistics.xmt_tco_frames); | |
1695 | qemu_put_be16s(f, &s->statistics.rcv_tco_frames); | |
1696 | qemu_put_be32s(f, &s->statistics.complete); | |
1697 | #if 0 | |
1698 | qemu_put_be16s(f, &s->status); | |
1699 | #endif | |
1700 | ||
1701 | /* Configuration bytes. */ | |
1702 | qemu_put_buffer(f, s->configuration, sizeof(s->configuration)); | |
663e8e51 TS |
1703 | } |
1704 | ||
b946a153 AL |
1705 | static void nic_cleanup(VLANClientState *vc) |
1706 | { | |
1707 | EEPRO100State *s = vc->opaque; | |
1708 | ||
1709 | unregister_savevm(vc->model, s); | |
1710 | ||
1711 | eeprom93xx_free(s->eeprom); | |
1712 | } | |
1713 | ||
1714 | static int pci_nic_uninit(PCIDevice *dev) | |
1715 | { | |
273a2142 | 1716 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, dev); |
b946a153 AL |
1717 | |
1718 | cpu_unregister_io_memory(s->mmio_index); | |
1719 | ||
1720 | return 0; | |
1721 | } | |
1722 | ||
81a322d4 | 1723 | static int nic_init(PCIDevice *pci_dev, uint32_t device) |
663e8e51 | 1724 | { |
273a2142 | 1725 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
663e8e51 | 1726 | |
aac443e6 | 1727 | TRACE(OTHER, logout("\n")); |
663e8e51 | 1728 | |
273a2142 | 1729 | s->dev.unregister = pci_nic_uninit; |
663e8e51 | 1730 | |
663e8e51 | 1731 | s->device = device; |
663e8e51 TS |
1732 | |
1733 | pci_reset(s); | |
1734 | ||
1735 | /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM, | |
1736 | * i82559 and later support 64 or 256 word EEPROM. */ | |
1737 | s->eeprom = eeprom93xx_new(EEPROM_SIZE); | |
1738 | ||
1739 | /* Handler for memory-mapped I/O */ | |
273a2142 | 1740 | s->mmio_index = |
1eed09cb | 1741 | cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s); |
663e8e51 | 1742 | |
273a2142 | 1743 | pci_register_bar(&s->dev, 0, PCI_MEM_SIZE, |
663e8e51 TS |
1744 | PCI_ADDRESS_SPACE_MEM | |
1745 | PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_mmio_map); | |
273a2142 | 1746 | pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_ADDRESS_SPACE_IO, |
663e8e51 | 1747 | pci_map); |
273a2142 | 1748 | pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_ADDRESS_SPACE_MEM, |
663e8e51 TS |
1749 | pci_mmio_map); |
1750 | ||
273a2142 | 1751 | qdev_get_macaddr(&s->dev.qdev, s->macaddr); |
663e8e51 TS |
1752 | logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6)); |
1753 | assert(s->region[1] == 0); | |
1754 | ||
1755 | nic_reset(s); | |
1756 | ||
273a2142 | 1757 | s->vc = qdev_get_vlan_client(&s->dev.qdev, |
463af534 | 1758 | nic_can_receive, nic_receive, NULL, |
b946a153 | 1759 | nic_cleanup, s); |
663e8e51 | 1760 | |
7cb7434b | 1761 | qemu_format_nic_info_str(s->vc, s->macaddr); |
aac443e6 | 1762 | TRACE(OTHER, logout("%s\n", s->vc->info_str)); |
663e8e51 | 1763 | |
a08d4367 | 1764 | qemu_register_reset(nic_reset, s); |
663e8e51 | 1765 | |
3031efab SW |
1766 | register_savevm(s->vc->model, eepro100_instance, eepro100_version, |
1767 | nic_save, nic_load, s); | |
81a322d4 | 1768 | return 0; |
663e8e51 TS |
1769 | } |
1770 | ||
81a322d4 | 1771 | static int pci_i82551_init(PCIDevice *dev) |
9d07d757 | 1772 | { |
81a322d4 | 1773 | return nic_init(dev, i82551); |
9d07d757 PB |
1774 | } |
1775 | ||
81a322d4 | 1776 | static int pci_i82557b_init(PCIDevice *dev) |
663e8e51 | 1777 | { |
81a322d4 | 1778 | return nic_init(dev, i82557B); |
663e8e51 TS |
1779 | } |
1780 | ||
81a322d4 | 1781 | static int pci_i82559er_init(PCIDevice *dev) |
663e8e51 | 1782 | { |
81a322d4 | 1783 | return nic_init(dev, i82559ER); |
663e8e51 TS |
1784 | } |
1785 | ||
0aab0d3a GH |
1786 | static PCIDeviceInfo eepro100_info[] = { |
1787 | { | |
1788 | .qdev.name = "i82551", | |
273a2142 | 1789 | .qdev.size = sizeof(EEPRO100State), |
0aab0d3a GH |
1790 | .init = pci_i82551_init, |
1791 | },{ | |
1792 | .qdev.name = "i82557b", | |
273a2142 | 1793 | .qdev.size = sizeof(EEPRO100State), |
0aab0d3a GH |
1794 | .init = pci_i82557b_init, |
1795 | },{ | |
1796 | .qdev.name = "i82559er", | |
273a2142 | 1797 | .qdev.size = sizeof(EEPRO100State), |
0aab0d3a GH |
1798 | .init = pci_i82559er_init, |
1799 | },{ | |
1800 | /* end of list */ | |
1801 | } | |
1802 | }; | |
1803 | ||
9d07d757 | 1804 | static void eepro100_register_devices(void) |
663e8e51 | 1805 | { |
0aab0d3a | 1806 | pci_qdev_register_many(eepro100_info); |
663e8e51 TS |
1807 | } |
1808 | ||
9d07d757 | 1809 | device_init(eepro100_register_devices) |