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663e8e51
TS		 1/*
2 * QEMU i8255x (PRO100) emulation
3 *
4 * Copyright (c) 2006-2007 Stefan Weil
5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
8167ee88 20 * along with this program; if not, see <http://www.gnu.org/licenses/>.
663e8e51
TS		 21 *
22 * Tested features (i82559):
23 * PXE boot (i386) no valid link
24 * Linux networking (i386) ok
25 *
26 * Untested:
27 * non-i386 platforms
28 * Windows networking
29 *
30 * References:
31 *
32 * Intel 8255x 10/100 Mbps Ethernet Controller Family
33 * Open Source Software Developer Manual
34 */
35
36#if defined(TARGET_I386)
37# warning "PXE boot still not working!"
38#endif
39
663e8e51 40#include <stddef.h> /* offsetof */
b84a5c6f 41#include <stdbool.h>
87ecb68b
PB		 42#include "hw.h"
43#include "pci.h"
44#include "net.h"
663e8e51
TS		 45#include "eeprom93xx.h"
46
47/* Common declarations for all PCI devices. */
48
663e8e51
TS		 49#define PCI_CONFIG_8(offset, value) \
50 (pci_conf[offset] = (value))
51#define PCI_CONFIG_16(offset, value) \
52 (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value))
53#define PCI_CONFIG_32(offset, value) \
54 (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value))
55
56#define KiB 1024
57
aac443e6 58/* Debug EEPRO100 card. */
663e8e51
TS		 59//~ #define DEBUG_EEPRO100
60
61#ifdef DEBUG_EEPRO100
001faf32 62#define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
663e8e51 63#else
001faf32 64#define logout(fmt, ...) ((void)0)
663e8e51
TS		 65#endif
66
67/* Set flags to 0 to disable debug output. */
aac443e6
SW		 68#define INT 1 /* interrupt related actions */
69#define MDI 1 /* mdi related actions */
70#define OTHER 1
71#define RXTX 1
72#define EEPROM 1 /* eeprom related actions */
663e8e51
TS		 73
74#define TRACE(flag, command) ((flag) ? (command) : (void)0)
75
7f1e9d4e 76#define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
663e8e51
TS		 77
78#define MAX_ETH_FRAME_SIZE 1514
79
80/* This driver supports several different devices which are declared here. */
c4c270e2 81#define i82550 0x82550
663e8e51 82#define i82551 0x82551
c4c270e2 83#define i82557A 0x82557a
663e8e51
TS		 84#define i82557B 0x82557b
85#define i82557C 0x82557c
c4c270e2 86#define i82558A 0x82558a
663e8e51 87#define i82558B 0x82558b
c4c270e2
SW		 88#define i82559A 0x82559a
89#define i82559B 0x82559b
663e8e51
TS		 90#define i82559C 0x82559c
91#define i82559ER 0x82559e
92#define i82562 0x82562
93
aac443e6 94/* Use 64 word EEPROM. TODO: could be a runtime option. */
663e8e51
TS		 95#define EEPROM_SIZE 64
96
97#define PCI_MEM_SIZE (4 * KiB)
98#define PCI_IO_SIZE 64
99#define PCI_FLASH_SIZE (128 * KiB)
100
101#define BIT(n) (1 << (n))
102#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
103
104/* The SCB accepts the following controls for the Tx and Rx units: */
105#define CU_NOP 0x0000 /* No operation. */
106#define CU_START 0x0010 /* CU start. */
107#define CU_RESUME 0x0020 /* CU resume. */
108#define CU_STATSADDR 0x0040 /* Load dump counters address. */
109#define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
110#define CU_CMD_BASE 0x0060 /* Load CU base address. */
111#define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
112#define CU_SRESUME 0x00a0 /* CU static resume. */
113
114#define RU_NOP 0x0000
115#define RX_START 0x0001
116#define RX_RESUME 0x0002
117#define RX_ABORT 0x0004
118#define RX_ADDR_LOAD 0x0006
119#define RX_RESUMENR 0x0007
120#define INT_MASK 0x0100
121#define DRVR_INT 0x0200 /* Driver generated interrupt. */
122
663e8e51
TS		 123/* Offsets to the various registers.
124 All accesses need not be longword aligned. */
125enum speedo_offsets {
126 SCBStatus = 0,
127 SCBAck = 1,
128 SCBCmd = 2, /* Rx/Command Unit command and status. */
129 SCBIntmask = 3,
130 SCBPointer = 4, /* General purpose pointer. */
131 SCBPort = 8, /* Misc. commands and operands. */
132 SCBflash = 12, SCBeeprom = 14, /* EEPROM and flash memory control. */
133 SCBCtrlMDI = 16, /* MDI interface control. */
134 SCBEarlyRx = 20, /* Early receive byte count. */
3257d2b6 135 SCBFlow = 24,
663e8e51
TS		 136};
137
138/* A speedo3 transmit buffer descriptor with two buffers... */
139typedef struct {
140 uint16_t status;
141 uint16_t command;
142 uint32_t link; /* void * */
7b8737de 143 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
663e8e51
TS		 144 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
145 uint8_t tx_threshold; /* transmit threshold */
146 uint8_t tbd_count; /* TBD number */
147 //~ /* This constitutes two "TBD" entries: hdr and data */
148 //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
149 //~ int32_t tx_buf_size0; /* Length of Tx hdr. */
150 //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
151 //~ int32_t tx_buf_size1; /* Length of Tx data. */
c227f099 152} eepro100_tx_t;
663e8e51
TS		 153
154/* Receive frame descriptor. */
155typedef struct {
156 int16_t status;
157 uint16_t command;
158 uint32_t link; /* struct RxFD * */
159 uint32_t rx_buf_addr; /* void * */
160 uint16_t count;
161 uint16_t size;
162 char packet[MAX_ETH_FRAME_SIZE + 4];
c227f099 163} eepro100_rx_t;
663e8e51
TS		 164
165typedef struct {
166 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
167 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
168 tx_multiple_collisions, tx_total_collisions;
169 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
170 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
171 rx_short_frame_errors;
172 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
173 uint16_t xmt_tco_frames, rcv_tco_frames;
ba42b646
SW		 174 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
175 uint32_t reserved[4];
c227f099 176} eepro100_stats_t;
663e8e51
TS		 177
178typedef enum {
179 cu_idle = 0,
180 cu_suspended = 1,
181 cu_active = 2,
182 cu_lpq_active = 2,
183 cu_hqp_active = 3
c227f099 184} cu_state_t;
663e8e51
TS		 185
186typedef enum {
187 ru_idle = 0,
188 ru_suspended = 1,
189 ru_no_resources = 2,
190 ru_ready = 4
c227f099 191} ru_state_t;
663e8e51 192
663e8e51 193typedef struct {
273a2142 194 PCIDevice dev;
663e8e51
TS		 195 uint8_t mult[8]; /* multicast mask array */
196 int mmio_index;
e00e365e 197 NICState *nic;
508ef936 198 NICConf conf;
663e8e51
TS		 199 uint8_t scb_stat; /* SCB stat/ack byte */
200 uint8_t int_stat; /* PCI interrupt status */
3706c43f 201 /* region must not be saved by nic_save. */
663e8e51 202 uint32_t region[3]; /* PCI region addresses */
663e8e51 203 uint16_t mdimem[32];
c227f099 204 eeprom_t *eeprom;
663e8e51
TS		 205 uint32_t device; /* device variant */
206 uint32_t pointer;
207 /* (cu_base + cu_offset) address the next command block in the command block list. */
208 uint32_t cu_base; /* CU base address */
209 uint32_t cu_offset; /* CU address offset */
210 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
211 uint32_t ru_base; /* RU base address */
212 uint32_t ru_offset; /* RU address offset */
c227f099 213 uint32_t statsaddr; /* pointer to eepro100_stats_t */
ba42b646 214
f3a52e50
SW		 215 /* Temporary status information (no need to save these values),
216 * used while processing CU commands. */
217 eepro100_tx_t tx; /* transmit buffer descriptor */
218 uint32_t cb_address; /* = cu_base + cu_offset */
219
ba42b646
SW		 220 /* Statistical counters. Also used for wake-up packet (i82559). */
221 eepro100_stats_t statistics;
222
663e8e51
TS		 223#if 0
224 uint16_t status;
225#endif
226
227 /* Configuration bytes. */
228 uint8_t configuration[22];
229
230 /* Data in mem is always in the byte order of the controller (le). */
231 uint8_t mem[PCI_MEM_SIZE];
151b2986
JQ		 232 /* vmstate for each particular nic */
233 VMStateDescription *vmstate;
ba42b646
SW		 234
235 /* Quasi static device properties (no need to save them). */
236 uint16_t stats_size;
237 bool has_extended_tcb_support;
663e8e51
TS		 238} EEPRO100State;
239
240/* Default values for MDI (PHY) registers */
241static const uint16_t eepro100_mdi_default[] = {
242 /* MDI Registers 0 - 6, 7 */
243 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
244 /* MDI Registers 8 - 15 */
245 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
246 /* MDI Registers 16 - 31 */
247 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
248 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
249};
250
251/* Readonly mask for MDI (PHY) registers */
252static const uint16_t eepro100_mdi_mask[] = {
253 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
254 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
255 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
256 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
257};
258
ba42b646
SW		 259/* XXX: optimize */
260static void stl_le_phys(target_phys_addr_t addr, uint32_t val)
261{
262 val = cpu_to_le32(val);
263 cpu_physical_memory_write(addr, (const uint8_t *)&val, sizeof(val));
264}
265
663e8e51
TS		 266#define POLYNOMIAL 0x04c11db6
267
268/* From FreeBSD */
269/* XXX: optimize */
7b8737de 270static unsigned compute_mcast_idx(const uint8_t * ep)
663e8e51
TS		 271{
272 uint32_t crc;
273 int carry, i, j;
274 uint8_t b;
275
276 crc = 0xffffffff;
277 for (i = 0; i < 6; i++) {
278 b = *ep++;
279 for (j = 0; j < 8; j++) {
280 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
281 crc <<= 1;
282 b >>= 1;
aac443e6 283 if (carry) {
663e8e51 284 crc = ((crc ^ POLYNOMIAL) | carry);
aac443e6 285 }
663e8e51
TS		 286 }
287 }
7b8737de 288 return (crc & BITS(7, 2)) >> 2;
663e8e51
TS		 289}
290
291#if defined(DEBUG_EEPRO100)
292static const char *nic_dump(const uint8_t * buf, unsigned size)
293{
294 static char dump[3 * 16 + 1];
295 char *p = &dump[0];
aac443e6 296 if (size > 16) {
663e8e51 297 size = 16;
aac443e6 298 }
663e8e51
TS		 299 while (size-- > 0) {
300 p += sprintf(p, " %02x", *buf++);
301 }
302 return dump;
303}
304#endif /* DEBUG_EEPRO100 */
305
306enum scb_stat_ack {
307 stat_ack_not_ours = 0x00,
308 stat_ack_sw_gen = 0x04,
309 stat_ack_rnr = 0x10,
310 stat_ack_cu_idle = 0x20,
311 stat_ack_frame_rx = 0x40,
312 stat_ack_cu_cmd_done = 0x80,
313 stat_ack_not_present = 0xFF,
314 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
315 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
316};
317
318static void disable_interrupt(EEPRO100State * s)
319{
320 if (s->int_stat) {
aac443e6 321 TRACE(INT, logout("interrupt disabled\n"));
273a2142 322 qemu_irq_lower(s->dev.irq[0]);
663e8e51
TS		 323 s->int_stat = 0;
324 }
325}
326
327static void enable_interrupt(EEPRO100State * s)
328{
329 if (!s->int_stat) {
aac443e6 330 TRACE(INT, logout("interrupt enabled\n"));
273a2142 331 qemu_irq_raise(s->dev.irq[0]);
663e8e51
TS		 332 s->int_stat = 1;
333 }
334}
335
336static void eepro100_acknowledge(EEPRO100State * s)
337{
338 s->scb_stat &= ~s->mem[SCBAck];
339 s->mem[SCBAck] = s->scb_stat;
340 if (s->scb_stat == 0) {
341 disable_interrupt(s);
342 }
343}
344
345static void eepro100_interrupt(EEPRO100State * s, uint8_t stat)
346{
347 uint8_t mask = ~s->mem[SCBIntmask];
348 s->mem[SCBAck] |= stat;
349 stat = s->scb_stat = s->mem[SCBAck];
350 stat &= (mask | 0x0f);
351 //~ stat &= (~s->mem[SCBIntmask] | 0x0xf);
352 if (stat && (mask & 0x01)) {
353 /* SCB mask and SCB Bit M do not disable interrupt. */
354 enable_interrupt(s);
355 } else if (s->int_stat) {
356 disable_interrupt(s);
357 }
358}
359
360static void eepro100_cx_interrupt(EEPRO100State * s)
361{
362 /* CU completed action command. */
363 /* Transmit not ok (82557 only, not in emulation). */
364 eepro100_interrupt(s, 0x80);
365}
366
367static void eepro100_cna_interrupt(EEPRO100State * s)
368{
369 /* CU left the active state. */
370 eepro100_interrupt(s, 0x20);
371}
372
373static void eepro100_fr_interrupt(EEPRO100State * s)
374{
375 /* RU received a complete frame. */
376 eepro100_interrupt(s, 0x40);
377}
378
379#if 0
380static void eepro100_rnr_interrupt(EEPRO100State * s)
381{
382 /* RU is not ready. */
383 eepro100_interrupt(s, 0x10);
384}
385#endif
386
387static void eepro100_mdi_interrupt(EEPRO100State * s)
388{
389 /* MDI completed read or write cycle. */
390 eepro100_interrupt(s, 0x08);
391}
392
393static void eepro100_swi_interrupt(EEPRO100State * s)
394{
395 /* Software has requested an interrupt. */
396 eepro100_interrupt(s, 0x04);
397}
398
399#if 0
400static void eepro100_fcp_interrupt(EEPRO100State * s)
401{
402 /* Flow control pause interrupt (82558 and later). */
403 eepro100_interrupt(s, 0x01);
404}
405#endif
406
407static void pci_reset(EEPRO100State * s)
408{
409 uint32_t device = s->device;
273a2142 410 uint8_t *pci_conf = s->dev.config;
ba42b646 411 bool power_management = 1;
663e8e51 412
aac443e6 413 TRACE(OTHER, logout("%p\n", s));
663e8e51
TS		 414
415 /* PCI Vendor ID */
deb54399 416 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
d6fd1e66 417 /* PCI Device ID depends on device and is set below. */
663e8e51 418 /* PCI Command */
508cc6b4 419 /* TODO: this is the default, do not override. */
663e8e51
TS		 420 PCI_CONFIG_16(PCI_COMMAND, 0x0000);
421 /* PCI Status */
508cc6b4 422 /* TODO: Value at RST# should be 0. */
61702408 423 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK);
663e8e51
TS		 424 /* PCI Revision ID */
425 PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
508cc6b4 426 /* TODO: this is the default, do not override. */
663e8e51 427 /* PCI Class Code */
508cc6b4 428 PCI_CONFIG_8(PCI_CLASS_PROG, 0x00);
173a543b 429 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
663e8e51
TS		 430 /* PCI Cache Line Size */
431 /* check cache line size!!! */
432 //~ PCI_CONFIG_8(0x0c, 0x00);
433 /* PCI Latency Timer */
508cc6b4 434 PCI_CONFIG_8(PCI_LATENCY_TIMER, 0x20); // latency timer = 32 clocks
663e8e51
TS		 435 /* PCI Header Type */
436 /* BIST (built-in self test) */
437#if defined(TARGET_I386)
438// !!! workaround for buggy bios
0392a017 439//~ #define PCI_BASE_ADDRESS_MEM_PREFETCH 0
663e8e51
TS		 440#endif
441#if 0
442 /* PCI Base Address Registers */
443 /* CSR Memory Mapped Base Address */
444 PCI_CONFIG_32(PCI_BASE_ADDRESS_0,
0392a017
IY		 445 PCI_BASE_ADDRESS_SPACE_MEMORY |
446 PCI_BASE_ADDRESS_MEM_PREFETCH);
663e8e51 447 /* CSR I/O Mapped Base Address */
0392a017 448 PCI_CONFIG_32(PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_SPACE_IO);
663e8e51
TS		 449#if 0
450 /* Flash Memory Mapped Base Address */
0392a017
IY		 451 PCI_CONFIG_32(PCI_BASE_ADDRESS_2,
452 0xfffe0000 | PCI_BASE_ADDRESS_SPACE_MEMORY);
663e8e51
TS		 453#endif
454#endif
455 /* Expansion ROM Base Address (depends on boot disable!!!) */
508cc6b4
MT		 456 /* TODO: not needed, set when BAR is registered */
457 PCI_CONFIG_32(PCI_ROM_ADDRESS, PCI_BASE_ADDRESS_SPACE_MEMORY);
663e8e51 458 /* Capability Pointer */
508cc6b4
MT		 459 /* TODO: revisions with power_management 1 use this but
460 * do not set new capability list bit in status register. */
461 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0xdc);
aac443e6 462 /* Interrupt Line */
663e8e51 463 /* Interrupt Pin */
508cc6b4
MT		 464 /* TODO: RST# value should be 0 */
465 PCI_CONFIG_8(PCI_INTERRUPT_PIN, 1); // interrupt pin 0
663e8e51 466 /* Minimum Grant */
508cc6b4 467 PCI_CONFIG_8(PCI_MIN_GNT, 0x08);
663e8e51 468 /* Maximum Latency */
508cc6b4 469 PCI_CONFIG_8(PCI_MAX_LAT, 0x18);
663e8e51
TS		 470
471 switch (device) {
ba42b646
SW		 472 case i82550:
473 // TODO: check device id.
474 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
475 /* Revision ID: 0x0c, 0x0d, 0x0e. */
476 PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
477 // TODO: check size of statistical counters.
478 s->stats_size = 80;
479 // TODO: check extended tcb support.
480 s->has_extended_tcb_support = 1;
481 break;
663e8e51 482 case i82551:
d6fd1e66 483 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
ba42b646 484 /* Revision ID: 0x0f, 0x10. */
663e8e51 485 PCI_CONFIG_8(PCI_REVISION_ID, 0x0f);
ba42b646
SW		 486 // TODO: check size of statistical counters.
487 s->stats_size = 80;
488 s->has_extended_tcb_support = 1;
489 break;
490 case i82557A:
491 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
492 PCI_CONFIG_8(PCI_REVISION_ID, 0x01);
508cc6b4 493 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
ba42b646 494 power_management = 0;
663e8e51
TS		 495 break;
496 case i82557B:
d6fd1e66 497 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
663e8e51 498 PCI_CONFIG_8(PCI_REVISION_ID, 0x02);
508cc6b4 499 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
ba42b646 500 power_management = 0;
663e8e51
TS		 501 break;
502 case i82557C:
d6fd1e66 503 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
663e8e51 504 PCI_CONFIG_8(PCI_REVISION_ID, 0x03);
508cc6b4 505 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
ba42b646
SW		 506 power_management = 0;
507 break;
508 case i82558A:
509 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
508cc6b4
MT		 510 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
511 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
ba42b646
SW		 512 PCI_CONFIG_8(PCI_REVISION_ID, 0x04);
513 s->stats_size = 76;
514 s->has_extended_tcb_support = 1;
663e8e51
TS		 515 break;
516 case i82558B:
d6fd1e66 517 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
508cc6b4
MT		 518 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
519 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
663e8e51 520 PCI_CONFIG_8(PCI_REVISION_ID, 0x05);
ba42b646
SW		 521 s->stats_size = 76;
522 s->has_extended_tcb_support = 1;
523 break;
524 case i82559A:
525 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
508cc6b4
MT		 526 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
527 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
ba42b646
SW		 528 PCI_CONFIG_8(PCI_REVISION_ID, 0x06);
529 s->stats_size = 80;
530 s->has_extended_tcb_support = 1;
531 break;
532 case i82559B:
533 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
508cc6b4
MT		 534 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
535 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
ba42b646
SW		 536 PCI_CONFIG_8(PCI_REVISION_ID, 0x07);
537 s->stats_size = 80;
538 s->has_extended_tcb_support = 1;
663e8e51
TS		 539 break;
540 case i82559C:
d6fd1e66 541 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
508cc6b4
MT		 542 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
543 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
ba42b646
SW		 544 PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
545 // TODO: Windows wants revision id 0x0c.
546 PCI_CONFIG_8(PCI_REVISION_ID, 0x0c);
547#if EEPROM_SIZE > 0
548 PCI_CONFIG_16(PCI_SUBSYSTEM_VENDOR_ID, 0x8086);
549 PCI_CONFIG_16(PCI_SUBSYSTEM_ID, 0x0040);
550#endif
551 s->stats_size = 80;
552 s->has_extended_tcb_support = 1;
663e8e51
TS		 553 break;
554 case i82559ER:
d6fd1e66 555 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
508cc6b4
MT		 556 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
557 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
663e8e51 558 PCI_CONFIG_8(PCI_REVISION_ID, 0x09);
ba42b646
SW		 559 s->stats_size = 80;
560 s->has_extended_tcb_support = 1;
561 break;
562 case i82562:
563 // TODO: check device id.
564 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
565 /* TODO: wrong revision id. */
566 PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
567 s->stats_size = 80;
568 s->has_extended_tcb_support = 1;
663e8e51 569 break;
663e8e51
TS		 570 default:
571 logout("Device %X is undefined!\n", device);
572 }
573
ba42b646
SW		 574 s->configuration[6] |= BIT(5);
575
576 if (s->stats_size == 80) {
577 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
578 if (s->configuration[6] & BIT(2)) {
579 /* TCO statistical counters. */
580 assert(s->configuration[6] & BIT(5));
581 } else {
582 if (s->configuration[6] & BIT(5)) {
583 /* No extended statistical counters, i82557 compatible. */
584 s->stats_size = 64;
585 } else {
586 /* i82558 compatible. */
587 s->stats_size = 76;
588 }
589 }
590 } else {
591 if (s->configuration[6] & BIT(5)) {
592 /* No extended statistical counters. */
593 s->stats_size = 64;
594 }
595 }
596 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
597
598 if (power_management) {
599 /* Power Management Capabilities */
600 PCI_CONFIG_8(0xdc, 0x01);
601 /* Next Item Pointer */
602 /* Capability ID */
603 PCI_CONFIG_16(0xde, 0x7e21);
604 /* TODO: Power Management Control / Status. */
605 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
606 }
607
608#if EEPROM_SIZE > 0
663e8e51 609 if (device == i82557C || device == i82558B || device == i82559C) {
ba42b646
SW		 610 // TODO: get vendor id from EEPROM for i82557C or later.
611 // TODO: get device id from EEPROM for i82557C or later.
612 // TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
613 // TODO: header type is determined by EEPROM for i82559.
614 // TODO: get subsystem id from EEPROM for i82557C or later.
615 // TODO: get subsystem vendor id from EEPROM for i82557C or later.
616 // TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
617 // TODO: capability pointer depends on EEPROM for i82558.
663e8e51
TS		 618 logout("Get device id and revision from EEPROM!!!\n");
619 }
ba42b646 620#endif /* EEPROM_SIZE > 0 */
663e8e51
TS		 621}
622
623static void nic_selective_reset(EEPRO100State * s)
624{
625 size_t i;
626 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
627 //~ eeprom93xx_reset(s->eeprom);
508ef936 628 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
663e8e51 629 eeprom_contents[0xa] = 0x4000;
f4e94dfe
RD		 630 if (s->device == i82557B || s->device == i82557C)
631 eeprom_contents[5] = 0x0100;
663e8e51
TS		 632 uint16_t sum = 0;
633 for (i = 0; i < EEPROM_SIZE - 1; i++) {
634 sum += eeprom_contents[i];
635 }
636 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
aac443e6 637 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
663e8e51
TS		 638
639 memset(s->mem, 0, sizeof(s->mem));
640 uint32_t val = BIT(21);
641 memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
642
643 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
644 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
645}
646
647static void nic_reset(void *opaque)
648{
769cf7a5 649 EEPRO100State *s = opaque;
aac443e6 650 TRACE(OTHER, logout("%p\n", s));
7b8737de
SW		 651 /* TODO: Clearing of multicast table for selective reset, too? */
652 memset(&s->mult[0], 0, sizeof(s->mult));
663e8e51
TS		 653 nic_selective_reset(s);
654}
655
656#if defined(DEBUG_EEPRO100)
b8f6ba0d 657static const char * const e100_reg[PCI_IO_SIZE / 4] = {
663e8e51
TS		 658 "Command/Status",
659 "General Pointer",
660 "Port",
661 "EEPROM/Flash Control",
662 "MDI Control",
663 "Receive DMA Byte Count",
b8f6ba0d 664 "Flow Control",
663e8e51
TS		 665 "General Status/Control"
666};
667
668static char *regname(uint32_t addr)
669{
ec169288 670 static char buf[32];
663e8e51 671 if (addr < PCI_IO_SIZE) {
b8f6ba0d 672 const char *r = e100_reg[addr / 4];
663e8e51 673 if (r != 0) {
41cbc23c 674 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
663e8e51 675 } else {
41cbc23c 676 snprintf(buf, sizeof(buf), "0x%02x", addr);
663e8e51
TS		 677 }
678 } else {
41cbc23c 679 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
663e8e51
TS		 680 }
681 return buf;
682}
683#endif /* DEBUG_EEPRO100 */
684
685#if 0
686static uint16_t eepro100_read_status(EEPRO100State * s)
687{
688 uint16_t val = s->status;
aac443e6 689 TRACE(OTHER, logout("val=0x%04x\n", val));
663e8e51
TS		 690 return val;
691}
692
693static void eepro100_write_status(EEPRO100State * s, uint16_t val)
694{
aac443e6 695 TRACE(OTHER, logout("val=0x%04x\n", val));
663e8e51
TS		 696 s->status = val;
697}
698#endif
699
700/*****************************************************************************
701 *
702 * Command emulation.
703 *
704 ****************************************************************************/
705
706#if 0
707static uint16_t eepro100_read_command(EEPRO100State * s)
708{
709 uint16_t val = 0xffff;
aac443e6 710 //~ TRACE(OTHER, logout("val=0x%04x\n", val));
663e8e51
TS		 711 return val;
712}
713#endif
714
715/* Commands that can be put in a command list entry. */
716enum commands {
717 CmdNOp = 0,
718 CmdIASetup = 1,
719 CmdConfigure = 2,
720 CmdMulticastList = 3,
721 CmdTx = 4,
722 CmdTDR = 5, /* load microcode */
723 CmdDump = 6,
724 CmdDiagnose = 7,
725
726 /* And some extra flags: */
727 CmdSuspend = 0x4000, /* Suspend after completion. */
728 CmdIntr = 0x2000, /* Interrupt after completion. */
729 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
730};
731
c227f099 732static cu_state_t get_cu_state(EEPRO100State * s)
663e8e51
TS		 733{
734 return ((s->mem[SCBStatus] >> 6) & 0x03);
735}
736
c227f099 737static void set_cu_state(EEPRO100State * s, cu_state_t state)
663e8e51
TS		 738{
739 s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6);
740}
741
c227f099 742static ru_state_t get_ru_state(EEPRO100State * s)
663e8e51
TS		 743{
744 return ((s->mem[SCBStatus] >> 2) & 0x0f);
745}
746
c227f099 747static void set_ru_state(EEPRO100State * s, ru_state_t state)
663e8e51
TS		 748{
749 s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2);
750}
751
752static void dump_statistics(EEPRO100State * s)
753{
754 /* Dump statistical data. Most data is never changed by the emulation
755 * and always 0, so we first just copy the whole block and then those
756 * values which really matter.
757 * Number of data should check configuration!!!
758 */
ba42b646
SW		 759 cpu_physical_memory_write(s->statsaddr,
760 (uint8_t *) & s->statistics, s->stats_size);
761 stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
762 stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
763 stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
764 stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
765 //~ stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
766 //~ stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
663e8e51
TS		 767 //~ missing("CU dump statistical counters");
768}
769
f3a52e50
SW		 770static void tx_command(EEPRO100State *s)
771{
7b8737de 772 uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
f3a52e50
SW		 773 uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
774 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
775 uint8_t buf[2600];
776 uint16_t size = 0;
777 uint32_t tbd_address = s->cb_address + 0x10;
778 TRACE(RXTX, logout
779 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
780 tbd_array, tcb_bytes, s->tx.tbd_count));
781
782 if (tcb_bytes > 2600) {
783 logout("TCB byte count too large, using 2600\n");
784 tcb_bytes = 2600;
785 }
786 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
787 logout
788 ("illegal values of TBD array address and TCB byte count!\n");
789 }
790 assert(tcb_bytes <= sizeof(buf));
791 while (size < tcb_bytes) {
792 uint32_t tx_buffer_address = ldl_phys(tbd_address);
793 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
794 //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
795 tbd_address += 8;
796 TRACE(RXTX, logout
797 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
798 tx_buffer_address, tx_buffer_size));
799 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
800 cpu_physical_memory_read(tx_buffer_address, &buf[size],
801 tx_buffer_size);
802 size += tx_buffer_size;
803 }
804 if (tbd_array == 0xffffffff) {
805 /* Simplified mode. Was already handled by code above. */
806 } else {
807 /* Flexible mode. */
808 uint8_t tbd_count = 0;
809 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
810 /* Extended Flexible TCB. */
811 for (; tbd_count < 2; tbd_count++) {
812 uint32_t tx_buffer_address = ldl_phys(tbd_address);
813 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
814 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
815 tbd_address += 8;
816 TRACE(RXTX, logout
817 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
818 tx_buffer_address, tx_buffer_size));
819 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
820 cpu_physical_memory_read(tx_buffer_address, &buf[size],
821 tx_buffer_size);
822 size += tx_buffer_size;
823 if (tx_buffer_el & 1) {
824 break;
825 }
826 }
827 }
828 tbd_address = tbd_array;
829 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
830 uint32_t tx_buffer_address = ldl_phys(tbd_address);
831 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
832 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
833 tbd_address += 8;
834 TRACE(RXTX, logout
835 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
836 tx_buffer_address, tx_buffer_size));
837 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
838 cpu_physical_memory_read(tx_buffer_address, &buf[size],
839 tx_buffer_size);
840 size += tx_buffer_size;
841 if (tx_buffer_el & 1) {
842 break;
843 }
844 }
845 }
846 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
847 qemu_send_packet(&s->nic->nc, buf, size);
848 s->statistics.tx_good_frames++;
849 /* Transmit with bad status would raise an CX/TNO interrupt.
850 * (82557 only). Emulation never has bad status. */
851 //~ eepro100_cx_interrupt(s);
852}
853
7b8737de
SW		 854static void set_multicast_list(EEPRO100State *s)
855{
856 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
857 uint16_t i;
858 memset(&s->mult[0], 0, sizeof(s->mult));
859 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
860 for (i = 0; i < multicast_count; i += 6) {
861 uint8_t multicast_addr[6];
862 cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6);
863 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
864 unsigned mcast_idx = compute_mcast_idx(multicast_addr);
865 assert(mcast_idx < 64);
866 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
867 }
868}
869
5fa9a0ae 870static void action_command(EEPRO100State *s)
663e8e51 871{
5fa9a0ae 872 for (;;) {
f3a52e50
SW		 873 s->cb_address = s->cu_base + s->cu_offset;
874 cpu_physical_memory_read(s->cb_address, (uint8_t *)&s->tx, sizeof(s->tx));
875 uint16_t status = le16_to_cpu(s->tx.status);
876 uint16_t command = le16_to_cpu(s->tx.command);
663e8e51
TS		 877 logout
878 ("val=0x%02x (cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
f3a52e50 879 val, status, command, s->tx.link);
663e8e51
TS		 880 bool bit_el = ((command & 0x8000) != 0);
881 bool bit_s = ((command & 0x4000) != 0);
882 bool bit_i = ((command & 0x2000) != 0);
883 bool bit_nc = ((command & 0x0010) != 0);
7f1e9d4e 884 bool success = true;
663e8e51
TS		 885 //~ bool bit_sf = ((command & 0x0008) != 0);
886 uint16_t cmd = command & 0x0007;
f3a52e50 887 s->cu_offset = le32_to_cpu(s->tx.link);
663e8e51
TS		 888 switch (cmd) {
889 case CmdNOp:
890 /* Do nothing. */
891 break;
892 case CmdIASetup:
f3a52e50 893 cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6);
aac443e6 894 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6)));
663e8e51
TS		 895 break;
896 case CmdConfigure:
f3a52e50 897 cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0],
663e8e51 898 sizeof(s->configuration));
aac443e6 899 TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16)));
663e8e51
TS		 900 break;
901 case CmdMulticastList:
7b8737de 902 set_multicast_list(s);
663e8e51
TS		 903 break;
904 case CmdTx:
7f1e9d4e
KW		 905 if (bit_nc) {
906 missing("CmdTx: NC = 0");
907 success = false;
908 break;
909 }
f3a52e50 910 tx_command(s);
663e8e51
TS		 911 break;
912 case CmdTDR:
aac443e6 913 TRACE(OTHER, logout("load microcode\n"));
663e8e51
TS		 914 /* Starting with offset 8, the command contains
915 * 64 dwords microcode which we just ignore here. */
916 break;
917 default:
918 missing("undefined command");
7f1e9d4e
KW		 919 success = false;
920 break;
663e8e51 921 }
7f1e9d4e 922 /* Write new status. */
f3a52e50 923 stw_phys(s->cb_address, status | 0x8000 | (success ? 0x2000 : 0));
663e8e51
TS		 924 if (bit_i) {
925 /* CU completed action. */
926 eepro100_cx_interrupt(s);
927 }
928 if (bit_el) {
aac443e6 929 /* CU becomes idle. Terminate command loop. */
663e8e51
TS		 930 set_cu_state(s, cu_idle);
931 eepro100_cna_interrupt(s);
5fa9a0ae 932 break;
663e8e51 933 } else if (bit_s) {
5fa9a0ae 934 /* CU becomes suspended. Terminate command loop. */
663e8e51
TS		 935 set_cu_state(s, cu_suspended);
936 eepro100_cna_interrupt(s);
5fa9a0ae 937 break;
663e8e51
TS		 938 } else {
939 /* More entries in list. */
aac443e6 940 TRACE(OTHER, logout("CU list with at least one more entry\n"));
663e8e51 941 }
5fa9a0ae
SW		 942 }
943 TRACE(OTHER, logout("CU list empty\n"));
944 /* List is empty. Now CU is idle or suspended. */
945}
946
947static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
948{
949 switch (val) {
950 case CU_NOP:
951 /* No operation. */
952 break;
953 case CU_START:
954 if (get_cu_state(s) != cu_idle) {
955 /* Intel documentation says that CU must be idle for the CU
956 * start command. Intel driver for Linux also starts the CU
957 * from suspended state. */
958 logout("CU state is %u, should be %u\n", get_cu_state(s), cu_idle);
959 //~ assert(!"wrong CU state");
960 }
961 set_cu_state(s, cu_active);
962 s->cu_offset = s->pointer;
963 action_command(s);
663e8e51
TS		 964 break;
965 case CU_RESUME:
966 if (get_cu_state(s) != cu_suspended) {
967 logout("bad CU resume from CU state %u\n", get_cu_state(s));
968 /* Workaround for bad Linux eepro100 driver which resumes
969 * from idle state. */
970 //~ missing("cu resume");
971 set_cu_state(s, cu_suspended);
972 }
973 if (get_cu_state(s) == cu_suspended) {
aac443e6 974 TRACE(OTHER, logout("CU resuming\n"));
663e8e51 975 set_cu_state(s, cu_active);
5fa9a0ae 976 action_command(s);
663e8e51
TS		 977 }
978 break;
979 case CU_STATSADDR:
980 /* Load dump counters address. */
981 s->statsaddr = s->pointer;
aac443e6 982 TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
663e8e51
TS		 983 break;
984 case CU_SHOWSTATS:
985 /* Dump statistical counters. */
aac443e6 986 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
663e8e51 987 dump_statistics(s);
ba42b646 988 stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
663e8e51
TS		 989 break;
990 case CU_CMD_BASE:
991 /* Load CU base. */
aac443e6 992 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
663e8e51
TS		 993 s->cu_base = s->pointer;
994 break;
995 case CU_DUMPSTATS:
996 /* Dump and reset statistical counters. */
aac443e6 997 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
663e8e51 998 dump_statistics(s);
ba42b646 999 stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
663e8e51
TS		 1000 memset(&s->statistics, 0, sizeof(s->statistics));
1001 break;
1002 case CU_SRESUME:
1003 /* CU static resume. */
1004 missing("CU static resume");
1005 break;
1006 default:
1007 missing("Undefined CU command");
1008 }
1009}
1010
1011static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
1012{
1013 switch (val) {
1014 case RU_NOP:
1015 /* No operation. */
1016 break;
1017 case RX_START:
1018 /* RU start. */
1019 if (get_ru_state(s) != ru_idle) {
1020 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
1021 //~ assert(!"wrong RU state");
1022 }
1023 set_ru_state(s, ru_ready);
1024 s->ru_offset = s->pointer;
aac443e6 1025 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
663e8e51
TS		 1026 break;
1027 case RX_RESUME:
1028 /* Restart RU. */
1029 if (get_ru_state(s) != ru_suspended) {
1030 logout("RU state is %u, should be %u\n", get_ru_state(s),
1031 ru_suspended);
1032 //~ assert(!"wrong RU state");
1033 }
1034 set_ru_state(s, ru_ready);
1035 break;
1036 case RX_ADDR_LOAD:
1037 /* Load RU base. */
aac443e6 1038 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
663e8e51
TS		 1039 s->ru_base = s->pointer;
1040 break;
1041 default:
1042 logout("val=0x%02x (undefined RU command)\n", val);
1043 missing("Undefined SU command");
1044 }
1045}
1046
1047static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1048{
1049 eepro100_ru_command(s, val & 0x0f);
1050 eepro100_cu_command(s, val & 0xf0);
1051 if ((val) == 0) {
aac443e6 1052 TRACE(OTHER, logout("val=0x%02x\n", val));
663e8e51
TS		 1053 }
1054 /* Clear command byte after command was accepted. */
1055 s->mem[SCBCmd] = 0;
1056}
1057
1058/*****************************************************************************
1059 *
1060 * EEPROM emulation.
1061 *
1062 ****************************************************************************/
1063
1064#define EEPROM_CS 0x02
1065#define EEPROM_SK 0x01
1066#define EEPROM_DI 0x04
1067#define EEPROM_DO 0x08
1068
1069static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1070{
1071 uint16_t val;
1072 memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
1073 if (eeprom93xx_read(s->eeprom)) {
1074 val |= EEPROM_DO;
1075 } else {
1076 val &= ~EEPROM_DO;
1077 }
aac443e6 1078 TRACE(EEPROM, logout("val=0x%04x\n", val));
663e8e51
TS		 1079 return val;
1080}
1081
c227f099 1082static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
663e8e51 1083{
aac443e6 1084 TRACE(EEPROM, logout("val=0x%02x\n", val));
663e8e51
TS		 1085
1086 /* mask unwriteable bits */
1087 //~ val = SET_MASKED(val, 0x31, eeprom->value);
1088
1089 int eecs = ((val & EEPROM_CS) != 0);
1090 int eesk = ((val & EEPROM_SK) != 0);
1091 int eedi = ((val & EEPROM_DI) != 0);
1092 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1093}
1094
1095static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
1096{
1097 s->pointer = le32_to_cpu(val);
aac443e6 1098 TRACE(OTHER, logout("val=0x%08x\n", val));
663e8e51
TS		 1099}
1100
1101/*****************************************************************************
1102 *
1103 * MDI emulation.
1104 *
1105 ****************************************************************************/
1106
1107#if defined(DEBUG_EEPRO100)
6a0b9cc9 1108static const char * const mdi_op_name[] = {
663e8e51
TS		 1109 "opcode 0",
1110 "write",
1111 "read",
1112 "opcode 3"
1113};
1114
6a0b9cc9 1115static const char * const mdi_reg_name[] = {
663e8e51
TS		 1116 "Control",
1117 "Status",
1118 "PHY Identification (Word 1)",
1119 "PHY Identification (Word 2)",
1120 "Auto-Negotiation Advertisement",
1121 "Auto-Negotiation Link Partner Ability",
1122 "Auto-Negotiation Expansion"
1123};
aac443e6
SW		 1124
1125static const char *reg2name(uint8_t reg)
1126{
1127 static char buffer[10];
1128 const char *p = buffer;
1129 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1130 p = mdi_reg_name[reg];
1131 } else {
1132 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1133 }
1134 return p;
1135}
663e8e51
TS		 1136#endif /* DEBUG_EEPRO100 */
1137
1138static uint32_t eepro100_read_mdi(EEPRO100State * s)
1139{
1140 uint32_t val;
1141 memcpy(&val, &s->mem[0x10], sizeof(val));
1142
1143#ifdef DEBUG_EEPRO100
1144 uint8_t raiseint = (val & BIT(29)) >> 29;
1145 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1146 uint8_t phy = (val & BITS(25, 21)) >> 21;
1147 uint8_t reg = (val & BITS(20, 16)) >> 16;
1148 uint16_t data = (val & BITS(15, 0));
1149#endif
1150 /* Emulation takes no time to finish MDI transaction. */
1151 val |= BIT(28);
1152 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1153 val, raiseint, mdi_op_name[opcode], phy,
aac443e6 1154 reg2name(reg), data));
663e8e51
TS		 1155 return val;
1156}
1157
663e8e51
TS		 1158static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
1159{
1160 uint8_t raiseint = (val & BIT(29)) >> 29;
1161 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1162 uint8_t phy = (val & BITS(25, 21)) >> 21;
1163 uint8_t reg = (val & BITS(20, 16)) >> 16;
1164 uint16_t data = (val & BITS(15, 0));
aac443e6
SW		 1165 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1166 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
663e8e51
TS		 1167 if (phy != 1) {
1168 /* Unsupported PHY address. */
1169 //~ logout("phy must be 1 but is %u\n", phy);
1170 data = 0;
1171 } else if (opcode != 1 && opcode != 2) {
1172 /* Unsupported opcode. */
1173 logout("opcode must be 1 or 2 but is %u\n", opcode);
1174 data = 0;
1175 } else if (reg > 6) {
1176 /* Unsupported register. */
1177 logout("register must be 0...6 but is %u\n", reg);
1178 data = 0;
1179 } else {
1180 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1181 val, raiseint, mdi_op_name[opcode], phy,
aac443e6 1182 reg2name(reg), data));
663e8e51
TS		 1183 if (opcode == 1) {
1184 /* MDI write */
1185 switch (reg) {
1186 case 0: /* Control Register */
1187 if (data & 0x8000) {
1188 /* Reset status and control registers to default. */
1189 s->mdimem[0] = eepro100_mdi_default[0];
1190 s->mdimem[1] = eepro100_mdi_default[1];
1191 data = s->mdimem[reg];
1192 } else {
1193 /* Restart Auto Configuration = Normal Operation */
1194 data &= ~0x0200;
1195 }
1196 break;
1197 case 1: /* Status Register */
1198 missing("not writable");
1199 data = s->mdimem[reg];
1200 break;
1201 case 2: /* PHY Identification Register (Word 1) */
1202 case 3: /* PHY Identification Register (Word 2) */
1203 missing("not implemented");
1204 break;
1205 case 4: /* Auto-Negotiation Advertisement Register */
1206 case 5: /* Auto-Negotiation Link Partner Ability Register */
1207 break;
1208 case 6: /* Auto-Negotiation Expansion Register */
1209 default:
1210 missing("not implemented");
1211 }
1212 s->mdimem[reg] = data;
1213 } else if (opcode == 2) {
1214 /* MDI read */
1215 switch (reg) {
1216 case 0: /* Control Register */
1217 if (data & 0x8000) {
1218 /* Reset status and control registers to default. */
1219 s->mdimem[0] = eepro100_mdi_default[0];
1220 s->mdimem[1] = eepro100_mdi_default[1];
1221 }
1222 break;
1223 case 1: /* Status Register */
1224 s->mdimem[reg] |= 0x0020;
1225 break;
1226 case 2: /* PHY Identification Register (Word 1) */
1227 case 3: /* PHY Identification Register (Word 2) */
1228 case 4: /* Auto-Negotiation Advertisement Register */
1229 break;
1230 case 5: /* Auto-Negotiation Link Partner Ability Register */
1231 s->mdimem[reg] = 0x41fe;
1232 break;
1233 case 6: /* Auto-Negotiation Expansion Register */
1234 s->mdimem[reg] = 0x0001;
1235 break;
1236 }
1237 data = s->mdimem[reg];
1238 }
1239 /* Emulation takes no time to finish MDI transaction.
1240 * Set MDI bit in SCB status register. */
1241 s->mem[SCBAck] |= 0x08;
1242 val |= BIT(28);
1243 if (raiseint) {
1244 eepro100_mdi_interrupt(s);
1245 }
1246 }
1247 val = (val & 0xffff0000) + data;
1248 memcpy(&s->mem[0x10], &val, sizeof(val));
1249}
1250
1251/*****************************************************************************
1252 *
1253 * Port emulation.
1254 *
1255 ****************************************************************************/
1256
1257#define PORT_SOFTWARE_RESET 0
1258#define PORT_SELFTEST 1
1259#define PORT_SELECTIVE_RESET 2
1260#define PORT_DUMP 3
1261#define PORT_SELECTION_MASK 3
1262
1263typedef struct {
1264 uint32_t st_sign; /* Self Test Signature */
1265 uint32_t st_result; /* Self Test Results */
c227f099 1266} eepro100_selftest_t;
663e8e51
TS		 1267
1268static uint32_t eepro100_read_port(EEPRO100State * s)
1269{
1270 return 0;
1271}
1272
1273static void eepro100_write_port(EEPRO100State * s, uint32_t val)
1274{
1275 val = le32_to_cpu(val);
1276 uint32_t address = (val & ~PORT_SELECTION_MASK);
1277 uint8_t selection = (val & PORT_SELECTION_MASK);
1278 switch (selection) {
1279 case PORT_SOFTWARE_RESET:
1280 nic_reset(s);
1281 break;
1282 case PORT_SELFTEST:
aac443e6 1283 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
c227f099 1284 eepro100_selftest_t data;
663e8e51
TS		 1285 cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
1286 data.st_sign = 0xffffffff;
1287 data.st_result = 0;
1288 cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
1289 break;
1290 case PORT_SELECTIVE_RESET:
aac443e6 1291 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
663e8e51
TS		 1292 nic_selective_reset(s);
1293 break;
1294 default:
1295 logout("val=0x%08x\n", val);
1296 missing("unknown port selection");
1297 }
1298}
1299
1300/*****************************************************************************
1301 *
1302 * General hardware emulation.
1303 *
1304 ****************************************************************************/
1305
1306static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1307{
1308 uint8_t val;
1309 if (addr <= sizeof(s->mem) - sizeof(val)) {
1310 memcpy(&val, &s->mem[addr], sizeof(val));
1311 }
1312
1313 switch (addr) {
1314 case SCBStatus:
1315 //~ val = eepro100_read_status(s);
aac443e6 1316 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1317 break;
1318 case SCBAck:
1319 //~ val = eepro100_read_status(s);
aac443e6 1320 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1321 break;
1322 case SCBCmd:
aac443e6 1323 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1324 //~ val = eepro100_read_command(s);
1325 break;
1326 case SCBIntmask:
aac443e6 1327 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1328 break;
1329 case SCBPort + 3:
aac443e6 1330 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1331 break;
1332 case SCBeeprom:
1333 val = eepro100_read_eeprom(s);
1334 break;
1335 case 0x1b: /* PMDR (power management driver register) */
1336 val = 0;
aac443e6 1337 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1338 break;
1339 case 0x1d: /* general status register */
1340 /* 100 Mbps full duplex, valid link */
1341 val = 0x07;
aac443e6 1342 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
663e8e51
TS		 1343 break;
1344 default:
1345 logout("addr=%s val=0x%02x\n", regname(addr), val);
1346 missing("unknown byte read");
1347 }
1348 return val;
1349}
1350
1351static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1352{
1353 uint16_t val;
1354 if (addr <= sizeof(s->mem) - sizeof(val)) {
1355 memcpy(&val, &s->mem[addr], sizeof(val));
1356 }
1357
663e8e51
TS		 1358 switch (addr) {
1359 case SCBStatus:
1360 //~ val = eepro100_read_status(s);
dbbaaff6 1361 case SCBCmd:
aac443e6 1362 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
663e8e51
TS		 1363 break;
1364 case SCBeeprom:
1365 val = eepro100_read_eeprom(s);
aac443e6 1366 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
663e8e51
TS		 1367 break;
1368 default:
1369 logout("addr=%s val=0x%04x\n", regname(addr), val);
1370 missing("unknown word read");
1371 }
1372 return val;
1373}
1374
1375static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1376{
1377 uint32_t val;
1378 if (addr <= sizeof(s->mem) - sizeof(val)) {
1379 memcpy(&val, &s->mem[addr], sizeof(val));
1380 }
1381
1382 switch (addr) {
1383 case SCBStatus:
1384 //~ val = eepro100_read_status(s);
aac443e6 1385 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
663e8e51
TS		 1386 break;
1387 case SCBPointer:
1388 //~ val = eepro100_read_pointer(s);
aac443e6 1389 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
663e8e51
TS		 1390 break;
1391 case SCBPort:
1392 val = eepro100_read_port(s);
aac443e6 1393 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
663e8e51
TS		 1394 break;
1395 case SCBCtrlMDI:
1396 val = eepro100_read_mdi(s);
1397 break;
1398 default:
1399 logout("addr=%s val=0x%08x\n", regname(addr), val);
1400 missing("unknown longword read");
1401 }
1402 return val;
1403}
1404
1405static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1406{
1407 if (addr <= sizeof(s->mem) - sizeof(val)) {
1408 memcpy(&s->mem[addr], &val, sizeof(val));
1409 }
1410
aac443e6 1411 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1412
1413 switch (addr) {
1414 case SCBStatus:
1415 //~ eepro100_write_status(s, val);
1416 break;
1417 case SCBAck:
1418 eepro100_acknowledge(s);
1419 break;
1420 case SCBCmd:
1421 eepro100_write_command(s, val);
1422 break;
1423 case SCBIntmask:
1424 if (val & BIT(1)) {
1425 eepro100_swi_interrupt(s);
1426 }
1427 eepro100_interrupt(s, 0);
1428 break;
1429 case SCBPort + 3:
aac443e6 1430 case SCBFlow: /* does not exist on 82557 */
3257d2b6
TS		 1431 case SCBFlow + 1:
1432 case SCBFlow + 2:
1433 case SCBFlow + 3:
aac443e6 1434 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1435 break;
1436 case SCBeeprom:
1437 eepro100_write_eeprom(s->eeprom, val);
1438 break;
1439 default:
1440 logout("addr=%s val=0x%02x\n", regname(addr), val);
1441 missing("unknown byte write");
1442 }
1443}
1444
1445static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1446{
1447 if (addr <= sizeof(s->mem) - sizeof(val)) {
1448 memcpy(&s->mem[addr], &val, sizeof(val));
1449 }
1450
aac443e6 1451 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
663e8e51
TS		 1452
1453 switch (addr) {
1454 case SCBStatus:
1455 //~ eepro100_write_status(s, val);
1456 eepro100_acknowledge(s);
1457 break;
1458 case SCBCmd:
1459 eepro100_write_command(s, val);
1460 eepro100_write1(s, SCBIntmask, val >> 8);
1461 break;
1462 case SCBeeprom:
1463 eepro100_write_eeprom(s->eeprom, val);
1464 break;
1465 default:
1466 logout("addr=%s val=0x%04x\n", regname(addr), val);
1467 missing("unknown word write");
1468 }
1469}
1470
1471static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1472{
1473 if (addr <= sizeof(s->mem) - sizeof(val)) {
1474 memcpy(&s->mem[addr], &val, sizeof(val));
1475 }
1476
1477 switch (addr) {
1478 case SCBPointer:
1479 eepro100_write_pointer(s, val);
1480 break;
1481 case SCBPort:
aac443e6 1482 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
663e8e51
TS		 1483 eepro100_write_port(s, val);
1484 break;
1485 case SCBCtrlMDI:
1486 eepro100_write_mdi(s, val);
1487 break;
1488 default:
1489 logout("addr=%s val=0x%08x\n", regname(addr), val);
1490 missing("unknown longword write");
1491 }
1492}
1493
aac443e6
SW		 1494/*****************************************************************************
1495 *
1496 * Port mapped I/O.
1497 *
1498 ****************************************************************************/
1499
663e8e51
TS		 1500static uint32_t ioport_read1(void *opaque, uint32_t addr)
1501{
1502 EEPRO100State *s = opaque;
1503 //~ logout("addr=%s\n", regname(addr));
1504 return eepro100_read1(s, addr - s->region[1]);
1505}
1506
1507static uint32_t ioport_read2(void *opaque, uint32_t addr)
1508{
1509 EEPRO100State *s = opaque;
1510 return eepro100_read2(s, addr - s->region[1]);
1511}
1512
1513static uint32_t ioport_read4(void *opaque, uint32_t addr)
1514{
1515 EEPRO100State *s = opaque;
1516 return eepro100_read4(s, addr - s->region[1]);
1517}
1518
1519static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
1520{
1521 EEPRO100State *s = opaque;
1522 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1523 eepro100_write1(s, addr - s->region[1], val);
1524}
1525
1526static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
1527{
1528 EEPRO100State *s = opaque;
1529 eepro100_write2(s, addr - s->region[1], val);
1530}
1531
1532static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
1533{
1534 EEPRO100State *s = opaque;
1535 eepro100_write4(s, addr - s->region[1], val);
1536}
1537
1538/***********************************************************/
1539/* PCI EEPRO100 definitions */
1540
663e8e51 1541static void pci_map(PCIDevice * pci_dev, int region_num,
6e355d90 1542 pcibus_t addr, pcibus_t size, int type)
663e8e51 1543{
273a2142 1544 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
663e8e51 1545
89e8b13c
IY		 1546 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1547 "size=0x%08"FMT_PCIBUS", type=%d\n",
aac443e6 1548 region_num, addr, size, type));
663e8e51
TS		 1549
1550 assert(region_num == 1);
1551 register_ioport_write(addr, size, 1, ioport_write1, s);
1552 register_ioport_read(addr, size, 1, ioport_read1, s);
1553 register_ioport_write(addr, size, 2, ioport_write2, s);
1554 register_ioport_read(addr, size, 2, ioport_read2, s);
1555 register_ioport_write(addr, size, 4, ioport_write4, s);
1556 register_ioport_read(addr, size, 4, ioport_read4, s);
1557
1558 s->region[region_num] = addr;
1559}
1560
aac443e6
SW		 1561/*****************************************************************************
1562 *
1563 * Memory mapped I/O.
1564 *
1565 ****************************************************************************/
1566
c227f099 1567static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
663e8e51
TS		 1568{
1569 EEPRO100State *s = opaque;
663e8e51
TS		 1570 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1571 eepro100_write1(s, addr, val);
1572}
1573
c227f099 1574static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
663e8e51
TS		 1575{
1576 EEPRO100State *s = opaque;
663e8e51
TS		 1577 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1578 eepro100_write2(s, addr, val);
1579}
1580
c227f099 1581static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
663e8e51
TS		 1582{
1583 EEPRO100State *s = opaque;
663e8e51
TS		 1584 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1585 eepro100_write4(s, addr, val);
1586}
1587
c227f099 1588static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
663e8e51
TS		 1589{
1590 EEPRO100State *s = opaque;
663e8e51
TS		 1591 //~ logout("addr=%s\n", regname(addr));
1592 return eepro100_read1(s, addr);
1593}
1594
c227f099 1595static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
663e8e51
TS		 1596{
1597 EEPRO100State *s = opaque;
663e8e51
TS		 1598 //~ logout("addr=%s\n", regname(addr));
1599 return eepro100_read2(s, addr);
1600}
1601
c227f099 1602static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
663e8e51
TS		 1603{
1604 EEPRO100State *s = opaque;
663e8e51
TS		 1605 //~ logout("addr=%s\n", regname(addr));
1606 return eepro100_read4(s, addr);
1607}
1608
d60efc6b 1609static CPUWriteMemoryFunc * const pci_mmio_write[] = {
663e8e51
TS		 1610 pci_mmio_writeb,
1611 pci_mmio_writew,
1612 pci_mmio_writel
1613};
1614
d60efc6b 1615static CPUReadMemoryFunc * const pci_mmio_read[] = {
663e8e51
TS		 1616 pci_mmio_readb,
1617 pci_mmio_readw,
1618 pci_mmio_readl
1619};
1620
1621static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
6e355d90 1622 pcibus_t addr, pcibus_t size, int type)
663e8e51 1623{
273a2142 1624 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
663e8e51 1625
89e8b13c
IY		 1626 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1627 "size=0x%08"FMT_PCIBUS", type=%d\n",
aac443e6 1628 region_num, addr, size, type));
663e8e51
TS		 1629
1630 if (region_num == 0) {
1631 /* Map control / status registers. */
273a2142
JQ		 1632 cpu_register_physical_memory(addr, size, s->mmio_index);
1633 s->region[region_num] = addr;
663e8e51
TS		 1634 }
1635}
1636
e00e365e 1637static int nic_can_receive(VLANClientState *nc)
663e8e51 1638{
e00e365e 1639 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
aac443e6 1640 TRACE(RXTX, logout("%p\n", s));
663e8e51
TS		 1641 return get_ru_state(s) == ru_ready;
1642 //~ return !eepro100_buffer_full(s);
1643}
1644
e00e365e 1645static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size)
663e8e51
TS		 1646{
1647 /* TODO:
1648 * - Magic packets should set bit 30 in power management driver register.
1649 * - Interesting packets should set bit 29 in power management driver register.
1650 */
e00e365e 1651 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
663e8e51
TS		 1652 uint16_t rfd_status = 0xa000;
1653 static const uint8_t broadcast_macaddr[6] =
1654 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1655
1656 /* TODO: check multiple IA bit. */
7f1e9d4e
KW		 1657 if (s->configuration[20] & BIT(6)) {
1658 missing("Multiple IA bit");
1659 return -1;
1660 }
663e8e51
TS		 1661
1662 if (s->configuration[8] & 0x80) {
1663 /* CSMA is disabled. */
1664 logout("%p received while CSMA is disabled\n", s);
4f1c942b 1665 return -1;
663e8e51
TS		 1666 } else if (size < 64 && (s->configuration[7] & 1)) {
1667 /* Short frame and configuration byte 7/0 (discard short receive) set:
1668 * Short frame is discarded */
067d01de 1669 logout("%p received short frame (%zu byte)\n", s, size);
663e8e51 1670 s->statistics.rx_short_frame_errors++;
4f1c942b 1671 //~ return -1;
663e8e51
TS		 1672 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & 8)) {
1673 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1674 * Long frames are discarded. */
067d01de 1675 logout("%p received long frame (%zu byte), ignored\n", s, size);
4f1c942b 1676 return -1;
508ef936 1677 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { // !!!
663e8e51
TS		 1678 /* Frame matches individual address. */
1679 /* TODO: check configuration byte 15/4 (ignore U/L). */
067d01de 1680 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
663e8e51
TS		 1681 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1682 /* Broadcast frame. */
067d01de 1683 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
663e8e51 1684 rfd_status |= 0x0002;
7b8737de 1685 } else if (buf[0] & 0x01) {
663e8e51 1686 /* Multicast frame. */
7b8737de 1687 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
7f1e9d4e 1688 if (s->configuration[21] & BIT(3)) {
7b8737de
SW		 1689 /* Multicast all bit is set, receive all multicast frames. */
1690 } else {
1691 unsigned mcast_idx = compute_mcast_idx(buf);
1692 assert(mcast_idx < 64);
1693 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1694 /* Multicast frame is allowed in hash table. */
1695 } else if (s->configuration[15] & 1) {
1696 /* Promiscuous: receive all. */
1697 rfd_status |= 0x0004;
1698 } else {
1699 TRACE(RXTX, logout("%p multicast ignored\n", s));
1700 return -1;
1701 }
663e8e51 1702 }
7b8737de 1703 /* TODO: Next not for promiscuous mode? */
663e8e51
TS		 1704 rfd_status |= 0x0002;
1705 } else if (s->configuration[15] & 1) {
1706 /* Promiscuous: receive all. */
067d01de 1707 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
663e8e51
TS		 1708 rfd_status |= 0x0004;
1709 } else {
067d01de 1710 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
aac443e6 1711 nic_dump(buf, size)));
4f1c942b 1712 return size;
663e8e51
TS		 1713 }
1714
1715 if (get_ru_state(s) != ru_ready) {
aac443e6
SW		 1716 /* No resources available. */
1717 logout("no resources, state=%u\n", get_ru_state(s));
663e8e51 1718 s->statistics.rx_resource_errors++;
aac443e6 1719 //~ assert(!"no resources");
4f1c942b 1720 return -1;
663e8e51
TS		 1721 }
1722 //~ !!!
1723//~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
c227f099 1724 eepro100_rx_t rx;
663e8e51 1725 cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
c227f099 1726 offsetof(eepro100_rx_t, packet));
663e8e51
TS		 1727 uint16_t rfd_command = le16_to_cpu(rx.command);
1728 uint16_t rfd_size = le16_to_cpu(rx.size);
7f1e9d4e
KW		 1729
1730 if (size > rfd_size) {
1731 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1732 "(%zu bytes); data truncated\n", rfd_size, size);
1733 size = rfd_size;
1734 }
663e8e51
TS		 1735 if (size < 64) {
1736 rfd_status |= 0x0080;
1737 }
aac443e6
SW		 1738 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1739 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
c227f099 1740 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
663e8e51 1741 rfd_status);
c227f099 1742 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
663e8e51
TS		 1743 /* Early receive interrupt not supported. */
1744 //~ eepro100_er_interrupt(s);
1745 /* Receive CRC Transfer not supported. */
7f1e9d4e
KW		 1746 if (s->configuration[18] & 4) {
1747 missing("Receive CRC Transfer");
1748 return -1;
1749 }
663e8e51
TS		 1750 /* TODO: check stripping enable bit. */
1751 //~ assert(!(s->configuration[17] & 1));
1752 cpu_physical_memory_write(s->ru_base + s->ru_offset +
c227f099 1753 offsetof(eepro100_rx_t, packet), buf, size);
663e8e51
TS		 1754 s->statistics.rx_good_frames++;
1755 eepro100_fr_interrupt(s);
1756 s->ru_offset = le32_to_cpu(rx.link);
1757 if (rfd_command & 0x8000) {
1758 /* EL bit is set, so this was the last frame. */
7f1e9d4e
KW		 1759 logout("receive: Running out of frames\n");
1760 set_ru_state(s, ru_suspended);
663e8e51
TS		 1761 }
1762 if (rfd_command & 0x4000) {
1763 /* S bit is set. */
1764 set_ru_state(s, ru_suspended);
1765 }
4f1c942b 1766 return size;
663e8e51
TS		 1767}
1768
151b2986
JQ		 1769static const VMStateDescription vmstate_eepro100 = {
1770 .version_id = 3,
1771 .minimum_version_id = 2,
1772 .minimum_version_id_old = 2,
1773 .fields = (VMStateField []) {
1774 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1775 VMSTATE_UNUSED(32),
1776 VMSTATE_BUFFER(mult, EEPRO100State),
1777 VMSTATE_BUFFER(mem, EEPRO100State),
1778 /* Save all members of struct between scb_stat and mem. */
1779 VMSTATE_UINT8(scb_stat, EEPRO100State),
1780 VMSTATE_UINT8(int_stat, EEPRO100State),
1781 VMSTATE_UNUSED(3*4),
1782 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1783 VMSTATE_UNUSED(19*4),
1784 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1785 /* The eeprom should be saved and restored by its own routines. */
1786 VMSTATE_UINT32(device, EEPRO100State),
1787 /* TODO check device. */
1788 VMSTATE_UINT32(pointer, EEPRO100State),
1789 VMSTATE_UINT32(cu_base, EEPRO100State),
1790 VMSTATE_UINT32(cu_offset, EEPRO100State),
1791 VMSTATE_UINT32(ru_base, EEPRO100State),
1792 VMSTATE_UINT32(ru_offset, EEPRO100State),
1793 VMSTATE_UINT32(statsaddr, EEPRO100State),
ba42b646 1794 /* Save eepro100_stats_t statistics. */
151b2986
JQ		 1795 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1796 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1797 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1798 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1799 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1800 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1801 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1802 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1803 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1804 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1805 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1806 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1807 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1808 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1809 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1810 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1811 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1812 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1813 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1814 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1815 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
2657c663 1816#if 0
151b2986 1817 VMSTATE_UINT16(status, EEPRO100State),
2657c663 1818#endif
151b2986
JQ		 1819 /* Configuration bytes. */
1820 VMSTATE_BUFFER(configuration, EEPRO100State),
1821 VMSTATE_END_OF_LIST()
aac443e6 1822 }
151b2986 1823};
663e8e51 1824
e00e365e 1825static void nic_cleanup(VLANClientState *nc)
b946a153 1826{
e00e365e 1827 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
b946a153 1828
e00e365e 1829 s->nic = NULL;
b946a153
AL		 1830}
1831
c4c270e2 1832static int pci_nic_uninit(PCIDevice *pci_dev)
b946a153 1833{
c4c270e2 1834 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
b946a153
AL		 1835
1836 cpu_unregister_io_memory(s->mmio_index);
151b2986 1837 vmstate_unregister(s->vmstate, s);
508ef936 1838 eeprom93xx_free(s->eeprom);
e00e365e 1839 qemu_del_vlan_client(&s->nic->nc);
b946a153
AL		 1840 return 0;
1841}
1842
e00e365e
MM		 1843static NetClientInfo net_eepro100_info = {
1844 .type = NET_CLIENT_TYPE_NIC,
1845 .size = sizeof(NICState),
1846 .can_receive = nic_can_receive,
1847 .receive = nic_receive,
1848 .cleanup = nic_cleanup,
1849};
1850
81a322d4 1851static int nic_init(PCIDevice *pci_dev, uint32_t device)
663e8e51 1852{
273a2142 1853 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
663e8e51 1854
aac443e6 1855 TRACE(OTHER, logout("\n"));
663e8e51 1856
663e8e51 1857 s->device = device;
663e8e51
TS		 1858
1859 pci_reset(s);
1860
1861 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1862 * i82559 and later support 64 or 256 word EEPROM. */
1863 s->eeprom = eeprom93xx_new(EEPROM_SIZE);
1864
1865 /* Handler for memory-mapped I/O */
273a2142 1866 s->mmio_index =
1eed09cb 1867 cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s);
663e8e51 1868
273a2142 1869 pci_register_bar(&s->dev, 0, PCI_MEM_SIZE,
0392a017
IY		 1870 PCI_BASE_ADDRESS_SPACE_MEMORY |
1871 PCI_BASE_ADDRESS_MEM_PREFETCH, pci_mmio_map);
1872 pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
663e8e51 1873 pci_map);
0392a017 1874 pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
663e8e51
TS		 1875 pci_mmio_map);
1876
508ef936 1877 qemu_macaddr_default_if_unset(&s->conf.macaddr);
663e8e51
TS		 1878 logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6));
1879 assert(s->region[1] == 0);
1880
1881 nic_reset(s);
1882
e00e365e
MM		 1883 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
1884 pci_dev->qdev.info->name, pci_dev->qdev.id, s);
663e8e51 1885
e00e365e
MM		 1886 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1887 TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
663e8e51 1888
a08d4367 1889 qemu_register_reset(nic_reset, s);
663e8e51 1890
151b2986
JQ		 1891 s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
1892 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
e00e365e 1893 s->vmstate->name = s->nic->nc.model;
151b2986 1894 vmstate_register(-1, s->vmstate, s);
4e9df06a 1895
81a322d4 1896 return 0;
663e8e51
TS		 1897}
1898
c4c270e2
SW		 1899static int pci_i82550_init(PCIDevice *pci_dev)
1900{
1901 return nic_init(pci_dev, i82550);
1902}
1903
1904static int pci_i82551_init(PCIDevice *pci_dev)
1905{
1906 return nic_init(pci_dev, i82551);
1907}
1908
1909static int pci_i82557a_init(PCIDevice *pci_dev)
1910{
1911 return nic_init(pci_dev, i82557A);
1912}
1913
1914static int pci_i82557b_init(PCIDevice *pci_dev)
1915{
1916 return nic_init(pci_dev, i82557B);
1917}
1918
1919static int pci_i82557c_init(PCIDevice *pci_dev)
1920{
1921 return nic_init(pci_dev, i82557C);
1922}
1923
1924static int pci_i82558a_init(PCIDevice *pci_dev)
1925{
1926 return nic_init(pci_dev, i82558A);
1927}
1928
1929static int pci_i82558b_init(PCIDevice *pci_dev)
1930{
1931 return nic_init(pci_dev, i82558B);
1932}
1933
1934static int pci_i82559a_init(PCIDevice *pci_dev)
1935{
1936 return nic_init(pci_dev, i82559A);
1937}
1938
1939static int pci_i82559b_init(PCIDevice *pci_dev)
1940{
1941 return nic_init(pci_dev, i82559B);
1942}
1943
1944static int pci_i82559c_init(PCIDevice *pci_dev)
9d07d757 1945{
c4c270e2 1946 return nic_init(pci_dev, i82559C);
9d07d757
PB		 1947}
1948
c4c270e2 1949static int pci_i82559er_init(PCIDevice *pci_dev)
663e8e51 1950{
c4c270e2 1951 return nic_init(pci_dev, i82559ER);
663e8e51
TS		 1952}
1953
c4c270e2 1954static int pci_i82562_init(PCIDevice *pci_dev)
663e8e51 1955{
c4c270e2 1956 return nic_init(pci_dev, i82562);
663e8e51
TS		 1957}
1958
0aab0d3a
GH		 1959static PCIDeviceInfo eepro100_info[] = {
1960 {
c4c270e2
SW		 1961 .qdev.name = "i82550",
1962 .qdev.size = sizeof(EEPRO100State),
1963 .init = pci_i82550_init,
6a90e308 1964 .exit = pci_nic_uninit,
508ef936
GH		 1965 .qdev.props = (Property[]) {
1966 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1967 DEFINE_PROP_END_OF_LIST(),
1968 },
c4c270e2 1969 },{
0aab0d3a 1970 .qdev.name = "i82551",
273a2142 1971 .qdev.size = sizeof(EEPRO100State),
0aab0d3a 1972 .init = pci_i82551_init,
e3936fa5 1973 .exit = pci_nic_uninit,
508ef936
GH		 1974 .qdev.props = (Property[]) {
1975 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1976 DEFINE_PROP_END_OF_LIST(),
1977 },
c4c270e2
SW		 1978 },{
1979 .qdev.name = "i82557a",
1980 .qdev.size = sizeof(EEPRO100State),
1981 .init = pci_i82557a_init,
6a90e308 1982 .exit = pci_nic_uninit,
508ef936
GH		 1983 .qdev.props = (Property[]) {
1984 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1985 DEFINE_PROP_END_OF_LIST(),
1986 },
0aab0d3a
GH		 1987 },{
1988 .qdev.name = "i82557b",
273a2142 1989 .qdev.size = sizeof(EEPRO100State),
0aab0d3a 1990 .init = pci_i82557b_init,
e3936fa5 1991 .exit = pci_nic_uninit,
508ef936
GH		 1992 .qdev.props = (Property[]) {
1993 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1994 DEFINE_PROP_END_OF_LIST(),
1995 },
c4c270e2
SW		 1996 },{
1997 .qdev.name = "i82557c",
1998 .qdev.size = sizeof(EEPRO100State),
1999 .init = pci_i82557c_init,
6a90e308 2000 .exit = pci_nic_uninit,
508ef936
GH		 2001 .qdev.props = (Property[]) {
2002 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2003 DEFINE_PROP_END_OF_LIST(),
2004 },
c4c270e2
SW		 2005 },{
2006 .qdev.name = "i82558a",
2007 .qdev.size = sizeof(EEPRO100State),
2008 .init = pci_i82558a_init,
6a90e308 2009 .exit = pci_nic_uninit,
508ef936
GH		 2010 .qdev.props = (Property[]) {
2011 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2012 DEFINE_PROP_END_OF_LIST(),
2013 },
c4c270e2
SW		 2014 },{
2015 .qdev.name = "i82558b",
2016 .qdev.size = sizeof(EEPRO100State),
2017 .init = pci_i82558b_init,
6a90e308 2018 .exit = pci_nic_uninit,
508ef936
GH		 2019 .qdev.props = (Property[]) {
2020 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2021 DEFINE_PROP_END_OF_LIST(),
2022 },
c4c270e2
SW		 2023 },{
2024 .qdev.name = "i82559a",
2025 .qdev.size = sizeof(EEPRO100State),
2026 .init = pci_i82559a_init,
6a90e308 2027 .exit = pci_nic_uninit,
508ef936
GH		 2028 .qdev.props = (Property[]) {
2029 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2030 DEFINE_PROP_END_OF_LIST(),
2031 },
c4c270e2
SW		 2032 },{
2033 .qdev.name = "i82559b",
2034 .qdev.size = sizeof(EEPRO100State),
2035 .init = pci_i82559b_init,
6a90e308 2036 .exit = pci_nic_uninit,
508ef936
GH		 2037 .qdev.props = (Property[]) {
2038 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2039 DEFINE_PROP_END_OF_LIST(),
2040 },
c4c270e2
SW		 2041 },{
2042 .qdev.name = "i82559c",
2043 .qdev.size = sizeof(EEPRO100State),
2044 .init = pci_i82559c_init,
6a90e308 2045 .exit = pci_nic_uninit,
508ef936
GH		 2046 .qdev.props = (Property[]) {
2047 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2048 DEFINE_PROP_END_OF_LIST(),
2049 },
0aab0d3a
GH		 2050 },{
2051 .qdev.name = "i82559er",
273a2142 2052 .qdev.size = sizeof(EEPRO100State),
0aab0d3a 2053 .init = pci_i82559er_init,
e3936fa5 2054 .exit = pci_nic_uninit,
938a6324 2055 .romfile = "pxe-i82559er.bin",
508ef936
GH		 2056 .qdev.props = (Property[]) {
2057 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2058 DEFINE_PROP_END_OF_LIST(),
2059 },
c4c270e2
SW		 2060 },{
2061 .qdev.name = "i82562",
2062 .qdev.size = sizeof(EEPRO100State),
2063 .init = pci_i82562_init,
6a90e308 2064 .exit = pci_nic_uninit,
508ef936
GH		 2065 .qdev.props = (Property[]) {
2066 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2067 DEFINE_PROP_END_OF_LIST(),
2068 },
0aab0d3a
GH		 2069 },{
2070 /* end of list */
2071 }
2072};
2073
9d07d757 2074static void eepro100_register_devices(void)
663e8e51 2075{
0aab0d3a 2076 pci_qdev_register_many(eepro100_info);
663e8e51
TS		 2077}
2078
9d07d757 2079device_init(eepro100_register_devices)
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