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663e8e51 TS |
1 | /* |
2 | * QEMU i8255x (PRO100) emulation | |
3 | * | |
4 | * Copyright (c) 2006-2007 Stefan Weil | |
5 | * | |
6 | * Portions of the code are copies from grub / etherboot eepro100.c | |
7 | * and linux e100.c. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
8167ee88 | 20 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
663e8e51 TS |
21 | * |
22 | * Tested features (i82559): | |
23 | * PXE boot (i386) no valid link | |
24 | * Linux networking (i386) ok | |
25 | * | |
26 | * Untested: | |
27 | * non-i386 platforms | |
28 | * Windows networking | |
29 | * | |
30 | * References: | |
31 | * | |
32 | * Intel 8255x 10/100 Mbps Ethernet Controller Family | |
33 | * Open Source Software Developer Manual | |
34 | */ | |
35 | ||
36 | #if defined(TARGET_I386) | |
37 | # warning "PXE boot still not working!" | |
38 | #endif | |
39 | ||
663e8e51 | 40 | #include <stddef.h> /* offsetof */ |
b84a5c6f | 41 | #include <stdbool.h> |
87ecb68b PB |
42 | #include "hw.h" |
43 | #include "pci.h" | |
44 | #include "net.h" | |
663e8e51 TS |
45 | #include "eeprom93xx.h" |
46 | ||
47 | /* Common declarations for all PCI devices. */ | |
48 | ||
663e8e51 TS |
49 | #define PCI_CONFIG_8(offset, value) \ |
50 | (pci_conf[offset] = (value)) | |
51 | #define PCI_CONFIG_16(offset, value) \ | |
52 | (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value)) | |
53 | #define PCI_CONFIG_32(offset, value) \ | |
54 | (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value)) | |
55 | ||
56 | #define KiB 1024 | |
57 | ||
aac443e6 | 58 | /* Debug EEPRO100 card. */ |
663e8e51 TS |
59 | //~ #define DEBUG_EEPRO100 |
60 | ||
61 | #ifdef DEBUG_EEPRO100 | |
001faf32 | 62 | #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__) |
663e8e51 | 63 | #else |
001faf32 | 64 | #define logout(fmt, ...) ((void)0) |
663e8e51 TS |
65 | #endif |
66 | ||
67 | /* Set flags to 0 to disable debug output. */ | |
aac443e6 SW |
68 | #define INT 1 /* interrupt related actions */ |
69 | #define MDI 1 /* mdi related actions */ | |
70 | #define OTHER 1 | |
71 | #define RXTX 1 | |
72 | #define EEPROM 1 /* eeprom related actions */ | |
663e8e51 TS |
73 | |
74 | #define TRACE(flag, command) ((flag) ? (command) : (void)0) | |
75 | ||
7f1e9d4e | 76 | #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n") |
663e8e51 TS |
77 | |
78 | #define MAX_ETH_FRAME_SIZE 1514 | |
79 | ||
80 | /* This driver supports several different devices which are declared here. */ | |
c4c270e2 | 81 | #define i82550 0x82550 |
663e8e51 | 82 | #define i82551 0x82551 |
c4c270e2 | 83 | #define i82557A 0x82557a |
663e8e51 TS |
84 | #define i82557B 0x82557b |
85 | #define i82557C 0x82557c | |
c4c270e2 | 86 | #define i82558A 0x82558a |
663e8e51 | 87 | #define i82558B 0x82558b |
c4c270e2 SW |
88 | #define i82559A 0x82559a |
89 | #define i82559B 0x82559b | |
663e8e51 TS |
90 | #define i82559C 0x82559c |
91 | #define i82559ER 0x82559e | |
92 | #define i82562 0x82562 | |
93 | ||
aac443e6 | 94 | /* Use 64 word EEPROM. TODO: could be a runtime option. */ |
663e8e51 TS |
95 | #define EEPROM_SIZE 64 |
96 | ||
97 | #define PCI_MEM_SIZE (4 * KiB) | |
98 | #define PCI_IO_SIZE 64 | |
99 | #define PCI_FLASH_SIZE (128 * KiB) | |
100 | ||
101 | #define BIT(n) (1 << (n)) | |
102 | #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) | |
103 | ||
104 | /* The SCB accepts the following controls for the Tx and Rx units: */ | |
105 | #define CU_NOP 0x0000 /* No operation. */ | |
106 | #define CU_START 0x0010 /* CU start. */ | |
107 | #define CU_RESUME 0x0020 /* CU resume. */ | |
108 | #define CU_STATSADDR 0x0040 /* Load dump counters address. */ | |
109 | #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */ | |
110 | #define CU_CMD_BASE 0x0060 /* Load CU base address. */ | |
111 | #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */ | |
112 | #define CU_SRESUME 0x00a0 /* CU static resume. */ | |
113 | ||
114 | #define RU_NOP 0x0000 | |
115 | #define RX_START 0x0001 | |
116 | #define RX_RESUME 0x0002 | |
117 | #define RX_ABORT 0x0004 | |
118 | #define RX_ADDR_LOAD 0x0006 | |
119 | #define RX_RESUMENR 0x0007 | |
120 | #define INT_MASK 0x0100 | |
121 | #define DRVR_INT 0x0200 /* Driver generated interrupt. */ | |
122 | ||
663e8e51 TS |
123 | /* Offsets to the various registers. |
124 | All accesses need not be longword aligned. */ | |
125 | enum speedo_offsets { | |
126 | SCBStatus = 0, | |
127 | SCBAck = 1, | |
128 | SCBCmd = 2, /* Rx/Command Unit command and status. */ | |
129 | SCBIntmask = 3, | |
130 | SCBPointer = 4, /* General purpose pointer. */ | |
131 | SCBPort = 8, /* Misc. commands and operands. */ | |
132 | SCBflash = 12, SCBeeprom = 14, /* EEPROM and flash memory control. */ | |
133 | SCBCtrlMDI = 16, /* MDI interface control. */ | |
134 | SCBEarlyRx = 20, /* Early receive byte count. */ | |
3257d2b6 | 135 | SCBFlow = 24, |
663e8e51 TS |
136 | }; |
137 | ||
138 | /* A speedo3 transmit buffer descriptor with two buffers... */ | |
139 | typedef struct { | |
140 | uint16_t status; | |
141 | uint16_t command; | |
142 | uint32_t link; /* void * */ | |
143 | uint32_t tx_desc_addr; /* transmit buffer decsriptor array address. */ | |
144 | uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */ | |
145 | uint8_t tx_threshold; /* transmit threshold */ | |
146 | uint8_t tbd_count; /* TBD number */ | |
147 | //~ /* This constitutes two "TBD" entries: hdr and data */ | |
148 | //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */ | |
149 | //~ int32_t tx_buf_size0; /* Length of Tx hdr. */ | |
150 | //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */ | |
151 | //~ int32_t tx_buf_size1; /* Length of Tx data. */ | |
c227f099 | 152 | } eepro100_tx_t; |
663e8e51 TS |
153 | |
154 | /* Receive frame descriptor. */ | |
155 | typedef struct { | |
156 | int16_t status; | |
157 | uint16_t command; | |
158 | uint32_t link; /* struct RxFD * */ | |
159 | uint32_t rx_buf_addr; /* void * */ | |
160 | uint16_t count; | |
161 | uint16_t size; | |
162 | char packet[MAX_ETH_FRAME_SIZE + 4]; | |
c227f099 | 163 | } eepro100_rx_t; |
663e8e51 TS |
164 | |
165 | typedef struct { | |
166 | uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions, | |
167 | tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions, | |
168 | tx_multiple_collisions, tx_total_collisions; | |
169 | uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors, | |
170 | rx_resource_errors, rx_overrun_errors, rx_cdt_errors, | |
171 | rx_short_frame_errors; | |
172 | uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported; | |
173 | uint16_t xmt_tco_frames, rcv_tco_frames; | |
174 | uint32_t complete; | |
c227f099 | 175 | } eepro100_stats_t; |
663e8e51 TS |
176 | |
177 | typedef enum { | |
178 | cu_idle = 0, | |
179 | cu_suspended = 1, | |
180 | cu_active = 2, | |
181 | cu_lpq_active = 2, | |
182 | cu_hqp_active = 3 | |
c227f099 | 183 | } cu_state_t; |
663e8e51 TS |
184 | |
185 | typedef enum { | |
186 | ru_idle = 0, | |
187 | ru_suspended = 1, | |
188 | ru_no_resources = 2, | |
189 | ru_ready = 4 | |
c227f099 | 190 | } ru_state_t; |
663e8e51 | 191 | |
663e8e51 | 192 | typedef struct { |
273a2142 | 193 | PCIDevice dev; |
663e8e51 TS |
194 | uint8_t mult[8]; /* multicast mask array */ |
195 | int mmio_index; | |
663e8e51 | 196 | VLANClientState *vc; |
508ef936 | 197 | NICConf conf; |
663e8e51 TS |
198 | uint8_t scb_stat; /* SCB stat/ack byte */ |
199 | uint8_t int_stat; /* PCI interrupt status */ | |
3706c43f | 200 | /* region must not be saved by nic_save. */ |
663e8e51 | 201 | uint32_t region[3]; /* PCI region addresses */ |
663e8e51 | 202 | uint16_t mdimem[32]; |
c227f099 | 203 | eeprom_t *eeprom; |
663e8e51 TS |
204 | uint32_t device; /* device variant */ |
205 | uint32_t pointer; | |
206 | /* (cu_base + cu_offset) address the next command block in the command block list. */ | |
207 | uint32_t cu_base; /* CU base address */ | |
208 | uint32_t cu_offset; /* CU address offset */ | |
209 | /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */ | |
210 | uint32_t ru_base; /* RU base address */ | |
211 | uint32_t ru_offset; /* RU address offset */ | |
c227f099 | 212 | uint32_t statsaddr; /* pointer to eepro100_stats_t */ |
4e3db917 | 213 | eepro100_stats_t statistics; /* statistical counters */ |
663e8e51 TS |
214 | #if 0 |
215 | uint16_t status; | |
216 | #endif | |
217 | ||
218 | /* Configuration bytes. */ | |
219 | uint8_t configuration[22]; | |
220 | ||
221 | /* Data in mem is always in the byte order of the controller (le). */ | |
222 | uint8_t mem[PCI_MEM_SIZE]; | |
151b2986 JQ |
223 | /* vmstate for each particular nic */ |
224 | VMStateDescription *vmstate; | |
663e8e51 TS |
225 | } EEPRO100State; |
226 | ||
227 | /* Default values for MDI (PHY) registers */ | |
228 | static const uint16_t eepro100_mdi_default[] = { | |
229 | /* MDI Registers 0 - 6, 7 */ | |
230 | 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000, | |
231 | /* MDI Registers 8 - 15 */ | |
232 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
233 | /* MDI Registers 16 - 31 */ | |
234 | 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
235 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
236 | }; | |
237 | ||
238 | /* Readonly mask for MDI (PHY) registers */ | |
239 | static const uint16_t eepro100_mdi_mask[] = { | |
240 | 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000, | |
241 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
242 | 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, | |
243 | 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
244 | }; | |
245 | ||
246 | #define POLYNOMIAL 0x04c11db6 | |
247 | ||
248 | /* From FreeBSD */ | |
249 | /* XXX: optimize */ | |
250 | static int compute_mcast_idx(const uint8_t * ep) | |
251 | { | |
252 | uint32_t crc; | |
253 | int carry, i, j; | |
254 | uint8_t b; | |
255 | ||
256 | crc = 0xffffffff; | |
257 | for (i = 0; i < 6; i++) { | |
258 | b = *ep++; | |
259 | for (j = 0; j < 8; j++) { | |
260 | carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); | |
261 | crc <<= 1; | |
262 | b >>= 1; | |
aac443e6 | 263 | if (carry) { |
663e8e51 | 264 | crc = ((crc ^ POLYNOMIAL) | carry); |
aac443e6 | 265 | } |
663e8e51 TS |
266 | } |
267 | } | |
268 | return (crc >> 26); | |
269 | } | |
270 | ||
271 | #if defined(DEBUG_EEPRO100) | |
272 | static const char *nic_dump(const uint8_t * buf, unsigned size) | |
273 | { | |
274 | static char dump[3 * 16 + 1]; | |
275 | char *p = &dump[0]; | |
aac443e6 | 276 | if (size > 16) { |
663e8e51 | 277 | size = 16; |
aac443e6 | 278 | } |
663e8e51 TS |
279 | while (size-- > 0) { |
280 | p += sprintf(p, " %02x", *buf++); | |
281 | } | |
282 | return dump; | |
283 | } | |
284 | #endif /* DEBUG_EEPRO100 */ | |
285 | ||
286 | enum scb_stat_ack { | |
287 | stat_ack_not_ours = 0x00, | |
288 | stat_ack_sw_gen = 0x04, | |
289 | stat_ack_rnr = 0x10, | |
290 | stat_ack_cu_idle = 0x20, | |
291 | stat_ack_frame_rx = 0x40, | |
292 | stat_ack_cu_cmd_done = 0x80, | |
293 | stat_ack_not_present = 0xFF, | |
294 | stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx), | |
295 | stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done), | |
296 | }; | |
297 | ||
298 | static void disable_interrupt(EEPRO100State * s) | |
299 | { | |
300 | if (s->int_stat) { | |
aac443e6 | 301 | TRACE(INT, logout("interrupt disabled\n")); |
273a2142 | 302 | qemu_irq_lower(s->dev.irq[0]); |
663e8e51 TS |
303 | s->int_stat = 0; |
304 | } | |
305 | } | |
306 | ||
307 | static void enable_interrupt(EEPRO100State * s) | |
308 | { | |
309 | if (!s->int_stat) { | |
aac443e6 | 310 | TRACE(INT, logout("interrupt enabled\n")); |
273a2142 | 311 | qemu_irq_raise(s->dev.irq[0]); |
663e8e51 TS |
312 | s->int_stat = 1; |
313 | } | |
314 | } | |
315 | ||
316 | static void eepro100_acknowledge(EEPRO100State * s) | |
317 | { | |
318 | s->scb_stat &= ~s->mem[SCBAck]; | |
319 | s->mem[SCBAck] = s->scb_stat; | |
320 | if (s->scb_stat == 0) { | |
321 | disable_interrupt(s); | |
322 | } | |
323 | } | |
324 | ||
325 | static void eepro100_interrupt(EEPRO100State * s, uint8_t stat) | |
326 | { | |
327 | uint8_t mask = ~s->mem[SCBIntmask]; | |
328 | s->mem[SCBAck] |= stat; | |
329 | stat = s->scb_stat = s->mem[SCBAck]; | |
330 | stat &= (mask | 0x0f); | |
331 | //~ stat &= (~s->mem[SCBIntmask] | 0x0xf); | |
332 | if (stat && (mask & 0x01)) { | |
333 | /* SCB mask and SCB Bit M do not disable interrupt. */ | |
334 | enable_interrupt(s); | |
335 | } else if (s->int_stat) { | |
336 | disable_interrupt(s); | |
337 | } | |
338 | } | |
339 | ||
340 | static void eepro100_cx_interrupt(EEPRO100State * s) | |
341 | { | |
342 | /* CU completed action command. */ | |
343 | /* Transmit not ok (82557 only, not in emulation). */ | |
344 | eepro100_interrupt(s, 0x80); | |
345 | } | |
346 | ||
347 | static void eepro100_cna_interrupt(EEPRO100State * s) | |
348 | { | |
349 | /* CU left the active state. */ | |
350 | eepro100_interrupt(s, 0x20); | |
351 | } | |
352 | ||
353 | static void eepro100_fr_interrupt(EEPRO100State * s) | |
354 | { | |
355 | /* RU received a complete frame. */ | |
356 | eepro100_interrupt(s, 0x40); | |
357 | } | |
358 | ||
359 | #if 0 | |
360 | static void eepro100_rnr_interrupt(EEPRO100State * s) | |
361 | { | |
362 | /* RU is not ready. */ | |
363 | eepro100_interrupt(s, 0x10); | |
364 | } | |
365 | #endif | |
366 | ||
367 | static void eepro100_mdi_interrupt(EEPRO100State * s) | |
368 | { | |
369 | /* MDI completed read or write cycle. */ | |
370 | eepro100_interrupt(s, 0x08); | |
371 | } | |
372 | ||
373 | static void eepro100_swi_interrupt(EEPRO100State * s) | |
374 | { | |
375 | /* Software has requested an interrupt. */ | |
376 | eepro100_interrupt(s, 0x04); | |
377 | } | |
378 | ||
379 | #if 0 | |
380 | static void eepro100_fcp_interrupt(EEPRO100State * s) | |
381 | { | |
382 | /* Flow control pause interrupt (82558 and later). */ | |
383 | eepro100_interrupt(s, 0x01); | |
384 | } | |
385 | #endif | |
386 | ||
387 | static void pci_reset(EEPRO100State * s) | |
388 | { | |
389 | uint32_t device = s->device; | |
273a2142 | 390 | uint8_t *pci_conf = s->dev.config; |
663e8e51 | 391 | |
aac443e6 | 392 | TRACE(OTHER, logout("%p\n", s)); |
663e8e51 TS |
393 | |
394 | /* PCI Vendor ID */ | |
deb54399 | 395 | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
d6fd1e66 | 396 | /* PCI Device ID depends on device and is set below. */ |
663e8e51 TS |
397 | /* PCI Command */ |
398 | PCI_CONFIG_16(PCI_COMMAND, 0x0000); | |
399 | /* PCI Status */ | |
400 | PCI_CONFIG_16(PCI_STATUS, 0x2800); | |
401 | /* PCI Revision ID */ | |
402 | PCI_CONFIG_8(PCI_REVISION_ID, 0x08); | |
403 | /* PCI Class Code */ | |
404 | PCI_CONFIG_8(0x09, 0x00); | |
173a543b | 405 | pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); |
663e8e51 TS |
406 | /* PCI Cache Line Size */ |
407 | /* check cache line size!!! */ | |
408 | //~ PCI_CONFIG_8(0x0c, 0x00); | |
409 | /* PCI Latency Timer */ | |
410 | PCI_CONFIG_8(0x0d, 0x20); // latency timer = 32 clocks | |
411 | /* PCI Header Type */ | |
412 | /* BIST (built-in self test) */ | |
413 | #if defined(TARGET_I386) | |
414 | // !!! workaround for buggy bios | |
415 | //~ #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0 | |
416 | #endif | |
417 | #if 0 | |
418 | /* PCI Base Address Registers */ | |
419 | /* CSR Memory Mapped Base Address */ | |
420 | PCI_CONFIG_32(PCI_BASE_ADDRESS_0, | |
421 | PCI_ADDRESS_SPACE_MEM | PCI_ADDRESS_SPACE_MEM_PREFETCH); | |
422 | /* CSR I/O Mapped Base Address */ | |
423 | PCI_CONFIG_32(PCI_BASE_ADDRESS_1, PCI_ADDRESS_SPACE_IO); | |
424 | #if 0 | |
425 | /* Flash Memory Mapped Base Address */ | |
426 | PCI_CONFIG_32(PCI_BASE_ADDRESS_2, 0xfffe0000 | PCI_ADDRESS_SPACE_MEM); | |
427 | #endif | |
428 | #endif | |
429 | /* Expansion ROM Base Address (depends on boot disable!!!) */ | |
430 | PCI_CONFIG_32(0x30, 0x00000000); | |
431 | /* Capability Pointer */ | |
432 | PCI_CONFIG_8(0x34, 0xdc); | |
aac443e6 | 433 | /* Interrupt Line */ |
663e8e51 TS |
434 | /* Interrupt Pin */ |
435 | PCI_CONFIG_8(0x3d, 1); // interrupt pin 0 | |
436 | /* Minimum Grant */ | |
437 | PCI_CONFIG_8(0x3e, 0x08); | |
438 | /* Maximum Latency */ | |
439 | PCI_CONFIG_8(0x3f, 0x18); | |
440 | /* Power Management Capabilities / Next Item Pointer / Capability ID */ | |
441 | PCI_CONFIG_32(0xdc, 0x7e210001); | |
442 | ||
443 | switch (device) { | |
444 | case i82551: | |
d6fd1e66 | 445 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); |
663e8e51 TS |
446 | PCI_CONFIG_8(PCI_REVISION_ID, 0x0f); |
447 | break; | |
448 | case i82557B: | |
d6fd1e66 | 449 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
663e8e51 TS |
450 | PCI_CONFIG_8(PCI_REVISION_ID, 0x02); |
451 | break; | |
452 | case i82557C: | |
d6fd1e66 | 453 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
663e8e51 TS |
454 | PCI_CONFIG_8(PCI_REVISION_ID, 0x03); |
455 | break; | |
456 | case i82558B: | |
d6fd1e66 | 457 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
663e8e51 TS |
458 | PCI_CONFIG_16(PCI_STATUS, 0x2810); |
459 | PCI_CONFIG_8(PCI_REVISION_ID, 0x05); | |
460 | break; | |
461 | case i82559C: | |
d6fd1e66 | 462 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
663e8e51 TS |
463 | PCI_CONFIG_16(PCI_STATUS, 0x2810); |
464 | //~ PCI_CONFIG_8(PCI_REVISION_ID, 0x08); | |
465 | break; | |
466 | case i82559ER: | |
d6fd1e66 | 467 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); |
663e8e51 TS |
468 | PCI_CONFIG_16(PCI_STATUS, 0x2810); |
469 | PCI_CONFIG_8(PCI_REVISION_ID, 0x09); | |
470 | break; | |
471 | //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1029); | |
472 | //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1030); /* 82559 InBusiness 10/100 */ | |
473 | default: | |
474 | logout("Device %X is undefined!\n", device); | |
475 | } | |
476 | ||
477 | if (device == i82557C || device == i82558B || device == i82559C) { | |
478 | logout("Get device id and revision from EEPROM!!!\n"); | |
479 | } | |
480 | } | |
481 | ||
482 | static void nic_selective_reset(EEPRO100State * s) | |
483 | { | |
484 | size_t i; | |
485 | uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom); | |
486 | //~ eeprom93xx_reset(s->eeprom); | |
508ef936 | 487 | memcpy(eeprom_contents, s->conf.macaddr.a, 6); |
663e8e51 | 488 | eeprom_contents[0xa] = 0x4000; |
f4e94dfe RD |
489 | if (s->device == i82557B || s->device == i82557C) |
490 | eeprom_contents[5] = 0x0100; | |
663e8e51 TS |
491 | uint16_t sum = 0; |
492 | for (i = 0; i < EEPROM_SIZE - 1; i++) { | |
493 | sum += eeprom_contents[i]; | |
494 | } | |
495 | eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum; | |
aac443e6 | 496 | TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1])); |
663e8e51 TS |
497 | |
498 | memset(s->mem, 0, sizeof(s->mem)); | |
499 | uint32_t val = BIT(21); | |
500 | memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val)); | |
501 | ||
502 | assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default)); | |
503 | memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem)); | |
504 | } | |
505 | ||
506 | static void nic_reset(void *opaque) | |
507 | { | |
769cf7a5 | 508 | EEPRO100State *s = opaque; |
aac443e6 | 509 | TRACE(OTHER, logout("%p\n", s)); |
663e8e51 TS |
510 | nic_selective_reset(s); |
511 | } | |
512 | ||
513 | #if defined(DEBUG_EEPRO100) | |
6a0b9cc9 | 514 | static const char * const reg[PCI_IO_SIZE / 4] = { |
663e8e51 TS |
515 | "Command/Status", |
516 | "General Pointer", | |
517 | "Port", | |
518 | "EEPROM/Flash Control", | |
519 | "MDI Control", | |
520 | "Receive DMA Byte Count", | |
aac443e6 | 521 | "Flow control", |
663e8e51 TS |
522 | "General Status/Control" |
523 | }; | |
524 | ||
525 | static char *regname(uint32_t addr) | |
526 | { | |
527 | static char buf[16]; | |
528 | if (addr < PCI_IO_SIZE) { | |
529 | const char *r = reg[addr / 4]; | |
530 | if (r != 0) { | |
41cbc23c | 531 | snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4); |
663e8e51 | 532 | } else { |
41cbc23c | 533 | snprintf(buf, sizeof(buf), "0x%02x", addr); |
663e8e51 TS |
534 | } |
535 | } else { | |
41cbc23c | 536 | snprintf(buf, sizeof(buf), "??? 0x%08x", addr); |
663e8e51 TS |
537 | } |
538 | return buf; | |
539 | } | |
540 | #endif /* DEBUG_EEPRO100 */ | |
541 | ||
542 | #if 0 | |
543 | static uint16_t eepro100_read_status(EEPRO100State * s) | |
544 | { | |
545 | uint16_t val = s->status; | |
aac443e6 | 546 | TRACE(OTHER, logout("val=0x%04x\n", val)); |
663e8e51 TS |
547 | return val; |
548 | } | |
549 | ||
550 | static void eepro100_write_status(EEPRO100State * s, uint16_t val) | |
551 | { | |
aac443e6 | 552 | TRACE(OTHER, logout("val=0x%04x\n", val)); |
663e8e51 TS |
553 | s->status = val; |
554 | } | |
555 | #endif | |
556 | ||
557 | /***************************************************************************** | |
558 | * | |
559 | * Command emulation. | |
560 | * | |
561 | ****************************************************************************/ | |
562 | ||
563 | #if 0 | |
564 | static uint16_t eepro100_read_command(EEPRO100State * s) | |
565 | { | |
566 | uint16_t val = 0xffff; | |
aac443e6 | 567 | //~ TRACE(OTHER, logout("val=0x%04x\n", val)); |
663e8e51 TS |
568 | return val; |
569 | } | |
570 | #endif | |
571 | ||
0859df68 NS |
572 | static bool device_supports_eTxCB(EEPRO100State * s) |
573 | { | |
574 | return (s->device != i82557B && s->device != i82557C); | |
575 | } | |
576 | ||
663e8e51 TS |
577 | /* Commands that can be put in a command list entry. */ |
578 | enum commands { | |
579 | CmdNOp = 0, | |
580 | CmdIASetup = 1, | |
581 | CmdConfigure = 2, | |
582 | CmdMulticastList = 3, | |
583 | CmdTx = 4, | |
584 | CmdTDR = 5, /* load microcode */ | |
585 | CmdDump = 6, | |
586 | CmdDiagnose = 7, | |
587 | ||
588 | /* And some extra flags: */ | |
589 | CmdSuspend = 0x4000, /* Suspend after completion. */ | |
590 | CmdIntr = 0x2000, /* Interrupt after completion. */ | |
591 | CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */ | |
592 | }; | |
593 | ||
c227f099 | 594 | static cu_state_t get_cu_state(EEPRO100State * s) |
663e8e51 TS |
595 | { |
596 | return ((s->mem[SCBStatus] >> 6) & 0x03); | |
597 | } | |
598 | ||
c227f099 | 599 | static void set_cu_state(EEPRO100State * s, cu_state_t state) |
663e8e51 TS |
600 | { |
601 | s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6); | |
602 | } | |
603 | ||
c227f099 | 604 | static ru_state_t get_ru_state(EEPRO100State * s) |
663e8e51 TS |
605 | { |
606 | return ((s->mem[SCBStatus] >> 2) & 0x0f); | |
607 | } | |
608 | ||
c227f099 | 609 | static void set_ru_state(EEPRO100State * s, ru_state_t state) |
663e8e51 TS |
610 | { |
611 | s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2); | |
612 | } | |
613 | ||
614 | static void dump_statistics(EEPRO100State * s) | |
615 | { | |
616 | /* Dump statistical data. Most data is never changed by the emulation | |
617 | * and always 0, so we first just copy the whole block and then those | |
618 | * values which really matter. | |
619 | * Number of data should check configuration!!! | |
620 | */ | |
621 | cpu_physical_memory_write(s->statsaddr, (uint8_t *) & s->statistics, 64); | |
622 | stl_phys(s->statsaddr + 0, s->statistics.tx_good_frames); | |
623 | stl_phys(s->statsaddr + 36, s->statistics.rx_good_frames); | |
624 | stl_phys(s->statsaddr + 48, s->statistics.rx_resource_errors); | |
625 | stl_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors); | |
626 | //~ stw_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames); | |
627 | //~ stw_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames); | |
628 | //~ missing("CU dump statistical counters"); | |
629 | } | |
630 | ||
5fa9a0ae | 631 | static void action_command(EEPRO100State *s) |
663e8e51 | 632 | { |
5fa9a0ae SW |
633 | for (;;) { |
634 | uint32_t cb_address = s->cu_base + s->cu_offset; | |
635 | eepro100_tx_t tx; | |
663e8e51 TS |
636 | cpu_physical_memory_read(cb_address, (uint8_t *) & tx, sizeof(tx)); |
637 | uint16_t status = le16_to_cpu(tx.status); | |
638 | uint16_t command = le16_to_cpu(tx.command); | |
639 | logout | |
640 | ("val=0x%02x (cu start), status=0x%04x, command=0x%04x, link=0x%08x\n", | |
641 | val, status, command, tx.link); | |
642 | bool bit_el = ((command & 0x8000) != 0); | |
643 | bool bit_s = ((command & 0x4000) != 0); | |
644 | bool bit_i = ((command & 0x2000) != 0); | |
645 | bool bit_nc = ((command & 0x0010) != 0); | |
7f1e9d4e | 646 | bool success = true; |
663e8e51 TS |
647 | //~ bool bit_sf = ((command & 0x0008) != 0); |
648 | uint16_t cmd = command & 0x0007; | |
649 | s->cu_offset = le32_to_cpu(tx.link); | |
650 | switch (cmd) { | |
651 | case CmdNOp: | |
652 | /* Do nothing. */ | |
653 | break; | |
654 | case CmdIASetup: | |
508ef936 | 655 | cpu_physical_memory_read(cb_address + 8, &s->conf.macaddr.a[0], 6); |
aac443e6 | 656 | TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6))); |
663e8e51 TS |
657 | break; |
658 | case CmdConfigure: | |
659 | cpu_physical_memory_read(cb_address + 8, &s->configuration[0], | |
660 | sizeof(s->configuration)); | |
aac443e6 | 661 | TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16))); |
663e8e51 TS |
662 | break; |
663 | case CmdMulticastList: | |
664 | //~ missing("multicast list"); | |
665 | break; | |
666 | case CmdTx: | |
667 | (void)0; | |
668 | uint32_t tbd_array = le32_to_cpu(tx.tx_desc_addr); | |
669 | uint16_t tcb_bytes = (le16_to_cpu(tx.tcb_bytes) & 0x3fff); | |
aac443e6 | 670 | TRACE(RXTX, logout |
663e8e51 | 671 | ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n", |
aac443e6 | 672 | tbd_array, tcb_bytes, tx.tbd_count)); |
7f1e9d4e KW |
673 | |
674 | if (bit_nc) { | |
675 | missing("CmdTx: NC = 0"); | |
676 | success = false; | |
677 | break; | |
678 | } | |
663e8e51 | 679 | //~ assert(!bit_sf); |
7f1e9d4e KW |
680 | if (tcb_bytes > 2600) { |
681 | logout("TCB byte count too large, using 2600\n"); | |
682 | tcb_bytes = 2600; | |
683 | } | |
663e8e51 TS |
684 | /* Next assertion fails for local configuration. */ |
685 | //~ assert((tcb_bytes > 0) || (tbd_array != 0xffffffff)); | |
686 | if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) { | |
687 | logout | |
688 | ("illegal values of TBD array address and TCB byte count!\n"); | |
689 | } | |
24e6f355 RD |
690 | // sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes |
691 | uint8_t buf[2600]; | |
663e8e51 TS |
692 | uint16_t size = 0; |
693 | uint32_t tbd_address = cb_address + 0x10; | |
694 | assert(tcb_bytes <= sizeof(buf)); | |
695 | while (size < tcb_bytes) { | |
696 | uint32_t tx_buffer_address = ldl_phys(tbd_address); | |
697 | uint16_t tx_buffer_size = lduw_phys(tbd_address + 4); | |
698 | //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); | |
699 | tbd_address += 8; | |
aac443e6 | 700 | TRACE(RXTX, logout |
663e8e51 | 701 | ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n", |
aac443e6 | 702 | tx_buffer_address, tx_buffer_size)); |
24e6f355 | 703 | tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); |
663e8e51 TS |
704 | cpu_physical_memory_read(tx_buffer_address, &buf[size], |
705 | tx_buffer_size); | |
706 | size += tx_buffer_size; | |
707 | } | |
708 | if (tbd_array == 0xffffffff) { | |
709 | /* Simplified mode. Was already handled by code above. */ | |
710 | } else { | |
711 | /* Flexible mode. */ | |
712 | uint8_t tbd_count = 0; | |
0859df68 | 713 | if (device_supports_eTxCB(s) && !(s->configuration[6] & BIT(4))) { |
3f9cb1c1 | 714 | /* Extended Flexible TCB. */ |
663e8e51 TS |
715 | for (; tbd_count < 2; tbd_count++) { |
716 | uint32_t tx_buffer_address = ldl_phys(tbd_address); | |
717 | uint16_t tx_buffer_size = lduw_phys(tbd_address + 4); | |
718 | uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); | |
719 | tbd_address += 8; | |
aac443e6 | 720 | TRACE(RXTX, logout |
3f9cb1c1 | 721 | ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n", |
aac443e6 | 722 | tx_buffer_address, tx_buffer_size)); |
24e6f355 | 723 | tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); |
663e8e51 TS |
724 | cpu_physical_memory_read(tx_buffer_address, &buf[size], |
725 | tx_buffer_size); | |
726 | size += tx_buffer_size; | |
727 | if (tx_buffer_el & 1) { | |
728 | break; | |
729 | } | |
730 | } | |
731 | } | |
732 | tbd_address = tbd_array; | |
733 | for (; tbd_count < tx.tbd_count; tbd_count++) { | |
734 | uint32_t tx_buffer_address = ldl_phys(tbd_address); | |
735 | uint16_t tx_buffer_size = lduw_phys(tbd_address + 4); | |
736 | uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); | |
737 | tbd_address += 8; | |
aac443e6 | 738 | TRACE(RXTX, logout |
663e8e51 | 739 | ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n", |
aac443e6 | 740 | tx_buffer_address, tx_buffer_size)); |
24e6f355 | 741 | tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); |
663e8e51 TS |
742 | cpu_physical_memory_read(tx_buffer_address, &buf[size], |
743 | tx_buffer_size); | |
744 | size += tx_buffer_size; | |
745 | if (tx_buffer_el & 1) { | |
746 | break; | |
747 | } | |
748 | } | |
749 | } | |
aac443e6 | 750 | TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size))); |
663e8e51 TS |
751 | qemu_send_packet(s->vc, buf, size); |
752 | s->statistics.tx_good_frames++; | |
753 | /* Transmit with bad status would raise an CX/TNO interrupt. | |
754 | * (82557 only). Emulation never has bad status. */ | |
755 | //~ eepro100_cx_interrupt(s); | |
756 | break; | |
757 | case CmdTDR: | |
aac443e6 | 758 | TRACE(OTHER, logout("load microcode\n")); |
663e8e51 TS |
759 | /* Starting with offset 8, the command contains |
760 | * 64 dwords microcode which we just ignore here. */ | |
761 | break; | |
762 | default: | |
763 | missing("undefined command"); | |
7f1e9d4e KW |
764 | success = false; |
765 | break; | |
663e8e51 | 766 | } |
7f1e9d4e KW |
767 | /* Write new status. */ |
768 | stw_phys(cb_address, status | 0x8000 | (success ? 0x2000 : 0)); | |
663e8e51 TS |
769 | if (bit_i) { |
770 | /* CU completed action. */ | |
771 | eepro100_cx_interrupt(s); | |
772 | } | |
773 | if (bit_el) { | |
aac443e6 | 774 | /* CU becomes idle. Terminate command loop. */ |
663e8e51 TS |
775 | set_cu_state(s, cu_idle); |
776 | eepro100_cna_interrupt(s); | |
5fa9a0ae | 777 | break; |
663e8e51 | 778 | } else if (bit_s) { |
5fa9a0ae | 779 | /* CU becomes suspended. Terminate command loop. */ |
663e8e51 TS |
780 | set_cu_state(s, cu_suspended); |
781 | eepro100_cna_interrupt(s); | |
5fa9a0ae | 782 | break; |
663e8e51 TS |
783 | } else { |
784 | /* More entries in list. */ | |
aac443e6 | 785 | TRACE(OTHER, logout("CU list with at least one more entry\n")); |
663e8e51 | 786 | } |
5fa9a0ae SW |
787 | } |
788 | TRACE(OTHER, logout("CU list empty\n")); | |
789 | /* List is empty. Now CU is idle or suspended. */ | |
790 | } | |
791 | ||
792 | static void eepro100_cu_command(EEPRO100State * s, uint8_t val) | |
793 | { | |
794 | switch (val) { | |
795 | case CU_NOP: | |
796 | /* No operation. */ | |
797 | break; | |
798 | case CU_START: | |
799 | if (get_cu_state(s) != cu_idle) { | |
800 | /* Intel documentation says that CU must be idle for the CU | |
801 | * start command. Intel driver for Linux also starts the CU | |
802 | * from suspended state. */ | |
803 | logout("CU state is %u, should be %u\n", get_cu_state(s), cu_idle); | |
804 | //~ assert(!"wrong CU state"); | |
805 | } | |
806 | set_cu_state(s, cu_active); | |
807 | s->cu_offset = s->pointer; | |
808 | action_command(s); | |
663e8e51 TS |
809 | break; |
810 | case CU_RESUME: | |
811 | if (get_cu_state(s) != cu_suspended) { | |
812 | logout("bad CU resume from CU state %u\n", get_cu_state(s)); | |
813 | /* Workaround for bad Linux eepro100 driver which resumes | |
814 | * from idle state. */ | |
815 | //~ missing("cu resume"); | |
816 | set_cu_state(s, cu_suspended); | |
817 | } | |
818 | if (get_cu_state(s) == cu_suspended) { | |
aac443e6 | 819 | TRACE(OTHER, logout("CU resuming\n")); |
663e8e51 | 820 | set_cu_state(s, cu_active); |
5fa9a0ae | 821 | action_command(s); |
663e8e51 TS |
822 | } |
823 | break; | |
824 | case CU_STATSADDR: | |
825 | /* Load dump counters address. */ | |
826 | s->statsaddr = s->pointer; | |
aac443e6 | 827 | TRACE(OTHER, logout("val=0x%02x (status address)\n", val)); |
663e8e51 TS |
828 | break; |
829 | case CU_SHOWSTATS: | |
830 | /* Dump statistical counters. */ | |
aac443e6 | 831 | TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val)); |
663e8e51 TS |
832 | dump_statistics(s); |
833 | break; | |
834 | case CU_CMD_BASE: | |
835 | /* Load CU base. */ | |
aac443e6 | 836 | TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val)); |
663e8e51 TS |
837 | s->cu_base = s->pointer; |
838 | break; | |
839 | case CU_DUMPSTATS: | |
840 | /* Dump and reset statistical counters. */ | |
aac443e6 | 841 | TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val)); |
663e8e51 TS |
842 | dump_statistics(s); |
843 | memset(&s->statistics, 0, sizeof(s->statistics)); | |
844 | break; | |
845 | case CU_SRESUME: | |
846 | /* CU static resume. */ | |
847 | missing("CU static resume"); | |
848 | break; | |
849 | default: | |
850 | missing("Undefined CU command"); | |
851 | } | |
852 | } | |
853 | ||
854 | static void eepro100_ru_command(EEPRO100State * s, uint8_t val) | |
855 | { | |
856 | switch (val) { | |
857 | case RU_NOP: | |
858 | /* No operation. */ | |
859 | break; | |
860 | case RX_START: | |
861 | /* RU start. */ | |
862 | if (get_ru_state(s) != ru_idle) { | |
863 | logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle); | |
864 | //~ assert(!"wrong RU state"); | |
865 | } | |
866 | set_ru_state(s, ru_ready); | |
867 | s->ru_offset = s->pointer; | |
aac443e6 | 868 | TRACE(OTHER, logout("val=0x%02x (rx start)\n", val)); |
663e8e51 TS |
869 | break; |
870 | case RX_RESUME: | |
871 | /* Restart RU. */ | |
872 | if (get_ru_state(s) != ru_suspended) { | |
873 | logout("RU state is %u, should be %u\n", get_ru_state(s), | |
874 | ru_suspended); | |
875 | //~ assert(!"wrong RU state"); | |
876 | } | |
877 | set_ru_state(s, ru_ready); | |
878 | break; | |
879 | case RX_ADDR_LOAD: | |
880 | /* Load RU base. */ | |
aac443e6 | 881 | TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val)); |
663e8e51 TS |
882 | s->ru_base = s->pointer; |
883 | break; | |
884 | default: | |
885 | logout("val=0x%02x (undefined RU command)\n", val); | |
886 | missing("Undefined SU command"); | |
887 | } | |
888 | } | |
889 | ||
890 | static void eepro100_write_command(EEPRO100State * s, uint8_t val) | |
891 | { | |
892 | eepro100_ru_command(s, val & 0x0f); | |
893 | eepro100_cu_command(s, val & 0xf0); | |
894 | if ((val) == 0) { | |
aac443e6 | 895 | TRACE(OTHER, logout("val=0x%02x\n", val)); |
663e8e51 TS |
896 | } |
897 | /* Clear command byte after command was accepted. */ | |
898 | s->mem[SCBCmd] = 0; | |
899 | } | |
900 | ||
901 | /***************************************************************************** | |
902 | * | |
903 | * EEPROM emulation. | |
904 | * | |
905 | ****************************************************************************/ | |
906 | ||
907 | #define EEPROM_CS 0x02 | |
908 | #define EEPROM_SK 0x01 | |
909 | #define EEPROM_DI 0x04 | |
910 | #define EEPROM_DO 0x08 | |
911 | ||
912 | static uint16_t eepro100_read_eeprom(EEPRO100State * s) | |
913 | { | |
914 | uint16_t val; | |
915 | memcpy(&val, &s->mem[SCBeeprom], sizeof(val)); | |
916 | if (eeprom93xx_read(s->eeprom)) { | |
917 | val |= EEPROM_DO; | |
918 | } else { | |
919 | val &= ~EEPROM_DO; | |
920 | } | |
aac443e6 | 921 | TRACE(EEPROM, logout("val=0x%04x\n", val)); |
663e8e51 TS |
922 | return val; |
923 | } | |
924 | ||
c227f099 | 925 | static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val) |
663e8e51 | 926 | { |
aac443e6 | 927 | TRACE(EEPROM, logout("val=0x%02x\n", val)); |
663e8e51 TS |
928 | |
929 | /* mask unwriteable bits */ | |
930 | //~ val = SET_MASKED(val, 0x31, eeprom->value); | |
931 | ||
932 | int eecs = ((val & EEPROM_CS) != 0); | |
933 | int eesk = ((val & EEPROM_SK) != 0); | |
934 | int eedi = ((val & EEPROM_DI) != 0); | |
935 | eeprom93xx_write(eeprom, eecs, eesk, eedi); | |
936 | } | |
937 | ||
938 | static void eepro100_write_pointer(EEPRO100State * s, uint32_t val) | |
939 | { | |
940 | s->pointer = le32_to_cpu(val); | |
aac443e6 | 941 | TRACE(OTHER, logout("val=0x%08x\n", val)); |
663e8e51 TS |
942 | } |
943 | ||
944 | /***************************************************************************** | |
945 | * | |
946 | * MDI emulation. | |
947 | * | |
948 | ****************************************************************************/ | |
949 | ||
950 | #if defined(DEBUG_EEPRO100) | |
6a0b9cc9 | 951 | static const char * const mdi_op_name[] = { |
663e8e51 TS |
952 | "opcode 0", |
953 | "write", | |
954 | "read", | |
955 | "opcode 3" | |
956 | }; | |
957 | ||
6a0b9cc9 | 958 | static const char * const mdi_reg_name[] = { |
663e8e51 TS |
959 | "Control", |
960 | "Status", | |
961 | "PHY Identification (Word 1)", | |
962 | "PHY Identification (Word 2)", | |
963 | "Auto-Negotiation Advertisement", | |
964 | "Auto-Negotiation Link Partner Ability", | |
965 | "Auto-Negotiation Expansion" | |
966 | }; | |
aac443e6 SW |
967 | |
968 | static const char *reg2name(uint8_t reg) | |
969 | { | |
970 | static char buffer[10]; | |
971 | const char *p = buffer; | |
972 | if (reg < ARRAY_SIZE(mdi_reg_name)) { | |
973 | p = mdi_reg_name[reg]; | |
974 | } else { | |
975 | snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg); | |
976 | } | |
977 | return p; | |
978 | } | |
663e8e51 TS |
979 | #endif /* DEBUG_EEPRO100 */ |
980 | ||
981 | static uint32_t eepro100_read_mdi(EEPRO100State * s) | |
982 | { | |
983 | uint32_t val; | |
984 | memcpy(&val, &s->mem[0x10], sizeof(val)); | |
985 | ||
986 | #ifdef DEBUG_EEPRO100 | |
987 | uint8_t raiseint = (val & BIT(29)) >> 29; | |
988 | uint8_t opcode = (val & BITS(27, 26)) >> 26; | |
989 | uint8_t phy = (val & BITS(25, 21)) >> 21; | |
990 | uint8_t reg = (val & BITS(20, 16)) >> 16; | |
991 | uint16_t data = (val & BITS(15, 0)); | |
992 | #endif | |
993 | /* Emulation takes no time to finish MDI transaction. */ | |
994 | val |= BIT(28); | |
995 | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", | |
996 | val, raiseint, mdi_op_name[opcode], phy, | |
aac443e6 | 997 | reg2name(reg), data)); |
663e8e51 TS |
998 | return val; |
999 | } | |
1000 | ||
663e8e51 TS |
1001 | static void eepro100_write_mdi(EEPRO100State * s, uint32_t val) |
1002 | { | |
1003 | uint8_t raiseint = (val & BIT(29)) >> 29; | |
1004 | uint8_t opcode = (val & BITS(27, 26)) >> 26; | |
1005 | uint8_t phy = (val & BITS(25, 21)) >> 21; | |
1006 | uint8_t reg = (val & BITS(20, 16)) >> 16; | |
1007 | uint16_t data = (val & BITS(15, 0)); | |
aac443e6 SW |
1008 | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", |
1009 | val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data)); | |
663e8e51 TS |
1010 | if (phy != 1) { |
1011 | /* Unsupported PHY address. */ | |
1012 | //~ logout("phy must be 1 but is %u\n", phy); | |
1013 | data = 0; | |
1014 | } else if (opcode != 1 && opcode != 2) { | |
1015 | /* Unsupported opcode. */ | |
1016 | logout("opcode must be 1 or 2 but is %u\n", opcode); | |
1017 | data = 0; | |
1018 | } else if (reg > 6) { | |
1019 | /* Unsupported register. */ | |
1020 | logout("register must be 0...6 but is %u\n", reg); | |
1021 | data = 0; | |
1022 | } else { | |
1023 | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", | |
1024 | val, raiseint, mdi_op_name[opcode], phy, | |
aac443e6 | 1025 | reg2name(reg), data)); |
663e8e51 TS |
1026 | if (opcode == 1) { |
1027 | /* MDI write */ | |
1028 | switch (reg) { | |
1029 | case 0: /* Control Register */ | |
1030 | if (data & 0x8000) { | |
1031 | /* Reset status and control registers to default. */ | |
1032 | s->mdimem[0] = eepro100_mdi_default[0]; | |
1033 | s->mdimem[1] = eepro100_mdi_default[1]; | |
1034 | data = s->mdimem[reg]; | |
1035 | } else { | |
1036 | /* Restart Auto Configuration = Normal Operation */ | |
1037 | data &= ~0x0200; | |
1038 | } | |
1039 | break; | |
1040 | case 1: /* Status Register */ | |
1041 | missing("not writable"); | |
1042 | data = s->mdimem[reg]; | |
1043 | break; | |
1044 | case 2: /* PHY Identification Register (Word 1) */ | |
1045 | case 3: /* PHY Identification Register (Word 2) */ | |
1046 | missing("not implemented"); | |
1047 | break; | |
1048 | case 4: /* Auto-Negotiation Advertisement Register */ | |
1049 | case 5: /* Auto-Negotiation Link Partner Ability Register */ | |
1050 | break; | |
1051 | case 6: /* Auto-Negotiation Expansion Register */ | |
1052 | default: | |
1053 | missing("not implemented"); | |
1054 | } | |
1055 | s->mdimem[reg] = data; | |
1056 | } else if (opcode == 2) { | |
1057 | /* MDI read */ | |
1058 | switch (reg) { | |
1059 | case 0: /* Control Register */ | |
1060 | if (data & 0x8000) { | |
1061 | /* Reset status and control registers to default. */ | |
1062 | s->mdimem[0] = eepro100_mdi_default[0]; | |
1063 | s->mdimem[1] = eepro100_mdi_default[1]; | |
1064 | } | |
1065 | break; | |
1066 | case 1: /* Status Register */ | |
1067 | s->mdimem[reg] |= 0x0020; | |
1068 | break; | |
1069 | case 2: /* PHY Identification Register (Word 1) */ | |
1070 | case 3: /* PHY Identification Register (Word 2) */ | |
1071 | case 4: /* Auto-Negotiation Advertisement Register */ | |
1072 | break; | |
1073 | case 5: /* Auto-Negotiation Link Partner Ability Register */ | |
1074 | s->mdimem[reg] = 0x41fe; | |
1075 | break; | |
1076 | case 6: /* Auto-Negotiation Expansion Register */ | |
1077 | s->mdimem[reg] = 0x0001; | |
1078 | break; | |
1079 | } | |
1080 | data = s->mdimem[reg]; | |
1081 | } | |
1082 | /* Emulation takes no time to finish MDI transaction. | |
1083 | * Set MDI bit in SCB status register. */ | |
1084 | s->mem[SCBAck] |= 0x08; | |
1085 | val |= BIT(28); | |
1086 | if (raiseint) { | |
1087 | eepro100_mdi_interrupt(s); | |
1088 | } | |
1089 | } | |
1090 | val = (val & 0xffff0000) + data; | |
1091 | memcpy(&s->mem[0x10], &val, sizeof(val)); | |
1092 | } | |
1093 | ||
1094 | /***************************************************************************** | |
1095 | * | |
1096 | * Port emulation. | |
1097 | * | |
1098 | ****************************************************************************/ | |
1099 | ||
1100 | #define PORT_SOFTWARE_RESET 0 | |
1101 | #define PORT_SELFTEST 1 | |
1102 | #define PORT_SELECTIVE_RESET 2 | |
1103 | #define PORT_DUMP 3 | |
1104 | #define PORT_SELECTION_MASK 3 | |
1105 | ||
1106 | typedef struct { | |
1107 | uint32_t st_sign; /* Self Test Signature */ | |
1108 | uint32_t st_result; /* Self Test Results */ | |
c227f099 | 1109 | } eepro100_selftest_t; |
663e8e51 TS |
1110 | |
1111 | static uint32_t eepro100_read_port(EEPRO100State * s) | |
1112 | { | |
1113 | return 0; | |
1114 | } | |
1115 | ||
1116 | static void eepro100_write_port(EEPRO100State * s, uint32_t val) | |
1117 | { | |
1118 | val = le32_to_cpu(val); | |
1119 | uint32_t address = (val & ~PORT_SELECTION_MASK); | |
1120 | uint8_t selection = (val & PORT_SELECTION_MASK); | |
1121 | switch (selection) { | |
1122 | case PORT_SOFTWARE_RESET: | |
1123 | nic_reset(s); | |
1124 | break; | |
1125 | case PORT_SELFTEST: | |
aac443e6 | 1126 | TRACE(OTHER, logout("selftest address=0x%08x\n", address)); |
c227f099 | 1127 | eepro100_selftest_t data; |
663e8e51 TS |
1128 | cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data)); |
1129 | data.st_sign = 0xffffffff; | |
1130 | data.st_result = 0; | |
1131 | cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data)); | |
1132 | break; | |
1133 | case PORT_SELECTIVE_RESET: | |
aac443e6 | 1134 | TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address)); |
663e8e51 TS |
1135 | nic_selective_reset(s); |
1136 | break; | |
1137 | default: | |
1138 | logout("val=0x%08x\n", val); | |
1139 | missing("unknown port selection"); | |
1140 | } | |
1141 | } | |
1142 | ||
1143 | /***************************************************************************** | |
1144 | * | |
1145 | * General hardware emulation. | |
1146 | * | |
1147 | ****************************************************************************/ | |
1148 | ||
1149 | static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr) | |
1150 | { | |
1151 | uint8_t val; | |
1152 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1153 | memcpy(&val, &s->mem[addr], sizeof(val)); | |
1154 | } | |
1155 | ||
1156 | switch (addr) { | |
1157 | case SCBStatus: | |
1158 | //~ val = eepro100_read_status(s); | |
aac443e6 | 1159 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1160 | break; |
1161 | case SCBAck: | |
1162 | //~ val = eepro100_read_status(s); | |
aac443e6 | 1163 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1164 | break; |
1165 | case SCBCmd: | |
aac443e6 | 1166 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1167 | //~ val = eepro100_read_command(s); |
1168 | break; | |
1169 | case SCBIntmask: | |
aac443e6 | 1170 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1171 | break; |
1172 | case SCBPort + 3: | |
aac443e6 | 1173 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1174 | break; |
1175 | case SCBeeprom: | |
1176 | val = eepro100_read_eeprom(s); | |
1177 | break; | |
1178 | case 0x1b: /* PMDR (power management driver register) */ | |
1179 | val = 0; | |
aac443e6 | 1180 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1181 | break; |
1182 | case 0x1d: /* general status register */ | |
1183 | /* 100 Mbps full duplex, valid link */ | |
1184 | val = 0x07; | |
aac443e6 | 1185 | TRACE(OTHER, logout("addr=General Status val=%02x\n", val)); |
663e8e51 TS |
1186 | break; |
1187 | default: | |
1188 | logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1189 | missing("unknown byte read"); | |
1190 | } | |
1191 | return val; | |
1192 | } | |
1193 | ||
1194 | static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr) | |
1195 | { | |
1196 | uint16_t val; | |
1197 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1198 | memcpy(&val, &s->mem[addr], sizeof(val)); | |
1199 | } | |
1200 | ||
663e8e51 TS |
1201 | switch (addr) { |
1202 | case SCBStatus: | |
1203 | //~ val = eepro100_read_status(s); | |
dbbaaff6 | 1204 | case SCBCmd: |
aac443e6 | 1205 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 TS |
1206 | break; |
1207 | case SCBeeprom: | |
1208 | val = eepro100_read_eeprom(s); | |
aac443e6 | 1209 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 TS |
1210 | break; |
1211 | default: | |
1212 | logout("addr=%s val=0x%04x\n", regname(addr), val); | |
1213 | missing("unknown word read"); | |
1214 | } | |
1215 | return val; | |
1216 | } | |
1217 | ||
1218 | static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr) | |
1219 | { | |
1220 | uint32_t val; | |
1221 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1222 | memcpy(&val, &s->mem[addr], sizeof(val)); | |
1223 | } | |
1224 | ||
1225 | switch (addr) { | |
1226 | case SCBStatus: | |
1227 | //~ val = eepro100_read_status(s); | |
aac443e6 | 1228 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1229 | break; |
1230 | case SCBPointer: | |
1231 | //~ val = eepro100_read_pointer(s); | |
aac443e6 | 1232 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1233 | break; |
1234 | case SCBPort: | |
1235 | val = eepro100_read_port(s); | |
aac443e6 | 1236 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1237 | break; |
1238 | case SCBCtrlMDI: | |
1239 | val = eepro100_read_mdi(s); | |
1240 | break; | |
1241 | default: | |
1242 | logout("addr=%s val=0x%08x\n", regname(addr), val); | |
1243 | missing("unknown longword read"); | |
1244 | } | |
1245 | return val; | |
1246 | } | |
1247 | ||
1248 | static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val) | |
1249 | { | |
1250 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1251 | memcpy(&s->mem[addr], &val, sizeof(val)); | |
1252 | } | |
1253 | ||
aac443e6 | 1254 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1255 | |
1256 | switch (addr) { | |
1257 | case SCBStatus: | |
1258 | //~ eepro100_write_status(s, val); | |
1259 | break; | |
1260 | case SCBAck: | |
1261 | eepro100_acknowledge(s); | |
1262 | break; | |
1263 | case SCBCmd: | |
1264 | eepro100_write_command(s, val); | |
1265 | break; | |
1266 | case SCBIntmask: | |
1267 | if (val & BIT(1)) { | |
1268 | eepro100_swi_interrupt(s); | |
1269 | } | |
1270 | eepro100_interrupt(s, 0); | |
1271 | break; | |
1272 | case SCBPort + 3: | |
aac443e6 | 1273 | case SCBFlow: /* does not exist on 82557 */ |
3257d2b6 TS |
1274 | case SCBFlow + 1: |
1275 | case SCBFlow + 2: | |
1276 | case SCBFlow + 3: | |
aac443e6 | 1277 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1278 | break; |
1279 | case SCBeeprom: | |
1280 | eepro100_write_eeprom(s->eeprom, val); | |
1281 | break; | |
1282 | default: | |
1283 | logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1284 | missing("unknown byte write"); | |
1285 | } | |
1286 | } | |
1287 | ||
1288 | static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val) | |
1289 | { | |
1290 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1291 | memcpy(&s->mem[addr], &val, sizeof(val)); | |
1292 | } | |
1293 | ||
aac443e6 | 1294 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 TS |
1295 | |
1296 | switch (addr) { | |
1297 | case SCBStatus: | |
1298 | //~ eepro100_write_status(s, val); | |
1299 | eepro100_acknowledge(s); | |
1300 | break; | |
1301 | case SCBCmd: | |
1302 | eepro100_write_command(s, val); | |
1303 | eepro100_write1(s, SCBIntmask, val >> 8); | |
1304 | break; | |
1305 | case SCBeeprom: | |
1306 | eepro100_write_eeprom(s->eeprom, val); | |
1307 | break; | |
1308 | default: | |
1309 | logout("addr=%s val=0x%04x\n", regname(addr), val); | |
1310 | missing("unknown word write"); | |
1311 | } | |
1312 | } | |
1313 | ||
1314 | static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val) | |
1315 | { | |
1316 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1317 | memcpy(&s->mem[addr], &val, sizeof(val)); | |
1318 | } | |
1319 | ||
1320 | switch (addr) { | |
1321 | case SCBPointer: | |
1322 | eepro100_write_pointer(s, val); | |
1323 | break; | |
1324 | case SCBPort: | |
aac443e6 | 1325 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1326 | eepro100_write_port(s, val); |
1327 | break; | |
1328 | case SCBCtrlMDI: | |
1329 | eepro100_write_mdi(s, val); | |
1330 | break; | |
1331 | default: | |
1332 | logout("addr=%s val=0x%08x\n", regname(addr), val); | |
1333 | missing("unknown longword write"); | |
1334 | } | |
1335 | } | |
1336 | ||
aac443e6 SW |
1337 | /***************************************************************************** |
1338 | * | |
1339 | * Port mapped I/O. | |
1340 | * | |
1341 | ****************************************************************************/ | |
1342 | ||
663e8e51 TS |
1343 | static uint32_t ioport_read1(void *opaque, uint32_t addr) |
1344 | { | |
1345 | EEPRO100State *s = opaque; | |
1346 | //~ logout("addr=%s\n", regname(addr)); | |
1347 | return eepro100_read1(s, addr - s->region[1]); | |
1348 | } | |
1349 | ||
1350 | static uint32_t ioport_read2(void *opaque, uint32_t addr) | |
1351 | { | |
1352 | EEPRO100State *s = opaque; | |
1353 | return eepro100_read2(s, addr - s->region[1]); | |
1354 | } | |
1355 | ||
1356 | static uint32_t ioport_read4(void *opaque, uint32_t addr) | |
1357 | { | |
1358 | EEPRO100State *s = opaque; | |
1359 | return eepro100_read4(s, addr - s->region[1]); | |
1360 | } | |
1361 | ||
1362 | static void ioport_write1(void *opaque, uint32_t addr, uint32_t val) | |
1363 | { | |
1364 | EEPRO100State *s = opaque; | |
1365 | //~ logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1366 | eepro100_write1(s, addr - s->region[1], val); | |
1367 | } | |
1368 | ||
1369 | static void ioport_write2(void *opaque, uint32_t addr, uint32_t val) | |
1370 | { | |
1371 | EEPRO100State *s = opaque; | |
1372 | eepro100_write2(s, addr - s->region[1], val); | |
1373 | } | |
1374 | ||
1375 | static void ioport_write4(void *opaque, uint32_t addr, uint32_t val) | |
1376 | { | |
1377 | EEPRO100State *s = opaque; | |
1378 | eepro100_write4(s, addr - s->region[1], val); | |
1379 | } | |
1380 | ||
1381 | /***********************************************************/ | |
1382 | /* PCI EEPRO100 definitions */ | |
1383 | ||
663e8e51 TS |
1384 | static void pci_map(PCIDevice * pci_dev, int region_num, |
1385 | uint32_t addr, uint32_t size, int type) | |
1386 | { | |
273a2142 | 1387 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
663e8e51 | 1388 | |
aac443e6 SW |
1389 | TRACE(OTHER, logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n", |
1390 | region_num, addr, size, type)); | |
663e8e51 TS |
1391 | |
1392 | assert(region_num == 1); | |
1393 | register_ioport_write(addr, size, 1, ioport_write1, s); | |
1394 | register_ioport_read(addr, size, 1, ioport_read1, s); | |
1395 | register_ioport_write(addr, size, 2, ioport_write2, s); | |
1396 | register_ioport_read(addr, size, 2, ioport_read2, s); | |
1397 | register_ioport_write(addr, size, 4, ioport_write4, s); | |
1398 | register_ioport_read(addr, size, 4, ioport_read4, s); | |
1399 | ||
1400 | s->region[region_num] = addr; | |
1401 | } | |
1402 | ||
aac443e6 SW |
1403 | /***************************************************************************** |
1404 | * | |
1405 | * Memory mapped I/O. | |
1406 | * | |
1407 | ****************************************************************************/ | |
1408 | ||
c227f099 | 1409 | static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
663e8e51 TS |
1410 | { |
1411 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1412 | //~ logout("addr=%s val=0x%02x\n", regname(addr), val); |
1413 | eepro100_write1(s, addr, val); | |
1414 | } | |
1415 | ||
c227f099 | 1416 | static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
663e8e51 TS |
1417 | { |
1418 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1419 | //~ logout("addr=%s val=0x%02x\n", regname(addr), val); |
1420 | eepro100_write2(s, addr, val); | |
1421 | } | |
1422 | ||
c227f099 | 1423 | static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
663e8e51 TS |
1424 | { |
1425 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1426 | //~ logout("addr=%s val=0x%02x\n", regname(addr), val); |
1427 | eepro100_write4(s, addr, val); | |
1428 | } | |
1429 | ||
c227f099 | 1430 | static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr) |
663e8e51 TS |
1431 | { |
1432 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1433 | //~ logout("addr=%s\n", regname(addr)); |
1434 | return eepro100_read1(s, addr); | |
1435 | } | |
1436 | ||
c227f099 | 1437 | static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr) |
663e8e51 TS |
1438 | { |
1439 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1440 | //~ logout("addr=%s\n", regname(addr)); |
1441 | return eepro100_read2(s, addr); | |
1442 | } | |
1443 | ||
c227f099 | 1444 | static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr) |
663e8e51 TS |
1445 | { |
1446 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1447 | //~ logout("addr=%s\n", regname(addr)); |
1448 | return eepro100_read4(s, addr); | |
1449 | } | |
1450 | ||
d60efc6b | 1451 | static CPUWriteMemoryFunc * const pci_mmio_write[] = { |
663e8e51 TS |
1452 | pci_mmio_writeb, |
1453 | pci_mmio_writew, | |
1454 | pci_mmio_writel | |
1455 | }; | |
1456 | ||
d60efc6b | 1457 | static CPUReadMemoryFunc * const pci_mmio_read[] = { |
663e8e51 TS |
1458 | pci_mmio_readb, |
1459 | pci_mmio_readw, | |
1460 | pci_mmio_readl | |
1461 | }; | |
1462 | ||
1463 | static void pci_mmio_map(PCIDevice * pci_dev, int region_num, | |
1464 | uint32_t addr, uint32_t size, int type) | |
1465 | { | |
273a2142 | 1466 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
663e8e51 | 1467 | |
aac443e6 SW |
1468 | TRACE(OTHER, logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n", |
1469 | region_num, addr, size, type)); | |
663e8e51 TS |
1470 | |
1471 | if (region_num == 0) { | |
1472 | /* Map control / status registers. */ | |
273a2142 JQ |
1473 | cpu_register_physical_memory(addr, size, s->mmio_index); |
1474 | s->region[region_num] = addr; | |
663e8e51 TS |
1475 | } |
1476 | } | |
1477 | ||
e3f5ec2b | 1478 | static int nic_can_receive(VLANClientState *vc) |
663e8e51 | 1479 | { |
e3f5ec2b | 1480 | EEPRO100State *s = vc->opaque; |
aac443e6 | 1481 | TRACE(RXTX, logout("%p\n", s)); |
663e8e51 TS |
1482 | return get_ru_state(s) == ru_ready; |
1483 | //~ return !eepro100_buffer_full(s); | |
1484 | } | |
1485 | ||
4f1c942b | 1486 | static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size) |
663e8e51 TS |
1487 | { |
1488 | /* TODO: | |
1489 | * - Magic packets should set bit 30 in power management driver register. | |
1490 | * - Interesting packets should set bit 29 in power management driver register. | |
1491 | */ | |
e3f5ec2b | 1492 | EEPRO100State *s = vc->opaque; |
663e8e51 TS |
1493 | uint16_t rfd_status = 0xa000; |
1494 | static const uint8_t broadcast_macaddr[6] = | |
1495 | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; | |
1496 | ||
1497 | /* TODO: check multiple IA bit. */ | |
7f1e9d4e KW |
1498 | if (s->configuration[20] & BIT(6)) { |
1499 | missing("Multiple IA bit"); | |
1500 | return -1; | |
1501 | } | |
663e8e51 TS |
1502 | |
1503 | if (s->configuration[8] & 0x80) { | |
1504 | /* CSMA is disabled. */ | |
1505 | logout("%p received while CSMA is disabled\n", s); | |
4f1c942b | 1506 | return -1; |
663e8e51 TS |
1507 | } else if (size < 64 && (s->configuration[7] & 1)) { |
1508 | /* Short frame and configuration byte 7/0 (discard short receive) set: | |
1509 | * Short frame is discarded */ | |
067d01de | 1510 | logout("%p received short frame (%zu byte)\n", s, size); |
663e8e51 | 1511 | s->statistics.rx_short_frame_errors++; |
4f1c942b | 1512 | //~ return -1; |
663e8e51 TS |
1513 | } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & 8)) { |
1514 | /* Long frame and configuration byte 18/3 (long receive ok) not set: | |
1515 | * Long frames are discarded. */ | |
067d01de | 1516 | logout("%p received long frame (%zu byte), ignored\n", s, size); |
4f1c942b | 1517 | return -1; |
508ef936 | 1518 | } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { // !!! |
663e8e51 TS |
1519 | /* Frame matches individual address. */ |
1520 | /* TODO: check configuration byte 15/4 (ignore U/L). */ | |
067d01de | 1521 | TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size)); |
663e8e51 TS |
1522 | } else if (memcmp(buf, broadcast_macaddr, 6) == 0) { |
1523 | /* Broadcast frame. */ | |
067d01de | 1524 | TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size)); |
663e8e51 TS |
1525 | rfd_status |= 0x0002; |
1526 | } else if (buf[0] & 0x01) { // !!! | |
1527 | /* Multicast frame. */ | |
067d01de | 1528 | TRACE(RXTX, logout("%p received multicast, len=%zu\n", s, size)); |
663e8e51 | 1529 | /* TODO: check multicast all bit. */ |
7f1e9d4e KW |
1530 | if (s->configuration[21] & BIT(3)) { |
1531 | missing("Multicast All bit"); | |
1532 | } | |
663e8e51 TS |
1533 | int mcast_idx = compute_mcast_idx(buf); |
1534 | if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) { | |
4f1c942b | 1535 | return size; |
663e8e51 TS |
1536 | } |
1537 | rfd_status |= 0x0002; | |
1538 | } else if (s->configuration[15] & 1) { | |
1539 | /* Promiscuous: receive all. */ | |
067d01de | 1540 | TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size)); |
663e8e51 TS |
1541 | rfd_status |= 0x0004; |
1542 | } else { | |
067d01de | 1543 | TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size, |
aac443e6 | 1544 | nic_dump(buf, size))); |
4f1c942b | 1545 | return size; |
663e8e51 TS |
1546 | } |
1547 | ||
1548 | if (get_ru_state(s) != ru_ready) { | |
aac443e6 SW |
1549 | /* No resources available. */ |
1550 | logout("no resources, state=%u\n", get_ru_state(s)); | |
663e8e51 | 1551 | s->statistics.rx_resource_errors++; |
aac443e6 | 1552 | //~ assert(!"no resources"); |
4f1c942b | 1553 | return -1; |
663e8e51 TS |
1554 | } |
1555 | //~ !!! | |
1556 | //~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}} | |
c227f099 | 1557 | eepro100_rx_t rx; |
663e8e51 | 1558 | cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx, |
c227f099 | 1559 | offsetof(eepro100_rx_t, packet)); |
663e8e51 TS |
1560 | uint16_t rfd_command = le16_to_cpu(rx.command); |
1561 | uint16_t rfd_size = le16_to_cpu(rx.size); | |
7f1e9d4e KW |
1562 | |
1563 | if (size > rfd_size) { | |
1564 | logout("Receive buffer (%" PRId16 " bytes) too small for data " | |
1565 | "(%zu bytes); data truncated\n", rfd_size, size); | |
1566 | size = rfd_size; | |
1567 | } | |
663e8e51 TS |
1568 | if (size < 64) { |
1569 | rfd_status |= 0x0080; | |
1570 | } | |
aac443e6 SW |
1571 | TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n", |
1572 | rfd_command, rx.link, rx.rx_buf_addr, rfd_size)); | |
c227f099 | 1573 | stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status), |
663e8e51 | 1574 | rfd_status); |
c227f099 | 1575 | stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size); |
663e8e51 TS |
1576 | /* Early receive interrupt not supported. */ |
1577 | //~ eepro100_er_interrupt(s); | |
1578 | /* Receive CRC Transfer not supported. */ | |
7f1e9d4e KW |
1579 | if (s->configuration[18] & 4) { |
1580 | missing("Receive CRC Transfer"); | |
1581 | return -1; | |
1582 | } | |
663e8e51 TS |
1583 | /* TODO: check stripping enable bit. */ |
1584 | //~ assert(!(s->configuration[17] & 1)); | |
1585 | cpu_physical_memory_write(s->ru_base + s->ru_offset + | |
c227f099 | 1586 | offsetof(eepro100_rx_t, packet), buf, size); |
663e8e51 TS |
1587 | s->statistics.rx_good_frames++; |
1588 | eepro100_fr_interrupt(s); | |
1589 | s->ru_offset = le32_to_cpu(rx.link); | |
1590 | if (rfd_command & 0x8000) { | |
1591 | /* EL bit is set, so this was the last frame. */ | |
7f1e9d4e KW |
1592 | logout("receive: Running out of frames\n"); |
1593 | set_ru_state(s, ru_suspended); | |
663e8e51 TS |
1594 | } |
1595 | if (rfd_command & 0x4000) { | |
1596 | /* S bit is set. */ | |
1597 | set_ru_state(s, ru_suspended); | |
1598 | } | |
4f1c942b | 1599 | return size; |
663e8e51 TS |
1600 | } |
1601 | ||
151b2986 JQ |
1602 | static const VMStateDescription vmstate_eepro100 = { |
1603 | .version_id = 3, | |
1604 | .minimum_version_id = 2, | |
1605 | .minimum_version_id_old = 2, | |
1606 | .fields = (VMStateField []) { | |
1607 | VMSTATE_PCI_DEVICE(dev, EEPRO100State), | |
1608 | VMSTATE_UNUSED(32), | |
1609 | VMSTATE_BUFFER(mult, EEPRO100State), | |
1610 | VMSTATE_BUFFER(mem, EEPRO100State), | |
1611 | /* Save all members of struct between scb_stat and mem. */ | |
1612 | VMSTATE_UINT8(scb_stat, EEPRO100State), | |
1613 | VMSTATE_UINT8(int_stat, EEPRO100State), | |
1614 | VMSTATE_UNUSED(3*4), | |
1615 | VMSTATE_MACADDR(conf.macaddr, EEPRO100State), | |
1616 | VMSTATE_UNUSED(19*4), | |
1617 | VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32), | |
1618 | /* The eeprom should be saved and restored by its own routines. */ | |
1619 | VMSTATE_UINT32(device, EEPRO100State), | |
1620 | /* TODO check device. */ | |
1621 | VMSTATE_UINT32(pointer, EEPRO100State), | |
1622 | VMSTATE_UINT32(cu_base, EEPRO100State), | |
1623 | VMSTATE_UINT32(cu_offset, EEPRO100State), | |
1624 | VMSTATE_UINT32(ru_base, EEPRO100State), | |
1625 | VMSTATE_UINT32(ru_offset, EEPRO100State), | |
1626 | VMSTATE_UINT32(statsaddr, EEPRO100State), | |
1627 | /* Save epro100_stats_t statistics. */ | |
1628 | VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State), | |
1629 | VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State), | |
1630 | VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State), | |
1631 | VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State), | |
1632 | VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State), | |
1633 | VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State), | |
1634 | VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State), | |
1635 | VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State), | |
1636 | VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State), | |
1637 | VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State), | |
1638 | VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State), | |
1639 | VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State), | |
1640 | VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State), | |
1641 | VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State), | |
1642 | VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State), | |
1643 | VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State), | |
1644 | VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State), | |
1645 | VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State), | |
1646 | VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State), | |
1647 | VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State), | |
1648 | VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State), | |
1649 | VMSTATE_UINT32(statistics.complete, EEPRO100State), | |
2657c663 | 1650 | #if 0 |
151b2986 | 1651 | VMSTATE_UINT16(status, EEPRO100State), |
2657c663 | 1652 | #endif |
151b2986 JQ |
1653 | /* Configuration bytes. */ |
1654 | VMSTATE_BUFFER(configuration, EEPRO100State), | |
1655 | VMSTATE_END_OF_LIST() | |
aac443e6 | 1656 | } |
151b2986 | 1657 | }; |
663e8e51 | 1658 | |
b946a153 AL |
1659 | static void nic_cleanup(VLANClientState *vc) |
1660 | { | |
1661 | EEPRO100State *s = vc->opaque; | |
1662 | ||
508ef936 | 1663 | s->vc = NULL; |
b946a153 AL |
1664 | } |
1665 | ||
c4c270e2 | 1666 | static int pci_nic_uninit(PCIDevice *pci_dev) |
b946a153 | 1667 | { |
c4c270e2 | 1668 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
b946a153 AL |
1669 | |
1670 | cpu_unregister_io_memory(s->mmio_index); | |
151b2986 | 1671 | vmstate_unregister(s->vmstate, s); |
508ef936 GH |
1672 | eeprom93xx_free(s->eeprom); |
1673 | qemu_del_vlan_client(s->vc); | |
b946a153 AL |
1674 | return 0; |
1675 | } | |
1676 | ||
81a322d4 | 1677 | static int nic_init(PCIDevice *pci_dev, uint32_t device) |
663e8e51 | 1678 | { |
273a2142 | 1679 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
663e8e51 | 1680 | |
aac443e6 | 1681 | TRACE(OTHER, logout("\n")); |
663e8e51 | 1682 | |
663e8e51 | 1683 | s->device = device; |
663e8e51 TS |
1684 | |
1685 | pci_reset(s); | |
1686 | ||
1687 | /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM, | |
1688 | * i82559 and later support 64 or 256 word EEPROM. */ | |
1689 | s->eeprom = eeprom93xx_new(EEPROM_SIZE); | |
1690 | ||
1691 | /* Handler for memory-mapped I/O */ | |
273a2142 | 1692 | s->mmio_index = |
1eed09cb | 1693 | cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s); |
663e8e51 | 1694 | |
273a2142 | 1695 | pci_register_bar(&s->dev, 0, PCI_MEM_SIZE, |
663e8e51 TS |
1696 | PCI_ADDRESS_SPACE_MEM | |
1697 | PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_mmio_map); | |
273a2142 | 1698 | pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_ADDRESS_SPACE_IO, |
663e8e51 | 1699 | pci_map); |
273a2142 | 1700 | pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_ADDRESS_SPACE_MEM, |
663e8e51 TS |
1701 | pci_mmio_map); |
1702 | ||
508ef936 | 1703 | qemu_macaddr_default_if_unset(&s->conf.macaddr); |
663e8e51 TS |
1704 | logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6)); |
1705 | assert(s->region[1] == 0); | |
1706 | ||
1707 | nic_reset(s); | |
1708 | ||
508ef936 GH |
1709 | s->vc = qemu_new_vlan_client(NET_CLIENT_TYPE_NIC, |
1710 | s->conf.vlan, s->conf.peer, | |
1711 | pci_dev->qdev.info->name, pci_dev->qdev.id, | |
1712 | nic_can_receive, nic_receive, NULL, NULL, | |
b946a153 | 1713 | nic_cleanup, s); |
663e8e51 | 1714 | |
508ef936 | 1715 | qemu_format_nic_info_str(s->vc, s->conf.macaddr.a); |
aac443e6 | 1716 | TRACE(OTHER, logout("%s\n", s->vc->info_str)); |
663e8e51 | 1717 | |
a08d4367 | 1718 | qemu_register_reset(nic_reset, s); |
663e8e51 | 1719 | |
151b2986 JQ |
1720 | s->vmstate = qemu_malloc(sizeof(vmstate_eepro100)); |
1721 | memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100)); | |
1722 | s->vmstate->name = s->vc->model; | |
1723 | vmstate_register(-1, s->vmstate, s); | |
81a322d4 | 1724 | return 0; |
663e8e51 TS |
1725 | } |
1726 | ||
c4c270e2 SW |
1727 | static int pci_i82550_init(PCIDevice *pci_dev) |
1728 | { | |
1729 | return nic_init(pci_dev, i82550); | |
1730 | } | |
1731 | ||
1732 | static int pci_i82551_init(PCIDevice *pci_dev) | |
1733 | { | |
1734 | return nic_init(pci_dev, i82551); | |
1735 | } | |
1736 | ||
1737 | static int pci_i82557a_init(PCIDevice *pci_dev) | |
1738 | { | |
1739 | return nic_init(pci_dev, i82557A); | |
1740 | } | |
1741 | ||
1742 | static int pci_i82557b_init(PCIDevice *pci_dev) | |
1743 | { | |
1744 | return nic_init(pci_dev, i82557B); | |
1745 | } | |
1746 | ||
1747 | static int pci_i82557c_init(PCIDevice *pci_dev) | |
1748 | { | |
1749 | return nic_init(pci_dev, i82557C); | |
1750 | } | |
1751 | ||
1752 | static int pci_i82558a_init(PCIDevice *pci_dev) | |
1753 | { | |
1754 | return nic_init(pci_dev, i82558A); | |
1755 | } | |
1756 | ||
1757 | static int pci_i82558b_init(PCIDevice *pci_dev) | |
1758 | { | |
1759 | return nic_init(pci_dev, i82558B); | |
1760 | } | |
1761 | ||
1762 | static int pci_i82559a_init(PCIDevice *pci_dev) | |
1763 | { | |
1764 | return nic_init(pci_dev, i82559A); | |
1765 | } | |
1766 | ||
1767 | static int pci_i82559b_init(PCIDevice *pci_dev) | |
1768 | { | |
1769 | return nic_init(pci_dev, i82559B); | |
1770 | } | |
1771 | ||
1772 | static int pci_i82559c_init(PCIDevice *pci_dev) | |
9d07d757 | 1773 | { |
c4c270e2 | 1774 | return nic_init(pci_dev, i82559C); |
9d07d757 PB |
1775 | } |
1776 | ||
c4c270e2 | 1777 | static int pci_i82559er_init(PCIDevice *pci_dev) |
663e8e51 | 1778 | { |
c4c270e2 | 1779 | return nic_init(pci_dev, i82559ER); |
663e8e51 TS |
1780 | } |
1781 | ||
c4c270e2 | 1782 | static int pci_i82562_init(PCIDevice *pci_dev) |
663e8e51 | 1783 | { |
c4c270e2 | 1784 | return nic_init(pci_dev, i82562); |
663e8e51 TS |
1785 | } |
1786 | ||
0aab0d3a GH |
1787 | static PCIDeviceInfo eepro100_info[] = { |
1788 | { | |
c4c270e2 SW |
1789 | .qdev.name = "i82550", |
1790 | .qdev.size = sizeof(EEPRO100State), | |
1791 | .init = pci_i82550_init, | |
508ef936 GH |
1792 | .qdev.props = (Property[]) { |
1793 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1794 | DEFINE_PROP_END_OF_LIST(), | |
1795 | }, | |
c4c270e2 | 1796 | },{ |
0aab0d3a | 1797 | .qdev.name = "i82551", |
273a2142 | 1798 | .qdev.size = sizeof(EEPRO100State), |
0aab0d3a | 1799 | .init = pci_i82551_init, |
e3936fa5 | 1800 | .exit = pci_nic_uninit, |
508ef936 GH |
1801 | .qdev.props = (Property[]) { |
1802 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1803 | DEFINE_PROP_END_OF_LIST(), | |
1804 | }, | |
c4c270e2 SW |
1805 | },{ |
1806 | .qdev.name = "i82557a", | |
1807 | .qdev.size = sizeof(EEPRO100State), | |
1808 | .init = pci_i82557a_init, | |
508ef936 GH |
1809 | .qdev.props = (Property[]) { |
1810 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1811 | DEFINE_PROP_END_OF_LIST(), | |
1812 | }, | |
0aab0d3a GH |
1813 | },{ |
1814 | .qdev.name = "i82557b", | |
273a2142 | 1815 | .qdev.size = sizeof(EEPRO100State), |
0aab0d3a | 1816 | .init = pci_i82557b_init, |
e3936fa5 | 1817 | .exit = pci_nic_uninit, |
508ef936 GH |
1818 | .qdev.props = (Property[]) { |
1819 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1820 | DEFINE_PROP_END_OF_LIST(), | |
1821 | }, | |
c4c270e2 SW |
1822 | },{ |
1823 | .qdev.name = "i82557c", | |
1824 | .qdev.size = sizeof(EEPRO100State), | |
1825 | .init = pci_i82557c_init, | |
508ef936 GH |
1826 | .qdev.props = (Property[]) { |
1827 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1828 | DEFINE_PROP_END_OF_LIST(), | |
1829 | }, | |
c4c270e2 SW |
1830 | },{ |
1831 | .qdev.name = "i82558a", | |
1832 | .qdev.size = sizeof(EEPRO100State), | |
1833 | .init = pci_i82558a_init, | |
508ef936 GH |
1834 | .qdev.props = (Property[]) { |
1835 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1836 | DEFINE_PROP_END_OF_LIST(), | |
1837 | }, | |
c4c270e2 SW |
1838 | },{ |
1839 | .qdev.name = "i82558b", | |
1840 | .qdev.size = sizeof(EEPRO100State), | |
1841 | .init = pci_i82558b_init, | |
508ef936 GH |
1842 | .qdev.props = (Property[]) { |
1843 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1844 | DEFINE_PROP_END_OF_LIST(), | |
1845 | }, | |
c4c270e2 SW |
1846 | },{ |
1847 | .qdev.name = "i82559a", | |
1848 | .qdev.size = sizeof(EEPRO100State), | |
1849 | .init = pci_i82559a_init, | |
508ef936 GH |
1850 | .qdev.props = (Property[]) { |
1851 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1852 | DEFINE_PROP_END_OF_LIST(), | |
1853 | }, | |
c4c270e2 SW |
1854 | },{ |
1855 | .qdev.name = "i82559b", | |
1856 | .qdev.size = sizeof(EEPRO100State), | |
1857 | .init = pci_i82559b_init, | |
508ef936 GH |
1858 | .qdev.props = (Property[]) { |
1859 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1860 | DEFINE_PROP_END_OF_LIST(), | |
1861 | }, | |
c4c270e2 SW |
1862 | },{ |
1863 | .qdev.name = "i82559c", | |
1864 | .qdev.size = sizeof(EEPRO100State), | |
1865 | .init = pci_i82559c_init, | |
508ef936 GH |
1866 | .qdev.props = (Property[]) { |
1867 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1868 | DEFINE_PROP_END_OF_LIST(), | |
1869 | }, | |
0aab0d3a GH |
1870 | },{ |
1871 | .qdev.name = "i82559er", | |
273a2142 | 1872 | .qdev.size = sizeof(EEPRO100State), |
0aab0d3a | 1873 | .init = pci_i82559er_init, |
e3936fa5 | 1874 | .exit = pci_nic_uninit, |
508ef936 GH |
1875 | .qdev.props = (Property[]) { |
1876 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1877 | DEFINE_PROP_END_OF_LIST(), | |
1878 | }, | |
c4c270e2 SW |
1879 | },{ |
1880 | .qdev.name = "i82562", | |
1881 | .qdev.size = sizeof(EEPRO100State), | |
1882 | .init = pci_i82562_init, | |
508ef936 GH |
1883 | .qdev.props = (Property[]) { |
1884 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1885 | DEFINE_PROP_END_OF_LIST(), | |
1886 | }, | |
0aab0d3a GH |
1887 | },{ |
1888 | /* end of list */ | |
1889 | } | |
1890 | }; | |
1891 | ||
9d07d757 | 1892 | static void eepro100_register_devices(void) |
663e8e51 | 1893 | { |
0aab0d3a | 1894 | pci_qdev_register_many(eepro100_info); |
663e8e51 TS |
1895 | } |
1896 | ||
9d07d757 | 1897 | device_init(eepro100_register_devices) |